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PDM41028LA15SOTY [ETC]

1 Megabit Static RAM 256K x 4-Bit; 1兆位静态RAM 256K ×4位
PDM41028LA15SOTY
型号： PDM41028LA15SOTY
厂家： ETC    ETC
描述：

1 Megabit Static RAM 256K x 4-Bit
1兆位静态RAM 256K ×4位

内存集成电路 静态存储器 光电二极管
文件： 总8页 (文件大小：237K)
中文：  中文翻译
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PDM41028  
1 Megabit Static RAM  
256K x 4-Bit  
1
2
Description  
Features  
The PDM41028 is a high-performance CMOS static  
RAM organized as 262,144 x 4 bits. Writing to this  
device is accomplished when the write enable (WE)  
and the chip enable (CE) inputs are both LOW.  
Reading is accomplished when WE remains HIGH  
and CE and OE are both LOW.  
■ High speed access times  
Com’l: 10, 12 and 15 ns  
Ind’l: 12 and 15 ns  
■ Low power operation (typical)  
- PDM41028SA  
3
Active: 400 mW  
Standby: 150 mW  
- PDM41028LA  
Active: 350 mW  
Standby: 100 mW  
The PDM41028 operates from a single +5V power  
supply and all the inputs and outputs are fully TTL-  
compatible. The PDM41028 comes in two versions,  
the standard power version PDM41028SA and a low  
power version the PDM41028LA. The two versions  
are functionally the same and only differ in their  
power consumption.  
■ Single +5V (±10%) power supply  
■ TTL-compatible inputs and outputs  
■ Packages  
5
The PDM41028 is available in a 28-pin 300-mil SOJ,  
and a 28-pin 400-mil SOJ for surface mount  
applications.  
Plastic SOJ (300 mil) - TSO  
Plastic SOJ (400 mil) - SO  
6
Functional Block Diagram  
7
A0  
Decoder  
Memory  
•
•
•
•
•
8
•
Addresses  
Matrix  
•
•
•
•
•
A17  
• • • • •  
Column I/O  
9
I/O0  
I/O1  
I/O2  
I/O3  
Input  
Data  
Control  
10  
11  
12  
CE  
WE  
OE  
Rev. 2.2 - 4/29/98  
1
PDM41028  
Pin Configuration  
SOJ  
Pin Description  
Vcc  
A6  
A5  
A4  
1
2
3
4
5
6
7
8
A7  
A8  
28  
27  
26  
25  
Name  
Description  
Address Inputs  
A17-A0  
I/O3-I/O0  
OE  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
CE  
Data Inputs/Outputs  
Output Enable Input  
Write Enable Input  
Chip Enable Input  
No Connect  
24 A3  
23 A2  
WE  
A1  
22  
CE  
21 A0  
20 NC  
9
NC  
19  
18  
17  
16  
15  
10  
11  
12  
13  
14  
I/O3  
I/O2  
I/O1  
I/O0  
WE  
V
Power (+5V)  
CC  
SS  
V
Ground  
OE  
Vss  
(1)  
Truth Table  
OE  
WE  
CE  
I/O  
MODE  
X
L
X
H
L
H
L
L
L
Hi-Z  
Standby  
Read  
D
OUT  
X
H
D
Write  
IN  
H
Hi-Z  
Output Disable  
NOTE: 1. H = V , L = V , X = DON’T CARE  
IH  
IL  
(1)  
Absolute Maximum Ratings  
Symbol  
Rating  
Com’l.  
Ind.  
Unit  
V
Terminal Voltage with Respect to V  
Temperature Under Bias  
Storage Temperature  
–0.5 to +7.0  
–55 to +125  
–55 to +125  
1.0  
–0.5 to +7.0  
–65 to +135  
–65 to +150  
1.0  
V
°C  
°C  
W
TERM  
BIAS  
STG  
SS  
T
T
P
Power Dissipation  
T
I
DC Output Current  
50  
50  
mA  
°C  
OUT  
(2)  
T
Maximum Junction Temperature  
125  
145  
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device.This is a stress rating only and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. Appropriate thermal calculations should be performed in all cases and specifically for  
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-  
culation should be of the form: T = T + P * θ where T is the ambient temperature, P  
j
a
ja  
a
is average operating power and θ the thermal resistance of the package. For this  
ja  
product, use the following θ values:  
ja  
o
SOJ: 76 C/W  
o
TSOP: 100 C/W  
2
Rev. 2.2 - 4/29/98  
PDM41028  
Recommended DC Operating Conditions  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
1
2
V
V
Supply Voltage  
4.5  
0
5.0  
0
5.5  
0
V
V
CC  
SS  
Supply Voltage  
Industrial  
Ambient Temperature  
Ambient Temperature  
–40  
0
25  
25  
85  
70  
°C  
°C  
Commercial  
3
DC Electrical Characteristics (V = 5.0V ± 10%)  
CC  
PDM41028SA  
PDM41028LA  
Unit  
Symbol  
Parameter  
Test Conditions  
Min.  
Max.  
Min.  
Max.  
I
Input Leakage Current  
V
= MAX., V = V to V  
CC  
Com’l/  
Ind.  
–5  
5
–5  
5
µA  
µA  
LI  
CC  
IN  
SS  
I
Output Leakage Current  
V
= MAX.,  
Com’l/  
Ind.  
–5  
5
–5  
5
LO  
CC  
5
CE = V , V  
= V to V  
SS CC  
IH OUT  
(1)  
(1)  
V
V
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
–0.5  
2.2  
0.8  
6.0  
–0.5  
2.2  
0.8  
6.0  
V
V
IL  
IH  
OL  
V
I
I
= 8 mA, V = Min.  
—
—
0.4  
0.5  
—
—
0.4  
0.5  
V
V
OL  
OL  
CC  
6
= 10 mA, V = Min.  
CC  
V
Output High Voltage  
I
= –4 mA, V = Min.  
2.4  
—
2.4  
—
V
OH  
OH  
CC  
NOTE: 1. V (min) = –3.0V for pulse width less than 20 ns  
IL  
7
Power Supply Characteristics  
-10  
-12  
-15  
8
Symbol Parameter  
Power Com’l. Com’l Ind. Com’l Ind. Unit  
I
Operating Current  
CE = V ,  
SA  
250  
230  
230  
210  
240  
185  
165  
195  
mA  
CC  
IL  
f = f  
= 1/t  
RC  
LA  
220  
175  
mA  
MAX  
9
V
= Max.  
= 0 mA  
CC  
I
OUT  
I
I
Standby Current  
CE = V  
SA  
LA  
SA  
LA  
80  
75  
20  
10  
70  
65  
15  
10  
70  
65  
25  
10  
55  
50  
10  
5
55  
50  
15  
10  
mA  
mA  
mA  
mA  
SB  
IH  
10  
11  
12  
f = f  
= 1/t  
RC  
MAX  
V
= Max.  
CC  
Full Standby Current  
SB1  
CE ≥ V  
HC  
f = 0  
V
V
= Max.,  
CC  
≥ V – 0.2V or ≤ 0.2V  
IN  
CC  
SHADED AREA = PRELIMINARY DATA  
NOTES: All values are maximum guaranteed values.  
≤ 0.2V, V ≥ V – 0.2V  
V
LC  
HC  
CC  
Rev. 2.2 - 4/29/98  
3
PDM41028  
(1)  
Capacitance (T = +25°C, f = 1.0 MHz)  
A
Symbol  
Parameter  
Max.  
Unit  
C
C
Input Capacitance  
Output Capacitance  
8
8
pF  
pF  
IN  
OUT  
NOTE:1. This parameter is determined by device characterization but is not production tested.  
AC Test Conditions  
Input pulse levels  
V
to 3.0V  
3 ns  
SS  
Input rise and fall times  
Input timing reference levels  
Output reference levels  
Output load  
1.5V  
1.5V  
See Figures 1 and 2  
+5V  
+5V  
480Ω  
480Ω  
DOUT  
255Ω  
DOUT  
255Ω  
5 pf  
30 pF  
Figure 2. Output Load Equivalent  
Figure 1. Output Load Equivalent  
(for t  
, t  
, t  
, t  
, t  
,
LZCE HZCE LZWE HZWE LZOE  
t
)
HZOE  
Typical Delta t  
vs Capacitive Loading  
AA  
5
4
3
2
1
0
60  
0
30  
90  
120  
Additional Lumped Capacitive Loading (pF)  
4
Rev. 2.2 - 4/29/98  
PDM41028  
(4, 5)  
Read Cycle No. 1  
t
RC  
1
2
ADDR  
t
AA  
t
OH  
D
PREVIOUS DATA VALID  
DATA VALID  
OUT  
3
(2, 4, 6)  
Read Cycle No. 2  
t
RC  
ADDR  
t
AA  
t
ACE  
CE  
OE  
t
t
HZCE  
5
LZCE  
t
t
t
HZOE  
LZOE  
D
OUT  
DATA VALID  
6
AOE  
7
AC Electrical Characteristics  
8
(7)  
(7)  
Description  
-10  
-12  
-15  
READ Cycle  
Sym  
Min. Max. Min. Max. Min. Max. Units  
READ cycle time  
t
10  
12  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
9
RC  
Address access time  
t
10  
10  
12  
12  
15  
15  
AA  
Chip enable access time  
Output hold from address change  
t
ACE  
t
3
5
3
5
3
5
OH  
10  
11  
12  
(1,3)  
Chip enable to output in low Z  
t
LZCE  
HZCE  
(1,2,3)  
Chip disable to output in high Z  
t
6
6
7
(3)  
Chip enable to power up time  
t
t
0
0
0
0
0
0
PU  
PD  
(3)  
Chip disable to power down time  
Output enable access time  
10  
6
12  
6
15  
6
t
AOE  
LZOE  
HZOE  
(1,3)  
(1,3)  
Output enable to output in low Z  
t
Output disable to output in high Z  
t
6
6
6
SHADED AREA = PRELIMINARY DATA  
Notes referenced are after Data Retention Table.  
Rev. 2.2 - 4/29/98  
5
PDM41028  
Write Cycle No. 1 (Write Enable Controlled)  
t
WC  
ADDR  
t
t
AH  
AW  
t
CW  
CE  
t
WP2  
WE  
t
t
t
AS  
DS  
DH  
D
IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH-Z  
HIGH-Z  
D
OUT  
Write Cycle No. 2 (Write Enable Controlled)  
t
WC  
ADDR  
t
t
AH  
AW  
t
CW  
CE  
t
AS  
t
WP1  
WE  
t
t
DH  
DS  
D
IN  
DATA VALID  
HIGH-Z  
D
OUT  
NOTE: Output Enable (OE) is inactive (high)  
Write Cycle No. 3 (Chip Enable Controlled)  
ADDR  
t
WC  
t
AW  
t
CW  
CE  
t
AS  
t
AH  
t
WP1  
WE  
t
t
DH  
DS  
D
IN  
DATA VALID  
HIGH-Z  
D
OUT  
6
Rev. 2.2 - 4/29/98  
PDM41028  
AC Electrical Characteristics  
(7)  
(7)  
Description  
-10  
-12  
-15  
1
2
WRITE Cycle  
Sym  
Min. Max. Min. Max. Min. Max. Units  
WRITE Cycle time  
t
t
10  
10  
10  
0
12  
10  
10  
0
15  
11  
11  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
Chip enable active time  
Address Valid to end of write  
Address setup time  
CW  
t
AW  
t
AS  
Address hold from end of write  
Write pulse width  
t
0
0
0
AH  
3
t
9
10  
11  
7
11  
12  
7
WP1  
Write pulse width  
t
10  
7
WP2  
Data setup time  
t
DS  
Data hold time  
t
0
0
0
DH  
(1,3)  
(1,3)  
Write disable to output in low Z  
t
0
0
0
LZWE  
HZWE  
Write enable to output in high Z  
t
7
7
7
SHADED AREA = PRELIMINARY DATA  
Notes referenced are after Data Retention Table  
5
Low V Data Retention Waveform  
6
CC  
Data Retention Mode  
V
4.5V  
4.5V  
CC  
V
DR  
7
t
t
CDR  
R
V
V
DR  
IH  
CE  
V
IL  
8
DON'T CARE  
Data Retention Electrical Characteristics (LA Version Only)  
9
Symbol Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
V
VCC for Retention Data  
Data Retention Current  
2
—
—
—
—
V
DR  
I
CE ≥ V – 0.2V  
V
V
= 2V  
= 3V  
—
—
500  
750  
µA  
µA  
CCDR  
CC  
CC  
10  
11  
12  
V
≥ V – 0.2V  
IN  
CC  
CC  
or ≤ 0.2V  
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
—
—
—
—
ns  
ns  
CDR  
(3)  
t
t
RC  
R
NOTES: (For three previous Electrical Characteristics tables)  
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.  
2. At any given temperature and voltage condition, t  
3. This parameter is sampled.  
4. WE is high for a READ cycle.  
5. The device is continuously selected. Chip Enable is held in its active state.  
6. The address is valid prior to or coincident with the latest occuring Chip Enable.  
7. Vcc = 5V ± 5%.  
is less than t  
.
HZCE  
LZCE  
Rev. 2.2 - 4/29/98  
7
PDM41028  
Ordering Information  
XXXXX  
X
XX  
Speed  
X
X
X
Device Type Power  
Package  
Type  
Process  
Temp. Range  
Preferred  
Shipping  
Container  
Blank Tubes  
TR  
TY  
Tape & Reel  
Tray  
Blank  
I
A
Commercial (0° to +70°C)  
Industrial (–40°C to +85°C)  
Automotive (–40°C to +105°C)  
TSO 28-pin 300-mil Plastic SOJ  
28-pin 400-mil Plastic SOJ  
SO  
Commercial Only  
10  
12  
15  
(Use 15ns for slower designs.)  
SA  
LA  
Standard Power  
Low Power  
PDM41028 - (256Kx4) Static RAM  
Faster Memories for a Faster World ™  
8
Rev. 2.2 - 4/29/98  

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