PDM41256LA12T [ETC]
256K Static RAM 32K x 8-Bit; 256K静态RAM 32K ×8位
| 型号： | PDM41256LA12T |
| 厂家： | 
ETC |
| 描述： | 256K Static RAM 32K x 8-Bit |
| 文件： | 总8页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDM41256
256K Static RAM
32K x 8-Bit
1
2
Description
Features
The PDM41256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. This product is
produced in Paradigm’s proprietary CMOS
technology which offers the designer the highest
speed parts. Writing to this device is accomplished
when the write enable (WE) and the chip enable
(CE) inputs are both LOW. Reading is accomplished
when WE remains HIGH and CE and OE are both
LOW.
■ High-speed access times
Com’l: 7, 8, 10, 12, and 15 ns
Ind’l: 8, 10, 12, and 15 ns
■ Low power operation (typical)
- PDM41256SA
3
Active: 400 mW
Standby: 150 mW
- PDM41256LA
Active: 350 mW
Standby: 25 mW
4
The PDM41256 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41256 comes in two versions,
the standard power version PDM41256SA and a low
power version the PDM41256LA. The two versions
are functionally the same and only differ in their
power consumption.
■ Single +5V (±10%) power supply
■ TTL-compatible inputs and outputs
■ Packages
5
Plastic SOJ (300 mil) - TSO
Plastic TSOP - T
The PDM41256 is available in a 28-pin plastic TSOP
and a 28-pin 300-mil plastic SOJ.
6
Functional Block Diagram
7
8
9
10
11
12
Rev. 2.0 - 7/17/96
3-33
PDM41256
SOJ
Pin Configurations
TSOP
Pin Description
Name
Description
A14-A0
I/O7-I/O0
OE
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+5V)
WE
CE
VCC
VSS
Ground
Truth Table
OE
WE
CE
I/O
MODE
X
L
X
H
L
H
L
L
L
Hi-Z
DOUT
DIN
Standby
Read
X
H
Write
H
Hi-Z
Output Disable
NOTE: 1. H = VIH, L = VIL, X = DON’T CARE
(1)
Absolute Maximum Ratings
Symbol
Rating
Com’l.
Ind.
Unit
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
V
°C
°C
W
Power Dissipation
IOUT
DC Output Current
50
50
mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
4.5
0
5.0
0
5.5
0
V
V
VSS
Supply Voltage
Commercial
Industrial
Ambient Temperature
Ambient Temperature
0
25
25
70
85
°C
°C
–40
3-34
Rev. 2.0 - 7/17/96
PDM41256
DC Electrical Characteristics (VCC = 5.0V ± 10%)
PSM41256SA
PSM41256LA
Unit
1
2
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
ILI
Input Leakage Current
VCC = MAX., VIN = Vss to VCC
Com’l/
Ind.
–5
5
–5
5
µA
µA
ILO
Output Leakage Current
VCC= MAX.,
CE = VIH, VOUT = Vss to VCC
Com’l/
Ind.
–5
5
–5
5
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.5(1)
2.2
0.8
6.0
–0.5(1)
2.2
0.8
6.0
V
V
V
VIH
VOL
3
IOL=8 mA, VCC = Min.
IOL = 10 mA, VCC = Min.
—
—
0.4
0.5
—
—
0.4
0.5
VOH
Output High Voltage
IOH = –4 mA, VCC = Min.
2.4
—
2.4
—
V
NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns.
4
Power Supply Characteristics
-7
-8
-10
-12
-15
5
Symbol Parameter
Power Com’l. Com’l. Ind. Com’l. Ind. Com’l. Ind. Com’l. Ind. Units
ICC
Operating Current
SA
LA
210
190
200
180
210
190
190
170
200
180
180
160
190
170
170
150
180
160
mA
mA
CE = VIL
f = fMAX = 1/tRC
VCC = Max
IOUT = 0 mA
6
ISB
Standby Current
CE = VIH
SA
LA
SA
LA
90
90
20
5
80
80
20
5
80
80
20
10
70
70
20
5
70
70
20
10
60
60
20
5
60
60
20
10
50
50
20
5
50
50
20
10
mA
mA
mA
mA
7
f = fMAX = 1/tRC
VCC = Max
ISB1
Full Standby Current
CE ≥ VCC – 0.2V
8
f = 0
VCC = Max
VIN ≥ VCC – 0.2V or ≤ 0.2V
SHADED AREA = PRELIMINARY DATA
NOTE:All values are maximum guaranteed values.
9
(1)
Capacitance (TA = +25°C, f = 1.0 MHz)
10
11
12
Symbol
Parameter
Max.
Unit
CIN
Input Capacitance
Output Capacitance
8
8
pF
pF
COUT
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
Rev. 2.0 - 7/17/96
3-35
PDM41256
AC Test Conditions
Input pulse levels
VSS to 3.0V
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
3 ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
, t
, t
, t
, t
,
LZCE HZCE LZWE HZWE LZOE
t
)
HZOE
Figure 3.
3-36
Rev. 2.0 - 7/17/96
PDM41256
(1)
Read Cycle No. 1
1
2
3
(2)
Read Cycle No. 2
4
5
6
7
AC Electrical Characteristics
Description
--7(6)
--8(6)
-10(6)
-12
-15
8
READ Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
READ cycle time
tRC
tAA
tACE
tOH
7
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
7
7
8
8
10
10
12
12
15
15
9
Chip enable access time
Output hold from address change
Chip enable to output in low Z(3, 4, 5)
Chip disable to output in high Z(3, 4, 5)
Chip enable to power up time(4)
Chip disable to power down time(4)
Output enable access time
3
5
3
5
3
5
3
5
3
5
tLZCE
tHZCE
tPU
5
6
6
6
6
10
11
12
0
0
0
0
0
0
0
0
0
0
tPD
7
5
8
5
10
5
12
6
15
8
tAOE
tLZOE
tHZOE
Output enable to output in low Z(4, 5)
Output disable to output in high Z(4, 5)
5
6
6
6
6
SHADED AREA = PRELIMINARY DATA.
Notes referenced are after Data Retention Table.
Rev. 2.0 - 7/17/96
3-37
PDM41256
Write Cycle No. 1 (Write Enable Controlled)
Write Cycle No. 2 (Chip Enable Controlled)
AC Electrical Characteristics
Description
-7(6)
-8(6)
-10(6)
-12
-15
WRITE Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
tWC
tCW
tAW
7
7
7
0
0
7
6
0
0
8
8
8
0
0
8
7
0
0
10
10
10
0
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable to end of write
Address valid to end of write
Address setup time
tAS
Address hold from end of write
Write pulse width
tAH
0
0
0
tWP
10
7
10
7
11
7
Data setup time
tDS
Data hold time
tDH
0
0
0
Write disable to output in low Z(4, 5)
Write enable to output in high Z(4, 5)
tLZWE
tHZWE
0
0
0
3
3
3
3
3
SHADED AREA = PRELIMINARY DATA.
3-38
Rev. 2.0 - 7/17/96
PDM41256
Low V Data Retention Waveform
CC
1
2
3
Data Retention Electrical Characteristics (LA Version Only)
4
Symbol Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDR
VCC for Retention Data
2
—
95
—
V
ICCDR
Data Retention Current
CE ≥ VCC – 0.2V
IN ≥ VCC – 0.2V
or ≤ 0.2V
VCC = 2V
VCC = 3V
—
—
500
750
µA
µA
5
V
350
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
—
—
—
—
ns
ns
(4)
tR
tRC
6
NOTES: (For three previous Electrical Characteristics tables)
1. The device is continuously selected. Chip Enable is held in its active state.
2. The address is valid prior to or coincident with the latest occuring Chip Enable.
3. At any given temperature and voltage condition, tHZCE is less than tLZCE
4. This parameter is sampled.
5. The parameter is tested with CL = 5 pF as shown in Figure 2.Transition is measured ±200 mV from steady state voltage
6. Vcc = 5V ± 5%.
.
7
8
9
10
11
12
Rev. 2.0 - 7/17/96
3-39
PDM41256
Ordering Information
3-40
Rev. 2.0 - 7/17/96
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