PFM19030 [ETC]
1930-1990 MHz, 30W, 2-Stage Power Module Enhancement-Mode Lateral MOSFETs; 一九三零年至1990年兆赫， 30W ， 2级功率模块，增强模式横向的MOSFET
| 型号： | PFM19030 |
| 厂家： | 
ETC |
| 描述： | 1930-1990 MHz, 30W, 2-Stage Power Module Enhancement-Mode Lateral MOSFETs |
| 文件： | 总15页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PFM19030 SPECIFICATION
1930-1990 MHz, 30W, 2-Stage Power Module
Enhancement-Mode Lateral MOSFETs
This versatile PCS module provides excellent linearity and efficiency in a
low-cost surface mount package. The PFM19030 includes two stages of
amplification, along with internal sense FETs that are on the same silicon
die as the RF devices. These thermally coupled sense FETs simplify the
task of bias temperature compensation of the overall amplifier. The module
includes RF input, interstage, and output matching elements. The source
and load impedances required for optimum operation of the module are
much higher (and simpler to realize) than for unmatched Si LDMOS
transistors of similar performance.
Package Type: Surface Mount
PN: PFM19030SM
The surface mount package base is typically soldered to a conventional
PCB pad with an array of via holes for grounding and thermal sinking
of the module. Optimized internal construction supports low FET
channel temperature for reliable operation.
Package Type: Flange
PN: PFM19030F
• 28 dB Gain
• IS95 CDMA Performance
5 Watts Average Output Level
20% Power Added Efficiency
–49 dBc ACPR
• 30 Watts Peak Output Power
• Internal Sense FETs
(for improved bias control)
Module Schematic Diagram
Module Substrate
Q2 Die Carrier
Q1 Die Carrier
Drain 2
Q2
RF OUT
Q1
Gate 1
RF IN
Input
Match
Output
Match
Lead
Input
Match
Output
Match
Lead
S2
S1
Lead
Lead
Sense S1
Gate 2
Sense S2
Lead
Lead
D1
Note: Additionally, there are 250 KOhm resistors connected in shunt with all leads, to enhance ESD protection.
Page 1 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Electrical Specification
Parameter
Min
Limits
Typ
Units
Comments
Max
1
2
Operating Frequency
1930
-
1990
MHz
dB
Gain
27.0
29.0
31.5
1.5
Note 1.
Pulsed CW compression measurement
(12 µsec pulse, 120 µsec period, 10%
duty cycle).
Gain Compression at
Pout =30 Watts
3
4
5
6
-
-
-
0.8
dB
dB
°
Gain Flatness over any
30 MHz bandwidth
Deviation from Linear
Phase over any 30
MHz bandwidth
± 0.2
± 0.8
± 0.3
± 1.5
Includes delay of test fixture (~0.6
nanosec.).
Note 3. Refer to applications data for
performance with other protocols.
Group Delay
-
3.1
-49
20.5
42
3.7
-
nanosec
dBc
%
ACPR with IS95A
CDMA Pave = 5 W
Efficiency under IS-95
Protocol, Pave = 5 W
Efficiency @ 30W
CW Output
7
8
-45
18
-
Note 3.
9
-
%
DC Drain Supply
Voltage
Operating
Testing for conformance with RF
specifications is at +27 V.
10
24
-40
-
27
30
Volts
Testing for conformance with RF
specification is at +25 °C.
11 Temperature Range
(base temperature)
-
-0.033
-
+115
-
°C
Gain Variation versus
Temperature
12
Bias quiescent currents held constant.
dB/°C
VSWR 10:1, all phase angles. No
degradation in output power before &
after test.
Output Mismatch
Stress
Watts
CW
13
-
30
14 Stability
-60
-
-
-
dBc
0<Pout<44.8 dBm CW, 3:1 VSWR
Theta jc is for output device. Verified
with IR scan. Note 2.
15 Theta jc (channel)
1.9
2.1
°C/W
Quiescent Currents
16 a) Q1
These DC quiescent currents are typical
of the levels that produce optimum
linearity for CDMA protocol.
75
260
mA
mA
b) Q2
Sense FET Current/RF
FET Current Ratio
Ratio of sense FET current, relative to RF
FET current. Ratios are: Stg 1: 33:1;
Stg 2: 58:1 Gates of sense & RF FETs
are DC connected. Measured with no RF
signal present.
17
18
a) Stg 1 Sense
b) Stg 2 Sense
3.0
1.7
%
%
ESD Protection
a) Human Body Model
b) Machine Model
a) 2000V, 100 pF, 1500 Ohms
b) 400V, 200 pF, zero Ohms
Mil STD 883E, Method 3015 for Human
Body Model and for Machine Model.
Class 1
Class M3
Page 2 of 15 Specifications subject to change without notice. US Patent No.6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Electrical Specification (Continued)
MAXIMUM RATINGS
Rating
Symbol
Value
Units
DC Drain Supply
a) Drain-to-Source Voltage, (VGS=0), D1 & D2
& Track D1 & Track D2
b) Normal Operation (Class AB operation)
VDS
+50
+30
Volts DC
Volts DC
19
VD_SUPPLY
DC Gate Supply
20
a) Gate-to-source Voltage (VDS=0)
Normal Operation (Class AB operation)
VGS
VG_SUPPLY
-0.5<VGS<+15
0<VGS<+6
Volts DC
Volts DC
21
22
RF Input Power
PIN
+25
dBm
PTOTAL
65
-0.7
Watts
Watts/°C
Maximum Power Dissipation (T ≤ +85 °C)
a) Derate above +85 °C base temperature.
23
24
Maximum Channel Operating Temperature
Storage Temperature Range
TCH
TSTG
+200
-40 to +150
°C
°C
RECOMMENDED SOURCE AND LOAD IMPEDANCES
Impedance Units
Comments
Nominal Source
Impedance for
Optimum Operation
Matched for near-optimum linearity and gain flatness.
19 + j1.9
21 + j6.3
Ohms
Ohms
Impedance is looking from the module input lead into the
input matching circuit. Reference plane is 0.105 inches from
the input end (case edge)of the module.
Matched for near-optimum linearity under CDMA protocol.
Impedance is from the module output lead looking into the
output matching circuit. Reference plane is 0.105 inches from
the output end (case edge) of the module.
Nominal Load
Impedance for
Optimum Operation
Specification Notes:
1) The module is mounted in a test fixture with external matching elements for all testing. Quiescent current bias
conditions are those appropriate for minimum ACPR under CDMA protocol. Supply voltage for all tests is
+27 volts DC. Testing is at +25 °C unless otherwise specified.
2) Theta jc is measured with a package mounting (base) temp of +85 °C, and with 10 Watts CW output.
3) Pout=5Watts average; IS-95A protocol: IS95 Forward Link PPS+ 9CH.
ACPR conditions: a) 900 kHz offset, 30 kHz BW, b) 2.75 MHz offset, 1 MHz BW.
4) Sense FETs are scaled versions of the main RF FETs, formed from electrically isolated cells at end of the RF
structure. Current scales according to periphery (threshold voltages offset is less than ±150 millivolts between
adjacent devices). RF & Sense FET gates and sources are DC connected. Drains are DC isolated. Leads S1 & S2
are DC connected to drains of sense FETs 1 & 2. Sources are connected to package base. Sense FETs are
electrically isolated from the RF signals.
Page 3 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Typical Module Performance
T=+25 °C, unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
Gain & Efficiency vs. Output Power
Typical Small-Signal Gain vs. Frequency
Pulsed Measurement, Vdc=+27V, F=1960 MHz
29
28
27
26
25
24
60%
50%
40%
30%
20%
10%
31
30
29
28
27
26
1840
1870
1900
1930
1960
1990
2020
2050
2080
30
32
34
36
38
40
42
44
46
Frequency (MHz)
Ouptput Power (dBm)
Typical Output Power at 1 dB Gain
Input and Output Return Loss vs Frequency.
Compression vs Freq. & Supply Voltage
47
46
45
44
43
0
-2
P1dB(+26V)
P1dB(+27V)
P1dB(+28V)
-4
OUTPUT
INPUT
-6
-8
-10
-12
-14
1870
1900
1930
1960
1990
2020
2050
Frequency (MHz)
1900
1930
1960
1990
2020
Frequency (MHz)
Typical CW Gain vs Swept CW Output Power,
with Various Quiescent Bias Conditions
Typical S21 Phase Variation Versus Frequency
30
29
28
27
26
25
24
(normalized about average insertion phase)
3
2
Bias for Best 2-Tone
IMDs
1
0
-1
-2
-3
G(75/250 mA)
G(68/225 mA)
G(60/200 mA)
G(82/275 mA)
1930
1945
1960
1975
1990
Frequency (MHz)
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
CW Swept Output Power (dBm)
T
t
i
m
e
d
e
l
a
y
o
f
f
s
e
s
t
=
3
.
2
n
a
.
n
o
s
e
c
(
i
n
c
l
u
d
e s
Note: This data illustrates the significance of quiescent bias
current level. The unit was press mounted in the fixture &
thermal effects are exagerated for this CW test.
i
m
e
d
e
l
a
y
o
f
t
e
t
f
i
x
t
u
r e )
Page 4 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Typical Module Performance
T=+25 °C, unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
Single-Signal IS95 CDMA ACPR & Efficiency
Typical CW 2-Tone Intermods vs. Output Power
vs Average Output Power (F=1960 MHz)
-10
-20
-30
-40
-50
-60
-70
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
30
27
24
21
18
15
12
9
IM3L
IM3U
IM5L
IM5U
IM7L
IM7U
ACPR(-900 KHz)
ACPR(+900 KHz)
ACPR(-1.25 MHz)
ACPR(+1.25 MHz)
ACPR(-2.75 MHz)
ACPR(+2.75 MHz)
PAE (%)
6
3
30 31 32 33 34 35 36 37 38 39 40 41 42 43
Average Output Power (dBm)
0
30
31
32
33
34
35
36
37
38
39
F1=1959.5 MHz, F2=1960.5 MHz
Vsupply = +27 V, Idsq1 = 75 mA, Idsq2=250 mA
Average CDMA Output Power (dBm)
2 IS95 CDMA Signal IM Distortion
vs. Ave Output Power (F=1955, 1965 MHz)
2-Tone IMD Rejection vs. Tone Separation
(Peak Envelope Power = 44.5 dBm)
-20
-25
-30
-35
-40
-45
-50
-55
-60
0
IM3L
IM3U
IM5L
IM5U
IM7L
IM7U
IM3(+15 MHz)
IM3(-15 MHz)
IM5(-25 MHz)
IM5(+25 MHz)
-10
-20
-30
-40
-50
-60
0
10
20
30
40
50
30
31
32
33
34
35
36
37
38
CW Tone Separation (MHz)
CDMA Total Average Power (dBm)
WCDMA ACLR & Efficiency vs Output
Power (F=1960 MHz, Test Model 1)
F1=1930 MHz, F2=1930.5 MHz to 1980 MHz
Vsupply = +27 V, Idsq1 = 75 mA, Idsq2=250 mA
-15
-20
-25
-30
-35
-40
-45
-50
28
24
20
16
12
8
ACLR(-5 MHz)
ACLR (+5 MHz)
Efficiency
4
0
30
31
32
33
34
35
36
37
38
39
Average WCDMA Output Power (dBm)
Page 5 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Typical Module Performance
T=+25 °C, unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
EDGE EVM & Efficiency vs. Pout
2-Tone 3rd Order IMD Rejection vs. Pout
& First Stage Quiescent Bias Currents
12
10
8
30.0%
25.0%
20.0%
15.0%
10.0%
5.0%
-20
-25
-30
-35
-40
-45
-50
-55
-60
IM3(75/250)
IM3(82/250)
IM3(67/250)
IM3(60/250)
Efficiency
RMS EVM %
Efficiency
Idsq1=Opt-20%
-10%
+10%
6
4
EVM
Idsq1=Optimum,
75 mA
2
0
0.0%
26
28
30
32
34
36
38
40
42
44
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Average Output Power (dBm)
Average Output Power (dBm)
2-Tone 3rd Order IMD Rejection vs. Pout
& Second Stage Quiescent Bias Currents
EDGE ACPR vs. Average Pout
0
-10
-20
-30
-40
-50
-60
-70
-80
IM3(75/250)
IM3(75/275)
IM3(75/225)
lower 200khz
upper 200khz
lower 250khz
upper 250khz
lower 400khz
upper 400khz
lower 600khz
upper 600khz
lower 1.2mhz
upper 1.2mhz
-20
-25
-30
-35
-40
-45
-50
-55
-60
IM3(75/200)
Idsq2=Optimum -20%
+10%
-10%
Idsq2 = Optimum,
250 mA
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
36
37
38
39
40
41
42
43
Average Output Power (dBm)
Average Output Power (dBm)
Page 6 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
PFM19030SM Package Outline
PFM19030F Package Outline
Page 7 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Module Application Notes
The PFM19030 was designed to provide a versatile low cost solution for a wide variety of wireless applications
requiring 30 Watt peak output levels. This hybrid module contains two stages of Si LDMOS FET amplification:
a nominally 5 Watt input stage driving a 30 Watt output stage. The module is optimized for efficient, linear operation
with EDGE and CDMA signals. The input and output of this module are partially matched, and require source and load
impedances of nominally 19 and 21 Ohms (much higher than typically required by unmatched Si LDMOS FETs).
These source and load impedances can be achieved with compact conventional external PCB circuitry.
Performance for particular signal protocols can be improved slightly by small adjustments in quiescent currents and
load impedances presented to the module. The data presented in the previous pages was taken at one set of quiescent
currents and in a fixture with source and load impedances that were fixed for all measurements. The data presented is
generally representative of the performance – benefits from further optimization in quiescent current are small.
In addition to the two RF gain stages, there are Sense FET (thermally tracking) devices that serve as optional DC circuit
elements. The Sense FETs are fabricated on the same epi material with nominally identical physical characteristics (but
smaller gate periphery) as the RF devices. The sense devices can be applied as temperature compensation elements in
conjunction with external bias circuitry. Alternatively, the two-stage amplifier can be operated with the Sense FETs
unused (S1 and S2 leads floating).
The base of the module is high conductivity copper of 40 mil thickness. It is well matched to typical PCB material, and
it serves as a heat spreader for the device when mounted as a surface-mount component. The module thermal
characteristics were measured with the unit soldered to a 20 mil thick PCB material with an array of plated via holes for
electrical grounding and thermal sinking. IR scans of this configuration demonstrated maximum die channel
temperatures of 142 degrees C with a PCB base temperature of +95 degrees C, and 10 Watts CW output power.
These modules can be provided in tape-and-reel configuration for high volume applications.
Typical PCB Mounting Pattern
The module outline is indicated by dashed line (0.60 X 1.00 inches). The ground pad is 1.030 X 0.630
inches. Ground vias in this example are 28 mil diameter on 35 mil (or 70 mil) centers. Thermal resistance is
proportional to the thickness of the PC board (height of vias), and inversely proportional to the total ground
hole array periphery (and thickness of plating in the holes). The densely spaced vias in this layout (on 35 mil
spaces) are located in areas of maximum heat generation. The gap between the lead pads and the ground
pad is 25 mils. Note that the underside of the PCB must be connected to a thermal heat sink and ground.
The above hole pattern is an example of one that maximizes thermal transfer. There are numerous
alternative approaches. Depending on the application (signal protocol, thermal environment, etc.), the
number of via holes can be reduced. High average power applications require the most extensive thermal
sinking.
Page 8 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Recommended Passive Bias Circuit
This schematic demonstrates a method of applying the Sense FETs internal to the module that uses passive
external circuitry. The circuit maintains a constant current through the Sense FETS, independent of
temperature of the die. The Sense FETs are configured in this case as diodes. The temperature dependence
of the Vf of the diode is very similar to that of the RF FET gate voltage, and therefore the quiescent current
remains nearly constant over a wide temperature range. The advantage of this circuit is its simplicity and
stability (avoidance of operational amplifiers) under all layout conditions. The main limitation of the circuit
is that quiescent currents must be adjusted for each individual module (they are not easily pre-set with
precision).
+10 to
+20 V
Gate
GND
+27 V
Note: Typical Q1 diode bias = 1.4 mA (VG1 ~ 3.96V)
Typical Q2 diode bias = 2.7 mA (VG2 ~ 4.21V)
(based on 6/4/04 measurements)
J1
8
7
6
5
4
3
2
1
C29
S1
S2
C28
C27
C12 C11 C10
R6
R5
C24
C23
R2
C22
C20
C21
C19
C9
C18 C17 C16 C15
C8
Drain 1
C7
Sense D2
Gate 2
C2
R3
C6
R1
Sense D1
PFM19030
RF
OUT
RF
Out
RF IN
RF
C1
Input
C4
C5
C3
Page 9 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
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PFM19030
Passive Bias Circuit Parts List
Designator
Description
Qty
C2
C3
C5
C4
C6
1
1
1
1
1
4
4
4
1
CAP, 1.2 PF±0.1 pF, 0603, ATC 600S
CAP, 2.0 PF±0.1 pF, 0603, ATC 600S
CAP, 1.8 PF±0.1 pF, 0603, ATC 600S
CAP, 4.7 PF±0.1 pF, 0603, ATC 600S
CAP, 3.0 PF±0.1 pF, 0603, ATC 600S
CAP, 27 PF±5%, 0603, ATC 600S
CAP, 27 PF±5%, 100V (min), 0603, any vendor.
CAP, 470 PF ±10%,100 V, 0603, any vendor.
CAP, 3300 PF±10%, 100 V, 0603, Murata GRM39X7R332K100??, or
equivalent.
C1, C7, C19, C20
C10, C13, C14, C15,
C8, C11, C16, C21
C22
C23, C9, C17, C12
C24, C18
4
2
CAP, 15000 PF±10%, 100 V, 0805, MurataGRM40X7R153K100??,
or equivalent.
CAP, 150000 1206, 50V, X7R, 10%
Suggest Murata GRM42-6-X7R-154-K-050-A-L or equivalent.
R5
RES, potentiometer, 10Kohms, Digikey SM4W103-ND
1
1
1
1
1
1
1
2
R6
RES, potentiometer, 5 Kohms, Digikey SM4W502-ND
RES, 1/16W, 0603, 1000 ohms, 5%
RES, 1/16W, 0805, 124 Ohms, 5%
R1
R3
C27
C29
C28
S1, S2
CAP, 2.2uf SMT TANTALUM, 50V (240097)
CAP, 10uf 16V SMT TANTALUM (240096)
CAP, 47UF, 50V, ELECTR SMT (240087)
SPST Switch, Digikey PN CKN1100CT-ND
Page 10 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Test Fixture
A metal-backed PCB with clamps for securing the module is used for module electrical testing and for
product demonstration. The fixture is supplied mounted to a finned heat sink. The fixture schematic is
provided on the following page.
This test fixture uses an active bias circuit, which sets the bias circuit through the Sense FETs (configured as
FETs) and applies the derived gate voltage to the associated RF FETs. This assures particular quiescent bias
currents, with accuracy determined by the Sense FET-to-RF FET current ratios.
Page 11 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Test Fixture Schematic
+27 V
OpAmp
+27 V
GND
J2 Not Used for Demo Fixture
J1
J2
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
RZ_FS1
RZ_FS2
C31
C37
C34
R33
C36
R36
R12
C32
R32
R31
R11
R16
U2
5
4
-
5 U1
R13
C43
4
3
LM8261
-
+
C42
3
LM8261
R34
C35
2
C41
+
1
R14
C40
2
R39
R37
R19
R40
R35
R20
C33
R15
R38
R17
S2
D2
R18
S1
D1
C28
C27
C26
C12 C11 C10
C25
C24
C22
C23
C21
C14
C9
C8
C7
C20
C19
C18 C17 C16 C15
Drain 1
Sense D2
Gate 2
C2
R2
C6
R1
Sense D1
RF IN
PFM19030SM
RF
OUT
RF
Out
RF
Input
C1
C4
C5
C3
See the following pages for the parts list and a description of the principle of operation. Note that an
alternative, less complex bias scheme is provided later in this applications note. The advantage of the above
bias design is that bias currents are set by the RF-to-Sense FET ratios, and once the optimum bias circuit
resistor (potentiometer) values are established, the circuit can stay fixed for multiple modules (thus
eliminating module-specific bias alignment). Additionally, aging effects are minimized because of the
Page 12 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
similar bias conditions for Sense and RF FETs. The disadvantage of this design is its relative complexity and
the incorporation of operational amplifiers, for which stability is potentially circuit layout dependent.
Parts List for Cree Microwave Test Fixture
Designator
Qty
Description
C2
C3
C5
C4
C6
1
1
1
1
1
4
4
4
1
4
6
CAP, 1.2 PF±0.1 pF, 0603, ATC 600S
CAP, 2.0 PF±0.1 pF, 0603, ATC 600S
CAP, 1.8 PF±0.1 pF, 0603, ATC 600S
CAP, 4.7 PF±0.1 pF, 0603, ATC 600S
CAP, 3.0 PF±0.1 pF, 0603, ATC 600S
CAP, 27 PF±5%, 0603, ATC 600S
CAP, 27 PF±5%, 100V (min), 0603, any vendor.
CAP, 470 PF ±10%,100 V, 0603, any vendor.
CAP, 3300 PF±10%, 100 V, 0603, Murata GRM39X7R332K100
CAP, 15000 PF±10%, 100 V, 0805, MurataGRM40X7R153K100
CAP, 150000 1206, 50V, X7R, 10%
C1, C7, C19, C20
C10, C13, C14, C15,
C8, C11, C16, C21
C22
C9, C23, C17, C12
C18, C24, C25, C26,
C31, C34
Murata GRM42-6-X7R-154-K-050-A-L
C27, C37
C28
CAP, 2.2uf SMT TANTALUM, 50V
CAP, 47UF, 50V, ELECTR SMT
2
1
2
2
4
1
1
2
2
4
4
2
1
1
2
2
2
2
2
2
C33, C35
C32, C36
C40, C41, C42, C43
R1
CAP, 18,000 PF ±10%,100 V, 0603
CAP, 33,000 PF ±10%,100 V, 0603
CAP, 1000 PF ±10%,100 V, 0603.
RES, 1/16W, 0603, 1000 ohms, 5%
R2
RES, 1/16W, 0805, 124 Ohms, 5%
RES, 1/16W, 0603, 332 Ohms, 1%
R11, R12
R31, R32
R13, R14, R33, R34
R16, R15, R35, R36
R19, R39
R18
RES, 1/16W, 0603, 147 Ohms, 1%
RES, 1/16W, 0603, 2370 Ohms, 1%
RES, 1/16W, 0603, 511 KOhms, 1%
RES, 1/16W, 0603, 100 KOhms, 5%
RES, 1/16W, 0603, 3320 Ohms, 5%
RES, 1/16W, 0603, 2000 Ohms, 5%
R38
R20, R40
R17, R37
RZ_FS1, RZ_FS2
D1, D2
RES, 1/8W, 1206, 1000 Ohms, 5%
RES, potentiometer, 10 Kohms, Digikey SM4W103-ND, 11T
RES, 1/16W, 0805, 0 Ohms (used as jumpers, demo fixture only)
Zener diode, 6.2 V, Digikey PN BZT52C6V27DICT-ND
SPST Switch, Digikey PN CKN1100CT-ND
Op Amp, High Output, LM8261M5 (5 pin, SOT23 package)
S1, S2
U1, U2
It is also possible to bias the two stages in a conventional manner, with the two tracking FET drains left
unused (floating or grounded). The above bias circuits are just two of several possibilities.
Page 13 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Test Fixture Active Bias Circuit Principles of Operation
The test fixture operates off of a single voltage supply. It contains two switches and two potentiometers.
The switches provide for independent on/off for the input and output devices of the module. The
potentiometers allow adjustment of quiescent current level of each stage. The adjustments should be made
with no RF applied to the module.
Q1 Die Carrier
Q1
Output
Match
Input
Match
Vsupply
S1
Vsupply
R1 <<Rbias
R1
R1
-
Differental Amp
+
Ids_sense
Ireference
Rbias
Principal of Operation of Bias Circuitry
The principal of operation of the fixture bias circuit is demonstrated in the above Figure. The potentiometer
establishes a reference current, and the operational amplifier adjusts gate voltage to maintain that current in
the sense device. The same DC gate voltage is also applied to the main (RF) device. Sense devices are
scaled versions of the main (RF) devices, on the same die (to facilitate temperature tracking). As the
temperature of the die changes due to RF drive (or ambient temperature changes), the operational amplifier
maintains constant current through the Sense FET, and thus constant quiescent bias for the main (RF) FET.
No RF signal is applied to the Sense FET.
There is a separate independent bias circuit for the input (Q1) device and for the output device (Q2) of the
module.
Experience has shown this bias circuit to be a reliable method of maintaining tight control of quiescent
current over operating temperature, and for minimizing the impact of device aging effects on amplifier
performance. However, there are some precautions regarding use of this circuit. The principle of the circuit
is for the differential amplifier (op amp) to adjust gate voltage until the desired current is achieved through
the sense FETs. If the current path is interrupted (thereby not allowing Ids_sense to flow), the operational
amplifier will increase gate bias in an attempt to increase current, with the possibility that the quiescent bias
current in the RF FET may increase beyond a safe limit (the device may be destroyed). The zener diodes in
the test fixture circuit (D1 and D2, test fixture schematic) are safeguards for prohibiting excessive gate
voltage to be applied to the transistors.
Page 14 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
PFM19030
Disclaimer: Specifications are subject to change without notice. Cree Microwave, Inc. believes the
information contained within this data sheet to be accurate and reliable. However, no responsibility is
assumed by Cree Microwave for any infringement of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of
Cree Microwave. Cree Microwave makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose. “Typical” parameters are the average values
expected by Cree Microwave in large quantities and are provided for information purposes only. These
values can and do vary in different applications, and actual performance can vary over time. All
operating parameters should be validated by customer’s technical experts for each application. Cree
Microwave products are not designed, intended, or authorized for use as components in applications
intended for surgical implant into the body or to support or sustain life, in applications in which the
failure of the Cree product could result in personal injury or death, or in applications for planning,
construction, maintenance or direct operation of a nuclear facility. Cree Microwave is a trademark and
Cree and the Cree logo are registered trademarks of Cree, Inc.
Contact Information:
Cree Microwave, Inc.
160 Gibraltar Court
Sunnyvale, CA 94089-1319
Sheryle Henson (Cree Microwave—Marketing Manager) 408-962-7783
Tom Dekker (Cree Microwave—Sales Director) 919-313-5639
Page 15 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
Rev. 2
http://www.cree.com/
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