PI6C2973 [ETC]
Clock IC | 3.3V. 125MHz. Selectable LVTTL/LVCMOS & LVPECL Inputs. Zero Delay Clock Driver w/ Programmable Divider ; 时钟IC | 3.3V 。 125MHz的。可选的LVTTL / LVCMOS与LVPECL输入。零延迟时钟驱动器瓦特/可编程分频器\n
| 型号： | PI6C2973 |
| 厂家： | 
ETC |
| 描述： | Clock IC | 3.3V. 125MHz. Selectable LVTTL/LVCMOS & LVPECL Inputs. Zero Delay Clock Driver w/ Programmable Divider
|
| 文件： | 总8页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2973
Low Voltage PLL Clock Driver
can be realized by pulsing low one clock edge prior to the
coincident edges of the Qa and Qc outputs. The Sync output will
indicate when the coincident rising edges of the above relation-
ships will occur. The Power–On Reset ensures proper program-
ming if the frequency select pins are set at power up. If the
fselFB2 pin is held high, it may be necessary to apply a reset after
power–up to ensure synchronization between the QFB output
and the other outputs. The internal power–on reset is designed
to provide this function, but with power–up conditions being
dependent, it is difficult to guarantee. All other conditions of the
fsel pins will automatically synchronize during PLL lock acquisi-
tion.
The PI6C2973 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2973 have internal
pull–up resistors.
ThePI6C2973isfully3.3Vcompatibleandrequiresnoexternal
loopfiltercomponents.AllinputsacceptLVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with
the capability to drive 50 Ohm transmission lines. For series
terminated lines each PI6C2973 output can drive two 50 Ohm
lines in parallel thus effectively doubling the fanout of the
device.
Features
• FullyIntegratedPLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• 3.3VV
CC
• + 100ps Typical Cycle–to–Cycle Jitter
• Packaging:
-52-pinLQFP
Description
ThePI6C2973are3.3Vcompatible,PLLbasedclockdriver
devices targeted for high-performance CISC or RISC processor
based systems. With output frequencies of up to 125 MHz and
skews of 550ps the PI6C2973 are ideally suited for most synchro-
nous systems. The devices offer twelve low skew outputs plus a
feedback and sync output for added flexibility and ease of
systemimplementation.
The PI6C2973 features an extensive level of frequency program-
mability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of
1:1,2:1,3:1,3:2,4:1,4:3,5:1,5:2,5:3,6:1and6:5betweenoutputs
PinConfiguration-PI6C2973
39 38 37 36 35 34 33 32 31 30 29 28 27
26
25
24
23
22
21
20
19
18
17
16
15
14
fselFB1
QSync
GNDO
Qc0
fselb1
fselb0
fsela1
fsela0
Qa3
40
41
42
43
44
45
46
47
48
49
50
51
52
VCCO
Qc1
VCCO
Qa2
fselc0
fselc1
Qc2
GNDO
Qa1
VCCO
Qc3
VCCO
Qa0
GND0
Inv_Clk
GND0
VCO_Sel
1
2
3
4
5
6
7
8
9 10 11 12 13
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PI6C2973
LowVoltagePLLClockDriver
BlockDiagram
PECL_CLK
PECL_CLK
VC0_Sel
PLL_En
REF_Sel
Sync
Frz
Q
D
Qa0
Qa1
Qa2
Qa3
0
1
0
1
TCLK0
PHASE
DETECTOR
VCO
TCLK1
TCLK_Sel
LPF
Ext_FB
Sync
Frz
Q
D
Qb0
Qb1
Qb2
Qb3
fselFB2
MR/OE
Q
D
Qc0
Qc1
POWER-ON
RESET
Sync
Frz
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
Sync
Frz
Q
Q
D
D
Qc2
Qc3
QFB
÷2, ÷4, ÷6, ÷8
2
2
0
1
fsela0:1
fselb0:1
÷4, ÷6, ÷8, ÷10
Sync Pulse
÷2
2
2
fselc0:1
fselFBO:1
Data Generator
Sync
Frz
D
QSync
Q
Frz_Clk
Output Disable
Circuitry
12
Frz_Data
Inv_Clk
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PI6C2973
LowVoltagePLLClockDriver
FunctionTable1
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1
fselc0
Qc
0
0
1
1
0
1
0
1
÷4
÷6
0
0
1
1
0
1
0
1
÷4
÷6
0
0
1
1
0
1
0
1
÷2
÷4
÷6
÷8
÷8
÷8
÷12
÷10
FunctionTable2
fselFB2
fselFB1
fselFB0
QFB
0
0
0
0
0
0
1
1
0
1
0
1
÷4
÷6
÷8
÷10
1
1
1
1
0
0
1
1
0
1
0
1
÷8
÷12
÷16
÷20
FunctionTable3
Control Pin
Logic '0'
Logic '1'
VCO_Sel
Ref_Sel
VCO/2
TCLK
VCO
PECL
TCLK_Sel
PLL_En
TCLK0
TCLK1
Bypass PLL
Master Reset/Output Hi-Z
Non-Inverted Qc2, Qc3
Enable PLL
Enable Outputs
Inverted Qc2, Qc3
MR/OE
Inv_CLK
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PI6C2973
LowVoltagePLLClockDriver
Timing Diagrams
fVCO
Qa
1:1 Mode
2:1 Mode
Qc
Sync
Qa
Qc
Sync
3:1 Mode
3:2 Mode
Qc( 2)
Qa( 6)
Sync
Qa( 4)
Qc( 6)
Sync
4:1 Mode
4:3 Mode
Qc( 2)
Qa( 8)
Sync
Qa( 6)
Qc( 8)
Sync
1:6 Mode
Qa( 12)
Qc( 2)
Sync
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PI6C2973
LowVoltagePLLClockDriver
AbsoluteMaximumRatings
Symbol
Parameter
Supply Voltage
Input Voltage
Min.
–0.3
–0.3
Max.
Units
V
V
CC
4.6
V
I
V
+0.3
V
DD
I
Input Current
±20
125
mA
°C
IN
T
Storage Temperature
–40
STOR
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute-maximum-rated conditions is not implied.
(4)
DC Characteristics (T = 0°C to 70°C, V = 3.3V ± 5%)
A
CC
Symbol
VIH
Conditions
Characteristic
Input HIGH Voltage
Input LOW Voltage
Min.
Typ.
Max.
3.6
Units
2.0
V
VIL
0.8
Peak-to Peak Input Voltage
PECL_CLK
VPP
300
1000
mV
V
Common Mode Range
PECL_CLK
VCMR
Note 1
VCC–2.0
2.4
VCC–0.6
VOH
VOL
IIN
IOH = 20mA(2)
IOL = 20mA(2)
Note 3
Output HIGH Voltage
Output LOW Voltage
0.5
±120
215
20
Input Current
µΑ
ICC
Maximum Quiescent Supply Current
Analog VCC Current
190
15
mA
ICCA
CIN
Cpd
Input Capacitance
4
pF
Per Output
Power Dissipation Capacitance
25
Notes:
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when
the “High” input is within the VCMR range and the input lies within the VPP specification.
2. The PI6C2973 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to VCC/2) transmission lines on the
incidentedge.
3. Inputs have pull–up/pull–down resistors which affect input current.
4. Special thermal handling may be required in some configurations.
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PI6C2973
LowVoltagePLLClockDriver
PLL Input Reference Characteristic (T = 0°C to 70°C)
A
Symbol
Conditions
Characteristics
Min.
Max.
Units
tr, tf
fref
TCLK Input Rise/Falls
Reference Input Frequency
Reference Input Duty Cycle
Crystal Oscillator Frequency
3.0
100, Note 5
75
ns
Note 5
Note 5
25
MHz
%
frefDC
txtal
10
25
MHz
Notes:
5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100 MHz,
minimum input reference frequency is limited by the VCO lock range and the feedback divider.
AC Characteristics (T = 0°C to 70°C, V = 3.3V ± 5%)
A
CC
Symbol
Characteristics
Conditions
Min.
Typ.
Max.
Units
tr, t
Output Rise/Fall Time (Note7)
Output Duty Cycle (Note7)
0.8 to 2.0V
0.15
1.2
ns
f
t
/2
t
/2
t
/2
CYCLE
–750
CYCLE
CYCLE
+750
t
pw
±500
TCLK0
TCLK1
PECL_CLK
–70
–130
–225
130
70
–25
330
270
175
Propagation Delay
Notes 7, 8, QFB = ÷8
ps
t
pd
t
Output-to-Output Skew
VCO Lock Range
Note 7
550
500
os
f
200
VCO
Maximum Output Frequency Q (÷2)
125
125
83.33
62.5
MHz
Q (÷4)
Q (÷6)
Q (÷8)
f
max
Note 7
tjitter
, t
Cycle–to–Cycle Jitter (Peak–to–Peak)
Output Disable Time
±100
ps
ns
t
2
2
8
PLZ PHZ
t
,t
Output ENable TIme
10
10
20
PZL PZH
t
Maximum PLL Lock Time
Maximum Frz_Clk Frequency
ms
lock
f
MHz
MAX
Notes:
7. 50 Ohm transmission line terminated into V /2
CC
8. tpd is specified for a 50 MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/
longer input reference periods. The tpd does not include jitter.
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PI6C2973
LowVoltagePLLClockDriver
Start
Bit
D0 D1 D2 D3
D4 D5
D6
D7
D8
D9 D10 D11
D0–D3 are the control bits for Qa0–Qa3, respectively
D4–D7 are the control bits for Qb0–Qb3, respectively
D8–D10 are the control bits for Qc1–Qc3, respectively
D11 is the control bit for QSync
FreezeDataInputProtocol
PackagingMechanical:52-PinLQFP
12.00 BSC
.472
Square
10.00 BSC
.394
0.09
0.20
Square
.004
.008
GAUGE PLANE
0
7
0.45
0.75
.018
.030
1.00 REF
.039
1.60
.063
Max.
.004
0.10
Seating Plane
1.35
1.45
0.05
0.15
0.65 BSC
.026
0.22
0.38
.009
.015
.053
.057
.002
.006
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
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PI6C2973
LowVoltagePLLClockDriver
OrderingInformation
Ordering Code
PI6C2973FC
Packaging Code
Packaging Type
FC
52-pin LQFP
Notes:
1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php
PericomSemiconductorCorporation
2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com
PS8685
05/27/03
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