PI74ALVCH1622601SA [ETC]
18-Bit Bus Transceiver ; 18位总线收发器\n型号: | PI74ALVCH1622601SA |
厂家: | ETC |
描述: | 18-Bit Bus Transceiver
|
文件: | 总5页 (文件大小:296K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PI74ALVCH1622601S
18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Description
Product Features
Pericom Semiconductors PI74ALVCH series of logic circuits are
producedintheCompanysadvanced0.5micronCMOStechnology,
achieving industry leading speed.
• PI74ALVCH1622601Sisdesignedforlowvoltageoperation
• V =2.3Vto3.6V
CC
• Hysteresis on all inputs
ThePI74ALVCH1622601SusesD-typelatchesand D-typeflip-flops
with 3-state outputs to allow data flow in transparent, latched, and
clocked modes.
• Typical VOLP (Output Ground Bounce)
< 0.8V at V = 3.3V, T = 25°C
CC
A
• Typical VOHV (Output VOH Undershoot)
< 2.0V at V = 3.3V, T = 25°C
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latched Enable (LEAB and LEBA), and Clock
(CLKAB and CLKBA) inputs. The clock can be controlled by the
Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B
data flow, the device operates in the transparent mode when LEAB
is HIGH. When LEAB is LOW, the A data is latched if CLKAB is
held at a high or low logic level. If LEAB is low, the A-bus is stored
in the latch/flip-flop on the low-to-high transition of CLKAB.
When OEAB is low, the outputs are active. When OEAB is HIGH,
the outputs are in the high-impedance state.
CC
A
• Inputs/Outputs have equivalent 26Ω series resistors,
no external resistors are required.
• Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
56-pin 240 mil wide plastic TSSOP (A56)
56-pin 300 mil wide plastic SSOP (V56)
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, CLKBA, and CLKENBA.
To reduce overshoot and undershoot, the inputs/outputs include
26Ω series resistors.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH1622601S has Bus Hold which retains the data
inputs last state whenever the data input goes to high-impedance
preventing floating inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
1D
C1
3
A1
54
B1
CLK
CE
1D
C1
CLK
To 17 Other Channels
05/11/98
1
PI74ALVCH1622601S
18-BIT UNIVERSAL BUS TRANSCEIVER
Truth Table(1)
Product Pin Description
Inputs
Pin Name
CLKEN
OE
Description
Output
B
CLKENAB OEAB LEAB CLKAB
A
X
L
Clock Enable Input (Active LOW)
Output Enable Input (Active LOW)
Latch Enable (Active HIGH)
Clock Input (Active HIGH)
Data I/O
X
X
X
H
H
L
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
L
X
X
S
Z
L
LE
H
X
X
L
H
CLK
Ax
X
X
L
B0
B0
L
Bx
Data I/O
GND
VCC
Ground
L
H
X
X
H
Power
L
B0
B0§
L
H
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
Product Pin Configuration
↑ = LOW-to-HIGH Transition
A-to-B data flow is shown:
B-to-A flow is similar but uses OEBA, LEBA,
CLKBA, and CLKENBA.
Output level before the indicated steady-state input
conditions were established.
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
LOW before LEAB goes LOW.
OEAB
LEAB
A1
CLKENAB
CLKAB
B1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
3
GND
A2
GND
B2
4
5
A3
B3
6
56-PIN
A-56
V-56
V
V
7
CC
CC
A4
A5
B4
8
B5
9
A6
B6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
A7
GND
B7
A8
B8
A9
B9
A10
A11
A12
GND
A13
A14
A15
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
V
CC
A16
A17
GND
A18
OEBA
LEBA
05/11/98
2
PI74ALVCH1622601S
18-BIT UNIVERSAL BUS TRANSCEIVER
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................. 65°C to +150°C
Ambient Temperature with Power Applied ................. 40°C to +85°C
Input Voltage Range, VIN ..................................... 0.5V to V +0.5V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
CC
Output Voltage Range, VOUT ............................... 0.5V to V +0.5V
CC
DC Input Voltage .......................................................... 0.5V to +5.0V
DC Output Current ......................................................................100mA
Power Dissipation ..........................................................................1.0W
Recommended Operating Conditions(1)
Parameters
Description
Test Conditions
Min.
2.3
Typ.
Max. Units
V
CC
Supply Voltage
3.6
V
= 2.3V to 2.7V
= 2.7V to 3.6V
= 2.3V to 2.7V
= 2.7V to 3.6V
1.7
CC
V
Input HIGH Voltage
Input LOW Voltage
IH
V
CC
2.0
V
CC
0.7
0.8
V
V
IL
V
CC
V
Input Voltage
0
0
V
CC
IN
V
OUT
Output Voltage
V
CC
V
= 2.3V
= 2.7V
= 3.0V
= 2.3V
= 2.7V
= 3.0V
-6
CC
I
OH
High-level Output Current
Low-level Output Current
V
CC
-8
-12
6
V
CC
mA
°C
V
CC
I
V
CC
8
OL
V
CC
12
85
T
Operating Free-Air Temperature
-40
A
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
05/11/98
3
PI74ALVCH1622601S
18-BIT UNIVERSAL BUS TRANSCEIVER
DCElectricalCharacteristics(OvertheOperatingRange, TA =40°Cto+85°C,VCC =3.3V±10%)
(1)
(2)
Parameters
Test Conditions
V
CC
Min.
V -0.2
CC
Typ.
Max. Units
I
= -100 mA
= -4 mA
Min. to Max.
2.3V
OH
I
OH
V
= 1.7V
= 1.7V
= 2.0V
= 2.0V
= 2.0V
1.9
IH
V
2.3V
1.7
2.4
2.0
2.0
IH
V
OH
I
OH
= -6 mA
V
3.0V
IH
I
OH
= -8 mA
= -12 mA
= 100 mA
= 4 mA
V
2.7V
IH
I
OH
V
3.0V
IH
V
I
OL
Min. to Max.
2.3V
V
CC
-0.2
0.2
I
OL
V
= 0.7V
= 0.7V
= 0.8V
= 0.8V
= 0.8V
0.4
0.55
0.55
0.6
IL
V
2.3V
IL
V
OL
I
OL
= 6 mA
V
IL
3.0V
I
OL
= 8 mA
V
IL
2.7V
I
OL
= 12 mA
V
IL
3.0V
0.8
I
I
V = V or GND
3.6V
±5
I
CC
V = 0.7V
45
-45
75
I
2.3V
3.0V
V = 1.7V
I
(3)
I (Hold)
I
V = 0.8V
I
V = 2.0V
I
-75
mA
V = 0 to 3.6V
3.6V
3.6V
3.6V
±500
±10
40
I
(4)
I
OZ
V = V or GND
O CC
I
CC
V = V or GND
I = 0
O
I
CC
DI
CC
One input at V -0.6V, other inputs at V or GND 3V to 3.6V
750
CC
CC
C Control Inputs V = V or GND
3.3V
3.3V
4
8
I
I
CC
pF
C
A or B ports V = V or GND
O CC
IO
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2.TypicalvaluesareatV =3.3V,+25°Cambientandmaximumloading.
CC
3. Bus Hold maximum dynamic current required to switch the input from one state to another.
4. For I/O ports, the I includes the input leakage current.
OZ
OperatingCharacteristics,TA =25°C
Vcc = 2.5V ± 0.2V Vcc = 3.3V ± 0.3V
Test
Parameter
Units
Conditions
Typical
Typical
Outputs Enabled
41
6
50
6
C
Power Dissipation
Capacitance
C = 50pF,
F = 10 MHz
PD
L
pF
Outputs Disabled
05/11/98
4
PI74ALVCH1622601S
18-BIT UNIVERSAL BUS TRANSCEIVER
TimingRequirementsoverOperatingRange
V
= 2.5V ± 0.2V
V
= 2.7V
V
= 3.3V ± 0.3V
CC
CC
CC
Parameters
Description
Units
Min.
0
Max.
Min.
0
Max.
150
Min.
0
Max.
f
Clock frequency
140
150
MHz
CLOCK
LE high
3.3
3.3
2.3
2.0
1.3
2.0
0.7
1.3
1.7
0.3
0
3.3
3.3
2.4
1.6
1.2
2.0
0.7
1.6
2.0
0.5
0
3.3
3.3
2.1
1.6
1.1
1.7
0.8
1.4
1.7
0.6
0
t
Pulse
W
Duration
CLK high or low
Data before CLK high
Data before LE low, CLK high
Data before LE low, CLK low
CLKEN before CLK high
Data after CLK high
t
SU
Setup
time
ns
Data after LE low, CLK high
Data after LE low, CLK low
CLKEN after CLK high
Input Transition Rise or Fall
t Hold
H
time
(1)
Dt/Dv
10
10
10
ns/V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
SwitchingCharacteristicsoverOperatingRange(1)
V
= 2.5V ± 0.2V
V
= 2.7V
V = 3.3V ± 0.3V
CC
CC
CC
From
To
Parameters
Units
(INPUT) (OUTPUT)
(2)
(2)
(2)
Min.
Max.
Min.
Max.
Min.
Max.
f
140
1.8
1.8
1.5
1.5
2
150
150
1.6
1.6
1.5
1.5
1.6
1.6
1.6
1.8
1.6
1.8
MHz
MAX
t
PD
A
B
A
B
A
B
A
B
B
A
A
5.4
5.4
6.1
6.1
6.7
6.7
6.6
5.9
6.6
5.9
5.2
5.2
5.9
5.9
6.3
6.3
6.7
5.3
6.7
5.3
4.5
4.5
5.1
5.1
5.5
5.5
5.7
4.8
5.7
4.8
t
PD
B
t
PD
LEAB
LEBA
CLKAB
CLKBA
OEAB
OEAB
OEBA
OEBA
t
PD
t
PD
ns
t
PD
1.2
1.7
2.5
1.7
2.5
t
EN
t
DIS
t
EN
t
DIS
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Pericom Semiconductor Corporation
2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com
05/11/98
5
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