PI74ALVCH16601 [ETC]

Logic | 18-Bit Universal Bus Transceiver ; 逻辑| 18位通用总线收发器\n
PI74ALVCH16601
型号: PI74ALVCH16601
厂家: ETC    ETC
描述:

Logic | 18-Bit Universal Bus Transceiver
逻辑| 18位通用总线收发器\n

总线收发器
文件: 总5页 (文件大小:259K)
中文:  中文翻译
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PI74ALVCH16601  
18-Bit Universal Bus Transceiver  
With 3-State Outputs  
Product Description  
Product Features  
PericomSemiconductor’sPI74ALVCHseriesoflogic  
circuits are produced using the Company’s advanced  
0.5 micron CMOS technology, achieving industry  
leading speed.  
CC  
OLP  
CC  
The PI74ALVCH16601 uses D-type latches and D-  
type flip-flops with 3-state outputs to allow data flow  
in transparent, latched, and clocked modes.  
A
A
OHV  
CC  
OH  
Data flow in each direction is controlled by Output  
Enable (OEAB and OEBA), Latched Enable (LEAB  
and LEBA), and Clock (CLKAB and CLKBA) inputs.  
The clock can be controlled by the Clock Enable  
(CLKENAB and CLKENBA) inputs. For A-to-B data  
flow, thedeviceoperatesinthetransparentmodewhen  
LEAB is HIGH. When LEAB is LOW, the A data is  
latched if CLKAB is held at a high or low logic level.  
IfLEABislow,theA-busisstoredinthelatch/flip-flop  
onthelow-to-hightransitionofCLKAB. WhenOEAB  
islow,theoutputsareactive.WhenOEABisHIGH,the  
outputs are in the high-impedance state.  
Logic Block Diagram  
Data flow for B to A is similar to that of A to B but uses  
OEBA,LEBA,CLKBA,andCLKENBA.  
To ensure the high-impedance state during power up  
orpowerdown,OEshouldbetiedtoVCC throughapull-  
up resistor; the minimum value of the resistor is  
determined by the current-sinking capability of the  
driver.  
The PI74ALVCH16601 has “Bus Hold” which retains  
the data input’s last state whenever the data input goes  
to high-impedance preventing “floating” inputs and  
eliminating the need for pullup/down resistors.  
PS8134A  
02/23/98  
1
PI74ALVCH16601  
18-Bit Universal Bus Transceiver  
TruthTable(1)†  
ProductPinDescription  
PinName  
Description  
Inputs  
Output B  
CLKENAB OEAB LEAB CLKAB  
A
X
L
X
X
X
H
H
L
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
L
X
X
X
X
X
Z
L
H
X
X
L
H
B ‡  
0
B ‡  
0
CC  
L
L
H
X
X
H
L
L
B ‡  
0
L
H
B §  
0
Product Pin Configuration  
Notes:  
1. H=HighSignalLevel  
L=LowSignalLevel  
Z = High Impedance  
CLKENAB  
CLKAB  
B1  
OEAB  
LEAB  
A1  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2
=LOW-to-HIGHTransition  
3
GND  
B2  
GND  
A2  
4
† A-to-B data flow is shown: B-to-A flow is similar but  
usesOEBA,LEBA,CLKBA,andCLKENBA.  
‡ Output level before the indicated steady-state input  
conditions were established.  
§ Output level before the indicated steady-state input  
conditions were established, provided that CLKAB is  
HIGH before LEAB goes LOW.  
5
B3  
A3  
6
V
CC  
V
CC  
7
B4  
A4  
A5  
8
B5  
9
B6  
A6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
B7  
GND  
A7  
B8  
A8  
B9  
A9  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
VCC  
B16  
B17  
GND  
B18  
CLKBA  
CLKENBA  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
56-PIN  
A-56  
V-56  
V
CC  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
PS8134A 02/23/98  
2
PI74ALVCH16601  
18-Bit Universal Bus Transceiver  
MaximumRatings  
(Above which the useful life may be impaired. For user guidelines, not tested.)  
Note:  
CC  
CC  
IN  
OUT  
RecommendedOperatingConditions(1)  
Parameters  
Description  
Test Conditions  
Min. Typ. Max. Units  
V
Supply Voltage  
2.3  
1.7  
2.0  
3.6  
CC  
V
= 2.3V to 2.7V  
= 2.7V to 3.6V  
= 2.3V to 2.7V  
= 2.7V to 3.6V  
CC  
V
Input HIGH Voltage  
Input LOW Voltage  
IH  
V
CC  
V
CC  
0.7  
0.8  
V
V
IL  
V
CC  
V
Input Voltage  
0
0
V
CC  
IN  
V
OUT  
Output Voltage  
V
CC  
V
= 2.3V  
= 2.7V  
= 3.0V  
= 2.3V  
= 2.7V  
= 3.0V  
-12  
CC  
I
High-level Output Current  
Low-level Output Current  
V
CC  
-12  
-24  
12  
OH  
V
CC  
mA  
°C  
V
CC  
I
V
CC  
12  
OL  
V
CC  
24  
T
A
Operating Free-Air Temperature  
-40  
85  
Note: Unused control inputs must be held HIGH or LOW to prevent them from floating.  
PS8134A 02/23/98  
3
PI74ALVCH16601  
18-Bit Universal Bus Transceiver  
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)  
(1)  
CC  
(2)  
Parameters  
Test Conditions  
V
Min.  
-0.2  
Typ.  
Max. Units  
Min. to  
Max.  
I
OH  
= -100µA  
V
V
CC  
I
= -6mA  
V
= 1.7V  
= 1.7V  
= 2.0V  
= 2.0V  
= 2.0V  
2.3V  
2.3V  
2.7V  
3.0V  
3.0V  
2.0  
OH  
IH  
V
IH  
1.7  
2.2  
2.4  
2.0  
V
OH  
I
OH  
= -12mA  
V
IH  
V
IH  
I
OH  
= -24mA  
= -100µA  
= 6mA  
V
IH  
Min. to  
Max.  
I
OH  
V
-0.2  
0.2  
CC  
I
OH  
V
IH  
= 0.7V  
= 0.7V  
= 0.8V  
= 0.8V  
2.3V  
2.3V  
2.7V  
3.0V  
3.6V  
0.4  
0.7  
0.4  
0.55  
±5  
V
OL  
V
IH  
I
OH  
= 12mA  
= 24mA  
V
IH  
I
OH  
V
IH  
I
V = V or GND  
I CC  
I
V = 0.7V  
45  
-45  
75  
I
2.3V  
3.0V  
V = 1.7V  
I
(3)  
I (Hold)  
I
V = 0.8V  
I
V = 2.0V  
I
-75  
µA  
V = 0 to 3.6V  
3.6V  
3.6V  
3.6V  
±500  
±10  
40  
I
(4)  
I
OZ  
V = V or GND  
O CC  
I
CC  
V = V or GND  
I = 0  
O
I
CC  
One input at V -0.6V, Other inputs at V or GND 3V to 3.6V  
750  
I  
CC  
CC  
CC  
C Control Inputs V = V or GND  
3.3V  
3.3V  
4
8
I
I
CC  
pF  
C
A or B ports V = V or GND  
O CC  
IO  
Notes:  
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.  
2.TypicalvaluesareatV =3.3V,+25°Cambientandmaximumloading.  
CC  
3. Bus Hold maximum dynamic current required to switch the input from one state to another.  
4. For I/O ports, the I includes the input leakage current.  
OZ  
PS8134A 02/23/98  
4
PI74ALVCH16601  
18-Bit Universal Bus Transceiver  
Timing Requirements over Operating Range  
V
CC  
= 2.5V ± 0.2V  
V
= 2.7V  
V
= 3.3V ± 0.3V  
CC  
CC  
Parameters  
Description  
Clock frequency  
Units  
Min.  
0
Max.  
Min.  
0
Max.  
150  
Min.  
0
Max.  
f
150  
150  
MHz  
CLOCK  
LE high  
3.3  
3.3  
2.3  
2.0  
1.3  
2.0  
0.7  
1.3  
1.7  
0.3  
0
3.3  
3.3  
2.4  
1.6  
1.2  
2.0  
0.7  
1.6  
2.0  
0.5  
0
3.3  
3.3  
2.1  
1.6  
1.1  
1.7  
0.8  
1.4  
1.7  
0.6  
0
t
Pulse  
W
Duration  
CLK high or low  
Data before CLK high  
Data before LE low, CLK high  
Data before LE low, CLK low  
CLKEN before CLK high  
Data after CLK high  
t
SU  
Setup  
time  
ns  
Data after LE low, CLK high  
Data after LE low, CLK low  
CLKEN after CLK high  
Input Transition Rise or Fall  
t
Hold  
time  
H
10  
10  
10  
ns/V  
t/v(1)  
Note: Unused control inputs must be held HIGH or LOW to prevent them from floating.  
SwitchingCharacteristicsoverOperatingRange(1)  
V
CC  
= 2.5V ±0.2V  
V
CC  
= 2.7V  
V = 3.3 V ± 0.3V  
CC  
From  
To  
(2)  
(2)  
(2)  
(INPUT)  
(OUTPUT)  
Parameters  
Min.  
Max.  
Min.  
150  
Max. Min.  
Max.  
Units  
f
150  
1.3  
150  
1
MHz  
MAX  
t
PD  
A or B  
B or A  
A or B  
4.9  
5.6  
4.6  
5.3  
4.1  
4.7  
LEBA or  
LEBA  
t
PD  
1.2  
1.7  
1.2  
2.1  
1
CLKAB or  
CLKBA  
t
PD  
6.2  
6.1  
5.4  
5.8  
6.1  
4.8  
1.4  
1.1  
1.6  
5
ns  
OEAB or  
OEBA  
t
EN  
5.2  
4.4  
OEAB or  
OEBA  
t
DIS  
Notes:  
1. See test circuit and waveforms.  
2. Minimum limits are guaranteed but not tested on Propagation Delays.  
OperatingCharacteristics,T =25ºC  
A
V
CC  
= 2.5V ± 0.2V  
V
CC  
= 3.3V ± 0.3V  
Parameter  
Test Conditions  
Units  
Typical  
Outputs Enabled  
41  
6
52  
6
C
Power Dissipation  
Capacitance  
C = 50pF,  
f = 10 MHz  
PD  
L
pF  
Outputs Disabled  
Pericom Semiconductor Corporation  
2380BeringDrive • SanJose,CA951311-800-435-2336 • Fax(408)435-1100http://www.pericom.com  
PS8134A 02/23/98  
5

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