PI74ALVCH32374NB [ETC]
FLIP-FLOP|32-BIT|D TYPE|AVC/ALVC-CMOS|BGA|96PIN|PLASTIC ; 触发器| 32位| D型| AVC / ALVC -CMOS | BGA | 96PIN |塑料\n
| 型号： | PI74ALVCH32374NB |
| 厂家： | 
ETC |
| 描述： | FLIP-FLOP|32-BIT|D TYPE|AVC/ALVC-CMOS|BGA|96PIN|PLASTIC
|
| 文件： | 总7页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
Product Features
ProductDescription
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
• PI74ALVCH32374 is designed for low voltage operation
• V = 2.3V to 3.6V
CC
• Typical V
(Output Ground Bounce)
OLP
This 32-bit edge-triggered D-type flip-flop is designed for 2.3V to
< 0.8V at V = 3.3V, T = 25°C
CC
A
3.6V V operation.
CC
• Typical V
(Output V Undershoot)
OH
OHV
The PI74ALVCH32374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as four 8-bit flip-flops or two
16-bitflip-flopsorone32-Bitflip-flop.Onthepositivetransitionof
theClock(CLK)input,theQoutputsoftheflip-floptakeonthelogic
levelssetupatthedata(D)inputs. OEcanbeusedtoplacetheeight
outputs in either a normal logic state (high or low logic levels) or a
high-impedance state. In that state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and the
increased drive provide the capability to drive bus lines without
needforinterfaceorpullupcomponents.OEdoesnotaffectinternal
operationsoftheflip-flop. Olddatacanberetainedornewdatacan
be entered while the outputs are in the high-impedance state.
> 2.0V atV = 3.3V, T = 25°C
CC
A
• Bus Hold retains last active bus state during 3-State
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine
pitch ball grid array, LFBGA(NB)
To ensure the high-impedance state during power up or power
down, OE should be tied to V through a pullup resistor; the
CC
minimumvalue of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
LogicBlockDiagram
H3
A3
2OE
1OE
H4
E5
A4
2CLK
2D1
1CLK
C1
C1
E2
A2
2Q1
1Q1
A5
1D
1D1
1D
To Seven Other Channels
To Seven Other Channels
T3
T4
J3
J4
4OE
3OE
4CLK
3CLK
C1
1D
C1
1D
N2
J2
4Q1
3Q1
N5
J5
4D1
3D1
To Seven Other Channels
To Seven Other Channels
PS8439
10/14/99
1
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
Product Pin Description
Truth Table(1)
Pin Name
OE
Description
Inputs
CLK
Outputs
Output Enable Input (Active LOW)
Clock Input (Active HIGH)
Data Inputs
OE
D
H
L
Q
H
L
CLK
Dx
L
L
Qx
3-State Outputs
Ground
L
H
H or L
X
X
X
Q
0
GND
Z
V
CC
Power
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
NB Package (Top View)
Z = High Impedance
↑ = LOW to HIGH Transition
n = 1,2
6
5
4
3
2
1
A
B C
D
E
F
G
H J
K
L
M N P R T
TerminalAssignments
6
5
4
3
2
1
1D2
1D1
1CLK
1OE
1Q1
1Q2
A
1D4
1D3
GND
GND
1Q3
1Q4
B
1D6
1D5
VCC
VCC
1Q5
1Q6
C
1D8
2D2
2D1
2D4
2D3
VCC
VCC
2Q3
2Q4
F
2D6
2D5
2D7
2D8
3D2
3D1
3D4
3D3
GND
GND
3Q3
3Q4
K
3D6
3D5
VCC
VCC
3Q5
3Q6
L
3D8
3D7
GND
GND
3Q7
3Q8
M
4D2
4D1
GND
GND
4Q1
4Q2
N
4D4
4D3
VCC
VCC
4Q3
4Q4
P
4D6
4D5
4D7
4D8
1D7
GND
GND
1Q7
1Q8
D
GND
GND
2Q1
2Q2
E
GND 2CLK 3CLK
GND 4CLK
GND
2Q5
2Q6
G
2OE
2Q8
2Q7
H
3OE
3Q1
3Q2
J
GND
4Q5
4Q6
R
4OE
4Q8
4Q7
T
PS8439
10/14/99
2
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range,V
...............................................................0.5V to 4.6V
CC
Note:
(1)
Input Voltage Range, V : Except I/O ports
..............................0.5V to 4.6V
........................... 0.5V to V + 0.5V
CC
I
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
(1,2)
I/O ports
(1,2)
Output Voltage Range, V
............................................ 0.5V to V +0.5V
CC
O
Input Clamp Current, I (V <0) ........................................................ 50mA
IK
I
Output Clamp Current, I (V <0) .................................................. 50mA
OK
O
Continuous Output Current, I ................................................................... ±50mA
O
Continuous Current through each V or GND ............................... ±100mA
CC
(3)
PackageThermalImpedance,θ
Storage Temperature Range, T
............................................................. 40ºC/W
............................................... 65ºC to 150ºC
JA
STG
Note:
1. The input negative voltage and output voltage ratings may be exceeded
if the input and output current ratings are observed.
2. Thisvalueislimitedto4.6Vmaximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
RecommendedOperatingConditions(1)
Parameters
Description
Test Conditions
Min.
2.3
Typ.
Max.
Units
V
CC
Supply Voltage
3.6
V
V
= 2.3V to 2.7V
= 2.7V to 3.6V
= 2.3V to 2.7V
= 2.7V to 3.6V
1.7
CC
V
Input HIGH Voltage
Input LOW Voltage
IH
V
CC
2.0
V
CC
0.7
0.8
V
IL
V
CC
V
Input Voltage
0
0
V
CC
IN
V
OUT
Output Voltage
V
CC
V
= 2.3V
= 2.7V
= 3.0V
= 2.3V
= 2.7V
= 3.0V
12
12
24
12
mA
CC
Output
HIGH
Current
I
OH
V
CC
V
CC
V
CC
Output
LOW
Current
I
OL
V
CC
12
V
CC
24
∆t/∆V
Input Transition Rise or Fall Rate
Operating Free-Air Temperature
0
10
ns/V
°C
T
A
40
85
Note 1: All unused inputs must be held at V or GND to ensure proper device operation
CC
PS8439
10/14/99
3
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
DCElectricalCharacteristics(OvertheOperatingRange,T =40°Cto+85°C,V =3.3V±10%)
A
CC
(1)
(2)
Parameters Description
Test Conditions
Min.
0.2
Typ.
Max.
Units
I
OH
= -100µA, V = Min. to Max.
V
CC
CC-
V
= 1.7V, I = -6mA V
CC =
2.3V
2.3V
2.7V
2.0
IH
OH
,
V
IH
= 1.7V, I = -12mA V
1.7
2.2
2.4
2.0
OH
,
CC =
CC =
V
OH
Output HIGH Voltage
V
IH
= 2.0V, I = -12mA V
OH ,
V
IH
= 2.0V, I = -12mA V =3.0V
OH , CC
V
IH
= 2.0V, I = -24mA V =3.0V
OH , CC
V
I
= -100µA, V = Min. to Max.
0.2
0.4
0.7
0.4
0.55
±5
OL
IL
V
= 0.7V, I = 6mA V
CC =
2.3V
2.3V
2.7V
IL
OL
,
V
Output LOW Voltage
Input Current
V = 0.7V, I = 12mA V
IL OL ,
OL
CC =
CC =
V
IL
= 0.8V, I = 12mA V
OL ,
V
IL
= 0.8V, I = 24mA V =3.0V
OL , CC
I
IN
V
= V or GND, V = 3.6V
IN CC CC
V
= 0.7V, V = 2.3V
45
45
75
IN
CC
V
IN
= 1.7V, V = 2.3V
CC
Input Hold
Current
I
IN
(
HOLD
)
V
= 0.8V, V = 3.0V
IN CC
V
IN
= 2.0V, V = 3.0V
75
CC
(3)
µA
V
= 0 to 3.6V, V = 3.6V
±500
±10
IN
CC
I
Output Current (3-State Outputs)
Supply Current
V
= V or GND, V = 3.6V
OZ
OUT CC CC
V
= 3.6V, I
= 0µA,
CC
CC
V
OUT
I
CC
40
= GND or V
IN
V
= 3.0V to 3.6V
CC
Supply Current per Input
@ TTL HIGH
∆I
CC
One Input at V - 0.6V
Other Inputs at V or GND
750
CC
CC
Control Inputs
Data Inputs
Outputs
3
6
7
C
V
= V or GND, V = 3.3V
I
IN CC CC
pF
C
V = V or GND, V = 3.3V
O CC CC
O
Notes:
1. For Min. or Max conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. TypicalvaluesareatV =3.3V, +25°Cambientandmaximumloading.
CC
3. This is the bushold maximum dynamic current. It is the mimum overdrive current necessary to switch the input from one
state to another.
PS8439
10/14/99
4
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
TimingRequirementsoverOperatingRange
V
= 2.5V ±0.2V
V
= 2.7V
V
CC
= 3.3V ±0.3V
Units
CC
CC
Parameters
Description
Min.
Max.
Min.
Max.
Min.
Max.
f
Clock Frequency
0
150
0
150
0
150
MHz
CLOCK
Pulse Duration
CLK HIGH or
LOW
t
W
3.3
3.3
3.3
Setup Time Data
Before CLK↑
ns
t
2.1
0.6
2.2
0.5
1.9
0.5
SU
Hold Time Data
After CLK↑
t
H
Switching Characteristics over Operating Range(1)
V
= 2.5V
±0.2V
V
= 3.3V
CC
±0.3V
CC
V
= 2.7V
CC
Parameters
From (INPUT)
To (OUTPUT)
Units
(2)
(2)
Min.
Max.
Min.
Max. Min.
Max.
f
150
1.0
1.0
1.0
150
150
1.0
1.0
1.0
MHz
MAX
t
PD
CLK
OE
5.3
6.2
5.3
4.9
5.9
4.7
4.2
4.8
4.3
t
EN
Q
ns
t
OE
DIS
Notes:
1. See test circuit and waveforms, Figures 1 and 2.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, T = 25ºC
A
V
CC
= 2.5V ±0.2V
V
CC
= 3.3V ±0.3V
Parameter
Test Conditions
Units
Typ.
Outputs Enabled
62
32
60
36
C
Power Dissipation
Capacitance
PD
C = 50pF, f = 10 MHz
L
pF
Outputs Disabled
PS8439
10/14/99
5
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ±0.2V
2 x VCC
S1
Open
GND
500Ω
From Output
Under Test
Test
S1
CL = 30pF
tpd
tPLZ/tPZH
tPHZ/tPZH
Open
2 x VCC
GND
500Ω
(See Note A)
LoadCircuit
VoltageWaveforms
PulseDuration
VCC
VoltageWaveforms
SetupandHoldTimes
Output
Control
(Low Level
Enabling)
VCC/2
VCC/2
tPLZ
0V
tPZL
VCC
0V
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
VCC
VCC/2
tPLH
VCC/2
tPHL
Input
VCC/2
VOL +0.15V
tPHZ
VOL
VOH
tPZH
Output
Waveform 2
S1 at GND
V
OH
OL
VOH –0.15V
/2
V
VCC/2
VCC/2
CC
Output
V
0V
(see Note B)
VoltageWaveforms
PropagationDelayTimes
VoltageWaveforms
Enable and Disable Times
Figure1.LoadCircuitandVoltageWaveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
PS8439
10/14/99
6
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7V and 3.3V ±0.3V
6V
S1
Open
GND
500Ω
From Output
Under Test
Test
S1
CL = 50pF
tpd
tPLZ/tPZH
tPHZ/tPZH
Open
6V
GND
500Ω
(See Note A)
LoadCircuit
VoltageWaveforms
PulseDuration
2.7V
Output
Control
(Low Level
Enabling)
VoltageWaveforms
SetupandHoldTimes
1.5V
1.5V
1.5V
0V
3V
tPZL
tPLZ
Output
Waveform 1
S1 at 6V
2.7V
0V
1.5V
tPHL
1.5V
tPLH
Input
VOL +0.3V
tPHZ
VOL
VOH
(see Note B)
tPZH
Output
Waveform 2
S1 at GND
VOH –0.3V
V
OH
OL
1.5V
1.5V
1.5V
Output
0V
(see Note B)
V
VoltageWaveforms
PropagationDelayTimes
VoltageWaveforms
Enable and Disable Times
Figure2.LoadCircuitandVoltageWaveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Pericom Semiconductor Corporation
2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com
PS8439
10/14/99
7
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