PIC16C63AT-20E/SOXXX [ETC]
8-Bit Microcontroller ; 8位微控制器\n
| 型号： | PIC16C63AT-20E/SOXXX |
| 厂家： | 
ETC |
| 描述： | 8-Bit Microcontroller
|
| 文件： | 总184页 (文件大小：2122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C63A/65B/73B/74B
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
PIC16C7X Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• PIC16C63A
• PIC16C65B
• PIC16C73B
• PIC16C74B
• Timer1: 16-bit timer/counter with prescaler
can be incremented during SLEEP via external
crystal/clock
PIC16CXX Microcontroller Core Features:
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• High performance RISC CPU
• Only 35 single word instructions to learn
• Capture, Compare, PWM modules
• All single cycle instructions except for program
branches which are two cycle
- Capture is 16-bit, max. resolution is 200 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 8-bit multichannel Analog-to-Digital converter
• 4 K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
• Synchronous Serial Port (SSP) with SPITM
and I2CTM
• Interrupt capability
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Parallel Slave Port (PSP), 8-bits wide with
external RD, WR and CS controls
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out detection circuitry for Brown-out Reset
(BOR)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Pin Diagram:
• Programmable code protection
• Power-saving SLEEP mode
• Selectable oscillator options
PDIP, Windowed CERDIP
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
MCLR/VPP
RA0/AN0
RB7
2
RB6
• Low power, high speed CMOS EPROM
technology
3
RB5
RA1/AN1
4
RB4
RA2/AN2
5
RB3
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
6
RB2
7
RB1
8
RB0/INT
VDD
9
• Commercial, Industrial and Automotive
temperature ranges
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
VSS
• Low power consumption:
- < 5 mA @ 5V, 4 MHz
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
- 23 µA typical @ 3V, 32 kHz
- < 1.2 µA typical standby current
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
I/O
A/D
Devices
PSP
Interrupts
Pins Chan.
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
22
33
22
33
-
-
No
Yes
No
10
11
11
12
5
8
Yes
2000 Microchip Technology Inc.
DS30605C-page 1
PIC16C63A/65B/73B/74B
SDIP, SOIC, Windowed CERDIP
• 1
MCLR/VPP
RA0/AN0
RA1/AN1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
2
3
4
5
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
6
7
8
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
9
10
11
12
13
14
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
PLCC
MQFP
TQFP
RB3
39
38
37
36
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
7
8
9
10
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
NC
RB2
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
RB1
RB0/INT
VDD
PIC16C65B
PIC16C74B
35
34
11
12
13
14
15
16
17
PIC16C65B
VSS
VDD
33
32
31
30
29
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
PIC16C74B 27
VSS
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
VDD
26
25
24
23
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RB0/INT
RB1
10
11
RB2
RB3
Key Features
PICmicro™ Mid-Range MCU Family
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
Reference Manual (DS33023)
Program Memory (EPROM) x 14
Data Memory (Bytes) x 8
Pins
4 K
192
28
—
2
4 K
192
40
Yes
2
4 K
192
28
—
2
4 K
192
40
Yes
2
Parallel Slave Port
Capture/Compare/PWM Modules
Timer Modules
3
3
3
3
A/D Channels
—
—
5
8
2
2
2
2
Serial Communication
In-Circuit Serial Programming
Brown-out Reset
SPI/I C, USART
SPI/I C, USART
SPI/I C, USART
SPI/I C, USART
Yes
Yes
10
Yes
Yes
11
Yes
Yes
11
Yes
Yes
12
Interrupt Sources
Packages
28-pin SDIP, SOIC,
SSOP,
Windowed CERDIP
40-pin PDIP;
44-pin PLCC,
MQFP, TQFP,
28-pin SDIP, SOIC,
SSOP,
Windowed CERDIP
40-pin PDIP;
44-pin PLCC,
MQFP, TQFP,
Windowed CERDIP
Windowed CERDIP
DS30605C-page 2
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16C63A/65B/73B/74B Device Varieties ................................................................................................................................. 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I/O Ports ..................................................................................................................................................................................... 29
6.0 Timer0 Module ........................................................................................................................................................................... 39
7.0 Timer1 Module ........................................................................................................................................................................... 43
8.0 Timer2 Module ........................................................................................................................................................................... 47
9.0 Capture/Compare/PWM Modules .............................................................................................................................................. 49
10.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 55
11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................ 65
12.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 79
13.0 Special Features of the CPU...................................................................................................................................................... 85
14.0 Instruction Set Summary............................................................................................................................................................ 99
15.0 Development Support............................................................................................................................................................... 107
16.0 Electrical Characteristics.......................................................................................................................................................... 113
17.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 139
18.0 Packaging Information.............................................................................................................................................................. 153
Appendix A: Revision History ........................................................................................................................................................ 165
Appendix B: Device Differences..................................................................................................................................................... 165
Appendix C: Device Migrations - PIC16C63/65A/73A/74A → PIC16C63A/65B/73B/74B ............................................................. 166
Appendix D: Migration from Baseline to Mid-Range Devices......................................................................................................... 168
On-Line Support................................................................................................................................................................................. 175
Reader Response.............................................................................................................................................................................. 176
Product Identification System ............................................................................................................................................................ 177
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2000 Microchip Technology Inc.
DS30605C-page 3
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 4
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
A highly reliable Watchdog Timer (WDT), with its own
on-chip RC oscillator, provides protection against soft-
ware lockup, and also provides one way of waking the
device from SLEEP.
1.0
GENERAL DESCRIPTION
The PIC16C63A/65B/73B/74B devices are low cost,
high performance, CMOS, fully-static, 8-bit micro-
controllers in the PIC16CXX mid-range family.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost effective One-Time-
Programmable (OTP) version is suitable for production
in any volume.
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller
family has enhanced core features, eight-level deep
stack and multiple internal and external interrupt
sources. The separate instruction and data buses of
the Harvard architecture allow a 14-bit wide instruction
word with the separate 8-bit wide data. The two stage
instruction pipeline allows all instructions to execute in
a single cycle, except for program branches, which
require two cycles. A total of 35 instructions (reduced
instruction set) are available. Additionally, a large reg-
ister set gives some of the architectural innovations
used to achieve a very high performance.
The PIC16C63A/65B/73B/74B devices fit nicely in
many applications ranging from security and remote
sensors to appliance control and automotive. The
EPROM technology makes customization of applica-
tion programs (transmitter codes, motor speeds,
receiver frequencies, etc.) extremely fast and con-
venient. The small footprint packages make this micro-
controller series perfect for all applications with space
limitations. Low cost, low power, high performance,
ease of use and I/O flexibility make the PIC16C63A/
65B/73B/74B devices very versatile, even in areas
where no microcontroller use has been considered
before (e.g., timer functions, serial communication,
capture and compare, PWM functions and coprocessor
applications).
The PIC16C63A/73B devices have 22 I/O pins. The
PIC16C65B/74B devices have 33 I/O pins. Each
device has 192 bytes of RAM. In addition, several
peripheral features are available, including: three timer/
counters, two Capture/Compare/PWM modules, and
two serial ports. The Synchronous Serial Port (SSP)
can be configured as either a 3-wire Serial Peripheral
Interface (SPI) or the two-wire Inter-Integrated Circuit
(I2C) bus. The Universal Synchronous Asynchronous
Receiver Transmitter (USART) is also known as the
Serial Communications Interface or SCI. Also, a 5-
channel high speed 8-bit A/D is provided on the
PIC16C73B, while the PIC16C74B offers 8 channels.
The 8-bit resolution is ideally suited for applications
requiring low cost analog interface, e.g., thermostat
control, pressure sensing, etc.
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller fam-
ily will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X can be easily ported to the PIC16CXX fam-
ily of devices (Appendix B).
1.2
Development Support
PICmicro® devices are supported by the complete line
of Microchip Development tools.
The PIC16C63A/65B/73B/74B devices have special
features to reduce external components, thus reducing
cost, enhancing system reliability and reducing power
consumption. There are four oscillator options, of which
the single pin RC oscillator provides a low cost solution,
the LP oscillator minimizes power consumption, XT is
a standard crystal, and the HS is for high speed crys-
tals. The SLEEP (power-down) feature provides a
power-saving mode. The user can wake-up the chip
from SLEEP through several external and internal
interrupts and RESETS.
Please refer to Section 15.0 for more details about
Microchip’s development tools.
2000 Microchip Technology Inc.
DS30605C-page 5
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 6
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.3
Quick-Turnaround-Production
(QTP) Devices
2.0
PIC16C63A/65B/73B/74B
DEVICE VARIETIES
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C63A/65B/73B/74B
Product Identification System section at the end of this
data sheet. When placing orders, please use that page
of the data sheet to specify the correct part number.
For the PIC16C7X family, there are two device “types”
as indicated in the device number:
1. C, as in PIC16C74. These devices have
EPROM type memory and operate over the
standard voltage range.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
2. LC, as in PIC16LC74. These devices have
EPROM type memory and operate over an
extended voltage range.
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers. The serial num-
bers may be random, pseudo-random or sequential.
2.1
UV Erasable Devices
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
The UV erasable version, offered in windowed CERDIP
packages, is optimal for prototype development and
pilot programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART Plus and PRO MATE II
programmers both support programming of the
PIC16C63A/65B/73B/74B.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
2000 Microchip Technology Inc.
DS30605C-page 7
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 8
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which
program and data are accessed from separate memo-
ries using separate buses. This improves bandwidth
over traditional von Neumann architecture, in which
program and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide, making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions (Example 3-1). Consequently, most
instructions execute in a single cycle (200 ns @
20 MHz) except for program branches.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
All devices covered by this data sheet contain
4K x 14-bit program memory and 192 x 8-bit data
memory.
The PIC16CXX can directly, or indirectly, address its
register files or data memory. All Special Function Reg-
isters, including the program counter, are mapped in
the data memory. The PIC16CXX has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
2000 Microchip Technology Inc.
DS30605C-page 9
PIC16C63A/65B/73B/74B
FIGURE 3-1:
PIC16C63A/65B/73B/74B BLOCK DIAGRAM
13
8
PORTA
PORTB
Data Bus
Program Counter
RA0/AN0(2)
RA1/AN1(2)
RA2/AN2(2)
RA3/AN3/VREF
RA4/T0CKI
EPROM
Program
Memory
(2)
RAM
File
Registers
8 Level Stack
(13-bit)
RA5/SS/AN4(2)
Program
Bus
14
RAM Addr(1)
9
Addr MUX
RB0/INT
RB7:RB1
Instruction reg
Indirect
Addr
7
Direct Addr
8
FSR reg
PORTC
STATUS reg
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
3
MUX
Power-up
Timer
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
PORTD(3)
8
Timing
Generation
Watchdog
Timer
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
Parallel Slave Port
(3)
PORTE(3)
MCLR VDD, VSS
RE0/RD/AN5(2,3)
RE1/WR/AN6(2,3)
RE2/CS/AN7(2,3)
Timer0
CCP1
Timer1
CCP2
Timer2
A/D(2)
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: A/D is not available on the PIC16C63A/65B.
3: PSP and Ports D and E are not available on PIC16C63A/73B.
DS30605C-page 10
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 3-1:
PIC16C63A/73B PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
9
9
I
ST/CMOS
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP
1
1
I/P
ST
Master clear (RESET) input or programming voltage input.
This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
(4)
(4)
RA0/AN0
2
3
4
5
2
3
4
5
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
RA0 can also be analog input 0
RA1 can also be analog input 1
RA2 can also be analog input 2
.
.
.
(4)
(4)
(4)
RA1/AN1
(4)
RA2/AN2
(4)
RA3/AN3/VREF
RA3 can also be analog input 3 or analog reference
(4)
voltage
.
RA4/T0CKI
6
7
6
7
I/O
I/O
ST
RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
(4)
(4)
RA5/SS/AN4
TTL
RA5 can also be analog input 4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
21
22
23
24
25
26
27
28
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0 can also be the external interrupt pin.
RB2
TTL
RB3
TTL
RB4
TTL
Interrupt-on-change pin.
RB5
TTL
Interrupt-on-change pin.
(2)
RB6
TTL/ST
TTL/ST
Interrupt-on-change pin. Serial programming clock.
Interrupt-on-change pin. Serial programming data.
PORTC is a bi-directional I/O port.
(2)
RB7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
11
12
13
14
15
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC3 can also be the synchronous serial clock input/output
2
for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5/SDO
16
17
16
17
I/O
I/O
ST
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit
or Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive
or Synchronous Data.
VSS
8, 19
20
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
P = power
VDD
Legend: I = input
O = output
I/O = input/output
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: A/D module is not available in the PIC16C63A.
2000 Microchip Technology Inc.
DS30605C-page 11
PIC16C63A/65B/73B/74B
TABLE 3-2:
PIC16C65B/74B PINOUT DESCRIPTION
TQFP
MQFP
Pin#
DIP
Pin#
PLCC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKIN
13
14
14
15
30
31
I
ST/CMOS
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master clear (RESET) input or programming voltage input.
This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
(5)
(5)
RA0/AN0
2
3
4
5
3
4
5
6
19
20
21
22
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
RA0 can also be analog input 0
RA1 can also be analog input 1
RA2 can also be analog input 2
.
.
.
(5)
(5)
(5)
RA1/AN1
(5)
RA2/AN2
(5)
RA3/AN3/VREF
RA3 can also be analog input 3 or analog reference
(5)
voltage
.
RA4/T0CKI
6
7
7
8
23
24
I/O
I/O
ST
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
(5)
(5)
RA5/SS/AN4
TTL
RA5 can also be analog input 4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
33
34
35
36
37
38
39
40
36
37
38
39
41
42
43
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0 can also be the external interrupt pin.
9
RB2
10
11
14
15
16
17
TTL
RB3
TTL
RB4
TTL
Interrupt-on-change pin.
RB5
TTL
Interrupt-on-change pin.
(2)
RB6
TTL/ST
TTL/ST
Interrupt-on-change pin. Serial programming clock.
(2)
RB7
44
Interrupt-on-change pin. Serial programming data.
P = power
Legend: I = input
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
— = Not used
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: A/D is not available on the PIC16C65B.
DS30605C-page 12
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 3-2:
PIC16C65B/74B PINOUT DESCRIPTION (CONTINUED)
TQFP
MQFP
Pin#
DIP
Pin#
PLCC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
15
16
17
18
23
24
25
26
16
18
19
20
25
26
27
29
32
35
36
37
42
43
44
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC3 can also be the synchronous serial clock input/
2
output for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
3
4
5
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
(5)
8
9
9
25
26
27
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
RE0 can also be read control for the parallel slave port,
RE0/RD/AN5
(5)
or analog input 5
.
(5)
10
11
RE1 can also be write control for the parallel slave port,
RE1/WR/AN6
(5)
or analog input 6
.
(5)
10
RE2 can also be select control for the parallel slave
RE2/CS/AN7
(5)
port, or analog input 7
.
VSS
VDD
NC
12,31
11,32
—
13,34
12,35
6,29
7,28
P
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
1,17,28, 12,13,
40
These pins are not internally connected. These pins should
be left unconnected.
33,34
Legend: I = input
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
P = power
— = Not used
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: A/D is not available on the PIC16C65B.
2000 Microchip Technology Inc.
DS30605C-page 13
PIC16C63A/65B/73B/74B
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
Note:
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is
“flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS30605C-page 14
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2
Data Memory Organization
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this data sheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
RP1:RP0 (STATUS<6:5>)
= 00→ Bank0
= 01→ Bank1
= 10→ Bank2
Accessing a location above 0FFFh will cause a wrap-
around.
= 11→ Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 4-1:
PIC16C63A/65B/73B/74B
PROGRAM MEMORY MAP
AND STACK
All implemented banks contain SFRs. Frequently used
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
PC<12:0>
13
Note: Maintain the IRP and RP1 bits clear in
CALL,RETURN
RETFIE,RETLW
these devices.
4.2.1
GENERAL PURPOSE REGISTER
FILE
Stack Level 1
The register file can be accessed either directly, or indi-
rectly, through the File Select Register (FSR)
(Section 4.5).
Stack Level 8
RESET Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
0800h
On-chip Program
Memory (Page 1)
0FFFh
1000h
1FFFh
2000 Microchip Technology Inc.
DS30605C-page 15
PIC16C63A/65B/73B/74B
FIGURE 4-2:
REGISTER FILE MAP
4.2.2
SPECIAL FUNCTION REGISTERS
File
File
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
Address
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
INDF(1)
INDF(1)
OPTION_REG 81h
80h
TMR0
PCL
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associ-
ated with the “core” functions are described in this sec-
tion, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
PR2
SSPADD
SSPSTAT
17h CCP1CON
18h
19h
1Ah
1Bh
1Ch
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
TXSTA
SPBRG
1Dh CCP2CON
ADRES(3)
1Eh
ADCON0(3)
1Fh
20h
ADCON1(3)
General
Purpose
Register
General
Purpose
Register
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations, read as ’0’.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C63A/73B, read as '0'.
3: These registers are not implemented on the
PIC16C63A/65B, read as '0'.
DS30605C-page 16
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on
all other
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(3)
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
INDF(4)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
PCL(4)
Program Counter's (PC) Least Significant Byte
STATUS(4)
FSR(4)
IRP(2)
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1(2)
RP0
TO
PD
Z
DC
C
PORTA
—
—
PORTB
PORTC
PORTD(5)
PORTE(5)
PCLATH(1,4)
INTCON(4)
PIR1
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
—
—
—
—
—
—
—
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIF(6)
—
T0IE
RCIF
—
INTE
TXIF
–
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
PSPIF(5)
—
TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
PIR2
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
TMR1H
T1CON
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR2
Timer2 module’s register
0000 0000 0000 0000
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx uuuu uuuu
SSPM0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES(6)
ADCON0(6)
USART Transmit Data register
USART Receive Data register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
A/D Result register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
2000 Microchip Technology Inc.
DS30605C-page 17
PIC16C63A/65B/73B/74B
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(3)
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF(4)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
OPTION_REG RBPU
INTEDG
Program Counter’s (PC) Least Significant Byte
IRP(2) RP1(2)
RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
PCL(4)
STATUS(4)
FSR(4)
TRISA
TRISB
TRISC
TRISD(5)
TRISE(5)
PCLATH(1,4)
INTCON(4)
PIE1
PD
Z
DC
C
—
—
PORTB Data Direction register
PORTC Data Direction register
PORTD Data Direction register
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction bits
Write Buffer for the upper 5 bits of the Program Counter
GIE
PSPIE(5)
—
PEIE
ADIE(6)
—
T0IE
RCIE
—
INTE
TXIE
—
RBIE
SSPIE
—
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
PIE2
PCON
—
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
Unimplemented
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
PR2
Timer2 Period register
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
SSPADD
SSPSTAT
—
Synchronous Serial Port (I2C mode) Address register
—
—
D/A
P
S
R/W
UA
BF
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator register
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1(6)
—
—
—
—
—
PCFG2
PCFG1
PCFG0 -----000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
DS30605C-page 18
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
It is recommended that only BCF, BSF, SWAPFand
MOVWFinstructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, C or DC bits
in the STATUS register. For other instructions which do
not affect status bits, see the "Instruction Set Sum-
mary."
4.2.2.1
STATUS Register
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS reg-
ister is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to the device
logic. Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>), maintain these bits
clear to ensure upward compatibility with
future products.
2: The C and DC bits operate as borrow and
digit borrow bits, respectively, in subtrac-
tion. See the SUBLWand SUBWFinstruc-
tions for examples.
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
IRP(1)
R/W-0
RP1(1)
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C(2)
bit 7
bit 0
bit 7
IRP(1): Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5
RP1(1):RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity
is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C
(2): Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note 1: Maintain the IRP and RP1 bits clear.
2: For borrow and digit borrow, the polarity is reversed. A subtraction is executed by
adding the two’s complement of the second operand. For rotate (RRF,RLF) instruc-
tions, this bit is loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 19
PIC16C63A/65B/73B/74B
4.2.2.2
OPTION Register
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the watchdog timer.
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external INT Interrupt,
TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
DS30605C-page 20
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.3
INTCON Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
REGISTER 4-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state(1)
0= None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will exist until PORTB is read. After reading PORTB, the RBIF
flag bit can be cleared.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 21
PIC16C63A/65B/73B/74B
4.2.2.4
PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 4-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE(2)
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
R/W-0
R/W-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE(2): A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented; always
maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D implemented; always maintain this bit
clear.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30605C-page 22
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.5
PIR1 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 4-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF(2)
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF TMR2IF
TMR1IF
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF(2): A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full (clear by reading RCREG)
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty (clear by writing to TXREG)
0= The USART transmit buffer is full
SSPIF: Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented. This bit loca-
tion is reserved on these devices.
2: PIC16C63A/65B devices do not have an A/D implemented. This bit location is
reserved on these devices.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 23
PIC16C63A/65B/73B/74B
4.2.2.6
PIE2 Register
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6:
PIE2 REGISTER (ADDRESS 8Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CCP2IE
bit 7
bit 0
bit 7-1
bit 0
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
4.2.2.7
PIR2 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the CCP2 interrupt flag bit.
REGISTER 4-7:
PIR2 REGISTER (ADDRESS 0Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CCP2IF
bit 7
bit 0
bit 7-1
bit 0
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30605C-page 24
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.8
PCON Register
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred. The BOR status
bit is a “don't care” and is not predictable if
the brown-out circuit is disabled (by clear-
ing the BODEN bit in the configuration
word).
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 4-8:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
POR
R/W-q
BOR
—
—
—
—
—
—
bit 7
bit 0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 25
PIC16C63A/65B/73B/74B
4.3
PCL and PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 4-3 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an inter-
rupt address.
4.4
Program Memory Paging
PIC16CXX devices are capable of addressing a contin-
uous 8K word block of program memory. The CALLand
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When executing a CALLor GOTOinstruction, the upper
2 bits of the address are provided by PCLATH<4:3>.
When doing a CALLor GOTOinstruction, the user must
ensure that the page select bits are programmed, so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is popped from the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack).
FIGURE 4-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
Destination
PC
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PC
PCL
Note 1: The contents of PCLATH are unchanged
after a return or RETFIE instruction is
executed. The user must set up PCLATH
for any subsequent CALL’s or GOTO’s
8
7
0
GOTO,CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
2: PCLATH<4> is not used in these
PICmicro® devices. The use of
PCLATH<4> as a general purpose read/
write bit is not recommended, since this
may affect upward compatibility with
future products.
4.3.1
COMPUTED GOTO
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
EXAMPLE 4-1:
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
4.3.2
STACK
ORG
BSF
0x500
PCLATH,3 ;Select page 1 (800h-FFFh)
The PIC16CXX family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
CALL SUB1_P1 ;Call subroutine in
:
;page 1 (800h-FFFh)
:
ORG
0x900
;page 1 (800h-FFFh)
SUB1_P1
:
:
:
;called subroutine
;page 1 (800h-FFFh)
RETURN
;return to Call subroutine
;in page 0 (000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30605C-page 26
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
EXAMPLE 4-2:
INDIRECT ADDRESSING
4.5
Indirect Addressing, INDF and
FSR Registers
movlw
movwf
0x20
FSR
;initialize pointer
;to RAM
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
clrf
incf
btfss
goto
INDF
;clear INDF register
FSR,F ;inc pointer
FSR,4 ;all done?
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-4.
NEXT
;no clear next
CONTINUE
:
;yes continue
Note: Maintain the IRP and RP1 bits clear.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP1:RP0
0
6
0
0
IRP
0
FSR register
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
Data
Memory
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
Note 1: For register file map detail, see Figure 4-2.
2: Shaded portions are not implemented; maintain the IRP and RP1 bits clear.
2000 Microchip Technology Inc.
DS30605C-page 27
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 28
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 5-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
Q
VDD
P
WR
Port
5.1
PORTA and TRISA Registers
CK
Data Latch
PORTA is a 6-bit latch.
(1)
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers), which can config-
ure these pins as output or input.
I/O pin
N
D
Q
WR
TRIS
VSS
Analog
Q
CK
Input
TRIS Latch
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
mode
TTL
Input
Buffer
RD TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
D
EN
RD Port
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
To A/D Converter
On the PIC16C73B/74B, PORTA pins are multiplexed
with analog inputs and analog VREF input. The opera-
tion of each pin is selected by clearing/setting the con-
trol bits in the ADCON1 register (A/D Control
Register1).
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On all RESETS, pins with analog functions
FIGURE 5-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
are configured as analog and digital inputs.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Data
Bus
D
Q
Q
WR
Port
CK
I/O pin(1)
N
Data Latch
EXAMPLE 5-1:
INITIALIZING PORTA
(PIC16C73B/74B)
D
Q
VSS
WR
TRIS
BCF
CLRF
STATUS, RP0
PORTA
;
Schmitt
Trigger
Input
Q
CK
; Initialize PORTA by
; clearing output
; data latches
TRIS Latch
Buffer
BSF
STATUS, RP0 ; Select Bank 1
MOVLW
MOVWF
MOVLW
0x06
ADCON1
0xCF
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
RD TRIS
Q
D
EN
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
RD Port
TMR0 Clock Input
Note 1: I/O pins have protection diodes to VDD and VSS.
2000 Microchip Technology Inc.
DS30605C-page 29
PIC16C63A/65B/73B/74B
TABLE 5-1:
Name
PORTA FUNCTIONS
Bit# Buffer Function
bit0
RA0/AN0(1)
RA1/AN1(1)
RA2/AN2(1)
RA3/AN3/VREF
TTL
TTL
TTL
TTL
Digital input/output or analog input.
Digital input/output or analog input.
Digital input/output or analog input.
Digital input/output or analog input or VREF.
bit1
bit2
bit3
(1)
Digital input/output or external clock input for Timer0.
Output is open drain type.
RA4/T0CKI
bit4
bit5
ST
RA5/SS/AN4(1)
TTL
Input/output or slave select input for synchronous serial port or analog input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not
implemented; maintain this register clear.
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
PORTA
TRISA
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
PORTA Data Direction Register
(1)
9Fh
—
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
ADCON1
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented;
maintain this register clear.
DS30605C-page 30
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
FIGURE 5-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
VDD
RBPU(2)
Weak
Pull-up
P
Data Latch
Data Bus
WR Port
D
Q
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
I/O pin(1)
CK
TRIS Latch
RB0/INT is discussed in detail in Section 13.5.1.
D
Q
TTL
FIGURE 5-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
Input
Buffer
WR TRIS
CK
VDD
RBPU(2)
Weak
P
Pull-up
RD TRIS
RD Port
Data Latch
Q
D
Data Bus
WR Port
D
Q
I/O pin(1)
EN
CK
TRIS Latch
RB0/INT
D
Q
Schmitt Trigger
Buffer
RD Port
TTL
Input
Buffer
WR TRIS
CK
ST
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
RD TRIS
RD Port
Latch
Q
Q
D
Four of PORTB’s pins, RB7:RB4, have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the value latched on the
last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’d together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
EN
Q1
Set RBIF
D
From other
RB7:RB4 pins
RD Port
Q3
EN
RB7:RB6 in Serial Programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
2000 Microchip Technology Inc.
DS30605C-page 31
PIC16C63A/65B/73B/74B
TABLE 5-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
(1)
RB0/INT
bit0
TTL/ST
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change). Internal software programmable weak
pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
TTL/ST
TTL/ST
Input/output pin (with interrupt-on-change). Internal software programmable weak
pull-up.
(2)
(2)
Input/output pin (with interrupt-on-change). Internal software programmable weak
pull-up. Serial programming clock.
Input/output pin (with interrupt-on-change). Internal software programmable weak
pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
uuuu uuuu
1111 1111
1111 1111
06h
86h
81h
PORTB
TRISB
OPTION_REG RBPU INTEDG T0CS T0SE PSA
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
1111 1111
1111 1111
PORTB Data Direction register
PS2
PS1
PS0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30605C-page 32
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 5-5:
PORTC BLOCK DIAGRAM
5.3
PORTC and TRISC Registers
PORTC is an 8-bit bi-directional port. Each pin is indi-
vidually configurable as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
PORT/PERIPHERAL Select(2)
Peripheral Data Out
0
VDD
Data Bus
D
Q
Q
WR
P
Port
CK
1
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-write
instructions (BSF, BCF, XORWF) with TRISC as des-
tination should be avoided. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
Data Latch
I/O pin(1)
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
EN
RD
Port
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
TABLE 5-5:
Name
PORTC FUNCTIONS
Bit#
bit0
bit1
Buffer Type
Function
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2
output/PWM2 output.
RC2/CCP1
bit2
bit3
bit4
bit5
bit6
ST
ST
ST
ST
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1 output.
2
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC3 can also be the Synchronous Serial Clock for both SPI and I C modes.
2
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I C mode).
Input/output port pin or Synchronous Serial Port Data output.
RC6/TX/CK
Input/output port pin or USART Asynchronous Transmit, or USART
Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive, or USART
Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
87h
PORTC
TRISC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
PORTC Data Direction register
Legend: x= unknown, u= unchanged
2000 Microchip Technology Inc.
DS30605C-page 33
PIC16C63A/65B/73B/74B
FIGURE 5-6:
PORTD BLOCK DIAGRAM
5.4
PORTD and TRISD Registers
Data
Bus
Note: The PIC16C63A and PIC16C73B do not
provide PORTD. The PORTD and TRISD
registers are not implemented.
D
Q
(1)
WR
Port
I/O pin
CK
Data Latch
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configured as an input or
output.
D
Q
WR
TRIS
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-7:
PORTD FUNCTIONS
Name
Bit#
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Buffer Type
Function
(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
ST/TTL
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on
all other
RESETS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
TRISD PORTD Data Direction register
TRISE IBF OBF IBOV PSPMODE
—
PORTE Data Direction bits
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS30605C-page 34
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 5-7:
PORTE BLOCK DIAGRAM
5.5
PORTE and TRISE Register
Data
Bus
Note 1: The PIC16C63A and PIC16C73B do not
provide PORTE. The PORTE and TRISE
registers are not implemented.
D
Q
I/O pin(1)
WR
Port
CK
Data Latch
2: The PIC16C63A/65B does not provide an
A/D module. A/D functions are not imple-
mented.
D
Q
WR
TRIS
PORTE has three pins: RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configured as
inputs or outputs. These pins have Schmitt Trigger
input buffers.
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs) and that register ADCON1 is configured for dig-
ital I/O. In this mode, the input buffers are TTL.
RD TRIS
Q
D
EN
RD Port
Register 5-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
PORTE pins may be multiplexed with analog inputs
(PIC16C74B only). The operation of these pins is
selected by control bits in the ADCON1 register. When
selected as an analog input, these pins will read as ’0’s.
Note 1: I/O pins have protection diodes to VDD and VSS.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as ‘0’s.
TABLE 5-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
(1)
RE0/RD/AN5
bit0
ST/TTL
Input/output port pin or read control input in Parallel Slave Port mode or analog
input:
RD
1 = Idle
0 = Read operation. Contents of PORTD register is output to PORTD
I/O pins (if chip selected).
(1)
RE1/WR/AN6
RE2/CS/AN7
bit1
bit2
ST/TTL
Input/output port pin or write control input in Parallel Slave Port mode or analog
input:
WR
1 = Idle
0 = Write operation. Value of PORTD I/O pins is latched into PORTD
register (if chip selected).
(1)
ST/TTL
Input/output port pin or chip select control input in Parallel Slave Port mode or
analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
2000 Microchip Technology Inc.
DS30605C-page 35
PIC16C63A/65B/73B/74B
REGISTER 5-1:
TRISE REGISTER (ADDRESS 89h)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
—
TRISE2 TRISE1
TRISE0
bit 7
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in
software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0 = General purpose I/O mode
bit 3
bit 2
Unimplemented: Read as '0'
TRISE2: Direction Control bit for pin RE2/CS/AN7
1= Input
0 = Output
bit 1
bit 0
TRISE1: Direction Control bit for pin RE1/WR/AN6
1= Input
0 = Output
TRISE0: Direction Control bit for pin RE0/RD/AN5
1= Input
0 = Output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
89h
9Fh
PORTE
TRISE
—
IBF
—
—
OBF
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
0000 -111 0000 -111
IBOV PSPMODE
PORTE Data Direction bits
ADCON1
—
—
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTE.
DS30605C-page 36
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
5.6
Parallel Slave Port (PSP)
Note: The PIC16C63A and PIC16C73B do not
provide a parallel slave port. The PORTD,
PORTE, TRISD and TRISE registers are
not implemented.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
PORTD operates as an 8-bit wide Parallel Slave Port
(PSP), or microprocessor port when control bit PSP-
MODE (TRISE<4>) is set. In Slave mode, it is asyn-
chronously readable and writable by the external world,
through RD control input pin RE0/RD/AN5 and WR
control input pin RE1/WR/AN6.
FIGURE 5-8:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input,
RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to
be the CS (chip select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the A/D port configuration bits PCFG2:PCFG0
(ADCON1<2:0>) must be set, which will configure pins
RE2:RE0 as digital I/O.
Data Bus
D
Q
WR
Port
RDx
pin
CK
TTL
Q
D
RD
Port
EN
There are actually two 8-bit latches, one for data out
(from the PICmicro® MCU) and one for data input. The
user writes 8-bit data to PORTD data latch and reads
data from the port pin latch (note that they have the
same address). In this mode, the TRISD register is
ignored since the external device is controlling the
direction of data flow.
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full (IBF) status flag bit (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete (Figure 5-9). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The Input Buffer Overflow (IBOV) status
flag bit (TRISE<5>) is set if a second write to the PSP
is attempted when the previous byte has not been read
out of the buffer.
Read
RD
TTL
Chip Select
CS
TTL
Write
TTL
WR
Note 1: I/O pins have protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 5-10), indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
2000 Microchip Technology Inc.
DS30605C-page 37
PIC16C63A/65B/73B/74B
FIGURE 5-9:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 5-10:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
09h
PORTD
PORTE
Port data latch when written, Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 000x 0000 000u
0000 -111 0000 -111
—
—
—
—
—
RBIE
—
RE2
T0IF
RE1
RE0
0Bh, 8Bh INTCON
GIE
IBF
PEIE
OBF
T0IE
INTE
INTF
RBIF
89h
0Ch
8Ch
9Fh
TRISE
PIR1
IBOV PSPMODE
PORTE Data Direction Bits
PSPIF ADIF RCIF
PSPIE ADIE RCIE
TXIF
TXIE
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE1
ADCON1
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
DS30605C-page 38
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment, either on every rising, or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
6.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The
prescaler is not readable or writable. Section 6.3
details the operation of the prescaler.
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
Timer0 Interrupt
Additional information on the Timer0 module is
available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the incre-
ment is inhibited for the following two instruction cycles.
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= FOSC/4)
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
TMR0 reg
Cycles
T0SE
T0CS
Set Flag bit T0IF
on Overflow
PSA
PRESCALER
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
2000 Microchip Technology Inc.
DS30605C-page 39
PIC16C63A/65B/73B/74B
module means that there is no prescaler for the Watch-
dog Timer, and vice-versa. This prescaler is not read-
able or writable (see Figure 6-1).
6.2
Using Timer0 with an External
Clock
The synchronization of T0CKI with the internal phase
clocks is accomplished by sampling the synchronized
input on the Q2 and Q4 cycles of the internal phase
clocks. Therefore, it is necessary for T0CKI to be high
for at least 2 TOSC (and a small RC delay of 20 ns) and
low for at least 2 TOSC (and a small RC delay of 20 ns).
Refer to the electrical specification for the desired
device.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF1,MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
6.3
Prescaler
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
REGISTER 6-1:
OPTION_REG REGISTER
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
RBPU
INTEDG
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023, Section 11.6) must be executed when changing the prescaler assign-
ment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
DS30605C-page 40
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
INTCON
OPTION_REG RBPU INTEDG T0CS
Timer0 Module’s register
xxxx xxxx uuuu uuuu
0Bh,8Bh
81h
GIE PEIE T0IE
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
2000 Microchip Technology Inc.
DS30605C-page 41
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 42
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
7.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 9.0) using the special event trigger.
Register 7-1 shows the Timer1 control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored, and these pins read as ‘0’.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
Additional information on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 7-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut-off (The oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 43
PIC16C63A/65B/73B/74B
7.1
Timer1 Operation in Timer Mode
7.2
Timer1 Operation in Synchronized
Counter Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
FIGURE 7-1:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
(2)
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
(2)
RC1/T1OSI/CCP2
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16C65B/73B/74B, the Schmitt Trigger is not implemented in External Clock mode.
DS30605C-page 44
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
7.3
Timer1 Operation in
Asynchronous Counter Mode
Osc Type
Freq
C1
C2
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 7.3.1).
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
In Asynchronous Counter mode, Timer1 can not be
used as a time-base for capture or compare opera-
tions.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-up
time.
7.3.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
7.5
Resetting Timer1 using a CCP
Trigger Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 or CCP2 module is configured in Compare
mode to generate “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
a
Timer1.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Reading the 16-bit value requires some care. Exam-
ples 12-2 and 12-3 in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in Asynchro-
nous mode.
Timer1 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
7.4
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset or a
Brown-out Reset, which shuts off the timer and leaves a
1:1 prescale. In all other resets, the register is unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
2000 Microchip Technology Inc.
DS30605C-page 45
PIC16C63A/65B/73B/74B
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PSPIF(1) ADIF(2)
PSPIE(1) ADIE(2)
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
0Eh
TMR1L
TMR1H
T1CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
0Fh
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605C-page 46
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.1
Timer2 Prescaler and Postscaler
8.0
TIMER2 MODULE
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, BOR, MCLR Reset, or
WDT Reset)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4,
or
1:16,
selected
by
control
bits
TMR2 is not cleared when T2CON is written.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate the
shift clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
Output(1)
RESET
bit TMR2IF
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Prescaler
TMR2 reg
FOSC/4
1:1, 1:4, 1:16
Register 8-1 shows the Timer2 control register.
Postscaler
2
Comparator
1:1 to 1:16
4
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
EQ
T2CKPS1:
T2CKPS0
PR2 reg
T2OUTPS3:
T2OUTPS0
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
REGISTER 8-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 47
PIC16C63A/65B/73B/74B
TABLE 8-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on:
POR,
BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
PSPIF(1)
PSPIE(1)
ADIF(2)
ADIE(2)
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
11h
TMR2
T2CON
PR2
Timer2 Module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period register
12h
—
92h
Legend: x= unknown, u= unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605C-page 48
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
CCP2 Module:
9.0
CAPTURE/COMPARE/PWM
MODULES
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in “Using the CCP Modules”
(AN594).
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 9-1 and Table 9-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
TABLE 9-1:
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
Capture
Compare
PWM
Timer1
Timer1
Timer2
TABLE 9-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
Capture
Compare
Compare
PWM
Same TMR1 time-base.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
Compare
None.
None.
PWM
2000 Microchip Technology Inc.
DS30605C-page 49
PIC16C63A/65B/73B/74B
REGISTER 9-1:
CCP1CON REGISTER/CCP2CON REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCPxX
CCPxY
CCPxM3
CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCPxIF bit is set)
1001= Compare mode, clear output on match (CCPxIF bit is set)
1010= Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011= Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module
is enabled)
11xx= PWM mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30605C-page 50
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.1.2
TIMER1 MODE SELECTION
9.1
Capture Mode
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the fol-
lowing and is configured using CCPxCON<3:0>:
• Every falling edge
• Every rising edge
9.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the previous captured value is overwritten by the
new captured value.
9.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
FIGURE 9-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
EXAMPLE 9-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Set Flag bit CCP1IF
(PIR1<2>)
CLRF
CCP1CON
; Turn CCP module off
Prescaler
÷ 1, 4, 16
MOVLW
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
RC2/CCP1
pin
CCPR1H CCPR1L
; move value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with this
; value
Capture
Enable
and
Edge Detect
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
2000 Microchip Technology Inc.
DS30605C-page 51
PIC16C63A/65B/73B/74B
9.2.4
SPECIAL EVENT TRIGGER
9.2
Compare Mode
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
• Driven high
• Driven low
• Remains unchanged
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
FIGURE 9-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
9.3
PWM Mode (PWM)
Special event trigger will:
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
RC2/CCP1
pin
Match
TRISC<2>
Output Enable
TMR1H TMR1L
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
CCP1CON<3:0>
Mode Select
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
9.2.1
CCP PIN CONFIGURATION
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCP1CON<5:4>
Duty Cycle Registers
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
CCPR1L
CCPR1H (Slave)
Comparator
9.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
Q
R
S
RC2/CCP1
(Note 1)
TMR2
9.2.3
SOFTWARE INTERRUPT MODE
TRISC<2>
Comparator
PR2
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock,
or 2 bits of the prescale, to create 10-bit time-base.
DS30605C-page 52
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
A PWM output (Figure 9-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
9.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
FIGURE 9-4:
PWM OUTPUT
Period
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Duty Cycle
TMR2 = PR2 (Timer2 RESET)
TMR2 = Duty Cycle
(Timer2 RESET)
TMR2 = PR2
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
9.3.1
PWM PERIOD
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
Maximum PWM resolution (bits) for a given PWM
frequency:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
FOSC
FPWM
PWM frequency is defined as 1 / [PWM period].
log( )
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Resolution
bits
=
log(2)
• TMR2 is cleared
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
9.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
Note: The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 9-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
5.5
Maximum Resolution (bits)
2000 Microchip Technology Inc.
DS30605C-page 53
PIC16C63A/65B/73B/74B
TABLE 9-4:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
0Dh
8Ch
8Dh
87h
INTCON
PIR1
GIE
PEIE
T0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0000 000x 0000 000u
PSPIF(1) ADIF(2)
TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
PIR2
—
—
PIE1
PSPIE(1) ADIE(2)
RCIE
—
TXIE
—
SSPIE
—
CCP1IE
—
TMR2IE
—
PIE2
—
—
TRISC
PORTC Data Direction register
0Eh
0Fh
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
—
—
CCP1X
CCP1Y
CCP1M3
CCP2M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
1Bh
1Ch
1Dh
Capture/Compare/PWM register2 (LSB)
Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
—
—
CCP2X
CCP2Y
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16C63A/73B; always maintain these bits clear.
2: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits clear.
TABLE 9-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
0Dh
8Ch
8Dh
87h
INTCON
PIR1
GIE
PEIE
T0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
0000 0000 0000 0000
---- ---0 ---- ---0
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
PSPIF(1) ADIF(2)
TMR1IF
CCP2IF
TMR1IE
CCP2IE
PIR2
—
—
PIE1
PSPIE(1) ADIE(2)
RCIE
—
TXIE
—
SSPIE
—
CCP1IE
—
TMR2IE
—
PIE2
—
—
TRISC
TMR2
PR2
PORTC Data Direction register
Timer2 Module’s register
11h
92h
Timer2 Module’s Period register
12h
T2CON
CCPR1L
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
CCPR2L
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1
CCP2M3 CCP2M2 CCP2M1
CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
1Bh
Capture/Compare/PWM register2 (LSB)
1Ch
1Dh
Legend:
CCPR2H Capture/Compare/PWM register2 (MSB)
CCP2CON CCP2X CCP2Y
xxxx xxxx uuuu uuuu
—
—
CCP2M0 --00 0000 --00 0000
x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605C-page 54
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 10-1:
SSP BLOCK DIAGRAM
(SPI MODE)
10.0 SYNCHRONOUS SERIAL PORT
(SSP) MODULE
Internal
Data Bus
10.1 SSP Module Overview
Read
Write
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
SSPBUF reg
SSPSR reg
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional informa-
RC4/SDI/SDA
RC5/SDO
Shift
Clock
bit0
tion on the SSP module can be found in the PICmicro™
Mid-Range
(DS33023).
MCU
Family
Reference Manual
Control
Enable
SS
Refer to Application Note AN578, “Use of the SSP
Module in the I 2C Multi-Master Environment.”
RA5/SS/AN4
Edge
Select
10.2 SPI Mode
2
This section contains register definitions and opera-
tional characteristics of the SPI module.
Clock Select
SSPM3:SSPM0
4
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accom-
plish communication, typically three pins are used:
TMR2 Output
2
Edge
Select
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
TCY
Prescaler
4, 16, 64
RC3/SCK/
SCL
TRISC<3>
Additionally, a fourth pin may be used when in a Slave
mode of operation:
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
• Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
• SDI must have TRISC<4> set
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3> cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
• Clock edge (output data on rising/falling edge of
SCK)
• ADCON1 must configure RA5 as a digital I/O pin.
.
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control must be
enabled.
2000 Microchip Technology Inc.
DS30605C-page 55
PIC16C63A/65B/73B/74B
REGISTER 10-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time (Microwire®)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2C mode:
This bit must be maintained clear
bit 6
CKE: SPI Clock Edge Select (see Figure 10-2, Figure 10-3, and Figure 10-4)
SPI mode:
CKP = 0:
1= Data transmitted on rising edge of SCK (Microwire alternate)
0= Data transmitted on falling edge of SCK
CKP = 1:
1= Data transmitted on falling edge of SCK (Microwire default)
0= Data transmitted on rising edge of SCK
I2C mode:
This bit must be maintained clear
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit (I2C mode only). This bit is cleared when the SSP module is disabled, or when the
START bit is detected last. SSPEN is cleared.
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit (I2C mode only). This bit is cleared when the SSP module is disabled, or when
the STOP bit is detected last. SSPEN is cleared.
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
R/W: Read/Write bit information (I2C mode only). This bit holds the R/W bit information follow-
ing the last address match. This bit is only valid from the address match to the next START bit,
STOP bit, or ACK bit.
1= Read
0= Write
bit 1
bit 0
UA: Update Address (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1= Transmit in progress, SSPBUF is full
0= Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30605C-page 56
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
REGISTER 10-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Flag bit
1= The SSPBUF register was written while still transmitting the previous word (must be
cleared in software)
0= No collision
SSPOV: Synchronous Serial Port Overflow Flag bit
In SPI mode:
1= A new byte was received while the SSPBUF register is still holding the previous unread
data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave
mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting
overflow. In Master mode, the overflow bit is not set since each new reception (and trans-
mission) is initiated by writing to the SSPBUF register.
0= No overflow
In I2C mode:
1= A byte was received while the SSPBUF register is still holding the previous unread byte.
SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either
mode.
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit. When enabled, the SSP pins must be properly
configured as input or output.
In SPI mode:
1= Enables serial port and configures SCK, SDO, and SDI as serial port pins
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level (Microwire default)
0= Idle state for clock is a low level (Microwire alternate)
In I2C mode:
SCK release control
1= Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1011= I2C firmware controlled Master mode (Slave idle)
1110= I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111= I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 57
PIC16C63A/65B/73B/74B
FIGURE 10-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
SSPIF
bit7
bit0
FIGURE 10-3:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
DS30605C-page 58
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 10-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
8Ch
87h
INTCON
PIR1
GIE
PEIE
T0IE
INTE RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
PSPIF
PSPIE
ADIF
ADIE
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
(2)
PIE1
TRISC
PORTC Data Direction register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit register
SSPCON WCOL
14h
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h
TRISA
—
—
PORTA Data Direction register
D/A R/W
--11 1111 --11 1111
0000 0000 0000 0000
94h
SSPSTAT
SMP
CKE
P
S
UA
BF
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
2000 Microchip Technology Inc.
DS30605C-page 59
PIC16C63A/65B/73B/74B
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
• I2C START and STOP bit interrupts enabled to
support firmware Master mode, Slave is idle
2
10.3 SSP I C Operation
The SSP module in I2C mode fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementation of the master func-
tions. The SSP module implements the standard mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer, the RC3/SCK/SCL
pin, which is the clock (SCL), and the RC4/SDI/SDA
pin, which is the data (SDA). The user must configure
these pins as inputs or outputs through the
TRISC<4:3> bits. External pull-up resistors for the SCL
and SDA pins must be provided in the application cir-
cuit for proper operation of the I2C module.
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
Additional information on SSP I2C operation can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
FIGURE 10-5:
SSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
10.3.1
SLAVE MODE
Read
Write
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
SSPBUF reg
RC3/SCK/SCL
Shift
Clock
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally generates the acknowledge (ACK) pulse, and
then loads the SSPBUF register with the received
value currently in the SSPSR register.
SSPSR reg
RC4/SDI/
SDA
MSb
LSb
Match Detect
Addr Match
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
SSPADD reg
START and
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
Set, Reset
S, P bits
(SSPSTAT reg)
STOP bit Detect
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SSP module has five registers for I2C operation.
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - not directly accessible
• SSP Address Register (SSPADD)
The SCL clock input must have minimum high and low
times for proper operation. The high and low times of
the I2C specification, as well as the requirement of the
SSP module, is shown in timing parameter #100 and
parameter #101.
DS30605C-page 60
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
1. Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
10.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
a) The SSPSR register value is loaded into the
SSPBUF register.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
7. Receive Repeated START condition.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 10-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address, the first byte
would equal ‘1111 0 A9 A8 0’, where A9and A8are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7 - 9 for
slave-transmitter:
TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Generate ACK
Transfer is Received
SSPSR → SSPBUF
Pulse
BF
SSPOV
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
Yes
Yes, SSPOV is set
Yes
Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
2000 Microchip Technology Inc.
DS30605C-page 61
PIC16C63A/65B/73B/74B
a) The Buffer Full flag bit, BF(SSPSTAT<0>) was
set, indicating that the byte in SSPBUF was
waiting to be read when another byte was
received. This sets the SSPOV flag.
10.3.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
b) The overflow flag, SSPOV (SSPCON1<6>) was
set.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as any situation where a received byte
in SSPBUF is overwritten by the next received byte
before it has been read. An overflow has occurred
when:
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 10-6:
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
R/W=0
Receiving Data
Receiving Data
ACK
9
ACK
9
ACK
9
A7 A6 A5 A4
SDA
SCL
A3 A2 A1
D5
D2
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
7
1
2
4
5
4
3
6
5
6
1
2
3
6
1
2
4
8
5
P
S
SSPIF (PIR1<3>)
Cleared in software
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full
ACK is not sent
DS30605C-page 62
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
10.3.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 10-7).
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line was high (not
ACK), then the data transfer is complete. When the
ACK is latched by the slave, the slave logic is reset
(resets SSPSTAT register) and the slave then monitors
for another occurrence of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register, which also loads the SSPSR reg-
ister. Then pin RC3/SCK/SCL should be enabled by
setting bit CKP.
FIGURE 10-7:
I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
R/W = 1
ACK
Transmitting Data
ACK
9
SDA
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
Cleared in software
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
From SSP Interrupt
Service Routine
SSPBUF is written in software
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
2000 Microchip Technology Inc.
DS30605C-page 63
PIC16C63A/65B/73B/74B
10.3.2
MASTER MODE
10.3.3
MULTI-MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET, or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I2C bus may be taken when the P
bit is set, or the bus is idle and both the S and P bits are
clear.
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (an SSP Interrupt will occur, if
enabled):
• Address Transfer
• Data Transfer
• START condition
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM3:SSPM0 = 1011), or with the
slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 10-3: REGISTERS ASSOCIATED WITH I2C OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh
0Ch
8Ch
13h
INTCON
PIR1
GIE
PEIE
T0IE
RCIF
RCIE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
PSPIF
PSPIE
ADIF
ADIE
TXIF SSPIF CCP1IF TMR2IF TMR1IF
TXIE SSPIE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
(1)
(2)
PIE1
SSPBUF Synchronous Serial Port Receive Buffer/Transmit register
2
93h
SSPADD Synchronous Serial Port (I C mode) Address register
14h
SSPCON
SSPSTAT
TRISC
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
(3)
(3)
94h
SMP
CKE
D/A
P
S
R/W
UA
BF
87h
PORTC Data Direction register
Legend: x= unknown, u= unchanged, - = unimplemented locations read as ’0’.
2
Shaded cells are not used by SSP module in I C mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: ADIF and ADIE are reserved on the PIC16C63A/65B; always maintain these bits clear.
2
3: Maintain these bits clear in I C mode.
DS30605C-page 64
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, Serial EEPROMs etc.
11.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bits SPEN (RCSTA<7>) and TRISC<7:6> have to be
set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the universal synchronous asynchro-
nous receiver transmitter.
REGISTER 11-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
R/W-0
BRGH
R-1
R/W-0
TX9D
—
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data. Can be parity bit.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 65
PIC16C63A/65B/73B/74B
REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
R-0
R-0
R-x
—
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
bit 2
Unimplemented: Read as '0'
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
bit 1
bit 0
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data. (Can be parity bit. Calculated by firmware.)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30605C-page 66
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
11.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 11-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
11.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
near the center of each bit time by a majority detect cir-
cuit to determine if a high or a low level is present at the
RX pin.
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
TABLE 11-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(SPBRG+1))
(Synchronous) Baud Rate = FOSC/(4(SPBRG+1))
Baud Rate = FOSC/(16(SPBRG+1))
N/A
TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
98h
18h
99h
TXSTA
RCSTA
CSRC
SPEN
TX9
RX9
TXEN SYNC
SREN CREN
—
—
BRGH
FERR
TRMT TX9D 0000 -010
OERR RX9D 0000 -00x
0000 0000
0000 -010
0000 -00x
0000 0000
SPBRG Baud Rate Generator register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
2000 Microchip Technology Inc.
DS30605C-page 67
PIC16C63A/65B/73B/74B
This interrupt can be enabled/disabled by setting/clear-
ing the USART Transmit Enable bit TXIE (PIE1<4>).
The flag bit TXIF will be set, regardless of the state of
enable bit TXIE and cannot be cleared in software. It
will reset only when new data is loaded into the TXREG
register. While flag bit TXIF indicates the status of the
TXREG register, another bit TRMT (TXSTA<1>) shows
the status of the TSR register. Status bit TRMT is a read
only bit, which is set when the TSR register is empty. No
interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
11.2 USART Asynchronous Mode
In this mode, the USART uses standard non-
return-to-zero (NRZ) format (one START bit, eight or
nine data bits, and one STOP bit). The most common
data format is 8 bits. An on-chip, dedicated, 8-bit baud
rate generator can be used to derive standard baud
rate frequencies from the oscillator. The USART trans-
mits and receives the LSb first. The USART’s transmit-
ter and receiver are functionally independent, but use
the same data format and baud rate. The baud rate
generator produces a clock, either x16 or x64 of the bit
shift rate, depending on bit BRGH (TXSTA<2>). Parity
is not supported by the hardware, but can be imple-
mented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 11-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
11.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
the USART Transmit Flag bit TXIF (PIR1<4>) is set.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 11-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS30605C-page 68
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Steps to follow when setting up an Asynchronous
Transmission:
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set flag bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1)
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. Load data to the TXREG register (starts trans-
mission).
3. If interrupts are desired, set interrupt enable bits
TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
FIGURE 11-2:
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit buffer
reg. empty flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 11-3:
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
START Bit
START Bit
Word 2
Bit 0
Bit 1
Word 1
Bit 7/8
Bit 0
STOP Bit
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 11-3: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
(2)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: u= unchanged, x= unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
2000 Microchip Technology Inc.
DS30605C-page 69
PIC16C63A/65B/73B/74B
ered register, i.e., it is a two-deep FIFO. It is possible
for two bytes of data to be received and transferred to
the RCREG FIFO and a third byte to begin shifting to
the RSR register. On the detection of the STOP bit of
the third byte, if the RCREG register is still full, then
overrun error bit OERR (RCSTA<1>) will be set. The
word in the RSR will be lost. The RCREG register can
be read twice to retrieve the two bytes in the FIFO.
Overrun bit OERR has to be cleared in software. This
is done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, and
no further data will be received; therefore, it is essential
to clear error bit OERR if it is set. Framing error bit
FERR (RCSTA<2>) is set if a STOP bit is detected as
clear. Bit FERR and the 9th receive bit are buffered the
same way as the receive data. Reading the RCREG
will load bits RX9D and FERR with new values, there-
fore, it is essential for the user to read the RCSTA reg-
ister before reading the RCREG register, in order not to
lose the old FERR and RX9D information.
11.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 11-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, USART Receive
Flag bit RCIF (PIR1<5>) is set. This interrupt can be
enabled/disabled by setting/clearing the USART
Receive Enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
FIGURE 11-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
RSR Register
MSb
LSb
÷ 64
or
÷ 16
Baud Rate Generator
1
0
START
STOP (8)
• • •
7
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
DS30605C-page 70
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Steps to follow when setting up an Asynchronous
Reception:
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, set interrupt enable bits
RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
FIGURE 11-5:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the
third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user’s firmware.
TABLE 11-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
1Ah
RCREG USART Receive register
(1)
(2)
8Ch
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
99h
SPBRG Baud Rate Generator register
Legend: u= unchanged, x= unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
2000 Microchip Technology Inc.
DS30605C-page 71
PIC16C63A/65B/73B/74B
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to
hi-impedance. If either bit CREN, or bit SREN is set
during a transmission, the transmission is aborted and
the DT pin reverts to a hi-impedance state (for a recep-
tion). The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from
Hi-impedance Receive mode to transmit and start driv-
ing. To avoid this, bit TXEN should be cleared.
11.2.3
USART SYNCHRONOUS MASTER
MODE
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e., transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
11.2.4
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and inter-
rupt flag bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 11.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set interrupt enable bits
TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 11-6). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 11-7). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally, when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
DS30605C-page 72
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 11-5: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
(1)
(2)
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
18h
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 0000
19h
TXREG USART Transmit Register
(1)
(2)
8Ch
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
98h
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: u= unchanged, x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
FIGURE 11-6:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX/CK
pin
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt Flag)
TRMT bit
’1’
’1’
TXEN bit
Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
FIGURE 11-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit2
bit1
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
2000 Microchip Technology Inc.
DS30605C-page 73
PIC16C63A/65B/73B/74B
Steps to follow when setting up a Synchronous Master
Reception:
11.2.5
USART SYNCHRONOUS MASTER
RECEPTION
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 11.1)
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The interrupt from the USART can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e., it is a
two-deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited,
and no further data will be received; therefore, it is
essential to clear bit OERR if it is set. The ninth receive
bit is buffered the same way as the receive data. Read-
ing the RCREG register will load bit RX9D with a new
value, therefore it is essential for the user to read the
RCSTA register before reading RCREG in order not to
lose the old RX9D information.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set interrupt enable bits
RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
DS30605C-page 74
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 11-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
RCREG USART Receive register
0000 0000 0000 0000
(1)
(2)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator register
Legend: u= unchanged, x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
FIGURE 11-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.
2000 Microchip Technology Inc.
DS30605C-page 75
PIC16C63A/65B/73B/74B
11.3.2
USART SYNCHRONOUS SLAVE
RECEPTION
11.3 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
The operation of the synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Also, bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register. If
interrupt enable bits RCIE and PEIE are set, the inter-
rupt generated will wake the chip from SLEEP. If the
global interrupt is enabled, the program will branch to
the interrupt vector (0004h), otherwise execution will
resume from the instruction following the SLEEP
instruction.
11.3.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a) The first word will immediately transfer to the
TSR register and transmit.
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
2. If interrupts are desired, set interrupt enable bits
RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
e) If interrupt enable bits TXIE and PEIE are set,
the interrupt will wake the chip from SLEEP. If
GIE is set, the program will branch to the inter-
rupt vector (0004h), otherwise execution will
resume from the instruction following the SLEEP
instruction.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up a Synchronous Slave
Transmission:
7. Read the 8-bit received data by reading the
RCREG register.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
8. If any error occurred, clear the error by clearing
bit CREN.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set interrupt enable bits
TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
DS30605C-page 76
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 11-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 0000
0000 000u
0000 0000
(1)
(2)
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
18h
RCSTA
SREN CREN
—
19h
TXREG USART Transmit register
(1)
(2)
8Ch
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
TXEN SYNC BRGH TRMT TX9D
98h
TXSTA
—
99h
SPBRG Baud Rate Generator register
Legend: u= unchanged, x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h
RCSTA
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
1Ah
RCREG USART Receive register
0000 0000 0000 0000
(1)
(2)
8Ch
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
99h
SPBRG Baud Rate Generator register
Legend: u= unchanged, x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
2000 Microchip Technology Inc.
DS30605C-page 77
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 78
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
12.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
Note: The PIC16C63A and PIC16C65B do not
include A/D modules. ADCON0, ADCON1
and ADRES registers are not imple-
mented. ADIF and ADIE bits are reserved
and should be maintained clear.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The 8-bit Analog-to-Digital (A/D) converter module has
five inputs for the PIC16C73B and eight for the
PIC16C74B.
The ADCON0 register, shown in Register 12-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 12-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference),
or as digital I/O.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD), or the
voltage level on the RA3/AN3/VREF pin.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023) and in Application Note,
AN546.
REGISTER 12-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
—
bit 7
bit 0
bit 7-6
bit 5-3
ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from the internal A/D module RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
101= channel 5, (RE0/AN5)(1)
110= channel 6, (RE1/AN6)(1)
111= channel 7, (RE2/AN7)(1)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut-off and consumes no operating current
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C74B only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2000 Microchip Technology Inc.
DS30605C-page 79
PIC16C63A/65B/73B/74B
REGISTER 12-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-3
bit 2-0
Unimplemented: Read as '0'
PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0 RA0
RA1
RA2
RA5
RA3 RE0(1) RE1(1) RE2(1) VREF
000
001
010
011
100
101
11x
A
A
A
A
A
A
D
A
A
A
A
A
A
D
A
A
A
A
D
D
D
A
A
A
A
D
D
D
A
VREF
A
A
A
D
D
D
D
D
A
A
D
D
D
D
D
A
A
D
D
D
D
D
VDD
RA3
VDD
RA3
VDD
RA3
VDD
VREF
A
VREF
D
A = Analog input
D = Digital I/O
Note 1: RE0, RE1 and RE2 are implemented on the PIC16C74B only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30605C-page 80
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The following steps should be followed for doing an A/D
conversion:
3. Wait the required acquisition time.
4. Set GO/DONE bit (ADCON0) to start conversion.
1. Configure the A/D module:
5. Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared (if
interrupts are disabled);
• Configure analog pins, voltage reference,
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit (PIR1<6>)
OR
Waiting for the A/D interrupt.
6. Read A/D result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
• Set ADIE bit (PIE1<6>)
• Set PEIE bit (INTCON<6>)
• Set GIE bit (INTCON<7>)
FIGURE 12-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111
(1)
RE2/AN7
110
(1)
RE1/AN6
101
(1)
RE0/AN5
100
RA5/AN4
VIN
011
(Input Voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
000or
010or
100or
11x
VREF
(Reference
Voltage)
001or
011or
101
PCFG2:PCFG0
Note 1: Not available on PIC16C73B.
2000 Microchip Technology Inc.
DS30605C-page 81
PIC16C63A/65B/73B/74B
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed), the acquisition time (TACQ) must
pass before the conversion can be started.
12.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 12-2. The source impedance affects the
offset voltage at the analog input (due to pin leakage
current).
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
For more information, see the PICmicro™ Mid-Range
MCU Family Reference Manual (DS33023). In general,
however, given a maximum source impedance of
10 kΩ and a worst case temperature of 100°C, TACQ
will be no more than 16 µsec.
FIGURE 12-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6 V
ANx
SS
RIC £ 1k
RSS
Rs
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6 V
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
I leakage = leakage current at the pin due to
various junctions
2V
RIC
= interconnect resistance
= sampling switch
SS
5 6 7 8 9 10 11
Sampling Switch
CHOLD
= sample/hold capacitance (from DAC)
(kΩ)
EQUATION 12-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
TAMP = 5 µS
TC = - (51.2 pF)(1 kΩ + RSS + RS) In(1/511)
TCOFF = (Temp -25°C)(0.05 µS/°C)
DS30605C-page 82
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
12.2 Selecting the A/D Conversion
Clock
12.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
• 2 TOSC
• 8 TOSC
• 32 TOSC
• Internal RC oscillator (2 - 6 µS)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
(parameter #130).
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
12.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
12.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All pins with analog functions
are configured as analog inputs.
2: Analog levels on any pin that is defined as
a digital input, but not as an analog input,
may cause the input buffer to consume
current that is out of the devices specifi-
cation.
The ADRES register will contain unknown data after a
Power-on Reset.
12.7 Use of the CCP Trigger
3: The TRISE register is not provided on the
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
PIC16C73B.
12.4 A/D Conversions
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2 TAD wait
is required before the next acquisition is started. After
this 2 TAD wait, an acquisition is automatically started
on the selected channel. The GO/DONE bit can then
be set to start another conversion.
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
2000 Microchip Technology Inc.
DS30605C-page 83
PIC16C63A/65B/73B/74B
TABLE 12-1: SUMMARY OF A/D REGISTERS (PIC16C73B/74B ONLY)
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE
PSPIF(1)
PSPIE(1)
—
PEIE
ADIF
ADIE
—
T0IE
RCIF
RCIE
—
INTE
TXIF
TXIE
—
RBIE
SSPIF
SSPIE
—
T0IF
CCP1IF
CCP1IE
—
INTF
RBIF
0000 000x
0000 0000
0000 0000
---- ---0
---- ---0
xxxx xxxx
0000 00-0
---- -000
--0x 0000
--11 1111
---- -xxx
0000 -111
0000 000u
0000 0000
0000 0000
---- ---0
---- ---0
uuuu uuuu
0000 00-0
---- -000
--0u 0000
--11 1111
---- -uuu
0000 -111
0Bh,8Bh
0Ch
8Ch
0Dh
8Dh
1Eh
1Fh
TMR2IF
TMR1IF
PIE1
TMR2IE TMR1IE
PIR2
—
—
CCP1IF
CCP1IE
PIE2
—
—
—
—
—
—
ADRES
A/D Result register
ADCON0 ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
PCFG2
—
ADON
ADCON1
—
—
—
—
—
—
PCFG1
PCFG0
9Fh
05h
PORTA
TRISA
PORTE
TRISE
—
RA5
RA4
RA3
RA2
RA1
RA0
85h
—
—
—
—
PORTA Data Direction register
—
—
—
—
09h
RE2
RE1
RE0
89h
IBF
OBF
IBOV
PSPMODE
PORTE Data Direction bits
Legend: x= unknown, u= unchanged, - = unimplemented, read as ’0’. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C63A/73B; always maintain these bits clear.
DS30605C-page 84
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only and is
designed to keep the part in RESET, while the power
supply stabilizes. With these two timers on-chip, most
applications need no external RESET circuitry.
13.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC16CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, WDT wake-up or through an
interrupt.
• Oscillator selection
• RESET
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost, while the LP crystal option
saves power. A set of configuration bits are used to
select various options.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
13.1 Configuration Bits
• Watchdog Timer (WDT)
• SLEEP
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Code protection
• ID locations
• In-Circuit Serial Programming (ICSP)
The user will note that address 2007h is beyond the
user program memory space, and can be accessed
only during programming.
The PIC16CXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
REGISTER 13-1: CONFIGURATION WORD (CONFIG 2007h)
CP1
CP0
CP1
CP0
CP1
CP0
—
BODEN CP1
CP0 PWRTE WDTE FOSC1 FOSC0
bit 0
bit 13
(2)
bits 13-8, CP1:CP0: Code Protection bits
5-4 11= Code protection off
10= Upper half of program memory code protected
01= Upper 3/4th of program memory code protected
00= All memory is code protected
bit 7
bit 6
Unimplemented: Read as '1'
(1)
BODEN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
(1)
bit 3
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of
PWRTE.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
2000 Microchip Technology Inc.
DS30605C-page 85
PIC16C63A/65B/73B/74B
FIGURE 13-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
13.2 Oscillator Configurations
13.2.1 OSCILLATOR TYPES
OSC CONFIGURATION)
The PIC16CXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
OSC1
To internal
logic
C1
C2
• LP
• XT
• HS
• RC
Low Power Crystal
XTAL
OSC2
SLEEP
PIC16CXX
RF
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
RS
(Note 1)
13.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
See Table 13-1 and Table 13-2 for recommended values of C1
and C2.
Note 1: A series resistor may be required for AT strip cut crystals.
In XT, LP, or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 13-1). The
PIC16CXX oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 13-2). See the PICmicro™ Mid-
Range MCU Reference Manual (DS33023) for details
on building an external oscillator.
FIGURE 13-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC CONFIGURATION)
OSC1
Clock from
ext. system
PIC16CXX
OSC2
Open
DS30605C-page 86
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 13-1: CERAMIC RESONATORS
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
Ranges Tested:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Note: These values are for design guidance only.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
See notes following Table 13-1 and Table 13-2.
Resonators Used:
455 kHz Panasonic EFO-A455K04B
2.0 MHz Murata Erie CSA2.00MG
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
16.0 MHz Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
4: Oscillator performance should be verified
at the expected voltage and temperature
extremes in which the application is
expected to operate.
13.2.3
RC OSCILLATOR
Note: Resonators used did not have built-in capacitors.
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. The oscillator frequency will vary from
unit to unit due to normal process variation. The differ-
ence in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 13-3 shows how the
R/C combination is connected to the PIC16CXX.
TABLE 13-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 3-2 for
waveform).
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
FIGURE 13-3:
RC OSCILLATOR MODE
20 MHz
VDD
Note: These values are for design guidance only.
See notes following Table 13-1 and Table 13-2.
REXT
Crystals Used:
Internal
OSC1
Clock
32 kHz
200 kHz
1 MHz
Epson C-001R32.768K-A
STD XTL 200.000KHz
ECS ECS-10-13-1
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
± 30 PPM
± 30 PPM
CEXT
VSS
PIC16CXX
OSC2/CLKOUT
4 MHz
ECS ECS-40-20-1
FOSC/4
8 MHz
EPSON CA-301 8.000M-C
EPSON CA-301 20.000M-C
Recommended Values: REXT = 3 kW to 100 kW
CEXT = 20 pf to 30 pF
20 MHz
2000 Microchip Technology Inc.
DS30605C-page 87
PIC16C63A/65B/73B/74B
on MCLR Reset during SLEEP, and on BOR. The TO
and PD bits are set or cleared differently in different
RESET situations, as indicated in Table 13-4. These
bits are used in software to determine the nature of the
RESET. See Table 13-6 for a full description of RESET
states of all registers.
13.3 RESET
The PIC16CXX differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR)
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 13-4.
The PICmicro devices have a MCLR noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on POR, on the MCLR and WDT Reset,
It should be noted that internal RESET sources do not
drive MCLR pin low.
FIGURE 13-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
10-bit Ripple Counter
Chip Reset
R
Q
OSC1
(Note 1)
PWRT
10-bit Ripple Counter
On-chip
RC OSC
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
DS30605C-page 88
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
13.4.4
BROWN-OUT RESET (BOR)
13.4 RESETS
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
13.4.1
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (parameters D003 and D004, in
the range of 1.5V - 2.1V). To take advantage of the
POR, just tie the MCLR pin directly (or through a resis-
tor) to VDD. This will eliminate external RC components
usually needed to create a POR.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72mS). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset pro-
cess will restart when VDD rises above VBOR with the
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. The device may be held in RESET by keeping
MCLR at Vss.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
13.4.5
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR occurs.
Then, OST starts counting 1024 oscillator cycles when
PWRT ends (LP, XT, HS). When the OST ends, the
device comes out of RESET.
13.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up from the POR. The PWRT oper-
ates on an internal RC oscillator. The device is kept in
RESET as long as the PWRT is active. The PWRT’s
time delay allows VDD to rise to an acceptable level. A
configuration bit is provided to enable/disable the
PWRT.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16CXX device operating in
parallel.
The power-up time delay will vary from chip to chip, due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
Table 13-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 13-6
shows the RESET conditions for all the registers.
13.4.3
OSCILLATOR START-UP TIMER
(OST)
13.4.6
POWER CONTROL/STATUS
REGISTER (PCON)
The Oscillator Start-up Timer provides a delay of 1024
oscillator cycles (from OSC1 input) after the PWRT
delay, if enabled. This helps to ensure that the crystal
oscillator or resonator has started and stabilized.
The Brown-out Reset Status bit, BOR, is unknown on a
POR. It must be set by the user and checked on sub-
sequent RESETS to see if bit BOR was cleared, indi-
cating a BOR occurred. The BOR bit is not predictable
if the Brown-out Reset circuitry is disabled.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
The Power-on Reset Status bit, POR, is cleared on a
POR and unaffected otherwise. The user must set this
bit following a POR and check it on subsequent
RESETS to see if it has been cleared.
2000 Microchip Technology Inc.
DS30605C-page 89
PIC16C63A/65B/73B/74B
TABLE 13-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Brown-out
Wake-up from SLEEP
PWRTE = 0
72 ms + 1024TOSC
72 ms
PWRTE = 1
1024TOSC
—
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
1024TOSC
—
TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
0
BOR
TO
1
PD
1
x
x
x
0
1
1
1
1
Power-on Reset
0
0
x
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
0
x
0
1
1
1
1
0
1
WDT Reset
1
0
0
WDT Wake-up
1
u
u
MCLR Reset during normal operation
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: x= don’t care, u= unchanged
TABLE 13-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
000x xuuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
Interrupt wake-up from SLEEP
PC + 1(1)
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
REGISTER 13-2: STATUS REGISTER
IRP
RP1
RP0
TO
PD
Z
DC
C
REGISTER 13-3: PCON REGISTER
—
—
—
—
—
—
POR
BOR
DS30605C-page 90
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
Register
Applicable Devices
W
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
PCL
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
STATUS
63A 65B 73B 74B
0001 1xxx
FSR
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
uuuu uuuu(1)
-u-- uuuu(1)
-uuu uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
-0-- 0000
-000 0000
0000 0000
0000 0000
---- ---0
-0-- 0000
-000 0000
0000 0000
0000 0000
---- ---0
PIR1
PIR2
---- ---u(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 -00x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 13-5 for RESET value for specific condition.
2000 Microchip Technology Inc.
DS30605C-page 91
PIC16C63A/65B/73B/74B
TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
Register
Applicable Devices
ADCON0
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
--00 0000
0-00 0000
-000 0000
0000 0000
---- ---0
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
--00 0000
0-00 0000
-000 0000
0000 0000
---- ---0
---- --uu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
--uu uuuu
u-uu uuuu
-uuu uuuu
uuuu uuuu
---- ---u
---- --uu
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
---- --0q(3)
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
---- -000
PCON
PR2
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
---- -000
1111 1111
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
---- -uuu
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 13-5 for RESET value for specific condition.
DS30605C-page 92
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
13.5 Interrupts
Note: If an interrupt occurs while the Global Inter-
rupt Enable (GIE) bit is being cleared, the
GIE bit may unintentionally be re-enabled
by the user’s Interrupt Service Routine (the
RETFIE instruction). The events that
would cause this to occur are:
The Interrupt Control register (INTCON) records indi-
vidual interrupt requests in flag bits. It also has individ-
ual and global interrupt enable bits.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit, or the GIE bit.
1. An instruction clears the GIE bit while an
interrupt is acknowledged.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
2. The program branches to the interrupt
vector and executes the Interrupt
Service Routine.
3. The Interrupt Service Routine completes
the execution of the RETFIEinstruction.
This causes the GIE bit to be set
(enables interrupts), and the program
returns to the instruction after the one
which was meant to disable interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
Perform the following to ensure that inter-
rupts are globally disabled:
LOOP BCF
INTCON, GIE ; Disable global
; interrupt bit
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
BTFSC INTCON, GIE ; Global interrupt
; disabled?
GOTO LOOP
:
; NO, try again
; Yes, continue
; with program
; flow
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack, and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or the GIE bit.
2000 Microchip Technology Inc.
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PIC16C63A/65B/73B/74B
FIGURE 13-5:
INTERRUPT LOGIC
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
ADIF
ADIE
T0IF
T0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
–
Yes
Yes
Yes
13.5.1
INT INTERRUPT
13.5.3
PORTB INTERRUPT-ON-CHANGE
The external interrupt on RB0/INT pin is edge trig-
gered: either rising if bit INTEDG (OPTION_REG<6>)
is set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 13.8 for details on SLEEP mode.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
13.5.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (see Section 6.0).
DS30605C-page 94
2000 Microchip Technology Inc.
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The example:
13.6 Context Saving During Interrupts
a) Stores the W register.
During an interrupt, only the return PC value is saved
on the stack. Users may wish to save key registers dur-
ing an interrupt i.e., W register and STATUS register.
This will have to be implemented in software.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the ISR code.
Example 13-1 stores and restores the STATUS, W, and
PCLATH registers. The register W_TEMP must be
defined in each bank and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
e) Restores the STATUS register
(and bank select bit).
f) Restores the W and PCLATH registers.
EXAMPLE 13-1:
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
:
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
(ISR)
:
;User ISR code goes here
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP, W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
13.7.1
WDT PERIOD
13.7 Watchdog Timer (WDT)
The WDT has a nominal time-out period of 18 ms
(parameter #31, TWDT). The time-out periods vary with
temperature, VDD, and process variations. If longer
time-out periods are desired, a prescaler with a division
ratio of up to 1:128 can be assigned to the WDT under
software control, by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. The WDT will run, even if the
clock on the OSC1/CLKIN and OSC2/CLKOUT pins of
the device has been stopped, for example, by execu-
tion of a SLEEPinstruction.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEPinstruction prevents the WDT from generat-
ing a RESET, but will allow the WDT to wake the device
from SLEEP mode.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
2000 Microchip Technology Inc.
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13.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 13-6:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 MUX (Figure 6-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 13-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
BODEN(1)
INTEDG
PWRTE(1)
PSA
Config. bits
–
CP1
CP0
OPTION_REG RBPU
T0CS T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
DS30605C-page 96
2000 Microchip Technology Inc.
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Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
13.8 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the WDT will be cleared but keeps running,
the PD bit (STATUS<3>) is cleared, the TO (STA-
TUS<4>) bit is set, and the oscillator driver is turned off.
The I/O ports maintain the status they had, before the
SLEEP instruction was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
13.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin must be at a logic high level (VIHMC).
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
13.8.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2. SSP (START/STOP) bit detect interrupt.
3. SSP transmit or receive in Slave mode
(SPI/I2C).
4. CCP Capture mode interrupt.
5. Parallel Slave port read or write
(PIC16C65B/74B only).
6. A/D conversion (when A/D clock source is RC).
7. USART TX or RX (Synchronous Slave mode).
2000 Microchip Technology Inc.
DS30605C-page 97
PIC16C63A/65B/73B/74B
FIGURE 13-7:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
(4)
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
(2)
Interrupt Latency
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note
1:
2:
3:
4:
XT, HS or LP oscillator mode assumed.
TOST = 1024Tosc (drawing not to scale). This delay is not present in RC osc mode.
GIE = ’1’ assumed. After wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
13.9 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
After RESET, to place the device into Programming/
Verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data are
then supplied to or from the device, depending if the
command was a load or a read. For complete details of
serial programming, please refer to the PIC16C6X/7X
Programming Specifications (Literature #DS30228).
Note: Microchip does not recommend code pro-
tecting windowed devices. Devices that
are code protected may be erased, but not
programmed again.
13.10 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the four least significant bits of the ID
location are used.
FIGURE 13-8:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
13.11 In-Circuit Serial Programming
PIC16CXX
PIC16CXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
+5V
0V
VDD
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
Data I/O
VDD
To Normal
Connections
DS30605C-page 98
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The instruction set is highly orthogonal and is grouped
into three basic categories:
14.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 14-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 14-1
shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
Table 14-2 lists the instructions recognized by the
MPASMTM assembler.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the address of the
file in which the bit is located.
Figure 14-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
All examples use the following format to represent a
hexadecimal number:
TABLE 14-1: OPCODE FIELD
DESCRIPTIONS
0xhh
Field
Description
where h signifies a hexadecimal digit.
f
W
b
k
Register file address (0x00 to 0x7F)
Working register (accumulator)
FIGURE 14-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Byte-oriented file register operations
13
8
7
6
0
0
Don’t care location (= 0 or 1)
OPCODE
d
f (FILE #)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
x
d
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
label Label name
OPCODE
f (FILE #)
TOS Top-of-Stack
PC Program Counter
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
0
PD Power-down bit
OPCODE
k (literal)
Destination either the W register or the specified
register file location
dest
k = 8-bit immediate value
[ ] Options
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
( ) Contents
→
Assigned to
< > Register bit field
In the set of
k (literal)
∈
italics User defined term (font is courier)
2000 Microchip Technology Inc.
DS30605C-page 99
PIC16C63A/65B/73B/74B
TABLE 14-2: PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d Add W and f
f, d AND W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
f
-
Clear f
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
f
-
Move W to f
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
Z
0000 0110 0100 TO,PD
1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVFPORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicroTM Mid-Range MCU
Family Reference Manual (DS33023).
DS30605C-page 100
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.1 Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
Syntax:
AND W with f
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
[label] ANDWF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(W) + k → (W)
C, DC, Z
Operation:
(W) .AND. (f) → (destination)
Status Affected:
Description:
Z
The contents of the W register are
added to the eight bit literal ’k’ and the
result is placed in the W register.
AND the W register with register 'f'. If
'd' is 0, the result is stored in the W
register. If 'd' is 1, the result is stored
back in register 'f'.
ADDWF
Syntax:
Add W and f
BCF
Bit Clear f
[label] ADDWF f,d
Syntax:
Operands:
[label] BCF f,b
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
(W) + (f) → (destination)
Operation:
0 → (f<b>)
Status Affected: C, DC, Z
Status Affected:
Description:
None
Add the contents of the W register
Description:
Bit 'b' in register 'f' is cleared.
with register ’f’. If ’d’ is 0, the result is
stored in the W register. If ’d’ is 1, the
result is stored back in register ’f’.
ANDLW
AND Literal with W
BSF
Bit Set f
Syntax:
[label] ANDLW
0 ≤ k ≤ 255
k
Syntax:
Operands:
[label] BSF f,b
Operands:
Operation:
Status Affected:
Description:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) .AND. (k) → (W)
Operation:
1 → (f<b>)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W register.
Bit 'b' in register 'f' is set.
2000 Microchip Technology Inc.
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PIC16C63A/65B/73B/74B
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
If bit ’b’ in register ’f’ is ’0’, the next
The contents of register ’f’ are cleared
and the Z bit is set.
Description:
instruction is executed.
If bit ’b’ is ’1’, then the next instruction
is discarded and a NOPis executed
instead making this a 2TCY instruction.
CLRW
Clear W
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] CLRW
None
Syntax:
[label] BTFSC f,b
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
00h → (W)
1 → Z
Operation:
skip if (f<b>) = 0
Status Affected:
Description:
Z
Status Affected: None
W register is cleared. Zero bit (Z) is
set.
If bit ’b’ in register ’f’ is ’1’, the next
Description:
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the next
instruction is discarded, and a NOPis
executed instead, making this a 2 TCY
instruction.
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
Operands:
Operation:
Operands:
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Call Subroutine. First, return address
Description:
(PC+1) is pushed onto the stack. The
eleven bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a two-cycle
instruction.
CLRWDTinstruction resets the Watch-
Description:
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
DS30605C-page 102
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
COMF
Complement f
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
Operands:
[ label ] COMF f,d
Syntax:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected: None
The contents of register ’f’ are comple-
mented. If ’d’ is 0, the result is stored
in W. If ’d’ is 1, the result is stored
back in register ’f’.
GOTOis an unconditional branch. The
Description:
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
DECF
Decrement f
INCF
Increment f
Syntax:
Operands:
[label] DECF f,d
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 127
d ∈ [0,1]
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ’f’. If ’d’ is 0, the
result is stored in the W register. If ’d’
is 1, the result is stored back in
register ’f’.
The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is
placed back in register ’f’.
DECFSZ
Syntax:
Decrement f, Skip if 0
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] DECFSZ f,d
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Status Affected: None
The contents of register ’f’ are decre-
The contents of register ’f’ are incre-
Description:
Description:
mented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is
placed back in register ’f’.
mented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is
placed back in register ’f’.
If the result is 1, the next instruction is
executed. If the result is 0, then a NOP
is executed instead making it a 2 TCY
instruction.
If the result is 1, the next instruction is
executed. If the result is 0, a NOPis
executed instead making it a 2 TCY
instruction.
2000 Microchip Technology Inc.
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PIC16C63A/65B/73B/74B
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
Status Affected:
Description:
(W) .OR. k → (W)
Z
k → (W)
None
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The eight bit literal 'k' is loaded into
W register. The don’t cares will
assemble as 0’s.
IORWF
Inclusive OR W with f
MOVWF
Move W to f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
Status Affected:
Description:
Operation:
(W) .OR. (f) → (destination)
None
Status Affected:
Description:
Z
Move data from W register to
register 'f'.
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
NOP
No Operation
[ label ] NOP
None
MOVF
Move f
Syntax:
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d ∈ [0,1]
No operation
Operation:
(f) → (destination)
Status Affected: None
Status Affected:
Description:
Z
No operation.
Description:
The contents of register f are moved
to a destination dependant upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
DS30605C-page 104
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PIC16C63A/65B/73B/74B
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RLF
Rotate Left f through Carry
Syntax:
Syntax:
Operands:
[ label ] RLF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d ∈ [0,1]
TOS → PC,
1 → GIE
Operation:
See description below
C
None
Status Affected:
Status Affected:
Description:
The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
C
Register f
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
RRF
Rotate Right f through Carry
Syntax:
Syntax:
Operands:
[ label ] RRF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d ∈ [0,1]
k → (W);
TOS → PC
Operation:
See description below
C
Status Affected: None
Status Affected:
Description:
The W register is loaded with the eight
The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
Description:
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
C
Register f
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN
None
SLEEP
Syntax:
[ label ] SLEEP
None
Operands:
Operation:
Operands:
Operation:
TOS → PC
00h → WDT,
0 → WDT prescaler,
1 → TO,
Status Affected: None
Return from subroutine. The stack is
Description:
0 → PD
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped. See
Section 13.8 for more details.
2000 Microchip Technology Inc.
DS30605C-page 105
PIC16C63A/65B/73B/74B
SUBLW
Subtract W from Literal
[ label ] SUBLW k
0 ≤ k ≤ 255
XORLW
Exclusive OR Literal with W
[label] XORLW k
0 ≤ k ≤ 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k - (W) → (W)
(W) .XOR. k → (W)
Z
Status Affected: C, DC, Z
The W register is subtracted (2’s com-
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W
register.
Description:
plement method) from the eight bit lit-
eral 'k'. The result is placed in the W
register.
XORWF
Syntax:
Exclusive OR W with f
SUBWF
Syntax:
Subtract W from f
[label] XORWF f,d
[ label ] SUBWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (destination)
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Z
Status Affected: C, DC, Z
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd'
is 1, the result is stored back in
register 'f'.
Subtract (2’s complement method) W
Description:
register from register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd' is
1, the result is stored back in register 'f'.
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
The upper and lower nibbles of regis-
Description:
ter 'f' are exchanged. If 'd' is 0, the
result is placed in W register. If 'd' is 1,
the result is placed in register 'f'.
DS30605C-page 106
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The MPLAB IDE allows you to:
15.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
15.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD for PIC16F87X
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
15.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
15.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2000 Microchip Technology Inc.
DS30605C-page 107
PIC16C63A/65B/73B/74B
15.4 MPLINK Object Linker/
MPLIB Object Librarian
15.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
15.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
15.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS30605C-page 108
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
15.8 MPLAB ICD In-Circuit Debugger
15.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F87X and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. The MPLAB ICD utilizes
the in-circuit debugging capability built into the
PIC16F87X. This feature, along with Microchip’s
In-Circuit Serial ProgrammingTM protocol, offers cost-
effective in-circuit FLASH debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by watching variables, single-
stepping and setting break points. Running at full
speed enables testing hardware in real-time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
15.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
15.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
15.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2000 Microchip Technology Inc.
DS30605C-page 109
PIC16C63A/65B/73B/74B
15.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
15.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
15.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS30605C-page 110
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 15-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2000 Microchip Technology Inc.
DS30605C-page 111
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 112
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50 - 100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
3: PORTD and PORTE not available on the PIC16C63A/73B.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2000 Microchip Technology Inc.
DS30605C-page 113
PIC16C63A/65B/73B/74B
FIGURE 16-1:
PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC16CXXX-20
3.5 V
3.0 V
2.5 V
2.0 V
20 MHz
Frequency
FIGURE 16-2:
PIC16LC63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
PIC16LCXXX-04
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
10 MHz
Frequency
FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS30605C-page 114
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-3:
PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC16CXXX-04
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
Frequency
2000 Microchip Technology Inc.
DS30605C-page 115
PIC16C63A/65B/73B/74B
16.1 DC Characteristics
Standard Operating Conditions (unless otherwise stated)
PIC16LC63A/65B/73B/74B-04
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
‡PIC16C63A/65B/73B/74B-04
‡PIC16C6A/65B/73B/74B-20
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ† Max
Units
Conditions
VDD Supply Voltage
PIC16LCXXX
D001
2.5
VBOR*
–
–
5.5
5.5
V
V
LP, XT, RC osc modes (DC - 4 MHz)
BOR enabled (Note 7)
PIC16CXXX
D001
D001A
4.0
4.5
VBOR*
–
–
–
5.5
5.5
5.5
V
V
V
XT, RC and LP osc mode
HS osc mode
BOR enabled (Note 7)
D002*
D003
VDR RAM Data Retention
–
–
1.5
–
V
Voltage (Note 1)
VPOR VDD Start Voltage to
ensure internal
VSS
–
V
See section on Power-on Reset for details
Power-on Reset signal
D004*
D004A*
SVDD VDD Rise Rate to
ensure internal
0.05
TBD
–
–
–
–
V/mS PWRT enabled (PWRTE bit clear)
V/mS PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
Power-on Reset signal
D005
VBOR Brown-out Reset
3.65
–
4.35
V
BODEN bit set
voltage trip point
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption. The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with external clock in RC mode.
9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input voltages.
10:Negative current is defined as current sourced by the pin.
DS30605C-page 116
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Standard Operating Conditions (unless otherwise stated)
PIC16LC63A/65B/73B/74B-04
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
‡PIC16C63A/65B/73B/74B-04
‡PIC16C6A/65B/73B/74B-20
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ† Max
Units
Conditions
IDD Supply Current (Notes 2, 5)
PIC16LCXXX
PIC16CXXX
D010
–
–
0.6
2.0
48
mA XT, RC osc modes:
FOSC = 4 MHz, VDD = 3.0V (Note 4)
µA LP osc mode:
D010A
22.5
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D010
D013
–
–
2.7
7
5
mA XT, RC osc modes:
FOSC = 4 MHz, VDD = 5.5 V (Note 4)
mA HS osc mode:
10
FOSC = 20 MHz, VDD = 5.5 V
IPD Power-down Current (Notes 3, 5)
PIC16LCXXX
D020
D021
D021A
–
–
–
7.5
0.9
0.9
20
3
3
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
PIC16CXXX
D020
D021
D021A
D021B
–
–
–
–
10.5
1.5
1.5
42
16
19
19
µA VDD = 4.0V, WDT enabled, -40°C to +85°C
µA VDD = 4.0V, WDT disabled, 0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
µA VDD = 4.0V, WDT disabled, -40°C to +125°C
2.5
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption. The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with external clock in RC mode.
9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input voltages.
10:Negative current is defined as current sourced by the pin.
2000 Microchip Technology Inc.
DS30605C-page 117
PIC16C63A/65B/73B/74B
Standard Operating Conditions (unless otherwise stated)
PIC16LC63A/65B/73B/74B-04
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
‡PIC16C63A/65B/73B/74B-04
‡PIC16C6A/65B/73B/74B-20
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ† Max
Units
Conditions
Module Differential
Current (Note 6)
D022* ∆IWDT Watchdog Timer
D022A* ∆IBOR Brown-out Reset
Input Low Voltage
–
–
6.0
20
µA WDTE bit set, VDD = 4.0V
µA BODEN bit set, VDD = 5.0
100
150
VIL
I/O ports
with TTL buffer
D030
D030A
VSS
VSS
–
–
0.15 VDD
0.8V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
D031
D032
D033
with Schmitt
Trigger buffer
VSS
Vss
Vss
–
–
–
0.2 VDD
0.2 VDD
0.3 VDD
V
V
V
MCLR, OSC1
(in RC mode)
OSC1 (in XT, HS, and
LP modes)
(Note 8)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption. The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with external clock in RC mode.
9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input voltages.
10:Negative current is defined as current sourced by the pin.
DS30605C-page 118
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Standard Operating Conditions (unless otherwise stated)
PIC16LC63A/65B/73B/74B-04
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
‡PIC16C63A/65B/73B/74B-04
‡PIC16C6A/65B/73B/74B-20
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ† Max
Units
Conditions
Input High Voltage
VIH I/O ports
with TTL buffer
2.0
D040
–
–
VDD
VDD
V
V
4.5 V ≤ VDD ≤ 5.5V
D040A
0.25 VDD +
0.8V
For entire VDD range
D041
with Schmitt
0.8 VDD
–
VDD
V
For entire VDD range
Trigger buffer
D042
MCLR
0.8 VDD
–
–
VDD
VDD
V
V
D042A
OSC1 (in XT, HS, and 0.7 VDD
LP modes)
(Note 8)
D043
D060
OSC1 (in RC mode)
0.9 VDD
–
–
VDD
V
Input Leakage
Current (Notes 9, 10)
IIL
I/O ports
–
±1
µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
–
–
–
–
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD,
XT, HS and LP osc modes
D070
IPURB PORTB Weak Pull-up
50
250
400
µA VDD = 5V, VPIN = VSS
Current
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption. The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with external clock in RC mode.
9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input voltages.
10:Negative current is defined as current sourced by the pin.
2000 Microchip Technology Inc.
DS30605C-page 119
PIC16C63A/65B/73B/74B
Standard Operating Conditions (unless otherwise stated)
PIC16LC63A/65B/73B/74B-04
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
‡PIC16C63A/65B/73B/74B-04
‡PIC16C6A/65B/73B/74B-20
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ† Max
Units
Conditions
Output Low Voltage
VOL I/O ports
D080
–
–
–
–
–
–
–
–
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083
OSC2/CLKOUT
(RC osc mode)
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
Output High Voltage
D090
D092
D150*
VOH I/O ports (Note 10)
VDD-0.7
VDD-0.7
VDD-0.7
VDD-0.7
–
–
–
–
–
–
–
–
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
OSC2/CLKOUT
(RC osc mode)
–
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
–
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
VOD Open-Drain
8.5
RA4 pin
High Voltage
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption. The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with external clock in RC mode.
9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input voltages.
10:Negative current is defined as current sourced by the pin.
DS30605C-page 120
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Standard Operating Conditions (unless otherwise stated)
PIC16LC63A/65B/73B/74B-04
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
‡PIC16C63A/65B/73B/74B-04
‡PIC16C6A/65B/73B/74B-20
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ† Max
Units
Conditions
Capacitive Loading
Specs on
Output Pins
D100
D101
D102
COSC2 OSC2 pin
–
–
–
–
–
–
15
50
pF In XT, HS and LP modes when external
clock is used to drive OSC1
CIO All I/O pins and OSC2
(in RC mode)
pF
Cb SCL, SDA
(in I2C mode)
400
pF
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption. The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with external clock in RC mode.
9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input voltages.
10:Negative current is defined as current sourced by the pin.
2000 Microchip Technology Inc.
DS30605C-page 121
PIC16C63A/65B/73B/74B
16.2 AC (Timing) Characteristics
16.2.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
rw
sc
ss
t0
OSC1
RD
RD or WR
SCK
ck
cs
di
SDI
do
dt
io
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
t1
wr
mc
Uppercase letters and their meanings:
S
F
H
I
Fall
High
P
R
V
Z
Period
Rise
Valid
Hi-impedance
Invalid (Hi-impedance)
Low
L
I2C only
AA
BUF
output access
Bus free
High
Low
High
Low
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
DS30605C-page 122
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.2.2
TIMING CONDITIONS
The temperature and voltages specified in Table 16-1
apply to all timing specifications unless otherwise
noted. Figure 16-4 specifies the load conditions for the
timing specifications.
TABLE 16-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 16.1.
LC parts operate for commercial/industrial temperatures only.
FIGURE 16-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
but including D and E outputs as ports
VSS
CL = 15 pF for OSC2 output
Note 1: PORTD and PORTE are not implemented on the PIC16C63A/73B.
2000 Microchip Technology Inc.
DS30605C-page 123
PIC16C63A/65B/73B/74B
16.2.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 16-5:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
4
Q4
Q1
OSC1
3
3
1
4
2
CLKOUT
TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
Sym
Characteristic
Min Typ†
Max
Units
Conditions
No.
1A
FOSC External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
MHz RC and XT osc modes
MHz HS osc mode (-04)
MHz HS osc mode (-20)
kHz LP osc mode
(Note 1)
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
20
200
—
MHz HS osc mode
5
kHz LP osc mode
1
TOSC External CLKIN Period
250
250
50
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
RC and XT osc modes
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
(Note 1)
—
—
5
—
Oscillator Period
(Note 1)
250
250
250
50
—
RC osc mode
XT osc mode
10,000
250
250
—
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
5
2
TCY Instruction Cycle Time (Note 1)
200
DC
—
TCY = 4/FOSC
3*
TosL, External Clock in (OSC1) High or 100
TosH Low Time
XT oscillator
2.5
—
LP oscillator
15
—
HS oscillator
4*
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
—
25
XT oscillator
50
LP oscillator
15
HS oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “Max.” cycle time limit is
“DC” (no clock) for all devices.
DS30605C-page 124
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-6:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
10* TosH2ckL
11* TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
—
—
50
—
200
200
100
100
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
OSC1↑ to CLKOUT↓
—
12* TckR
13* TckF
CLKOUT rise time
CLKOUT fall time
—
—
14* TckL2ioV CLKOUT ↓ to Port out valid
15* TioV2ckH Port in valid before CLKOUT ↑
—
0.5TCY + 20 ns
TOSC + 200
—
—
ns
ns
ns
ns
16* TckH2ioI
Port in hold after CLKOUT ↑
0
17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
—
150
—
18*
OSC1↑ (Q2 cycle) to Port PIC16CXX
100
TosH2ioI
input invalid (I/O in hold
18A*
PIC16LCXX
time)
200
0
—
—
—
—
ns
ns
Port input valid to OSC1↑ (I/O in setup
time)
19* TioV2osH
20*
PIC16CXX
Port output rise time
—
—
10
—
10
—
—
—
40
80
40
80
—
—
ns
ns
ns
ns
ns
ns
TioR
20A*
PIC16LCXX
21*
TioF
21A*
PIC16CXX
Port output fall time
—
PIC16LCXX
—
22††* Tinp
23††* Trbp
INT pin high or low time
TCY
TCY
RB7:RB4 change INT high or low time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2000 Microchip Technology Inc.
DS30605C-page 125
PIC16C63A/65B/73B/74B
FIGURE 16-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note:
Refer to Figure 16-4 for load conditions.
FIGURE 16-8:
BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param No. Sym Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
—
—
µs VDD = 5V, -40°C to +125°C
ms VDD = 5V, -40°C to +125°C
Watchdog Timer Time-out
Period (No Prescaler)
31*
TWDT
TOST
7
18
33
Oscillation Start-up Timer
Period
32
33*
34
—
28
—
1024 TOSC
—
132
2.1
—
—
TOSC = OSC1 period
TPWRT Power-up Timer Period
72
—
—
ms VDD = 5V, -40°C to +125°C
µs
I/O Hi-impedance from MCLR
Low or WDT Reset
TIOZ
35
TBOR Brown-out Reset Pulse Width 100
µs VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
DS30605C-page 126
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-9:
T0CKI
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
T0CKI High Pulse Width
Min
Typ† Max Units
Conditions
40*
Tt0H
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20
10
ns Must also meet
parameter 42
ns
TCY + 40
ns
With Prescaler Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4,..., 256)
N
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
PIC16CXX
PIC16LCXX
PIC16CXX
PIC16LCXX
15
ns
25
ns
Asynchronous
30
ns
50
ns
T1CKI Low Time Synchronous, Prescaler = 1
0.5TCY + 20
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
PIC16CXX
PIC16LCXX
PIC16CXX
PIC16LCXX
PIC16CXX
15
25
30
50
ns
ns
ns
ns
Asynchronous
Synchronous
T1CKI input
period
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
PIC16LCXX
Greater of:
50 or TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous
PIC16CXX
60
100
DC
—
—
—
—
—
ns
ns
PIC16LCXX
Ft1
Timer1 oscillator input frequency range
200 kHz
(oscillator enabled by setting bit T1OSCEN)
48
TCKEZtmr1 Delay from external clock edge to timer increment
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
2TOSC
—
7TOSC
—
*
†
2000 Microchip Technology Inc.
DS30605C-page 127
PIC16C63A/65B/73B/74B
FIGURE 16-10:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture mode)
50
51
52
54
CCPx
(Compare or PWM mode)
53
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
Sym
Characteristic
Min
Typ† Max Units Conditions
No.
50* TccL CCP1 and
CCP2
No Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
With Prescaler PIC16CXX
PIC16LCXX
10
ns
input low time
20
0.5TCY + 20
10
ns
51* TccH CCP1 and
CCP2
No Prescaler
ns
With Prescaler PIC16CXX
PIC16LCXX
ns
input high time
20
ns
52* TccP CCP1 and CCP2 input period
3TCY + 40
N
ns N = prescale
value (1,4, or 16)
53* TccR CCP1 and CCP2 output rise time PIC16CXX
PIC16LCXX
—
—
—
—
10
25
10
25
25
45
25
45
ns
ns
ns
ns
54* TccF CCP1 and CCP2 output fall time PIC16CXX
PIC16LCXX
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
DS30605C-page 128
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-11:
PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Param No.
Sym
Characteristic
Min Typ† Max Units
Conditions
62*
63*
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20
—
—
—
—
—
—
—
—
80
30
ns
ns
ns
ns
ns
TwrH2dtI
20
35
—
10
WR↑ or CS↑ to data in
PIC16CXX
invalid (hold time)
PIC16LCXX
64
TrdL2dtV
TrdH2dtI
RD↓ and CS↓ to data out valid
RD↑ or CS↑ to data out invalid
65*
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
2000 Microchip Technology Inc.
DS30605C-page 129
PIC16C63A/65B/73B/74B
FIGURE 16-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
Symbol
Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
—
ns
71
71A
72
TscH
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
40
1.25TCY + 30
40
ns (Note 1)
TscL
ns
SCK input low time
(Slave mode)
72A
73
ns (Note 1)
TdiV2scH,
TdiV2scL
100
ns
Setup time of SDI data input to SCK edge
73A
74
TB2B
1.5TCY + 40
100
—
—
—
—
ns (Note 1)
Last clock edge of Byte1 to the 1st clock
edge of Byte2
TscH2diL,
TscL2diL
ns
Hold time of SDI data input to SCK edge
75
TdoR
—
—
—
—
—
—
—
—
10
20
10
10
20
10
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
SDO data output rise time PIC16CXX
PIC16LCXX
76
78
TdoF
TscR
SDO data output fall time
SCK output rise time
(Master mode)
PIC16CXX
PIC16LCXX
79
80
TscF
SCK output fall time (Master mode)
TscH2doV,
TscL2doV
SDO data output valid
after SCK edge
PIC16CXX
PIC16LCXX
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605C-page 130
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param
Symbol
TscH
TscL
Characteristic
Min
Typ† Max Units Conditions
No.
71
71A
72
SCK input high time
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
(Slave mode)
40
1.25TCY + 30
40
ns (Note 1)
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns (Note 1)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
75
TdoR
SDO data output rise
time
PIC16CXX
—
10
20
10
10
20
10
—
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LCXX
76
78
TdoF
TscR
SDO data output fall time
—
—
SCK output rise time
(Master mode)
PIC16CXX
PIC16LCXX
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16CXX
PIC16LCXX
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
2000 Microchip Technology Inc.
DS30605C-page 131
PIC16C63A/65B/73B/74B
FIGURE 16-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param
Symbol
Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
—
ns
71
71A
72
TscH
TscL
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
40
1.25TCY + 30
40
ns (Note 1)
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns (Note 1)
74
75
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
TdoR
SDO data output rise time PIC16CXX
PIC16LCXX
—
10
20
10
—
25
45
25
50
ns
ns
ns
ns
76
77
TdoF
SDO data output fall time
—
TssH2doZ
10
SS↑ to SDO output hi-impedance
78
TscR
SCK output rise time
(Master mode)
PIC16CXX
—
10
20
10
—
—
—
25
45
ns
ns
ns
ns
ns
ns
PIC16LCXX
79
80
TscF
SCK output fall time (Master mode)
—
—
25
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16CXX
50
PIC16LCXX
100
—
83
TscH2ssH,
TscL2ssH
1.5TCY + 40
SS ↑ after SCK edge
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605C-page 132
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
Symbol
Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH,
TssL2scL
TCY
—
—
ns
SS↓ to SCK↓ or SCK↑ input
Continuous
1.25TCY + 30
—
—
—
—
—
—
—
—
ns
71
71A
72
SCK input high time
(Slave mode)
TscH
TscL
TB2B
Single Byte
Continuous
Single Byte
40
1.25TCY + 30
40
ns (Note 1)
ns
SCK input low time
(Slave mode)
ns (Note 1)
72A
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns (Note 1)
73A
74
TscH2diL,
TscL2diL
100
ns
Hold time of SDI data input to SCK edge
PIC16CXX
—
10
20
10
25
45
25
ns
ns
ns
SDO data output rise
time
TdoR
75
PIC16LCXX
TdoF
—
76
77
SDO data output fall time
TssH2doZ
10
—
—
—
—
—
—
—
—
10
20
10
—
—
—
—
50
25
ns
ns
ns
ns
ns
ns
ns
ns
SS↑ to SDO output hi-impedance
PIC16CXX
SCK output rise time
(Master mode)
TscR
78
79
80
PIC16LCXX
45
TscF
25
SCK output fall time (Master mode)
PIC16CXX
50
TscH2doV,
TscL2doV
SDO data output valid
after SCK edge
PIC16LCXX
PIC16CXX
PIC16LCXX
100
50
SDO data output valid
after SS↓ edge
TssL2doV
82
83
100
TscH2ssH,
TscL2ssH
1.5TCY + 40
—
—
ns
SS ↑ after SCK edge
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
2000 Microchip Technology Inc.
DS30605C-page 133
PIC16C63A/65B/73B/74B
FIGURE 16-16:
I2C BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
STOP
Condition
START
Condition
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-12: I2C BUS START/STOP BITS REQUIREMENTS
Param
Sym
Characteristic
Min Typ Max Units
Conditions
No.
90*
TSU:STA START condition 100 kHz mode
Setup time 400 kHz mode
THD:STA START condition 100 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
START condition
91*
92*
93
4000
600
ns After this period the first clock
pulse is generated
Hold time
TSU:STO STOP condition
Setup time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
ns
THD:STO STOP condition
Hold time
4000
600
ns
* These parameters are characterized but not tested.
FIGURE 16-17:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note:
Refer to Figure 16-4 for load conditions.
DS30605C-page 134
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 16-13: I2C BUS DATA REQUIREMENTS
Param.
No.
Sym
Characteristic
100 kHz mode
Min
Max Units
Conditions
100*
THIGH
Clock high time
4.0
—
—
µs
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101*
TLOW
Clock low time
100 kHz mode
µs
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
SSP Module
1.3
—
Device must operate at a
minimum of 10 MHz
1.5TCY
—
102*
103*
TR
TF
SDA and SCL rise 100 kHz mode
time
—
1000
ns
ns
400 kHz mode 20 + 0.1Cb 300
Cb is specified to be from
10-400 pF
SDA and SCL fall
time
100 kHz mode
—
300
ns
ns
400 kHz mode 20 + 0.1Cb 300
Cb is specified to be from
10-400 pF
90*
91*
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for Repeated
START condition
THD:STA START condition
hold time
—
After this period the first
clock pulse is generated
—
106*
107*
92*
THD:DAT Data input hold time 100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data input setup
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO STOP condition
setup time
—
—
109*
110*
TAA
Output valid from
clock
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
Cb
Bus capacitive loading
—
400
pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the
requirement Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the stan-
dard mode I2C bus specification) before the SCL line is released.
2000 Microchip Technology Inc.
DS30605C-page 135
PIC16C63A/65B/73B/74B
FIGURE 16-18:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 16-4 for load conditions.
122
TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Sym
Characteristic
Min Typ† Max
Units Conditions
No.
120* TckH2dtV SYNC XMIT (MASTER &
SLAVE)
PIC16CXX
—
—
—
—
80
ns
ns
PIC16LCXX
100
Clock high to data out valid
121* Tckrf
122* Tdtrf
Clock out rise time and fall
time (Master mode)
PIC16CXX
—
—
—
—
—
—
—
—
45
50
45
50
ns
ns
ns
ns
PIC16LCXX
Data out rise time and fall time PIC16CXX
PIC16LCXX
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
FIGURE 16-19:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
125*
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup
time)
15
15
—
—
—
—
ns
ns
126*
TckL2dtl
Data hold after CK ↓ (DT hold time)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
DS30605C-page 136
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 16-16: A/D CONVERTER CHARACTERISTICS:
PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR Resolution
PIC16CXX
—
—
8 bits
bit VREF = VDD = 5.12 V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 2.5 V
PIC16LCXX
—
—
—
—
8 bits
< ± 1
bit
VREF = VDD = 5.12 V,
Vss ≤ VAIN ≤ VREF
VREF = VDD = 5.12 V,
Vss ≤ VAIN ≤ VREF
VREF = VDD = 5.12 V,
Vss ≤ VAIN ≤ VREF
VREF = VDD = 5.12 V,
Vss ≤ VAIN ≤ VREF
VREF = VDD = 5.12 V,
Vss ≤ VAIN ≤ VREF
Vss ≤ VAIN ≤ VREF
A02
A03
A04
A05
A06
EABS Total Absolute error
EIL Integral linearity error
EDL Differential linearity error
EFS Full scale error
LSb
—
—
—
—
—
—
—
—
< ± 1
< ± 1
< ± 1
< ± 1
LSb
LSb
LSb
LSb
EOFF Offset error
A10
A20
A25
A30
—
Monotonicity (Note 3)
—
2.5V
guaranteed
—
—
V
VREF Reference voltage
VAIN Analog input voltage
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VSS - 0.3
—
V
ZAIN Recommended impedance of
analog voltage source
kΩ
Average current
consumption when A/D
is on (Note 1)
During VAIN acquisition
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 12.1
During A/D Conversion
cycle
A40
A50
IAD A/D conversion PIC16CXX
—
—
180
90
—
—
µA
µA
current (VDD)
PIC16LCXX
IREF VREF input current (Note 2)
10
—
1000
µA
—
—
10
µA
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2000 Microchip Technology Inc.
DS30605C-page 137
PIC16C63A/65B/73B/74B
FIGURE 16-20:
A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 16-17: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
130
TAD A/D clock period
PIC16CXX
1.6
2.0
—
—
—
—
µs TOSC based, VREF ≥ 3.0 V
PIC16LCXX
µs TOSC based,
2.5V ≤ VREF ≤ 5.5 V
PIC16CXX
2.0
3.0
11
4.0
6.0
—
6.0
9.0
11
µs A/D RC mode
µs A/D RC mode
TAD
PIC16LCXX
131 TCNV Conversion time (not including S/H
time) (Note 1)
132 TACQ Acquisition time
5*
—
—
µs The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1 LSb
(i.e., 20.0mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
134
TGO Q4 to A/D clock start
—
TOSC/2
—
—
—
If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 TSWC Switching from convert → sample time 1.5
—
TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 for minimum conditions.
DS30605C-page 138
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The data presented in this section is a statistical sum-
mary of data collected on units from different lots over
a period of time.
17.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Note: Standard deviation is denoted by sigma (σ).
The graphs and tables provided in this section are for
design guidance and are not tested nor guaranteed. In
some graphs or tables the data presented is outside
specified operating range (e.g., outside specified VDD
range). This is for information only and devices are
ensured to operate properly only within the specified
range.
• Typ or Typical represents the mean of the
distribution at 25°C.
• Max or Maximum represents the mean + 3σ over
the temperature range of -40°C to 85°C.
• Min or Minimum represents the mean - 3σ over
the temperature range of -40°C to 85°C.
2000 Microchip Technology Inc.
DS30605C-page 139
PIC16C63A/65B/73B/74B
FIGURE 17-1:
TYPICAL IDD vs. FOSC OVER VDD – HS MODE
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
7
6
5
4
3
2
1
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
0
4
6
8
10
12
14
16
18
20
FOSC (MHz)
FIGURE 17-2:
MAXIMUM IDD vs. FOSC OVER VDD – HS MODE
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
7
6
5
4
3
2
1
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
0
4
6
8
10
12
14
16
18
20
FOSC (MHz)
DS30605C-page 140
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 17-3:
TYPICAL IDD vs. FOSC OVER VDD – LP MODE
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
100
90
80
70
60
50
40
30
20
10
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
0
30
40
50
60
70
80
90
100
FOSC (kHz)
FIGURE 17-4:
MAXIMUM IDD vs. FOSC OVER VDD – LP MODE
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
160
140
120
100
80
5.5 V
5.0 V
4.5 V
60
4.0 V
3.5 V
40
3.0 V
2.5 V
20
0
30
40
50
60
70
80
90
100
FOSC (kHz)
2000 Microchip Technology Inc.
DS30605C-page 141
PIC16C63A/65B/73B/74B
FIGURE 17-5:
TYPICAL IDD vs. FOSC OVER VDD – XT MODE
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 17-6:
MAXIMUM IDD vs. FOSC OVER VDD – XT MODE
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS30605C-page 142
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 17-7:
AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 20 PF
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Not recommended for operation over 4 MHz
3.3 k
5.1 k
10 k
100 k
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-8:
AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 100 PF
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.5
2.0
1.5
1.0
0.5
3.3 k
5.1 k
10 k
100 k
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2000 Microchip Technology Inc.
DS30605C-page 143
PIC16C63A/65B/73B/74B
FIGURE 17-9:
AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 300 PF
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1,000
900
800
700
600
500
400
300
200
100
3.3 k
5.1 k
10 k
100 k
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-10:
VTH vs. VDD OVER TEMPERATURE – TTL INPUT
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Max (-40°C)
Typ (25°C)
Min (125°C)
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30605C-page 144
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 17-11:
VIL, VIH vs. VDD OVER TEMPERATURE – SCHMITT TRIGGER INPUT (I2C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VIH Typ (25°C)
VIH Max (125°C)
VIH Min (-40°C)
VIL Max (125°C)
VIL Min (-40°C)
VIL Typ (25°C)
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-12:
VIL, VIH vs. VDD OVER TEMPERATURE – SCHMITT TRIGGER INPUT
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VIH Max (125°C)
VIH Typ (25°C)
VIH Min (-40°C)
VIL Max (125°C)
VIL Typ (25°C)
VIL Min (-40°C)
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2000 Microchip Technology Inc.
DS30605C-page 145
PIC16C63A/65B/73B/74B
FIGURE 17-13:
VOH vs. IOH AT VDD = 3.0 V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (-40°C)
Typical (25°C)
Min (125°C)
0.0
0
5
10
15
20
25
IOH (mA)
FIGURE 17-14:
VOH vs. IOH AT VDD = 5.0 V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (-40°C)
Typical (25°C)
Min (125°C)
0.0
0
5
10
15
20
25
IOH (mA)
DS30605C-page 146
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 17-15:
VOL vs. IOL AT VDD = 3.0 V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Max (125°C)
Typ (25°C)
Min (-40°C)
0.0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
IOL (-mA)
FIGURE 17-16:
VOL vs. IOL AT VDD = 5.0 V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Max (125°C)
Typ (25°C)
Min (-40°C)
0.0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
IOL (-mA)
2000 Microchip Technology Inc.
DS30605C-page 147
PIC16C63A/65B/73B/74B
FIGURE 17-17:
IPD vs. VDD (85°C) – SLEEP MODE, ALL PERIPHERALS DISABLED
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
140
120
100
80
Max 85°C
60
Typ 85°C
40
20
Max 25°CMax -40°C
0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
FIGURE 17-18:
IPD vs. VDD (125°C) – SLEEP MODE, ALL PERIPHERALS DISABLED
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1,400
1,200
1,000
800
Max (125°C)
600
Typ (125°C)
400
200
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30605C-page 148
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 17-19:
∆IBOR vs. VDD OVER TEMPERATURE (-40°C TO +125°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
200
180
160
140
120
100
80
Max (125°C)
Typ (25°C)
Device
in
SLEEP
Indeterminant
State
Device
in
Max (125°C)
Typ (25°C)
RESET
60
RESET current depends on
oscillator mode, frequency, and
circuit.
40
20
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-20:
∆ITIMER1 vs. VDD (-10°C TO +70°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
120
100
80
Max (-10°C to 70°C)
60
Typical (25°C)
40
20
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2000 Microchip Technology Inc.
DS30605C-page 149
PIC16C63A/65B/73B/74B
FIGURE 17-21:
∆IWDT vs. VDD (-40°C TO +125°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
20
18
16
14
12
10
8
Max (-40°C to 125°C)
Typical (25°C)
6
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-22:
WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
40
35
30
25
20
15
10
5
Maximum (125°C)
Typical (25°C)
Minimum (-40°C)
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30605C-page 150
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 17-23:
AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
40
35
30
25
20
15
10
5
125°C
85°C
25°C
-40°C
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2000 Microchip Technology Inc.
DS30605C-page 151
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 152
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.0 PACKAGING INFORMATION
18.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16C73B-04/SP
0017HAT
28-Lead CERDIP Windowed
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
PIC16C73B/JW
0017CAT
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC16C73B-20/SO
YYWWNNN
0017SAA
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC16C73B-
20I/SS025
0017SBP
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2000 Microchip Technology Inc.
DS30605C-page 153
PIC16C63A/65B/73B/74B
Package Marking Information (Cont’d)
40-Lead PDIP
Example
PIC16C74B-04/P
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
0017SAA
40-Lead CERDIP Windowed
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C74B/JW
YYWWNNN
0017HAT
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16C74B
-20/PT
0017HAT
44-Lead MQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16C74B
-20/PQ
0017SAT
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16C74B
-20/L
0017SAT
DS30605C-page 154
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.2 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
1
n
α
E
A2
L
A
c
B1
β
A1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
2000 Microchip Technology Inc.
DS30605C-page 155
PIC16C63A/65B/73B/74B
18.3 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
E1
W2
D
2
1
n
W1
E
A2
A
c
L
B1
B
A1
eB
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.183
.160
.023
.313
.290
1.458
.140
.010
.058
.019
.385
.140
.300
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.195
4.32
3.94
4.64
4.06
0.57
7.94
7.37
37.02
3.56
0.25
1.46
0.47
9.78
3.56
7.62
4.95
A2
A1
.155
.015
.300
.285
1.430
.135
.008
.050
.016
.345
.130
.290
.165
.030
.325
.295
1.485
.145
.012
.065
.021
.425
.150
.310
4.19
0.76
8.26
7.49
37.72
3.68
0.30
1.65
0.53
10.80
3.81
7.87
0.38
7.62
7.24
36.32
3.43
0.20
1.27
0.41
8.76
3.30
7.37
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
B1
B
§
eB
W1
W2
Window Length
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-058
Drawing No. C04-080
DS30605C-page 156
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.4 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
1
n
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
2000 Microchip Technology Inc.
DS30605C-page 157
PIC16C63A/65B/73B/74B
18.5 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
n
1
α
A
c
A2
A1
φ
L
β
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.396
.022
.004
0
.072
.010
.319
.212
.407
.037
.010
8
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
§
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
DS30605C-page 158
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.6 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
1
α
n
E
A2
A
L
c
B1
B
β
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
eB
α
β
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
5
10
15
5
10
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
2000 Microchip Technology Inc.
DS30605C-page 159
PIC16C63A/65B/73B/74B
18.7 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
D
2
n
1
E
A2
L
c
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.205
.160
.045
.600
.520
2.050
.140
.011
.053
.020
.660
.350
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.185
.225
4.70
3.94
5.21
4.06
5.72
A2
A1
.155
.030
.595
.514
2.040
.135
.008
.050
.016
.610
.340
.165
.060
.625
.526
2.060
.145
.014
.055
.023
.710
.360
4.19
1.52
0.76
15.11
13.06
51.82
3.43
1.14
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
15.24
13.21
52.07
3.56
15.88
13.36
52.32
3.68
Tip to Seating Plane
Lead Thickness
c
0.20
0.28
0.36
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
B
1.27
1.33
1.40
B1
eB
W
0.41
0.51
0.58
§
15.49
8.64
16.76
8.89
18.03
9.14
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-103
Drawing No. C04-014
DS30605C-page 160
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.8 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form
(TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
φ
β
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
CH
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
2000 Microchip Technology Inc.
DS30605C-page 161
PIC16C63A/65B/73B/74B
18.9 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead
Form (MQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
c
n
°
CH x 45
α
A1
A
φ
β
(F)
L
A2
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.079
.077
.002
.029
.086
.080
.006
.035
.063
3.5
.093
2.00
1.95
2.18
2.03
0.15
0.88
1.60
3.5
2.35
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.083
.010
.041
2.10
0.25
1.03
§
0.05
0.73
Foot Length
Footprint (Reference)
Foot Angle
0
.510
.510
.390
.390
.005
.012
.025
5
7
.530
.530
.398
.398
.009
.018
.045
15
0
12.95
12.95
9.90
9.90
0.13
0.30
0.64
5
7
13.45
13.45
10.10
10.10
0.23
0.45
1.14
15
Overall Width
E
D
.520
.520
.394
.394
.007
.015
.035
10
13.20
13.20
10.00
10.00
0.18
0.38
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-022
Drawing No. C04-071
DS30605C-page 162
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.10 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45°
CH1 x 45°
α
A3
A2
A
35°
B1
B
c
A1
β
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.050
11
1.27
11
Pins per Side
Overall Height
n1
A
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
2000 Microchip Technology Inc.
DS30605C-page 163
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 164
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
7/98
This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234, and
the PIC16C7X Data Sheet, DS30390.
B
1/99
Corrections to Version A data sheet for technical accuracy.
Added data:
• Operation of the SMP and CKE bits of the SSPSTAT register in I2C mode
have been specified
• Frequency vs. VDD graphs for device operating area (in Electrical
Specifications)
• Formula for calculating A/D acquisition time, TACQ (in the A/D section)
• Brief description of instructions
Removed data (see PICmicroTM Mid-Range MCU Family Reference Manual,
DS33023, for additional data):
• USART Baud Rate Tables (formulas for calculating baud rate remain)
• Minor changes to text to clarify content
C
12/00
• Revised some DC specifications
• Included characteristic charts and graphs
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet are listed in Table B-1.
TABLE B-1:
Difference
DEVICE DIFFERENCES
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
A/D
no
no
5 channels, 8 bits
no
8 channels, 8 bits
yes
Parallel Slave Port
Packages
no
yes
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
SSOP
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
MQFP, 44-pin PLCC
MQFP, 44-pin PLCC SSOP
2000 Microchip Technology Inc.
DS30605C-page 165
PIC16C63A/65B/73B/74B
APPENDIX C: DEVICE MIGRATIONS -
PIC16C63/65A/73A/74A → PIC16C63A/65B/73B/74B
This document is intended to describe the functional differences and the electrical specification differences that are
present when migrating from one device to the next. Table C-1 shows functional differences, while Table C-2 shows
electrical and timing differences.
Note: Even though compatible devices are specified to be tested to the same electrical specification, the device
characteristics may be different from each other (due to process differences). For systems that were
designed to the device specifications, these process differences should not cause any issues in the appli-
cation. For systems that did not tightly meet the electrical specifications, the process differences may cause
the device to behave differently in the application.
Note: While there are no functional or electrical changes to the device oscillator specifications, the user should
verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values
and/or the oscillator mode may be required.
TABLE C-1:
No. Module
FUNCTIONAL DIFFERENCES
Differences from PIC16C63/65A/73A/74A
H/W S/W Prog.
1
2
3
4
5
6
7
CCP
CCP Special Event Trigger clears Timer1.
Compare mode drives pin correctly.
—
—
—
—
—
—
—
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
—
Timers Writing to TMR1L does not affect TMR1H.
WDT/TMR0 prescaler assignment changes do not affect TMR0 count.
SSP
TMR2 SPI clock synchronized to start of SPI Transmission.
Can now transmit multiple words in SPI mode.
Supports all four SPI modes. (Now uses SSP vs. BSSP module.)
See SSP module in the PICmicro™ Mid-Range MCU Family Reference Man-
ual (DS33023).
8
9
I2C no longer generates ACK pulses when module is enabled.
—
—
—
✔
✔
✔
—
—
—
USART Async receive errors due to BRGH setting corrected.
10
A/D
VREF = VDD when all inputs are configured as digital.
This allows conversion of digital inputs. (A/D on PIC16C73X/74X only.)
H/W - Issues may exist with regard to the application circuits.
S/W - Issues may exist with regard to the user program.
Prog. - Issues may exist when writing the program to the controller.
DS30605C-page 166
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE C-2:
Param
SPECIFICATION DIFFERENCES
PIC16C63/65A/73A/74A
PIC16C63A/65B/73B/74B
Symbol
Characteristic
Unit
No.
Min
Typ†
Max
Min
Typ†
Max
Core
D001
D001A
VDD
Supply Voltage
4.0
—
—
—
6.0
—
4.0
—
—
5.5
5.5
V
V
(1)
VBOR
3.65
-
D005
BVDD
VOD
Brown-out Reset Voltage
3.7
4.0
4.3
—
—
4.35
8.5
V
V
D150*
Open-Drain High Voltage on
RA4
—
—
14.0
A/D Converter
A20
131
VREF
TCNV
Reference voltage
3.0
—
VDD + 0.3
2.5
—
—
VDD + 0.3
V
Conversion time (Note 2)
—
9.5
—
11
11
TAD
(not including S/H time)
(Note 3)
(Note 4)
(Note 4)
SSP in SPI mode
71
TscH
SCK input high
time (Slave mode)
Continuous TCY+20
Single Byte
—
—
—
—
1.25TCY + 30
—
—
—
—
—
—
—
—
ns
ns
ns
ns
71A
72
40
1.25TCY + 30
40
TscL
SCK input low
time
(Slave mode)
Continuous TCY+20
Single Byte
72A
73
TdiV2scH Setup time of SDI data input to
TdiV2scL SCK edge
50
—
50
—
—
—
—
10
—
—
—
25
100
1.5TCY + 40
100
—
—
—
—
—
—
ns
ns
ns
73A
(Note 5)
TB2B
Last clock edge of Byte1 to the
1st clock edge of Byte2
74
TscH2diL Hold time of SDI data input to
TscL2diL SCK edge
75
TdoR
SDO data output PIC16CXX
—
—
—
—
10
20
10
20
25
45
25
45
ns
ns
ns
ns
rise time
PIC16LCXX
PIC16CXX
PIC16LCXX
78
80
83
TscR
SCK output rise
time (Master
mode)
—
—
—
10
—
—
25
50
50
TscH2doV SDO data output PIC16CXX
—
—
—
—
50
ns
ns
TscL2doV valid after SCK
edge
PIC16LCXX
100
TscH2ssH SS ↑ after SCK edge
1.5TCY + 40
—
—
ns
TscL2ssH
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When BOR is enabled, the device will operate until VDD drops below VBOR.
2: ADRES register may be read on the following TCY cycle.
3: This is the time that the actual conversion requires.
4: This is the time from when the GO/DONE bit is set, to when the conversion result appears in ADRES.
5: Specification 73A is only required if specifications 71A and 72A are used.
2000 Microchip Technology Inc.
DS30605C-page 167
PIC16C63A/65B/73B/74B
APPENDIX D: MIGRATION FROM BASELINE TO MID-RANGE DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16CXXX).
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1. Remove any program memory page select
The following are the list of modifications over the
PIC16C5X microcontroller family:
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
1. Instruction word length is increased to 14-bits.
This allows larger page sizes, both in program
memory (2 K now as opposed to 512 before)
and register file (128 bytes now versus 32 bytes
before).
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all writes to STATUS, OPTION and FSR
registers since these have changed.
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1
and PA0 are removed from STATUS register.
5. Change RESET vector to 0000h.
3. Data memory paging is redefined slightly.
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLWand SUBLW.
Two instructions, TRISand OPTION,are being
phased out, although they are kept for compati-
bility with PIC16C5X.
5. OPTION and TRIS registers are made address-
able.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8-deep.
8. RESET vector is changed to 0000h.
9. RESET of all registers is revisited. Five different
RESET (and wake-up) types are recognized.
Registers are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These tim-
ers are invoked selectively to avoid unneces-
sary delays on power-up and wake-up.
12. PORTB
has
weak
pull-ups
and
interrupt-on-change feature.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full 8-bit register.
15. “In-Circuit Serial Programming” (ICSP) is made
possible. The user can program PIC16CXX
devices using only five pins: VDD, VSS,
MCLR/VPP, RB6 (clock) and RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset status bit (POR).
17. Code protection scheme is enhanced, such that
portions of the program memory can be pro-
tected, while the remainder is unprotected.
18. Brown-out protection circuitry has been added.
Controlled by configuration word bit BODEN.
Brown-out Reset ensures the device is placed in
a RESET condition if VDD dips below a fixed
setpoint.
DS30605C-page 168
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
INDEX
BOR bit......................................................................... 25, 89
BRGH bit ............................................................................ 67
Brown-out Reset (BOR)
Timing Diagram ........................................................ 126
Buffer Full Status bit, BF..................................................... 56
A
A/D
ADCON0 Register....................................................... 79
ADCON1 Register....................................................... 80
Analog Input Model Block Diagram............................. 82
Analog-to-Digital Converter......................................... 79
Block Diagram............................................................. 81
Configuring Analog Port Pins...................................... 83
Configuring the Interrupt ............................................. 81
Configuring the Module............................................... 81
Conversion Clock........................................................ 83
Conversions................................................................ 83
Converter Characteristics ......................................... 137
Effects of a RESET ..................................................... 83
Faster Conversion - Lower Resolution Trade-off ........ 83
Internal Sampling Switch (Rss) Impedance................ 82
Operation During SLEEP............................................ 83
Sampling Requirements.............................................. 82
Source Impedance...................................................... 82
Timing Diagram......................................................... 138
Using the CCP Trigger................................................ 83
Absolute Maximum Ratings .............................................. 113
ACK............................................................................... 60, 62
ADRES Register ........................................................... 17, 79
Application Notes
C
C bit .................................................................................... 19
Capture/Compare/PWM
Capture
Block Diagram.................................................... 51
CCP1CON Register............................................ 50
CCP1IF............................................................... 51
Mode .................................................................. 51
Prescaler ............................................................ 51
CCP Timer Resources................................................ 49
Compare
Block Diagram.................................................... 52
Mode .................................................................. 52
Software Interrupt Mode..................................... 52
Special Event Trigger......................................... 52
Special Trigger Output of CCP1......................... 52
Special Trigger Output of CCP2......................... 52
Interaction of Two CCP Modules................................ 49
Section........................................................................ 49
Special Event Trigger and A/D Conversions............... 52
Capture/Compare/PWM (CCP)
PWM Block Diagram .................................................. 52
PWM Mode................................................................. 52
PWM, Example Frequencies/Resolutions .................. 53
Timing Diagram ........................................................ 128
CCP2IE bit.......................................................................... 24
CCP2IF bit .......................................................................... 24
CCPR1H Register......................................................... 17, 49
CCPR1L Register ............................................................... 49
CCPR2H Register............................................................... 17
CCPR2L Register ............................................................... 17
CCPxM0 bit......................................................................... 50
CCPxM1 bit......................................................................... 50
CCPxM2 bit......................................................................... 50
CCPxM3 bit......................................................................... 50
CCPxX bit........................................................................... 50
CCPxY bit........................................................................... 50
CKE .................................................................................... 56
CKP .................................................................................... 57
Clock Polarity Select bit, CKP............................................. 57
Clocking Scheme................................................................ 14
Code Examples
AN552 (Implementing Wake-up on Key Strokes
Using PIC16CXXX)..................................................... 31
AN556 (Table Reading Using PIC16CXX).................. 26
2
AN578 (Use of the SSP Module in the I C
Multi-Master Environment).......................................... 55
AN607, (Power-up Trouble Shooting)......................... 89
Architecture
Overview....................................................................... 9
Assembler
MPASM® Assembler ................................................. 107
B
Baud Rate Formula............................................................. 67
BF ................................................................................. 56, 60
Block Diagrams
A/D.............................................................................. 81
Analog Input Model..................................................... 82
Capture ....................................................................... 51
Compare ..................................................................... 52
2
I C Mode..................................................................... 60
On-Chip Reset Circuit................................................. 88
PIC16C74 ................................................................... 10
PIC16C74A................................................................. 10
PIC16C77 ................................................................... 10
PORTC ....................................................................... 33
PORTD (In I/O Port Mode).......................................... 34
PORTD and PORTE as a Parallel Slave Port............. 37
PORTE (In I/O Port Mode).......................................... 35
PWM ........................................................................... 52
RA4/T0CKI Pin............................................................ 29
RB3:RB0 Port Pins ..................................................... 31
RB7:RB4 Port Pins ..................................................... 31
Call of a Subroutine in Page 1 from Page 0 ............... 26
Indirect Addressing..................................................... 27
Initializing PORTA....................................................... 29
Code Protection............................................................ 85, 98
Computed GOTO................................................................ 26
Configuration Bits ............................................................... 85
CREN bit............................................................................. 66
CS pin................................................................................. 37
2
SSP in I C Mode......................................................... 60
SSP in SPI Mode ........................................................ 55
Timer0/WDT Prescaler................................................ 39
Timer2......................................................................... 47
USART Receive.......................................................... 70
USART Transmit......................................................... 68
Watchdog Timer.......................................................... 96
2000 Microchip Technology Inc.
DS30605C-page 169
PIC16C63A/65B/73B/74B
COMF ....................................................................... 103
DECF........................................................................ 103
DECFSZ ................................................................... 103
GOTO ....................................................................... 103
INCF ......................................................................... 103
INCFSZ..................................................................... 103
IORLW ...................................................................... 104
IORWF...................................................................... 104
MOVF ....................................................................... 104
MOVLW .................................................................... 104
MOVWF.................................................................... 104
NOP.......................................................................... 104
RETFIE..................................................................... 105
RETLW ..................................................................... 105
RETURN................................................................... 105
RLF........................................................................... 105
RRF .......................................................................... 105
SLEEP ...................................................................... 105
SUBLW ..................................................................... 106
SUBWF..................................................................... 106
SWAPF..................................................................... 106
XORLW..................................................................... 106
XORWF .................................................................... 106
Section........................................................................ 99
Summary Table......................................................... 100
INT Interrupt........................................................................ 94
INTCON Register................................................................ 21
INTEDG bit ................................................................... 20, 94
Internal Sampling Switch (Rss) Impedance........................ 82
Interrupts............................................................................. 85
PORTB Change.......................................................... 94
RB7:RB4 Port Change................................................ 31
Section........................................................................ 93
TMR0.......................................................................... 94
IRP bit................................................................................. 19
D
D/A ......................................................................................56
Data Memory
Register File Map........................................................16
Data/Address bit, D/A..........................................................56
DC bit ..................................................................................19
Development Support ...........................................................5
Device Differences............................................................165
Direct Addressing................................................................27
E
Electrical Characteristics...................................................113
Errata ....................................................................................3
F
FERR bit..............................................................................66
FSR Register........................................................... 17, 18, 27
G
General Description ..............................................................5
GIE bit .................................................................................93
I
I/O Ports
PORTA........................................................................29
PORTB........................................................................31
PORTC........................................................................33
PORTD..................................................................34, 37
PORTE........................................................................35
Section ........................................................................29
2
I C
Addressing ..................................................................61
Block Diagram.............................................................60
2
I C Operation ..............................................................60
Master Mode...............................................................64
Mode ...........................................................................60
Mode Selection ...........................................................60
Multi-Master Mode ......................................................64
K
KEELOQ Evaluation and Programming Tools.................... 110
Reception....................................................................62
L
Reception Timing Diagram..........................................62
SCL and SDA pins......................................................60
Slave Mode.................................................................60
Transmission...............................................................63
Loading of PC..................................................................... 26
M
MCLR............................................................................ 87, 90
Memory
2
I C (SSP Module)
Timing Diagram, Data ...............................................134
Timing Diagram, START/STOP Bits..........................134
In-Circuit Serial Programming....................................... 85, 98
INDF Register ......................................................... 17, 18, 27
Indirect Addressing .............................................................27
Instruction Cycle..................................................................14
Instruction Flow/Pipelining ..................................................14
Instruction Format ...............................................................99
Instruction Set
Data Memory .............................................................. 15
Program Memory........................................................ 15
Program Memory Maps
PIC16C73........................................................... 15
PIC16C73A......................................................... 15
PIC16C74........................................................... 15
PIC16C74A......................................................... 15
Register File Maps
PIC16C73........................................................... 16
PIC16C73A......................................................... 16
PIC16C74........................................................... 16
PIC16C74A......................................................... 16
PIC16C76........................................................... 16
PIC16C77........................................................... 16
MPLAB® Integrated Development
ADDLW .....................................................................101
ADDWF.....................................................................101
ANDLW .....................................................................101
ANDWF.....................................................................101
BCF...........................................................................101
BSF...........................................................................101
BTFSC ......................................................................102
BTFSS ......................................................................102
CALL .........................................................................102
CLRF.........................................................................102
CLRW........................................................................102
CLRWDT...................................................................102
Environment Software ...................................................... 107
DS30605C-page 170
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
RD1/PSP1 .................................................................. 13
RD2/PSP2 .................................................................. 13
RD3/PSP3 .................................................................. 13
RD4/PSP4 .................................................................. 13
RD5/PSP5 .................................................................. 13
RD6/PSP6 .................................................................. 13
RD7/PSP7 .................................................................. 13
RE0/RD/AN5 .............................................................. 13
RE1/WR/AN6.............................................................. 13
RE2/CS/AN7............................................................... 13
VDD ........................................................................11, 13
VSS ........................................................................11, 13
Pinout Descriptions
O
OERR bit............................................................................. 66
OPCODE ............................................................................ 99
OPTION Register................................................................ 20
OSC Selection .................................................................... 85
Oscillator
HS......................................................................... 86, 90
LP.......................................................................... 86, 90
RC............................................................................... 86
XT ......................................................................... 86, 90
Oscillator Configurations..................................................... 86
Output of TMR2 .................................................................. 47
PIC16C73................................................................... 11
PIC16C73A................................................................. 11
PIC16C74................................................................... 12
PIC16C74A................................................................. 12
PIC16C76................................................................... 11
PIC16C77................................................................... 12
PIR1 Register ..................................................................... 23
PIR2 Register ..................................................................... 24
POP .................................................................................... 26
POR.................................................................................... 89
Oscillator Start-up Timer (OST) ............................ 85, 89
Power Control Register (PCON)................................. 89
Power-on Reset (POR)................................... 85, 89, 91
Power-up Timer (PWRT) ............................................ 85
Power-Up-Timer (PWRT) ........................................... 89
TO............................................................................... 87
POR bit......................................................................... 25, 89
Port RB Interrupt................................................................. 94
PORTA ............................................................................... 91
PORTA Register........................................................... 17, 29
PORTB ............................................................................... 91
PORTB Register........................................................... 17, 31
PORTC ............................................................................... 91
PORTC Register........................................................... 17, 33
PORTD ............................................................................... 91
PORTD Register........................................................... 17, 34
PORTE ............................................................................... 91
PORTE Register........................................................... 17, 35
Power-down Mode (SLEEP)............................................... 97
Power-on Reset (POR)
P
P.......................................................................................... 56
Packaging ......................................................................... 153
Paging, Program Memory................................................... 26
Parallel Slave Port ........................................................ 34, 37
Parallel Slave Port (PSP)
Timing Diagram......................................................... 129
PCFG0 bit ........................................................................... 80
PCFG1 bit ........................................................................... 80
PCFG2 bit ........................................................................... 80
PCL Register........................................................... 17, 18, 26
PCLATH.............................................................................. 91
PCLATH Register ................................................... 17, 18, 26
PCON Register ............................................................. 25, 89
PD bit ............................................................................ 19, 87
PICDEMTM 1 Low Cost PICmicro
Demonstration Board ........................................................ 109
PICDEMTM 2 Low Cost PIC16CXX
Demonstration Board ........................................................ 109
PICDEMTM 3 Low Cost PIC16CXXX
Demonstration Board ........................................................ 110
PICSTART® Plus Entry Level
Development System........................................................ 109
PIE1 Register...................................................................... 22
PIE2 Register...................................................................... 24
Pin Functions
MCLR/VPP............................................................. 11, 12
OSC1/CLKIN......................................................... 11, 12
OSC2/CLKOUT..................................................... 11, 12
RA0/AN0............................................................... 11, 12
RA1/AN1............................................................... 11, 12
RA2/AN2............................................................... 11, 12
RA3/AN3/VREF...................................................... 11, 12
RA4/T0CKI............................................................ 11, 12
RA5/AN4/SS ......................................................... 11, 12
RB0/INT ................................................................ 11, 12
RB1....................................................................... 11, 12
RB2....................................................................... 11, 12
RB3....................................................................... 11, 12
RB4....................................................................... 11, 12
RB5....................................................................... 11, 12
RB6....................................................................... 11, 12
RB7....................................................................... 11, 12
RC0/T1OSO/T1CKI .............................................. 11, 13
RC1/T1OSI/CCP2................................................. 11, 13
RC2/CCP1 ............................................................ 11, 13
RC3/SCK/SCL ...................................................... 11, 13
RC4/SDI/SDA ....................................................... 11, 13
RC5/SDO.............................................................. 11, 13
RC6/TX/CK ............................................... 11, 13, 65–76
RC7/RX/DT............................................... 11, 13, 65–76
RD0/PSP0................................................................... 13
Timing Diagram ........................................................ 126
PR2 Register ................................................................ 18, 47
PRO MATE® II Universal Programmer............................. 109
Product Identification System ........................................... 177
Program Memory
Paging ........................................................................ 26
Program Memory Maps
PIC16C73................................................................... 15
PIC16C73A................................................................. 15
PIC16C74................................................................... 15
PIC16C74A................................................................. 15
Program Verification ........................................................... 98
PS0 bit ................................................................................ 20
PS1 bit ................................................................................ 20
PS2 bit ................................................................................ 20
PSA bit................................................................................ 20
PSPMODE bit......................................................... 34, 35, 37
PUSH.................................................................................. 26
2000 Microchip Technology Inc.
DS30605C-page 171
PIC16C63A/65B/73B/74B
SSPSTAT.................................................................... 56
SPI Clock Edge Select bit, CKE ......................................... 56
SPI Data Input Sample Phase Select bit, SMP .................. 56
SREN bit............................................................................. 66
SSP
R
R/W .....................................................................................56
R/W bit .................................................................... 61, 62, 63
RBIF bit ......................................................................... 31, 94
RBPU bit .............................................................................20
RC Oscillator................................................................. 87, 90
RCSTA Register..................................................................66
RD pin .................................................................................37
Read/Write bit Information, R/W .........................................56
Receive Overflow Indicator bit, SSPOV..............................57
Register File........................................................................15
Register File Map................................................................16
Registers
Module Overview........................................................ 55
Section........................................................................ 55
SSPCON .................................................................... 57
SSPSTAT.................................................................... 56
SSPADD Register............................................................... 18
SSPBUF Register............................................................... 17
SSPCON............................................................................. 57
SSPCON Register .............................................................. 17
SSPEN................................................................................ 57
SSPM3:SSPM0 .................................................................. 57
SSPOV ......................................................................... 57, 60
SSPSTAT Register....................................................... 18, 56
Stack................................................................................... 26
Overflows.................................................................... 26
Underflow ................................................................... 26
START bit, S....................................................................... 56
STATUS Register ............................................................... 19
STOP bit, P......................................................................... 56
Synchronous Serial Port Enable bit, SSPEN...................... 57
Synchronous Serial Port Mode Select bits,
Maps
PIC16C73 ...........................................................16
PIC16C73A.........................................................16
PIC16C74 ...........................................................16
PIC16C74A.........................................................16
RESET Conditions......................................................90
SSPSTAT ....................................................................56
Summary.....................................................................17
RESET .......................................................................... 85, 87
Timing Diagram.........................................................126
RESET Conditions for Special Registers............................90
Revision History ................................................................165
RP0 bit .......................................................................... 15, 19
RP1 bit ................................................................................19
RX9 bit ................................................................................66
SSPM3:SSPM0 .................................................................. 57
Synchronous Serial Port Module ........................................ 55
Synchronous Serial Port Status Register ........................... 56
RX9D bit..............................................................................66
T
T0CS bit.............................................................................. 20
T1CKPS0 bit....................................................................... 43
T1CKPS1 bit....................................................................... 43
T1CON Register ................................................................. 43
T1OSCEN bit...................................................................... 43
T1SYNC bit......................................................................... 43
T2CKPS0 bit....................................................................... 47
T2CKPS1 bit....................................................................... 47
T2CON Register ................................................................. 47
TAD...................................................................................... 83
Timer0
RTCC.......................................................................... 91
Timing Diagram ........................................................ 127
Timer1
Timing Diagram ........................................................ 127
Timers
S
S..........................................................................................56
SCL .....................................................................................60
Serial Communication Interface (SCI) Module,
See USART
Services
One-Time-Programmable (OTP)...................................7
Quick-Turnaround-Production (QTP)............................7
Serialized Quick-Turnaround Production
(SQTP)..........................................................................7
Slave Mode
SCL .............................................................................60
SDA.............................................................................60
SLEEP........................................................................... 85, 87
SMP ....................................................................................56
Software Simulator (MPLAB-SIM).....................................108
SPBRG Register .................................................................18
Special Features of the CPU...............................................85
Special Function Registers
PIC16C73 ...................................................................17
PIC16C73A.................................................................17
PIC16C74 ...................................................................17
PIC16C74A.................................................................17
Special Function Registers, Section ...................................16
SPEN bit..............................................................................66
SPI
Timer0
External Clock .................................................... 40
Interrupt .............................................................. 39
Prescaler ............................................................ 40
Prescaler Block Diagram.................................... 39
Section................................................................ 39
T0CKI ................................................................. 40
T0IF .................................................................... 94
TMR0 Interrupt ................................................... 94
Timer1
Asynchronous Counter Mode............................. 45
Capacitor Selection ............................................ 45
Operation in Timer Mode.................................... 44
Oscillator............................................................. 45
Prescaler ............................................................ 45
Resetting of Timer1 Registers............................ 45
Resetting Timer1 using a CCP
Trigger Output .................................................... 45
Synchronized Counter Mode.............................. 44
T1CON ............................................................... 43
Block Diagram.............................................................55
Master Mode Timing ...................................................58
Serial Clock.................................................................55
Serial Data In ..............................................................55
Serial Data Out............................................................55
Slave Mode Timing .....................................................59
Slave Mode Timing Diagram.......................................58
Slave Select................................................................55
SSPCON.....................................................................57
DS30605C-page 172
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TMR1H ............................................................... 45
TMR1L ................................................................ 45
Timer2
U
UA....................................................................................... 56
Universal Synchronous Asynchronous Receiver
Transmitter (USART).......................................................... 65
Update Address bit, UA...................................................... 56
USART
Block Diagram .................................................... 47
Module ................................................................ 47
Postscaler ........................................................... 47
Prescaler............................................................. 47
T2CON................................................................ 47
Asynchronous Mode................................................... 68
Asynchronous Receiver.............................................. 70
Asynchronous Reception............................................ 71
Asynchronous Transmitter.......................................... 68
Baud Rate Generator (BRG) ...................................... 67
Receive Block Diagram .............................................. 70
Sampling..................................................................... 67
Synchronous Master Mode......................................... 72
Timing Diagram, Synchronous Receive ........... 136
Timing Diagram, Synchronous Transmission... 136
Synchronous Master Reception ................................. 74
Synchronous Master Transmission ............................ 72
Synchronous Slave Mode........................................... 76
Synchronous Slave Reception ................................... 76
Synchronous Slave Transmit...................................... 76
Transmit Block Diagram ............................................. 68
UV Erasable Devices............................................................ 7
Timing Diagrams
2
I C Reception (7-bit Address)..................................... 62
SPI Master Mode ........................................................ 58
SPI Slave Mode (CKE = 1) ......................................... 59
SPI Slave Mode Timing (CKE = 0).............................. 58
USART Asynchronous Master Transmission.............. 69
USART Asynchronous Reception............................... 71
USART Synchronous Reception................................. 75
USART Synchronous Transmission............................ 73
Wake-up from SLEEP via Interrupt............................. 98
Timing Diagrams and Specifications................................. 124
A/D Conversion......................................................... 138
Brown-out Reset (BOR)............................................ 126
Capture/Compare/PWM (CCP)................................. 128
CLKOUT and I/O....................................................... 125
External Clock........................................................... 124
2
I C Bus Data............................................................. 134
I C Bus START/STOP Bits ....................................... 134
W
2
Wake-up from SLEEP......................................................... 97
Watchdog Timer (WDT).................................... 85, 87, 90, 95
Timing Diagram ........................................................ 126
WCOL................................................................................. 57
WDT ................................................................................... 90
Block Diagram ............................................................ 96
Period ......................................................................... 95
Programming Considerations..................................... 96
Time-out...................................................................... 91
WR pin................................................................................ 37
Write Collision Detect bit, WCOL........................................ 57
WWW, On-Line Support ....................................................... 3
Oscillator Start-up Timer (OST)................................. 126
Parallel Slave Port (PSP).......................................... 129
Power-up Timer (PWRT)........................................... 126
RESET...................................................................... 126
Timer0 and Timer1.................................................... 127
USART Synchronous Receive (Master/Slave) ......... 136
USART SynchronousTransmission (Master/Slave) .. 136
Watchdog Timer (WDT) ............................................ 126
TMR0 Register.................................................................... 17
TMR1CS bit ........................................................................ 43
TMR1H Register ................................................................. 17
TMR1L Register.................................................................. 17
TMR1ON bit ........................................................................ 43
TMR2 Register.................................................................... 17
TMR2ON bit ........................................................................ 47
TO bit .................................................................................. 19
TOUTPS0 bit....................................................................... 47
TOUTPS1 bit....................................................................... 47
TOUTPS2 bit....................................................................... 47
TOUTPS3 bit....................................................................... 47
TRISA Register ............................................................. 18, 29
TRISB Register ............................................................. 18, 31
TRISC Register............................................................. 18, 33
TRISD Register............................................................. 18, 34
TRISE Register....................................................... 18, 35, 36
TXSTA Register .................................................................. 65
Z
Z bit..................................................................................... 19
2000 Microchip Technology Inc.
DS30605C-page 173
PIC16C63A/65B/73B/74B
NOTES:
DS30605C-page 174
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Systems Information and Upgrade Hot Line
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from our FTP site.
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001024
ConnectingtotheMicrochipInternetWebSite
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DS30605C-page 175
PIC16C63A/65B/73B/74B
READER RESPONSE
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Literature Number:
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Device:
PIC16C63A/65B/73B/74B
Questions:
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DS30605C-page 176
2000 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Examples:
Frequency Temperature Package
Range Range
Pattern
a) PIC16C74B -04/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
b)
PIC16LC63A - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
Device
PIC16C6X(1), PIC16C6XT(2); VDD range 4.0V to 5.5V
PIC16LC6X(1), PIC16LC6XT(2); VDD range 2.5V to 5.5V
PIC16C7X(1), PIC16C7XT(2); VDD range 4.0V to 5.5V
PIC16LC7X(1), PIC16LC7XT(2); VDD range 2.5V to 5.5V
c)
PIC16C65B - 20I/P = Industrial temp., PDIP
package, 20 MHz, normal VDD limits.
Frequency Range
04
20
= 4 MHz
= 20 MHz
Note 1:
2:
C
= CMOS
LC = Low Power CMOS
T
= in tape and reel - SOIC, SSOP,
PLCC, QFP, TQ and FP
packages only.
Temperature Range
blank
I
E
=
=
=
0°C to
70°C (Commercial)
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package
JW
PQ
PT
SO
SP
P
=
=
=
=
=
=
=
=
Windowed CERDIP
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
PLCC
SSOP
L
SS
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2000 Microchip Technology Inc.
DS30605C-page 177
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DS30605C-page 183
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC (continued)
Corporate Office
China - Beijing
Microchip Technology Beijing Office
Unit 915
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Rocky Mountain
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
China - Shanghai
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Hong Kong
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
France
India
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Microchip Technology Inc.
India Liaison Office
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Divyasree Chambers
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
4570 Westgrove Drive, Suite 160
Addison, TX 75001
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Two Prestige Place, Suite 130
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Tel: 949-263-1888 Fax: 949-263-1338
Tel: 82-2-554-7200 Fax: 82-2-558-5934
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
10/01/00
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 12/00
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30605C-page 184
2000 Microchip Technology Inc.
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