PIC16F874-20L [ETC]
8-Bit Microcontroller ; 8位微控制器\n
| 型号： | PIC16F874-20L |
| 厂家： | 
ETC |
| 描述： | 8-Bit Microcontroller
|
| 文件： | 总200页 (文件大小：3338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F87X
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
Pin Diagram
PDIP
• PIC16F873
• PIC16F874
• PIC16F876
• PIC16F877
MCLR/VPP/THV
RA0/AN0
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
2
Microcontroller Core Features:
RA1/AN1
3
RB5
• High-performance RISC CPU
RA2/AN2/VREF-
4
RB4
RA3/AN3/VREF+
RA4/T0CKI
RB3/PGM
RB2
5
• Only 35 single word instructions to learn
6
• All single cycle instructions except for program
branches which are two cycle
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
7
RB1
8
RB0/INT
VDD
9
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
VSS
• Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
Up to 256 x 8 bytes of EEPROM data memory
RD6/PSP6
RD5/PSP5
RD4/PSP4
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC7/RX/DT
RC6/TX/CK
RC5/SDO
• Pinout compatible to the PIC16C73B/74B/76/77
• Interrupt capability (up to 14 sources)
• Eight level deep hardware stack
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD1/PSP1
RD2/PSP2
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
Peripheral Features:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Low-power, high-speed CMOS FLASH/EEPROM
technology
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Fully static design
• In-Circuit Serial Programming (ICSP) via two
pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI (Master
Mode) and I2C (Master/Slave)
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
- < 2 mA typical @ 5V, 4 MHz
• Brown-out detection circuitry for
Brown-out Reset (BOR)
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
1999 Microchip Technology Inc.
DS30292B-page 1
PIC16F87X
Pin Diagrams
DIP, SOIC
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RB1
RB0/INT
VDD
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VSS
10
11
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
12
13
14
RC3/SCK/SCL
PLCC
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
39
38
37
RB3/PGM
RB2
7
8
RB1
9
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
PIC16F877
PIC16F874
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
QFP
NC
33
1
2
3
4
5
6
7
8
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
RC0/T1OSO/T1CKI
32
31
30
29
28
27
26
OSC2/CLKOUT
OSC1/CLKIN
VSS
PIC16F877
PIC16F874
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
9
10
11
25
24
23
DS30292B-page 2
1999 Microchip Technology Inc.
PIC16F87X
Key Features
PICmicro™ Mid-Range Reference
Manual (DS33023)
PIC16F873
PIC16F874
PIC16F876
PIC16F877
Operating Frequency
Resets (and Delays)
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
POR, BOR
POR, BOR
POR, BOR
POR, BOR
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
FLASH Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
EEPROM Data Memory
Interrupts
192
192
368
368
128
128
256
256
13
14
13
14
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM modules
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Instruction Set
2
MSSP, USART
—
2
2
MSSP, USART
—
2
MSSP, USART
PSP
MSSP, USART
PSP
5 input channels 8 input channels 5 input channels 8 input channels
35 Instructions
35 Instructions
35 Instructions
35 Instructions
1999 Microchip Technology Inc.
DS30292B-page 3
PIC16F87X
Table of Contents
1.0 Device Overview ........................................................................................................................................................................... 5
2.0 Memory Organization.................................................................................................................................................................. 11
3.0 I/O Ports...................................................................................................................................................................................... 29
4.0 Data EEPROM and FLASH Program Memory ........................................................................................................................... 41
5.0 Timer0 Module ............................................................................................................................................................................ 47
6.0 Timer1 Module ............................................................................................................................................................................ 51
7.0 Timer2 Module ........................................................................................................................................................................... 55
8.0 Capture/Compare/PWM (CCP) Module(s).................................................................................................................................. 57
9.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................... 63
10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..................................................................................... 95
11.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................. 111
12.0 Special Features of the CPU..................................................................................................................................................... 121
13.0 Instruction Set Summary........................................................................................................................................................... 137
14.0 Development Support ............................................................................................................................................................... 145
15.0 Electrical Characteristics........................................................................................................................................................... 151
16.0 DC and AC Characteristics Graphs and Tables........................................................................................................................ 173
17.0 Packaging Information .............................................................................................................................................................. 175
Appendix A: Revision History......................................................................................................................................................... 183
Appendix B: Device Differences..................................................................................................................................................... 183
Appendix C: Conversion Considerations........................................................................................................................................ 183
Index
................................................................................................................................................................................... 185
On-Line Support................................................................................................................................................................................. 191
Product Identification System............................................................................................................................................................. 193
To Our Valued Customers
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DS30292B-page 4
1999 Microchip Technology Inc.
PIC16F87X
There are four devices (PIC16F873, PIC16F874,
PIC16F876 and PIC16F877) covered by this data
sheet. The PIC16F876/873 devices come in 28-pin
packages and the PIC16F877/874 devices come in 40-
pin packages. The 28-pin devices do not have a Paral-
lel Slave Port implemented.
1.0
DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1: PIC16F873 AND PIC16F876 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data
EEPROM
PIC16F873
PIC16F876
4K
8K
192 Bytes
368 Bytes
128 Bytes
256 Bytes
13
8
PORTA
Data Bus
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
FLASH
Program
Memory
RAM
File
Registers
8 Level Stack
(13-bit)
RA5/AN4/SS
Program
Bus
14
RAM Addr (1)
PORTB
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
In-Circuit
Debugger
Low-Voltage
Programming
MCLR VDD, VSS
Timer2
Timer0
Timer1
10-bit A/D
Data EEPROM
Synchronous
Serial Port
USART
CCP1,2
Note 1: Higher order bits are from the STATUS register.
1999 Microchip Technology Inc.
DS30292B-page 5
PIC16F87X
FIGURE 1-2: PIC16F874 AND PIC16F877 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data
EEPROM
PIC16F874
PIC16F877
4K
8K
192 Bytes
368 Bytes
128 Bytes
256 Bytes
13
8
PORTA
Data Bus
RAM
Program Counter
FLASH
RA0/AN0
RA1/AN1
Program
Memory
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
8 Level Stack
(13-bit)
File
Registers
RA5/AN4/SS
Program
Bus
14
RAM Addr (1)
PORTB
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
3
MUX
Power-up
Timer
Oscillator
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
PORTD
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
RD7/PSP7:RD0/PSP0
In-Circuit
Debugger
Low-Voltage
Programming
PORTE
Parallel Slave Port
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
MCLR VDD, VSS
Timer0
Timer1
Timer2
10-bit A/D
USART
Data EEPROM
Synchronous
Serial Port
CCP1,2
Note 1: Higher order bits are from the STATUS register.
DS30292B-page 6
1999 Microchip Technology Inc.
PIC16F87X
TABLE 1-1:
PIC16F873 AND PIC16F876 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
9
9
I
Oscillator crystal input/external clock source input.
ST/CMOS
OSC2/CLKOUT
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1, and denotes the instruction
cycle rate.
MCLR/VPP/THV
1
1
I/P
ST
Master clear (reset) input or programming voltage input or high
voltage test mode control. This pin is an active low reset to the
device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0
RA1 can also be analog input1
RA0/AN0
2
3
4
2
3
4
I/O
I/O
I/O
TTL
TTL
TTL
RA1/AN1
RA2/AN2/VREF-
RA2 can also be analog input2 or negative analog reference
voltage
RA3/AN3/VREF+
RA4/T0CKI
5
6
7
5
6
7
I/O
I/O
I/O
TTL
ST
RA3 can also be analog input3 or positive analog reference
voltage
RA4 can also be the clock input to the Timer0 module. Output
is open drain type.
RA5/SS/AN4
TTL
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
21
21
I/O
RB0 can also be the external interrupt pin.
TTL/ST
TTL
RB1
22
23
24
25
26
27
22
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
I/O
RB2
TTL
RB3/PGM
RB4
TTL
RB3 can also be the low voltage programming input
Interrupt on change pin.
TTL
RB5
TTL
Interrupt on change pin.
(2)
RB6/PGC
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.
TTL/ST
(2)
RB7/PGD
28
28
I/O
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.
TTL/ST
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
11
12
13
14
15
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or Timer1 clock
input.
RC1 can also be the Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/PWM1
output.
RC3/SCK/SCL
RC4/SDI/SDA
RC3 can also be the synchronous serial clock input/output for
2
both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5/SDO
16
17
16
17
I/O
I/O
ST
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
20
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1999 Microchip Technology Inc.
DS30292B-page 7
PIC16F87X
TABLE 1-2:
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKIN
13
14
14
15
30
31
I
Oscillator crystal input/external clock source input.
ST/CMOS
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs CLK-
OUT which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP/THV
1
2
18
I/P
ST
Master clear (reset) input or programming voltage input or high
voltage test mode control. This pin is an active low reset to the
device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0
RA1 can also be analog input1
RA0/AN0
2
3
4
3
4
5
19
20
21
I/O
I/O
I/O
TTL
TTL
TTL
RA1/AN1
RA2/AN2/VREF-
RA2 can also be analog input2 or negative analog
reference voltage
RA3/AN3/VREF+
RA4/T0CKI
5
6
7
6
7
8
22
23
24
I/O
I/O
I/O
TTL
ST
RA3 can also be analog input3 or positive analog
reference voltage
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4
TTL
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
33
36
8
I/O
RB0 can also be the external interrupt pin.
TTL/ST
TTL
RB1
34
35
36
37
38
39
37
38
39
41
42
43
9
I/O
I/O
I/O
I/O
I/O
I/O
RB2
10
11
14
15
16
TTL
RB3/PGM
RB4
TTL
RB3 can also be the low voltage programming input
Interrupt on change pin.
TTL
RB5
TTL
Interrupt on change pin.
(2)
RB6/PGC
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.
TTL/ST
(2)
RB7/PGD
40
44
17
I/O
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.
TTL/ST
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
15
16
17
18
23
24
25
26
16
18
19
20
25
26
27
29
32
35
36
37
42
43
44
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or a Timer1
clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC3 can also be the synchronous serial clock input/output
2
for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30292B-page 8
1999 Microchip Technology Inc.
PIC16F87X
TABLE 1-2:
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTD is a bi-directional I/O port or parallel slave port when
interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
3
4
5
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
9
9
25
26
27
I/O
I/O
I/O
RE0 can also be read control for the parallel slave port, or
analog input5.
ST/TTL
ST/TTL
ST/TTL
10
11
RE1 can also be write control for the parallel slave port, or
analog input6.
10
RE2 can also be select control for the parallel slave port,
or analog input7.
VSS
VDD
NC
12,31
11,32
—
13,34
6,29
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
12,35
7,28
P
1,17,28, 12,13,
40 33,34
These pins are not internally connected. These pins should be
left unconnected.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1999 Microchip Technology Inc.
DS30292B-page 9
PIC16F87X
NOTES:
DS30292B-page 10
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 2-2: PIC16F874/873 PROGRAM
MEMORY MAP AND STACK
2.0
MEMORY ORGANIZATION
There are three memory blocks in each of these
PICmicro MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
EEPROM data memory block is detailed in
Section 4.0.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Additional information on device memory may be found
Stack Level 1
in the PICmicro
(DS33023).
Mid-Range Reference Manual,
Stack Level 2
2.1
Program Memory Organization
Stack Level 8
Reset Vector
The PIC16F87X devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The PIC16F877/876 devices have 8K x 14
words of FLASH program memory and the PIC16F873/
874 devices have 4K x 14. Accessing a location above
the physically implemented address will cause a wrap-
around.
0000h
Interrupt Vector
Page 0
0004h
0005h
The reset vector is at 0000h and the interrupt vector is
at 0004h.
On-Chip
Program
Memory
07FFh
0800h
FIGURE 2-1: PIC16F877/876 PROGRAM
MEMORY MAP AND STACK
Page 1
0FFFh
1000h
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
Page 1
On-Chip
Program
Memory
0FFFh
1000h
Page 2
Page 3
17FFh
1800h
1FFFh
1999 Microchip Technology Inc.
DS30292B-page 11
PIC16F87X
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1(STATUS<6>) and
RP0 (STATUS<5>) are the bank select bits.
RP1:RP0
Bank
00
01
10
11
0
1
2
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
Note: EEPROM Data Memory description can be
found in Section 4.0 of this Data Sheet
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR.
DS30292B-page 12
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP
File
Address
Indirect addr.(*)
Indirect addr.(*)
Indirect addr.(*)
TMR0
Indirect addr.(*)
OPTION_REG 81h
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
80h
OPTION_REG
181h
TMR0
PCL
PCL
PCL
STATUS
FSR
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
PCL
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD (1)
PORTE (1)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD (1)
TRISE (1)
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)
PCLATH
INTCON
PIE1
EEDATA
EEADR
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
EEDATH
EEADRH
SSPCON2
PR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
SSPADD
SSPSTAT
General
Purpose
Register
General
Purpose
Register
RCSTA
TXREG
TXSTA
16 Bytes
16 Bytes
SPBRG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
ADRESL
ADCON1
1A0h
A0h
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
80 Bytes
80 Bytes
80 Bytes
1EFh
1F0h
96 Bytes
EFh
F0h
16Fh
170h
accesses
70h - 7Fh
accesses
70h-7Fh
accesses
70h-7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
2: These registers are reserved, maintain these registers clear.
1999 Microchip Technology Inc.
DS30292B-page 13
PIC16F87X
FIGURE 2-4: PIC16F874/873 REGISTER FILE MAP
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
PCL
Indirect addr.(*)
TMR0
Indirect addr.(*)
OPTION_REG 81h
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
80h
TMR0
PCL
PCL
PCL
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
STATUS
STATUS
FSR
FSR
PORTA
PORTB
PORTC
PORTD (1)
PORTE (1)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD (1)
TRISE (1)
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)
PCLATH
INTCON
PIE1
EEDATA
EEADR
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
EEDATH
EEADRH
SSPCON2
PR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
SSPADD
SSPSTAT
RCSTA
TXREG
TXSTA
SPBRG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
ADRESL
ADCON1
1A0h
120h
A0h
General
Purpose
Register
General
Purpose
Register
accesses
20h-7Fh
accesses
A0h - FFh
1EFh
1F0h
96 Bytes
96 Bytes
16Fh
170h
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
2: These registers are reserved, maintain these registers clear.
DS30292B-page 14
1999 Microchip Technology Inc.
PIC16F87X
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on
Value on:
Addres
all other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
s
resets
(2)
Bank 0
00h(4)
INDF
TMR0
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
01h
02h(4)
03h(4)
Program Counter's (PC) Least Significant Byte
STATUS
FSR
IRP
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
04h(4)
05h
PORTA
PORTB
PORTC
—
—
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
06h
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
07h
08h(5)
PORTD
PORTE
PCLATH
INTCON
PIR1
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
09h(5)
0Ah(1,4)
0Bh(4)
0Ch
—
—
—
—
—
—
—
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIF
(6)
T0IE
RCIF
—
INTE
TXIF
EEIF
RBIE
SSPIF
BCLIF
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
PSPIF(3)
—
TMR1IF 0000 0000 0000 0000
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
PIR2
CCP2IF -r-0 0--0 -r-0 0--0
xxxx xxxx uuuu uuuu
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
TMR1H
T1CON
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR2
Timer2 module’s register
0000 0000 0000 0000
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
SSPM0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
xxxx xxxx uuuu uuuu
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
A/D Result Register High Byte
xxxx xxxx uuuu uuuu
GO/
DONE
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
—
ADON
0000 00-0 0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
1999 Microchip Technology Inc.
DS30292B-page 15
PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
resets
(2)
Value on:
POR,
BOR
Addres
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
s
Bank 1
80h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
OPTION_R
EG
81h
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(4)
83h(4)
PCL
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
0000 0000 0000 0000
0001 1xxx 000q quuu
STATUS
PD
Z
DC
C
84h(4)
85h
FSR
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
TRISA
TRISB
TRISC
TRISD
—
—
86h
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
87h
88h(5)
89h(5)
TRISE
PCLATH
INTCON
PIE1
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
8Ah(1,4)
Write Buffer for the upper 5 bits of the Program Counter
8Bh(4)
8Ch
GIE
PEIE
ADIE
T0IE
RCIE
INTE
TXIE
RBIE
T0IF
INTF
RBIF
PSPIE(3)
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
CCP2IE -r-0 0--0 -r-0 0--0
8Dh
8Eh
8Fh
90h
91h
92h
93h
PIE2
—
—
(6)
—
—
EEIE
—
BCLIE
—
—
—
—
PCON
—
—
POR
BOR
---- --qq ---- --uu
Unimplemented
Unimplemented
—
—
—
—
—
SSPCON2
PR2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
R/W
RSEN
UA
SEN
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
SSPADD
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SSPSTAT
SMP
CKE
D/A
P
S
BF
—
Unimplemented
Unimplemented
Unimplemented
CSRC
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator Register
Unimplemented
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADRESL
ADCON1
A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
PCFG0 0---0000 0---0000
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
DS30292B-page 16
1999 Microchip Technology Inc.
PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
Value on:
Addres
all other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
s
resets
(2)
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000
0000 0000
101h
TMR0
PCL
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
102h(4)
103h(4)
Program Counter's (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
104h(4)
105h
106h
107h
108h
109h
FSR
—
Indirect data memory address pointer
Unimplemented
xxxx xxxx uuuu uuuu
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
10Ah(1,4)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
10Bh(4)
10Ch
10Dh
10Eh
10Fh
INTCON
GIE
PEIE
T0IE
EEDATA
EEADR
EEPROM data register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEPROM address register
EEDATH
EEADRH
—
—
—
—
EEPROM data register high byte
EEPROM address register high byte
—
Bank 3
180h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
OPTION_R
EG
181h
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
182h(4)
183h(4)
PCL
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
STATUS
PD
Z
DC
C
184h(4)
185h
186h
187h
188h
189h
FSR
—
Indirect data memory address pointer
Unimplemented
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 1111 1111
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
18Ah(1,4)
Write Buffer for the upper 5 bits of the Program Counter
PCLATH
—
—
—
---0 0000 ---0 0000
18Bh(4)
18Ch
18Dh
18Eh
18Fh
INTCON
EECON1
EECON2
—
GIE
PEIE
—
T0IE
—
INTE
—
RBIE
T0IF
INTF
WR
RBIF
RD
0000 000x 0000 000u
x--- x000 x--- u000
---- ---- ---- ----
0000 0000 0000 0000
0000 0000 0000 0000
EEPGD
WRERR
WREN
EEPROM control register2 (not a physical register)
Reserved maintain clear
—
Reserved maintain clear
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
1999 Microchip Technology Inc.
DS30292B-page 17
PIC16F87X
2.2.2.1
STATUS REGISTER
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see the
"Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
bit 3:
bit 2:
bit 1:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)
(for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
DS30292B-page 18
1999 Microchip Technology Inc.
PIC16F87X
2.2.2.2
OPTION_REG REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1
RBPU INTEDG
bit7
R/W-1 R/W-1 R/W-1 R/W-1
T0CS T0SE PSA PS2
R/W-1 R/W-1
PS1
PS0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the
TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device.
1999 Microchip Technology Inc.
DS30292B-page 19
PIC16F87X
2.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
- n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
DS30292B-page 20
1999 Microchip Technology Inc.
PIC16F87X
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
enable any peripheral interrupt.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1) ADIE
R/W-0
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
1999 Microchip Technology Inc.
DS30292B-page 21
PIC16F87X
2.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
PSPIF(1) ADIF
R/W-0
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF TMR2IF TMR1IF
bit0
R = Readable bit
W = Writable bit
- n= Value at POR reset
bit7
(1)
bit 7:
bit 6:
bit 5:
bit 4:
bit 7:
PSPIF : Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1= The SSP interrupt condition has occurred, and must be cleared in software before returning from the interrupt ser-
vice routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
2
I C Slave
A transmission/reception has taken place.
2
I C Master
A transmission/reception has taken place.
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0= No SSP interrupt condition has occurred.
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PSPIF is reserved on 28-pin devices; always maintain this bit clear.
DS30292B-page 22
1999 Microchip Technology Inc.
PIC16F87X
2.2.2.6
PIE2 REGISTER
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
CCP2IE
bit0
—
—
—
EEIE
BCLIE
—
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIE: EEPROM Write Operation Interrupt Enable
1= Enable EE Write Interrupt
0= Disable EE Write Interrupt
bit 3:
BCLIE: Bus Collision Interrupt Enable
1= Enable Bus Collision Interrupt
0= Disable Bus Collision Interrupt
bit 2-1: Unimplemented: Read as '0'
bit 0:
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
1999 Microchip Technology Inc.
DS30292B-page 23
PIC16F87X
.
2.2.2.7
PIR2 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
CCP2IF
bit0
—
—
—
EEIF
BCLIF
—
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3:
BCLIF: Bus Collision Interrupt Flag
1= A bus collision has occurred in the SSP, when configured for I2C master mode
0= No bus collision has occurred
bit 2-1: Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused
DS30292B-page 24
1999 Microchip Technology Inc.
PIC16F87X
2.2.2.8
PCON REGISTER
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent rests
to see if BOR is clear, indicating a brown-
out has occurred. The BOR status bit is a
don’t care and is not predictable if the
brown-out circuit is disabled (by clearing
the BODEN bit in the configuration word).
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watch-dog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-1
BOR
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
1999 Microchip Technology Inc.
DS30292B-page 25
PIC16F87X
2.3
PCL and PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the PC
will be cleared. Figure 2-5 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
2: There are no instructions/mnemonics
called PUSHor POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc-
tions or the vectoring to an interrupt
address.
2.4
Program Memory Paging
PIC16CXX devices are capable of addressing a contin-
uous 8K word block of program memory. The CALLand
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALLor GOTOinstruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack)
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
PC
Destination
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PCL
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt ser-
vice routine (if interrupts are used).
8
7
0
GOTO,CALL
PC
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
EXAMPLE 2-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3
CALLSUB1_P1
;Select page 1 (800h-FFFh)
;Call subroutine in
2.3.1
COMPUTED GOTO
:
:
;page 1 (800h-FFFh)
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
ORG 0x900
;page 1 (800h-FFFh)
SUB1_P1
:
:
:
;called subroutine
;page 1 (800h-FFFh)
application note, “Implementing
a
Table Read"
RETURN
;return to Call subroutine
;in page 0 (000h-7FFh)
(AN556).
2.3.2
STACK
The PIC16CXX family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSHor POPoperation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30292B-page 26
1999 Microchip Technology Inc.
PIC16F87X
2.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 2-2: INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-6.
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-6: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP1:RP0
6
0
0
IRP
FSR register
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
Data
Memory
(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail see Figure 2-3.
1999 Microchip Technology Inc.
DS30292B-page 27
PIC16F87X
NOTES:
DS30292B-page 28
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 3-1: BLOCK DIAGRAM OF
3.0
I/O PORTS
RA3:RA0 AND RA5 PINS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
VDD
WR
Port
Additional information on I/O ports may be found in the
PICmicro™
(DS33023).
Q
CK
Mid-Range
Reference
Manual,
P
Data Latch
D
3.1
PORTA and the TRISA Register
I/O pin(1)
N
Q
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
WR
TRIS
VSS
Analog
Input
Q
CK
TRIS Latch
Mode
TTL
RD TRIS
Input
Buffer
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
RD PORT
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note: On a Power-on Reset, these pins are con-
Data
Bus
figured as analog inputs and read as '0'.
D
Q
Q
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
WR
PORT
CK
I/O pin(1)
N
Data Latch
D
Q
VSS
EXAMPLE 3-1: INITIALIZING PORTA
WR
TRIS
BCF
BCF
CLRF
STATUS, RP0
STATUS, RP1
PORTA
;
Schmitt
Trigger
Input
Q
CK
; Bank0
; Initialize PORTA by
; clearing output
; data latches
TRIS Latch
Buffer
BSF
STATUS, RP0
0x06
ADCON1
0xCF
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
RD TRIS
MOVLW
MOVWF
MOVLW
Q
D
EN
RD PORT
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
1999 Microchip Technology Inc.
DS30292B-page 29
PIC16F87X
TABLE 3-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Input/output or analog input
Input/output or analog input
Input/output or analog input
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Input/output or analog input or VREF
Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4
bit5
TTL
Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on: Value on all
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
resets
--0x 0000 --0u 0000
--11 1111 --11 1111
--0- 0000 --0- 0000
05h
85h
9Fh
PORTA
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
TRISA
PORTA Data Direction Register
PCFG3 PCFG2 PCFG1 PCFG0
ADCON1 ADFM
—
—
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG3:PCFG0 = 0100,0101, 011x, 1101, 1110, 1111.
DS30292B-page 30
1999 Microchip Technology Inc.
PIC16F87X
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Three pins of PORTB are multiplexed with the Low Volt-
age Programming function; RB3/PGM, RB6/PGC and
RB7/PGD. The alternate functions of these pins are
described in the Special Features Section.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
VDD
RBPU(2)
weak
pull-up
RB0/INT is discussed in detail in Section 12.10.1.
P
Data Latch
Data Bus
WR Port
D
Q
FIGURE 3-4: BLOCK DIAGRAM OF
I/O
pin(1)
RB7:RB4 PINS
CK
TRIS Latch
VDD
RBPU(2)
weak
P
D
Q
pull-up
TTL
Data Latch
Data Bus
Input
Buffer
WR TRIS
CK
D
Q
I/O
pin(1)
WR Port
CK
TRIS Latch
RD TRIS
RD Port
D
Q
Q
D
WR TRIS
TTL
Input
Buffer
CK
EN
ST
Buffer
RB0/INT
RB3/PGM
RD TRIS
RD Port
Latch
Schmitt Trigger
Buffer
RD Port
Q
Q
D
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
EN
Q1
Set RBIF
D
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
From other
RB7:RB4 pins
RD Port
Q3
EN
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Note: When using Low Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the
TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device.
1999 Microchip Technology Inc.
DS30292B-page 31
PIC16F87X
TABLE 3-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
bit2
bit3
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
RB2
RB3/PGM
Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4
bit4
bit5
bit6
bit7
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6/PGC
RB7/PGD
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
other
resets
06h, 106h
86h, 186h
81h, 181h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
PS2
RB1
PS1
RB0 xxxx xxxx uuuu uuuu
1111 1111 1111 1111
TRISB
PORTB Data Direction Register
RBPU INTEDG T0CS T0SE PSA
OPTION_REG
PS0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30292B-page 32
1999 Microchip Technology Inc.
PIC16F87X
3.3
PORTC and the TRISC Register
FIGURE 3-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
OVERRIDE) RC<3:4>
PORT/PERIPHERAL Select(2)
Peripheral Data Out
VDD
0
Data Bus
D
Q
Q
P
WR
1
PORT
CK
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC (3:4) pins
can be configured with normal I2C levels or with
SMBUS levels by using the CKE bit (SSPSTAT <6>).
Data Latch
I/O
pin(1)
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
Vss
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
Schmitt
Trigger
with
SMBus
levels
EN
RD
PORT
0
SSPl Input
1
CKE
SSPSTAT<6>
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<0:2>
RC<5:7>
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
PORT/PERIPHERAL Select(2)
Peripheral Data Out
VDD
0
Data Bus
D
Q
Q
P
WR
1
PORT
CK
Data Latch
I/O
pin(1)
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
EN
RD
PORT
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
1999 Microchip Technology Inc.
DS30292B-page 33
PIC16F87X
TABLE 3-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI bit0
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI/CCP2
bit1
bit2
bit3
Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output
RC2/CCP1
ST
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3 can also be the synchronous serial clock for both SPI and I2C
RC3/SCK/SCL
modes.
RC4/SDI/SDA
RC5/SDO
bit4
bit5
bit6
ST
ST
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port data output
RC6/TX/CK
Input/output port pin or USART Asynchronous Transmit or Synchro-
nous Clock
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive or Synchro-
nous Data
Legend: ST = Schmitt Trigger input
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
all
other
resets
Value on:
POR,
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
07h
87h
PORTC RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
TRISC PORTC Data Direction Register
Legend: x= unknown, u= unchanged.
DS30292B-page 34
1999 Microchip Technology Inc.
PIC16F87X
3.4
PORTD and TRISD Registers
FIGURE 3-7: PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
This section is not applicable to the PIC16F873 or
PIC16F876.
Data
Bus
D
Q
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
WR
PORT
I/O pin(1)
CK
Data Latch
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
D
Q
WR
TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 3-7:
Name
PORTD FUNCTIONS
Bit#
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Buffer Type
Function
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 3-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
RD3
—
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD
TRISD
TRISE
RD7
RD6
RD5
RD4
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by PORTD.
1999 Microchip Technology Inc.
DS30292B-page 35
PIC16F87X
3.5
PORTE and TRISE Register
FIGURE 3-8: PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
This section is not applicable to the PIC16F873 or
PIC16F876.
Data
Bus
D
Q
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
WR
PORT
I/O pin(1)
CK
Data Latch
D
Q
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
WR
TRIS
Schmitt
Trigger
input
CK
TRIS Latch
buffer
RD TRIS
Register 3-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
Q
D
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as ’0’s.
EN
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs.
REGISTER 3-1: TRISE REGISTER (ADDRESS 89h)
R-0
IBF
bit7
R-0
R/W-0
IBOV
R/W-0
U-0
R/W-1
R/W-1
R/W-1
bit0
OBF
PSPMODE
—
bit2
bit1
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n= Value at POR reset
Parallel Slave Port Status/Control Bits
bit 7 :
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
bit 6:
bit 5:
bit 4:
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel slave port mode
0= General purpose I/O mode
bit 3:
bit 2:
Unimplemented: Read as ’0’
PORTE Data Direction Bits
Bit2: Direction Control bit for pin RE2/CS/AN7
1= Input
0= Output
bit 1:
bit 0:
Bit1: Direction Control bit for pin RE1/WR/AN6
1= Input
0= Output
Bit0: Direction Control bit for pin RE0/RD/AN5
1= Input
0= Output
DS30292B-page 36
1999 Microchip Technology Inc.
PIC16F87X
TABLE 3-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
ST/TTL(1)
Input/output port pin or read control input in parallel slave port mode or
analog input:
RE0/RD/AN5
bit0
RD
1= Not a read operation
0= Read operation. Reads PORTD register (if chip selected)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or write control input in parallel slave port mode or
analog input:
WR
1= Not a write operation
0= Write operation. Writes PORTD register (if chip selected)
RE1/WR/AN6
RE2/CS/AN7
bit1
bit2
Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1= Device is not selected
0= Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
BOR
Value on all
other resets
Addr
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
89h
9Fh
PORTE
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
0000 -111 0000 -111
TRISE
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
ADCON1 ADFM
—
—
—
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.
1999 Microchip Technology Inc.
DS30292B-page 37
PIC16F87X
3.6
Parallel Slave Port
FIGURE 3-9: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
The Parallel Slave Port is not implemented on the
PIC16F873 or PIC16F876.
PORTD operates as an 8-bit wide Parallel Slave Port or
microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
Data Bus
D
Q
WR
PORT
RDx
pin
CK
TTL
Q
D
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port con-
figuration bits PCFG3:PCFG0 (ADCON1<3:0>) must
be set to configure pins RE2:RE0 as digital I/O.
RD
PORT
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
There are actually two 8-bit latches. One for data-out
and one for data input. The user writes 8-bit data to the
PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, the TRISD register is ignored, since the micro-
processor is controlling the direction of data flow.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-10). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
Note: I/O pin has protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-11) indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
DS30292B-page 38
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
09h
89h
0Ch
8Ch
9Fh
PORTD Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
PORTE
TRISE
PIR1
—
—
—
—
—
—
RE2
RE1
RE0
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
PSPIF ADIF RCIF
PSPIE ADIE RCIE
TXIF
TXIE
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
PIE1
ADCON1 ADFM
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
1999 Microchip Technology Inc.
DS30292B-page 39
PIC16F87X
NOTES:
DS30292B-page 40
1999 Microchip Technology Inc.
PIC16F87X
The value written to program memory does not need to
be a valid instruction. Therefore, up to 14-bit numbers
can be stored in memory for use as calibration param-
eters, serial numbers, packed 7-bit ASCII, etc. Execut-
ing a program memory location containing data that
forms an invalid instruction results in a NOP.
4.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire VDD range. A bulk erase operation may not be
issued from user code (which includes removing code
protection). The data memory is not directly mapped in
the register file space. Instead it is indirectly addressed
through the Special Function Registers (SFR).
4.1
EEADR
The address registers can address up to a maximum of
256 bytes of data EEPROM or up to a maximum of 8K
words of program FLASH.
There are six SFRs used to read and write the program
and data EEPROM memory. These registers are:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
When selecting a program address value, the MSByte
of the address is written to the EEADRH register and
the LSByte is written to the EEADR register. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register.
• EEADRH
On the PIC16F873/874 devices with 128 bytes of
EEPROM, the MSbit of the EEADR must always be
cleared to prevent inadvertent access to the wrong
location. This also applies to the program memory. The
upper MSbits of EEADRH must always be clear.
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. The
registers EEDATH and EEADRH are not used for data
EEPROM access. These devices have up to 256 bytes
of data EEPROM with an address range from 0h to
FFh.
4.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write sequence.
The EEPROM data memory is rated for high erase/
write cycles. The write time is controlled by an on-chip
timer. The write time will vary with voltage and temper-
ature, as well as from chip-to-chip. Please refer to the
specifications for exact limits.
Control bit EEPGD determines if the access will be a
program or a data memory access. When clear, any
subsequent operations will operate on the data mem-
ory. When set, any subsequent operations will operate
on the program memory.
The program memory allows word reads and writes.
Program memory access allows for checksum calcula-
tion and calibration table storage. A byte or word write
automatically erases the location and writes the new
data (erase before write). Writing to program memory
will cease operation until the write is complete. The pro-
gram memory cannot be accessed during the write,
therefore code cannot execute. During the write opera-
tion, the oscillator continues to clock the peripherals,
and therefore they continue to operate. Interrupt events
will be detected and essentially “queued” until the write
is completed. When the write completes, the next
instruction in the pipeline is executed and the branch to
the interrupt vector address will occur.
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The value of
the data and address registers and the EEPGD bit
remains unchanged.
When interfacing to the program memory block, the
EEDATH:EEDATA registers form a two byte word,
which holds the 14-bit data for read/write. The
EEADRH:EEADR registers form a two byte word,
which holds the 13-bit address of the EEPROM loca-
tion being accessed. These devices can have up to 8K
words of program EEPROM with an address range
from 0h to 3FFFh. The unused upper bits in both the
EEDATH and EEDATA registers all read as “0’s”.
Interrupt flag bit EEIF, in the PIR2 register, is set when
write is complete. It must be cleared in software.
1999 Microchip Technology Inc.
DS30292B-page 41
PIC16F87X
REGISTER 4-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
EEPGD
bit7
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
RD
—
—
—
WRERR WREN
WR
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n= Value at POR reset
bit 7:
EEPGD: Program / Data EEPROM Select bit
1= Accesses Program memory
0= Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
bit 6:4: Unimplemented: Read as '0'
bit 3:
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0= The write operation completed
bit 2:
bit 1:
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be
set (not cleared) in software.
0= Write cycle to the EEPROM is complete
bit 0:
RD: Read Control bit
1= Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0= Does not initiate an EEPROM read
DS30292B-page 42
1999 Microchip Technology Inc.
PIC16F87X
4.3
Reading the Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is writ-
ten to by the user (during a write operation).
EXAMPLE 4-1: DATA EEPROM READ
BSF
BCF
STATUS, RP1
;
STATUS, RP0 ;Bank 2
MOVLW DATA_EE_ADDR
MOVWF EEADR
;
;Data Memory Address to read
BSF
BCF
BSF
BCF
STATUS, RP0 ;Bank 3
EECON1, EEPGD;Point to DATA memory
EECON1, RD
STATUS, RP0 ;Bank 2
;W = EEDATA
;EEPROM Read
MOVF EEDATA, W
4.4
Writing to the Data EEPROM Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then the sequence in
Example 4-2 must be followed to initiate the write cycle.
EXAMPLE 4-2: DATA EEPROM WRITE
BSF
STATUS, RP1
STATUS, RP0
DATA_EE_ADDR
EEADR
;
BCF
; Bank 2
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; Data Memory Address to write
DATA_EE_DATA
EEDATA
;
; Data Memory Value to write
; Bank 3
STATUS, RP0
BCF
EECON1, EEPGD ; Point to DATA memory
EECON1, WREN ; Enable writes
BSF
BCF
INTCON, GIE
55h
; Disable Interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
;
Required
Sequence
EECON2
; Write 55h
AAh
;
EECON2
; Write AAh
EECON1, WR
INTCON, GIE
; Set WR bit to begin write
; Enable Interrupts
BSF
SLEEP
BCF
; Wait for interrupt to signal write complete
EECON1, WREN ; Disable writes
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
1999 Microchip Technology Inc.
DS30292B-page 43
PIC16F87X
data is available in the EEDATA and EEDATH registers
after the second NOP instruction. Therefore, it can be
read as two bytes in the following instructions. The
EEDATA and EEDATH registers will hold this value until
another read operation or until it is written to by the user
(during a write operation).
4.5
Reading the FLASH Program Memory
A program memory location may be read by writing two
bytes of the address to the EEADR and EEADRH reg-
isters, setting the EEPGD control bit (EECON1<7>)
and then setting control bit RD (EECON1<0>). Once
the read control bit is set, the microcontroller will use
the next two instruction cycles to read the data. The
EXAMPLE 4-3: FLASH PROGRAM READ
BSF
STATUS, RP1
STATUS, RP0
ADDRH
;
BCF
; Bank 2
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EEADRH
; MSByte of Program Address to read
ADDRL
;
EEADR
; LSByte of Program Address to read
; Bank 3
STATUS, RP0
EECON1, EEPGD
EECON1, RD
BSF
; Point to PROGRAM memory
; EEPROM Read
Required
Sequence
BSF
NOP
NOP
; memory is read in the next two cycles after BSF EECON1,RD
;
BCF
STATUS, RP0
; Bank 2
MOVF
MOVF
EEDATA, W
EEDATH, W
; W = LSByte of Program EEDATA
; W = MSByte of Program EEDATA
DS30292B-page 44
1999 Microchip Technology Inc.
PIC16F87X
trol bit (EECON1<7>), and then set control bit WR
(EECON1<1>). The sequence in Example 4-4 must be
followed to initiate a write to program memory.
4.6
Writing to the FLASH Program
Memory
A word of the FLASH program memory may only be
written to if the word is in a non-code protected seg-
ment of memory and the WRT configuration bit is set.
To write a FLASH program location, the first two bytes
of the address must be written to the EEADR and
EEADRH registers and two bytes of the data to the
EEDATA and EEDATH registers, set the EEPGD con-
The microcontroller will then halt internal operations
during the next two instruction cycles for the TPEW
(parameter D133) in which the write takes place. This
is not SLEEP mode, as the clocks and peripherals will
continue to run. Therefore, the two instructions follow-
ing the “BSF EECON, WR” should be NOPinstructions.
After the write cycle, the microcontroller will resume
operation with the 3rd instruction after the EECON1
write instruction.
EXAMPLE 4-4: FLASH PROGRAM WRITE
BSF
STATUS, RP1
STATUS, RP0
ADDRH
;
BCF
; Bank 2
;
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EEADRH
; MSByte of Program Address to read
ADDRL
;
EEADR
; LSByte of Program Address to read
DATAH
;
EEDATH
; MS Program Memory Value to write
;
DATAL
EEDATA
; LS Program Memory Value to write
; Bank 3
STATUS, RP0
EECON1, EEPGD
EECON1, WREN
BSF
; Point to PROGRAM memory
; Enable writes
BSF
BCF
INTCON, GIE
55h
; Disable Interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
;
Required
Sequence
EECON2
AAh
; Write 55h
;
EECON2
EECON1, WR
; Write AAh
; Set WR bit to begin write
NOP
NOP
; Instructions here are ignored by the microcontroller
; Microcontroller will halt operation and wait for
; a write complete. After the write
; the microcontroller continues with 3rd instruction
; Enable Interrupts
BSF
BCF
INTCON, GIE
EECON1, WREN
; Disable writes
4.7
Write Verify
Depending on the application, good programming prac-
tice may dictate that the value written to the memory
should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
Generally a write failure will be a bit which was written
as a '1', but reads back as a '0' (due to leakage off the
bit).
1999 Microchip Technology Inc.
DS30292B-page 45
PIC16F87X
4.8
Protection Against Spurious Write
4.9
Operation during Code Protect
4.8.1
EEPROM DATA MEMORY
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
4.9.1
DATA EEPROM MEMORY
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
4.9.2
PROGRAM FLASH MEMORY
4.8.2
PROGRAM FLASH MEMORY
The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
of the state of the code protect configuration bits. How-
ever the WRT configuration bit and the code protect bits
have different effects on writing to program memory.
Table 4-1 shows the various configurations and status
of reads and writes. To erase the WRT or code protec-
tion bits in the configuration word requires that the
device be fully erased.
To protect against spurious writes to FLASH program
memory, the WRT bit in the configuration word may be
programmed to ‘0’ to prevent writes. The write initiate
sequence must also be followed. WRT and the config-
uration word cannot be programmed by user code, only
through the use of an external programmer.
TABLE 4-1:
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Internal
Read
Internal
Write
Memory Location
ICSP Read ICSP Write
CP1
CP0
WRT
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
x
0
0
1
1
0
0
1
1
0
1
All program memory
Unprotected areas
Protected areas
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
No
No
Yes
No
No
Yes
No
Yes
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Unprotected areas
Protected areas
Yes
No
Unprotected areas
Protected areas
Yes
No
Unprotected areas
Protected areas
Yes
No
All program memory
All program memory
Yes
Yes
TABLE 4-2:
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Bh, 18Bh
10Dh
10Fh
10Ch
10Eh
18Ch
18Dh
8Dh
EEADR
EEPROM address register
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
x--- u000
EEADRH
—
—
—
EEPROM address high
EEDATA EEPROM data resister
EEDATH
EECON1
—
—
—
EEPROM data resister high
WRERR
EEPGD
—
—
WREN
WR
RD
EECON2 EEPROM control resister2 (not a physical resister)
PIE2
PIR2
—
—
(1)
(1)
—
—
EEIE
EEIF
BCLIE
BCLIF
—
—
—
—
CCP2IE
CCP2IF
-r-0 0--0
-r-0 0--0
-r-0 0--0
-r-0 0--0
0Dh
Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented read as ’0’. Shaded cells are not used during FLASH/
EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.
DS30292B-page 46
1999 Microchip Technology Inc.
PIC16F87X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer0 Interrupt
Additional information on the Timer0 module is available
in the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (= FOSC/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
Pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set Flag Bit T0IF
on Overflow
PSA
PRESCALER
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
1999 Microchip Technology Inc.
DS30292B-page 47
PIC16F87X
module means that there is no prescaler for the watch-
dog timer, and vice-versa. This prescaler is not readable
or writable (see Figure 5-1).
5.2
Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>) deter-
mine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
5.3
Prescaler
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
REGISTER 5-1: OPTION_REG REGISTER
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1 R/W-1 R/W-1
PSA PS2 PS1
R/W-1
PS0
R
= Readable bit
INTEDG
W = Writable bit
U
bit 7
bit 0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
RBPU
INTEDG
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4:
bit 3:
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
DS30292B-page 48
1999 Microchip Technology Inc.
PIC16F87X
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h,101h
TMR0
INTCON
OPTION_REG RBPU INTEDG T0CS
Timer0 module’s register
xxxx xxxx uuuu uuuu
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
0Bh,8Bh,
10Bh,18Bh
GIE PEIE T0IE
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
81h,181h
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1999 Microchip Technology Inc.
DS30292B-page 49
PIC16F87X
NOTES:
DS30292B-page 50
1999 Microchip Technology Inc.
PIC16F87X
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by either of the two CCP modules
(Section 8.0). Register 6-1 shows the Timer1 control
register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
Additional information on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
1999 Microchip Technology Inc.
DS30292B-page 51
PIC16F87X
6.1
Timer1 Operation in Timer Mode
6.2
Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
Timer1 may operate in asynchronous or usynchronous
mode depnding on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After
Timer1 is enabled in counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
clock input
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
(2)
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
(2)
RC1/T1OSI/CCP2
2
Q Clock
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F873/876, the Schmitt Trigger is not implemented in external clock mode.
DS30292B-page 52
1999 Microchip Technology Inc.
PIC16F87X
6.4
Timer1 Operation in Asynchronous
Counter Mode
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Note 1: Higher capacitance increases the stability of
oscillator but also increases the start-up time.
2: Since each resonator/crystal has its own charac-
teristics, the user should consult the resonator/
crystal manufacturer for appropriate values of
external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
6.6
Resetting Timer1 using a CCP Trigger
Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 or CCP2 module is configured in compare
mode to generate “special event trigger”
a
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Reading the 16-bit value requires some care. Examples
12-2 and 12-3 in the PICmicro™ Mid-Range MCU Fam-
ily Reference Manual (DS33023) show how to read and
write Timer1 when it is running in asynchronous mode.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 and CCP2
special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
1999 Microchip Technology Inc.
DS30292B-page 53
PIC16F87X
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
10Bh,
18Bh
(1)
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/874; always maintain these bits clear.
DS30292B-page 54
1999 Microchip Technology Inc.
PIC16F87X
7.1
Timer2 Prescaler and Postscaler
7.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device reset.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (POR, MCLR reset, WDT reset
or BOR)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
TMR2 is not cleared when T2CON is written.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSPort module, which optionally uses it to generate
shift clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
Sets flag
TMR2
output (1)
bit TMR2IF
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Reset
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FOSC/4
Register 7-1 shows the Timer2 control register.
Postscaler
2
Comparator
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
1:1 to 1:16
EQ
T2CKPS1:
T2CKPS0
4
PR2 reg
T2OUTPS3:
T2OUTPS0
Note 1: TMR2 register output can be software selected
by the SSP module as a baud clock.
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
1999 Microchip Technology Inc.
DS30292B-page 55
PIC16F87X
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh,18Bh
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
PIR1
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
11h
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
12h
—
92h
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/874; always maintain these bits clear.
DS30292B-page 56
1999 Microchip Technology Inc.
PIC16F87X
CCP2 Module:
8.0
CAPTURE/COMPARE/PWM
MODULES
Capture/Compare/PWM Register1 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is gen-
erated by a compare match and will reset Timer1 and
start an A/D conversion (if the A/D module is enabled).
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM master/slave Duty Cycle register
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note 594, “Using
the CCP Modules” (DS00594).
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
TABLE 8-1:
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
CCP1 Module:
Capture
Compare
PWM
Timer1
Timer1
Timer2
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is gen-
erated by a compare match and will reset Timer1.
TABLE 8-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
Capture
Compare
Compare
PWM
Same TMR1 time-base.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
Compare
None.
None.
PWM
1999 Microchip Technology Inc.
DS30292B-page 57
PIC16F87X
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1dh)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit, read as
‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets
TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
DS30292B-page 58
1999 Microchip Technology Inc.
PIC16F87X
8.1.2
TIMER1 MODE SELECTION
8.1
Capture Mode
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
• Every falling edge
• Every rising edge
8.1.3
SOFTWARE INTERRUPT
• Every 4th rising edge
• Every 16th rising edge
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
8.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. Any reset will clear the
prescaler counter.
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a cap-
ture condition.
FIGURE 8-1: CAPTURE MODE OPERATION
BLOCK DIAGRAM
Set flag bit CCP1IF
(PIR1<2>)
Prescaler
÷ 1, 4, 16
EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
RC2/CCP1
Pin
CCPR1H
CCPR1L
TMR1L
CLRF
CCP1CON
;Turn CCP module off
MOVLW
NEW_CAPT_PS ;Load the W reg with
; the new precscaler
Capture
Enable
and
edge detect
; move value and CCP ON
TMR1H
MOVWF
CCP1CON
;Load CCP1CON with this
; value
CCP1CON<3:0>
Q’s
1999 Microchip Technology Inc.
DS30292B-page 59
PIC16F87X
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
8.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
• Driven high
• Driven low
• Remains unchanged
8.3
PWM Mode (PWM)
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
In pulse width modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
FIGURE 8-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
Figure 8-3 shows a simplified block diagram of the CCP
module in PWM mode.
Set flag bit CCP1IF
(PIR1<2>)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCPR1H (Slave)
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Q
R
S
Comparator
8.2.2
TIMER1 MODE SELECTION
RC2/CCP1
(Note 1)
TMR2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
8.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
DS30292B-page 60
1999 Microchip Technology Inc.
PIC16F87X
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 8-4: PWM OUTPUT
Maximum PWM resolution (bits) for a given PWM
frequency:
Period
FOSC
log( )
FPWM
Resolution
bits
=
Duty Cycle
TMR2 = PR2
log(2)
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
8.3.3
SET-UP FOR PWM OPERATION
8.3.1
PWM PERIOD
The following steps should be taken when configuring
the CCP module for PWM operation:
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
8.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
1999 Microchip Technology Inc.
DS30292B-page 61
PIC16F87X
TABLE 8-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
(1)
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF
—
ADIF
—
RCIF
—
TXIF
—
SSPIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
(1)
PIE1
PSPIE
—
ADIE
—
RCIE
—
TXIE
—
SSPIE
—
PIE2
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
PORTC Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB)
CCP1CON
CCPR2L
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
CCP2CON CCP2X CCP2Y
xxxx xxxx uuuu uuuu
—
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F873/876; always maintain these bits clear.
TABLE 8-4:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF
0000 0000 0000 0000
(1)
0Ch
0Dh
8Ch
8Dh
87h
11h
92h
12h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF
—
ADIF
—
RCIF
—
TXIF
—
SSPIF
—
PIR2
—
—
CCP2IF ---- ---0 ---- ---0
(1)
PIE1
PSPIE
—
ADIE
—
RCIE
—
TXIE
—
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000
---- ---0 ---- ---0
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
PIE2
—
—
—
CCP2IE
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 module’s register
Timer2 module’s period register
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
DS30292B-page 62
1999 Microchip Technology Inc.
PIC16F87X
9.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
2
• Inter-Integrated Circuit (I C)
Figure 9-1 shows a block diagram for the SPI mode,
while Figure 9-5 and Figure 9-9 show the block dia-
2
grams for the two different I C modes of operation.
1999 Microchip Technology Inc.
DS30292B-page 63
PIC16F87X
REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0 R/W-0
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
SMP
bit7
CKE
R/W
bit0
- n = Value at POR reset
bit 7:
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6:
CKE: SPI Clock Edge Select (Figure 9-4, Figure 9-5 and Figure 9-6)
SPI Mode:
CKP = 0
1 = Transmit happens on transistion from active clock state to idle clock state
0 = Transmit happens on transistion from idle clock state to active clock state
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
In I2C Master or Slave Mode:
1 = Input levels conform to SMBUS spec
0 = Input levels conform to I2C specs
bit 5:
bit 4:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
bit 2:
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to
the next start bit, stop bit or not ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1:
bit 0:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
DS30292B-page 64
1999 Microchip Technology Inc.
PIC16F87X
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
SSPOV
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
WCOL
bit7
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit0
- n = Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
Master Mode:
2
1 = A write to SSPBUF was attempted while the I C conditions were not valid
0 = No collision
Slave Mode:
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. . In
slave mode the user must read the SSPBUF, even if only transmitting data, to avoid overflows. In master
mode the overflow bit is not set since each operation is initiated by writing to the SSPBUF register. (Must
be cleared in software).
0 = No overflow
2
In I C mode
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in trans-
mit mode. (Must be cleared in software).
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode, when enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I C mode, when enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
2
In I C slave mode, SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
2
In I C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
2
0110 = I C slave mode, 7-bit address
2
0111 = I C slave mode, 10-bit address
2
1000 = I C master mode, clock = FOSC / (4 * (SSPADD+1) )
2
1011 = I C firmware controlled master mode (slave idle)
2
1110 = I C firmware controlled master mode, 7-bit address with start and stop bit interrupts enabled
2
1111 = I C firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled.
1001, 1010, 1100, 1101 = reserved
1999 Microchip Technology Inc.
DS30292B-page 65
PIC16F87X
REGISTER 9-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
R =Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
GCEN
bit7
ACKSTAT
ACKDT
ACKEN
SEN
bit0
- n =Value at POR reset
2
bit 7:
bit 6:
GCEN: General Call Enable bit (In I C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
2
ACKSTAT: Acknowledge Status bit (In I C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
2
bit 5:
bit 4:
ACKDT: Acknowledge Data bit (In I C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
2
ACKEN: Acknowledge Sequence Enable bit (In I C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence idle
2
bit 3:
RCEN: Receive Enable bit (In I C master mode only).
2
1 = Enables Receive mode for I C
0 = Receive idle
2
bit 2:
PEN: Stop Condition Enable bit (In I C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
2
bit 1: RSEN: Repeated Start Condition Enabled bit (In I C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
2
bit 0: SEN: Start Condition Enabled bit (In I C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
2
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I C module is not in the idle mode, this bit may not
be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS30292B-page 66
1999 Microchip Technology Inc.
PIC16F87X
9.1
SPI Mode
FIGURE 9-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
Internal
Data Bus
Read
Write
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
SSPBUF reg
SSPSR reg
Additionally, a fourth pin may be used when in a slave
mode of operation:
Shift
Clock
SDI
bit0
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
SDO
Control
Enable
SS
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
SS
Edge
Select
• Data input sample phase
(middle or end of data output time)
2
Clock Select
• Clock edge
(output data on rising/falling edge of SCK)
SSPM3:SSPM0
SMP:CKE
• Clock Rate (Master mode only)
4
TMR2 output
2
2
• Slave Select Mode (Slave mode only)
Edge
Select
Figure 9-4 shows the block diagram of the MSSP mod-
ule when in SPI mode.
TOSC
Prescaler
4, 16, 64
SCK
Data to TX/RX in SSPSR
Data direction bit
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
1999 Microchip Technology Inc.
DS30292B-page 67
PIC16F87X
9.1.1
MASTER MODE
Figure 9-6, Figure 9-8 and Figure 9-9 where the MSb is
transmitted first. In master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broad-
cast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
FIGURE 9-2: SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
SSPIF
bit7
bit0
DS30292B-page 68
1999 Microchip Technology Inc.
PIC16F87X
9.1.2
SLAVE MODE
While in sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from sleep.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
Note: When the SPI module is in Slave Mode
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
reset if the SS pin is set to VDD.
While in slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
Note: If the SPI is used in Slave Mode with
CKE = '1', then SS pin control must be
enabled.
FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
1999 Microchip Technology Inc.
DS30292B-page 69
PIC16F87X
TABLE 9-1
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
POR,
BOR
MCLR,
WDT
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
13h
14h
94h
PIR1
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
PIE1
SSPBUF
SSPCON
SSPSTAT
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
0000 0000 0000 0000
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: These bits are reserved on the 28-pin devices; always maintain these bits clear.
DS30292B-page 70
1999 Microchip Technology Inc.
PIC16F87X
2
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
9.2
MSSP I C Operation
2
The MSSP module in I C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts-on-start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
2
2
The MSSP module has six registers for I C operation.
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
Refer to Application Note AN578, "Use of the SSP
Module in the I C Multi-Master Environment."
2
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independant of device frequency.
• SSP Address Register (SSPADD)
2
The SSPCON register allows control of the I C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I C modes to be selected:
2
FIGURE 9-5: I C SLAVE MODE BLOCK
2
DIAGRAM
2
• I C Slave mode (7-bit address)
Internal
Data Bus
2
• I C Slave mode (10-bit address)
2
• I C Master mode, clock = OSC/4 (SSPADD +1)
Read
Write
2
Before selecting any I C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I C mode, by setting the
SSPBUF reg
SSPSR reg
2
SCL
SDA
SSPEN bit, enables the SCL and SDA pins to be used
Shift
Clock
2
as the clock and data lines in I C mode.
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either master or slave mode.
When CKE = 1, the levels will conform to the SMBUS
specification. When CKE = 0, the levels will conform to
MSb
LSb
Addr Match
Match detect
SSPADD reg
2
the I C specification.
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit detect
1999 Microchip Technology Inc.
DS30292B-page 71
PIC16F87X
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address, if the next byte is the comple-
tion of 10-bit address, and if this will be a read or write
data transfer.
9.2.1.1
ADDRESSING
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
SSPBUF is the register to which the transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
a) The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
b) The buffer full bit, BF, is set on the falling edge of
the 8th SCL pulse.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) on the falling
edge of the 9th SCL pulse.
The SSPADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slave-transmit-
ter:
9.2.1
SLAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required (slave-
transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
1. Receive first (high) byte of Address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with the second
(low) byte of Address (clears bit UA and
releases the SCL line).
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF and UA are set).
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
5. Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set. Table 9-2 shows what happens when a data trans-
fer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister, while bit SSPOV is cleared through software.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I C specification, as well as the requirement of
the MSSP module, is shown in timing parameter #100
and parameter #101 of the electrical specifications.
Note: Following the Repeated Start condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
2
DS30292B-page 72
1999 Microchip Technology Inc.
PIC16F87X
9.2.1.2
SLAVE RECEPTION
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is updated.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
TABLE 9-2
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
Generate ACK
Pulse
(SSP Interrupt occurs
if enabled)
BF
SSPOV
SSPSR → SSPBUF
0
1
1
0
0
0
1
1
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Ye s
No
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
9.2.1.3
SLAVE TRANSMISSION
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP (SSP-
CON<4>). The master must monitor the SCL pin prior
to asserting another clock pulse. The slave devices
may be holding off the master by stretching the clock.
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 9-7).
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
2
FIGURE 9-6: I C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W=0
ACK
Not
Receiving Address
A7 A6 A5 A4
Receiving Data
Receiving Data
ACK
ACK
D5
D2
6
D0
8
D5
D2
D0
8
SDA
A3 A2 A1
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
9
5
4
7
1
2
4
9
3
6
9
5
1
2
3
6
1
2
4
8
5
P
SCL
S
SSPIF
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
1999 Microchip Technology Inc.
DS30292B-page 73
PIC16F87X
2
FIGURE 9-7: I C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Not ACK
R/W = 1
Receiving Address
Transmitting Data
ACK
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
9.2.2
GENERAL CALL ADDRESS SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
SSPIF flag is set.
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF to determine if the address was device spe-
cific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is config-
ured in 10-bit address mode, then the second half of
the address is not necessary, the UA bit will not be set,
and the slave will begin receiving data after the
acknowledge (Figure 9-8).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a start-bit detect, 8-bits are shifted
into SSPSR and the address is compared against
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 9-8: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt flag
Receiving data
D5 D4 D3 D2 D1
ACK
9
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
S
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV
(SSPCON<6>)
'0'
'1'
GCEN
(SSPCON2<7>)
DS30292B-page 74
1999 Microchip Technology Inc.
PIC16F87X
9.2.3
SLEEP OPERATION
9.2.4
EFFECTS OF A RESET
2
While in sleep mode, the I C module can receive
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
A reset disables the SSP module and terminates the
current transfer.
2
TABLE 9-3
Address
REGISTERS ASSOCIATED WITH I C OPERATION
POR,
BOR
MCLR,
WDT
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
PIR1
PSPIF(1)
PSPIE(1)
—
ADIF
ADIE
(2)
RCIF
RCIE
—
TXIF
TXIE
EEIF
EEIE
SSPIF
SSPIE
BCLIF
BCLIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE1
PIR2
—
—
—
—
CCP2IF -r-0 0--0 -r-0 0--0
CCP2IE -r-0 0--0 -r-0 0--0
xxxx xxxx uuuu uuuu
PIE2
—
(2)
—
SSPBUF
SSPCON
SSPCON2
SSPSTAT
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
GCEN
SMP
SSPOV
ACKSTAT
CKE
SSPEN
ACKDT
D/A
CKP
ACKEN
P
SSPM3 SSPM2
SSPM1
RSEN
UA
SSPM0 0000 0000 0000 0000
RCEN
S
PEN
R/W
SEN
0000 0000 0000 0000
0000 0000 0000 0000
BF
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: These bits are reserved on the 28-pin devices; always maintain these bits clear.
2: These bits are reserved on these devices; always maintain these bits clear.
1999 Microchip Technology Inc.
DS30292B-page 75
PIC16F87X
9.2.5
MASTER MODE
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
2
abled. Control of the I C bus may be TACKEN when the
• STOP condition
P bit is set, or the bus is idle with both the S and P bits
clear.
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
2
FIGURE 9-9: SSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0,
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
Shift
Clock
SDA
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
SCL in
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
DS30292B-page 76
1999 Microchip Technology Inc.
PIC16F87X
2
9.2.6
MULTI-MASTER MODE
9.2.7.1
I C MASTER MODE OPERATION
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
Start condition. Since the Repeated Start condition is
2
2
when the MSSP module is disabled. Control of the I C
also the beginning of the next serial transfer, the I C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
bus will not be released.
In Master Transmitter mode serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In multi-master operation, the SDA line must be moni-
tored for abitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
In Master receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
2
9.2.7
I C MASTER MODE SUPPORT
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once master mode is enabled, the user
has six options.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
-
-
Assert a start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
2
100 kHz, 400 kHz or 1 MHz I C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the SSP-
BUF. Once the given operation is complete (i.e. trans-
mission of the last data bit is followed by ACK) the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
-
Write to the SSPBUF register initiating trans-
mission of data/address.
-
-
-
Generate a stop condition on SDA and SCL.
Configure the I C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
2
A typical transmit sequence would go as follows:
2
Note: The MSSP Module, when configured in I C
Master Mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a start condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
a) The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
b) SSPIF is set. The module will wait the required
start time before any other operation takes
place.
c) The user loads the SSPBUF with address to
transmit.
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
e) The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register ( SSPCON2<6>).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of
data.
h) DATA is shifted out the SDA pin until all 8 bits
are transmitted.
1999 Microchip Technology Inc.
DS30292B-page 77
PIC16F87X
i) The MSSP module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
In I2C master mode, the BRG is reloaded automatically.
If Clock Arbitration is taking place for instance, the BRG
will be reloaded when the SCL pin is sampled high
(Figure 9-11).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
FIGURE 9-10: BAUD RATE GENERATOR
BLOCK DIAGRAM
k) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
SSPM3:SSPM0
SSPADD<6:0>
l) Interrupt is generated once the STOP condition
is complete.
9.2.8
BAUD RATE GENERATOR
SSPM3:SSPM0
SCL
Reload
Control
Reload
2
In I C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 9-10). When the BRG is loaded with this value,
the BRG counts down to 0 and stops until another
reload has taken place. The BRG count is decremented
twice per instruction cycle (TCY), on the Q2 and Q4
clock.
FOSC/4
BRG Down Counter
CLKOUT
FIGURE 9-11: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements
(on Q2 and Q4 cycles)
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
reload
DS30292B-page 78
1999 Microchip Technology Inc.
PIC16F87X
2
9.2.9
I C MASTER MODE START CONDITION
TIMING
Note: If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag (BCLIF) is set,
the START condition is aborted, and the
To initiate a START condition, the user sets the start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is re-loaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended
leaving the SDA line held low, and the START condition
is complete.
2
I C module is reset into its IDLE state.
9.2.9.1
WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 9-12: FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
At completion of start bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
1st Bit 2nd Bit
SDA
TBRG
SCL
TBRG
S
1999 Microchip Technology Inc.
DS30292B-page 79
PIC16F87X
2
9.2.10 I C MASTER MODE REPEATED START
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I C mod-
2
ule is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low. When the SCL pin is sampled
low, the baud rate generator is loaded with the contents
of SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (TBRG). When the baud rate generator times out
if SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA is low) for
one TBRG, while SCL is high. Following this, the RSEN
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not beset until the baud rate generator hastimed-out.
9.2.10.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
Note 2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
FIGURE 9-13: REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
SCL = 1
occurs here.
At completion of start bit,
hardware clear RSEN bit
and set SSPIF
SDA = 1,
SCL(no change)
TBRG
TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here.
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated Start
DS30292B-page 80
1999 Microchip Technology Inc.
PIC16F87X
2
9.2.11 I C MASTER MODE TRANSMISSION
9.2.11.3 ACKSTAT STATUS FLAG
Transmission of a data byte, a 7-bit address or either
half of a 10-bit address is accomplished by simply writ-
ing a value to SSPBUF register. This action will set the
buffer full flag (BF) and allow the baud rate generator to
begin counting and start the next transmission. Each
bit of address/data will be shifted out onto the SDA pin
after the falling edge of SCL is asserted (see data hold
time spec). SCL is held low for one baud rate gener-
ator rollover count (TBRG). Data should be valid before
SCL is released high (see data setup time spec).
When the SCL pin is released high, it is held that way
for TBRG. The data on the SDA pin must remain stable
for that duration and some hold time after the next fall-
ing edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF flag is cleared
and the master releases SDA allowing the slave device
being addressed to respond with an ACK bit during the
ninth bit time, if an address match occurs or if data was
received properly. The status of ACK is read into the
ACKDT on the falling edge of the ninth clock. If the
master receives an acknowledge, the acknowledge
status bit (ACKSTAT) is cleared. If not, the bit is set.
After the ninth clock, the SSPIF is set and the master
clock (baud rate generator) is suspended until the next
data byte is loaded into the SSPBUF, leaving SCL low
and SDA unchanged (Figure 9-14).
In transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), and is set when the slave does not acknowl-
edge (ACK = 1). A slave sends an acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
9.2.11.1 BF STATUS FLAG
In transmit mode, the BF bit (SSPSTAT<0>) is set when
the CPU writes to SSPBUF and is cleared when all 8
bits are shifted out.
9.2.11.2 WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
1999 Microchip Technology Inc.
DS30292B-page 81
PIC16F87X
2
FIGURE 9-14: I C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS30292B-page 82
1999 Microchip Technology Inc.
PIC16F87X
2
9.2.12 I C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note: The SSP module must be in an IDLE
STATE before the RCEN bit is set or the
RCEN bit will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to
low/low to high), and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the receive
enable flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an acknowledge
bit at the end of reception, by setting the acknowledge
sequence enable bit, ACKEN (SSPCON2<4>).
9.2.12.1 BF STATUS FLAG
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
9.2.12.2 SSPOV STATUS FLAG
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
9.2.12.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e. SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
1999 Microchip Technology Inc.
DS30292B-page 83
PIC16F87X
2
FIGURE 9-15: I C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
DS30292B-page 84
1999 Microchip Technology Inc.
PIC16F87X
9.2.13 ACKNOWLEDGE SEQUENCE TIMING
the baud rate generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the baud rate generator is turned off,
and the SSP module then goes into IDLE mode.
(Figure 9-16)
An acknowledge sequence is enabled by setting the
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to
generate an acknowledge, the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
9.2.13.1 WCOL STATUS FLAG
If the user writes the SSPBUF when an acknowledege
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
(T
), and the SCL pin is deasserted (pulled high).
BRG
When the SCL pin is sampled high (clock arbitration),
FIGURE 9-16: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of acknowledge sequence
Note: TBRG = one baud rate generator period.
1999 Microchip Technology Inc.
DS30292B-page 85
PIC16F87X
9.2.14 STOP CONDITION TIMING
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 9-17).
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/trans-
mit, the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be deasserted. When the SDA pin is sampled high
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
9.2.14.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup stop condition.
Note: TBRG = one baud rate generator period.
DS30292B-page 86
1999 Microchip Technology Inc.
PIC16F87X
9.2.15 CLOCK ARBITRATION
9.2.16 SLEEP OPERATION
2
Clock arbitration occurs when the master, during any
receive, transmit, or repeated start/stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-18).
While in sleep mode, the I C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
9.2.17 EFFECTS OF A RESET
A reset disables the SSP module and terminates the
current transfer.
FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SDA
SCL line sampled once every machine cycle (TOSC • 4).
Hold off BRG until SCL is sampled high.
TBRG
TBRG
TBRG
1999 Microchip Technology Inc.
DS30292B-page 87
PIC16F87X
9.2.18 MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
If a START, Repeated Start, STOP or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I2C bus is free, the user can resume communica-
tion by asserting a START condition.
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
a bus collision has TACKEN place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
2
I C port to its IDLE state. (Figure 9-19).
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted, and
the SSPBUF can be written to. When the user services
In multi-master mode, the interrupt generation on the
detection of start and stop conditions allows the deter-
2
2
the bus collision interrupt service routine, and if the I C
mination of when the bus is free. Control of the I C bus
bus is free, the user can resume communication by
asserting a START condition.
can be TACKEN when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt.
BCLIF
DS30292B-page 88
1999 Microchip Technology Inc.
PIC16F87X
9.2.18.1 BUS COLLISION DURING A START
CONDITION
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
During a START condition, a bus collision occurs if:
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-22). If however a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0. During this time, if the SCL pins are
sampled as '0', a bus collision does not occur. At the
end of the BRG count ,the SCL pin is asserted low.
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-20).
b) SCL is sampled low before SDA is asserted low.
(Figure 9-21).
During a START condition both the SDA and the SCL
pins are monitored.
If:
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, REPEATED
START or STOP conditions.
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 9-20).
The START condition begins with the SDA and SCL
pins deasserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
FIGURE 9-20: BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1
SDA
SCL
Set SEN, enable start
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
SEN
SDA sampled low before
START condition.
Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1
BCLIF
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
1999 Microchip Technology Inc.
DS30292B-page 89
PIC16F87X
FIGURE 9-21: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
SEN
Set SEN, enable start
sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF.
BCLIF
Interrupts cleared
in software.
S
'0'
'0'
'0'
'0'
SSPIF
FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA
SDA
SCL
s
SCL pulled low after BRG
Timeout
SEN
Set SEN, enable start
sequence if SDA = 1, SCL = 1
'0'
BCLIF
S
SSPIF
Interrupts cleared
in software.
SDA = 0, SCL = 1
Set SSPIF
DS30292B-page 90
1999 Microchip Technology Inc.
PIC16F87X
9.2.18.2 BUS COLLISION DURING A REPEATED
START CONDITION
sampled high, the BRG is reloaded and begins count-
ing. If SDA goes from high to low before the BRG times
out, no bus collision occurs, because no two masters
can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, a
bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
Start condition.
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
If at the end of the BRG time out both SCL and SDA are
still high, the SDA pin is driven low, the BRG is reloaded
and begins counting. At the end of the count, regard-
less of the status of the SCL pin, the SCL pin is driven
low and the Repeated Start condition is complete
(Figure 9-23).
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted, and
when sampled high, the SDA pin is sampled. If SDA is
low, a bus collision has occurred (i.e. another master is
attempting to transmit a data ’0’). If however SDA is
FIGURE 9-23: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
RSEN
BCLIF
Cleared in software
'0'
'0'
'0'
S
'0'
SSPIF
FIGURE 9-24: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
BCLIF
RSEN
Interrupt cleared
in software
'0'
'0'
'0'
'0'
S
SSPIF
1999 Microchip Technology Inc.
DS30292B-page 91
PIC16F87X
9.2.18.3 BUS COLLISION DURING A STOP
CONDITION
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allow to float.
When the pin is sampled high (clock arbitration), the
baud rate generator is loaded with SSPADD<6:0> and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs.
This is a case of another master attempting to drive a
data '0' (Figure 9-25).
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 9-25: BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
Set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
'0'
'0'
'0'
'0'
SSPIF
FIGURE 9-26: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high
Set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
'0'
'0'
SSPIF
DS30292B-page 92
1999 Microchip Technology Inc.
PIC16F87X
2
example, with a supply voltage of VDD = 5V+10% and
9.3
Connection Considerations for I C
Bus
VOL max = 0.4V at 3 mA, R
= (5.5-0.4)/0.003 =
p min
1.7 kΩ. VDD as a function of R is shown in Figure 9-27.
p
2
For standard-mode I C bus devices, the values of
The desired noise margin of 0.1VDD for the low level
resistors R and R in Figure 9-27 depend on the fol-
limits the maximum value of R . Series resistors are
p
s
s
lowing parameters:
optional and used to improve ESD susceptibility.
• Supply voltage
• Bus capacitance
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
• Number of connected devices
(input current + leakage current).
imum value of R due to the specified rise time
(Figure 9-27).
p
The supply voltage limits the minimum value of resistor
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I C mode (master or slave).
R
due to the specified minimum sink current of 3 mA
p
2
at VOL max = 0.4V for the specified output stages. For
2
FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I C BUS
VDD + 10%
DEVICE
Rp
Rp
Rs
Rs
SDA
SCL
Cb=10 - 400 pF
Note:
I2C devices with input levels related to VDD must have one common supply
line to which the pull-up resistor is also connected.
1999 Microchip Technology Inc.
DS30292B-page 93
PIC16F87X
NOTES:
DS30292B-page 94
1999 Microchip Technology Inc.
PIC16F87X
The USART can be configured in the following modes:
10.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI). The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, serial EEPROMs etc.
The USART module also has a multi-processor com-
munication capability using 9-bit address detection.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
bit7
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
bit0
TRMT
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3:
bit 2:
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1= High speed
0= Low speed
Synchronous mode
Unused in this mode
bit 1:
bit 0:
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
1999 Microchip Technology Inc.
DS30292B-page 95
PIC16F87X
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
bit7
R/W-0
RX9
R/W-0
SREN
R/W-0
R/W-0
R-0
R-0
R-x
RX9D
bit0
CREN ADDEN
FERR
OERR
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
SPEN: Serial Port Enable bit
1= Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3:
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1= Enables address detection, enable interrupt and load of the receive burffer when RSR<8> is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2:
bit 1:
bit 0:
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data (Can be parity bit)
DS30292B-page 96
1999 Microchip Technology Inc.
PIC16F87X
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
10.1
USART Baud Rate Generator (BRG)
The BRG supports both the asynchronous and syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
POR,
BOR
other
resets
0000 -010 0000 -010
0000 000x 0000 000x
0000 0000 0000 0000
98h
18h
99h
TXSTA
CSRC TX9 TXEN SYNC
—
BRGH TRMT TX9D
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
SPBRG Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.
1999 Microchip Technology Inc.
DS30292B-page 97
PIC16F87X
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
SPBRG
SPBRG
%
%
%
value
value
value
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
255
129
31
15
9
-
-
-
207
103
25
12
8
-
-
-
129
64
15
7
1.221
2.404
9.766
19.531
31.250
34.722
62.500
1.221
1.75
0.17
1.73
1.72
8.51
3.34
8.51
-
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.202
0.17
0.17
1.73
1.72
8.51
6.99
9.58
-
2.4
2.404
2.404
9.6
9.615
9.766
19.2
28.8
33.6
57.6
HIGH
19.231
27.778
35.714
62.500
0.977
19.531
31.250
31.250
52.083
0.610
4
8
6
4
4
3
2
255
0
255
0
255
0
LOW 312.500
-
250.000
-
156.250
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
%
%
ERROR
ERROR
KBAUD
(decimal) KBAUD
(decimal)
0.3
1.2
0.300
1.202
2.404
8.929
20.833
31.250
-
0
207
51
25
6
0.301
1.216
2.432
9.322
18.643
-
0.33
1.33
1.33
2.90
2.90
-
185
46
22
5
0.17
0.17
6.99
8.51
8.51
-
2.4
9.6
19.2
28.8
33.6
57.6
HIGH
LOW
2
2
1
-
-
-
-
-
62.500
0.244
62.500
8.51
-
0
55.930
0.218
55.930
2.90
-
0
255
0
255
0
-
-
-
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
KBAUD
ERROR
KBAUD
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.4
-
-
-
-
-
-
2.441
9.615
19.531
28.409
32.895
56.818
2.441
625.000
1.71
0.16
1.72
1.36
2.10
1.36
-
255
64
31
21
18
10
255
0
9.6
9.615
19.231
29.070
33.784
59.524
4.883
0.16
0.16
0.94
0.55
3.34
-
129
64
42
36
20
255
0
9.615
19.231
29.412
33.333
58.824
3.906
1000.000
0.16
0.16
2.13
0.79
2.13
-
103
51
33
29
16
255
0
19.2
28.8
33.6
57.6
HIGH
LOW 1250.000
-
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
%
%
ERROR
ERROR
KBAUD
(decimal) KBAUD
(decimal)
0.3
1.2
-
-
-
207
103
25
12
8
-
-
-
185
92
22
11
7
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.203
0.25
0.25
1.32
2.90
2.90
4.88
2.90
-
2.4
2.404
2.406
9.6
9.615
9.727
19.2
28.8
33.6
57.6
HIGH
LOW
19.231
27.798
35.714
62.500
0.977
18.643
27.965
31.960
55.930
0.874
6
6
3
3
255
0
255
0
250.000
-
273.722
-
DS30292B-page 98
1999 Microchip Technology Inc.
PIC16F87X
( PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit, which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty.
10.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one start bit, eight or nine data bits,
and one stop bit). The most common data format is 8
bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
SPBRG
TRMT
SPEN
TX9
TX9D
Baud Rate Generator
1999 Microchip Technology Inc.
DS30292B-page 99
PIC16F87X
Steps to follow when setting up an Asynchronous
Transmission:
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 10.1)
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. Load data to the TXREG register (starts trans-
mission).
3. If interrupts are desired, then set enable bit
TXIE.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
Word 1
Bit 7/8
Stop Bit
TXIF bit
(Transmit buffer
reg. empty flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
Start Bit
Start Bit
Word 2
Bit 0
Bit 1
Word 1
Bit 7/8
Bit 0
Stop Bit
TRMT bit
(Transmit shift
reg. empty flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
RCSTA
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
DS30292B-page 100
1999 Microchip Technology Inc.
PIC16F87X
10.2.2 USART ASYNCHRONOUS RECEIVER
for two bytes of data to be received and transferred to
the RCREG FIFO and a third byte to begin shifting to
the RSR register. On the detection of the STOP bit of
the third byte, if the RCREG register is still full, the over-
run error bit OERR (RCSTA<1>) will be set. The word
in the RSR will be lost. The RCREG register can be
read twice to retrieve the two bytes in the FIFO. Over-
run bit OERR has to be cleared in software. This is
done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, so it
is essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
ered register (i.e. it is a two deep FIFO). It is possible
FIGURE 10-4: USART RECEVE BLOCK DIAGRAM
x64 Baud Rate CLK
CREN
FERR
OERR
SPBRG
÷64
RSR register
MSb
LSb
or
÷16
0
Baud Rate Generator
7
1
Stop (8)
Start
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
FIGURE 10-5: ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1999 Microchip Technology Inc.
DS30292B-page 101
PIC16F87X
Steps to follow when setting up an Asynchronous
Reception:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 10.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
DS30292B-page 102
1999 Microchip Technology Inc.
PIC16F87X
10.2.3 SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
• Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if enable
bit RCIE was set.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enabled:
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired, set
bit BRGH.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
RSR register
MSb
LSb
or
÷ 16
0
Baud Rate Generator
7
1
Stop (8)
Start
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
Enable
Load of
ADDEN
Receive
Buffer
RX9
ADDEN
RSR<8>
8
RX9D
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
1999 Microchip Technology Inc.
DS30292B-page 103
PIC16F87X
FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Load RSR
Read
WORD 1
RCREG
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN = 1.
FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Load RSR
Read
WORD 1
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN was not updated and still = 0.
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
DS30292B-page 104
1999 Microchip Technology Inc.
PIC16F87X
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-imped-
ance receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
10.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manne (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
10.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 10-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-10). This is advantageous when slow
baud rates are selected, since the BRG is kept in reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If either bit CREN or bit SREN is set during a
transmission, the transmission is aborted and the DT
1999 Microchip Technology Inc.
DS30292B-page 105
PIC16F87X
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
FIGURE 10-9: SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1 Q2Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
WORD 2
bit 7
WORD 1
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
T
TRMT bit
’1’
’1’
TXEN bit
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS30292B-page 106
1999 Microchip Technology Inc.
PIC16F87X
10.3.2 USART SYNCHRONOUS MASTER
RECEPTION
OERR if it is set. The ninth receive bit is buffered the
same way as the receive data. Reading the RCREG
register will load bit RX9D with a new value, therefore it
is essential for the user to read the RCSTA register
before reading RCREG in order not to lose the old
RX9D information.
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
CREN takes precedence. After clocking the last bit, the
received data in the Receive Shift Register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardware. In this case, it is reset when the RCREG reg-
ister has been read and is empty. The RCREG is a dou-
ble buffered register (i.e., it is a two deep FIFO). It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin
shifting into the RSR register. On the clocking of the last
bit of the third byte, if the RCREG register is still full,
then overrun error bit OERR (RCSTA<1>) is set. The
word in the RSR will be lost. The RCREG register can
be read twice to retrieve the two bytes in the FIFO. Bit
OERR has to be cleared in software (by clearing bit
CREN). If bit OERR is set, transfers from the RSR to
the RCREG are inhibited, so it is essential to clear bit
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 10.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR,
BOR
Value on all
other Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
RCSTA
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
1999 Microchip Technology Inc.
DS30292B-page 107
PIC16F87X
10.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
10.4
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
The operation of the synchronous master and slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
10.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
Steps to follow when setting up a Synchronous Slave
Transmission:
8. If any error occurred, clear the error by clearing
bit CREN.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
DS30292B-page 108
1999 Microchip Technology Inc.
PIC16F87X
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCRE
G
USART Receive Register
0000 0000 0000 0000
(1)
8Ch
98h
99h
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
1999 Microchip Technology Inc.
DS30292B-page 109
PIC16F87X
NOTES:
DS30292B-page 110
1999 Microchip Technology Inc.
PIC16F87X
The A/D module has four registers. These registers
are:
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has five
inputs for the 28-pin devices and eight for the other
devices.
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the
input into the converter. The converter then generates
a digital result of this analog level via successive
approximation. The A/D conversion of the analog input
signal results in a corresponding 10-bit digital number.
The A/D module has high and low voltage reference
input that is software selectable to some combination
of VDD, VSS, RA2 or RA3.
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage refer-
ence) or as digital I/O.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
The A/D converter has a unique feature of being able to
operate while the device is in SLEEP mode. To operate
in sleep, the A/D clock must be derived from the A/D’s
internal RC oscillator.
REGISTER 11-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
R/W-0
ADON
bit0
ADCS1 ADCS0
GO/DONE
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from an RC oscillation)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
101= channel 5, (RE0/AN5)
110= channel 6, (RE1/AN6)
111= channel 7, (RE2/AN7)
(1)
(1)
(1)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shutoff and consumes no operating current
Note 1: These channels are not available on the 28-pin devices.
1999 Microchip Technology Inc.
DS30292B-page 111
PIC16F87X
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
ADFM
bit7
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG0
bit0
—
—
—
PCFG3
PCFG2
PCFG1
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
ADFM: A/D Result format select
1= Right Justified. 6 most significant bits of ADRESH are read as ‘0’.
0= Left Justified. 6 least significant bits of ADRESL are read as ‘0’.
bit 6-4: Unimplemented: Read as ’0’
bit 3-0: PCFG3:PCFG0: A/D Port Configuration Control bits
(1)
(1)
(1)
PCFG3: AN7
PCFG0
AN6
AN5
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
CHAN /
Refs
VREF+
VREF-
(2)
RE2
RE1
RE0
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
RA3
RA3
RA3
VDD
RA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RA2
VSS
VSS
RA2
RA2
RA2
VSS
RA2
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
VREF+
A
A
VREF+
A
A
D
VREF+
D
D
D
VREF+
A
VREF-
A
VREF+
VREF+
VREF+
VREF+
D
A
VREF-
VREF-
VREF-
D
VREF+
VREF-
A = Analog input
D = Digital I/O
Note 1: These channels are not available on the 28-pin devices.
2: This column indicates the number of analog channels available as A/D inputs and the numer of analog channels
used as voltage reference inputs.
DS30292B-page 112
1999 Microchip Technology Inc.
PIC16F87X
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed, the A/D conversion can
be started. The following steps should be followed for
doing an A/D conversion:
1. Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
1999 Microchip Technology Inc.
DS30292B-page 113
PIC16F87X
FIGURE 11-1: A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
100
011
010
001
000
(1)
(1)
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4
(1)
VAIN
(Input voltage)
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
A/D
Converter
VDD
RA0/AN0
VREF+
(Reference
voltage)
PCFG3:PCFG0
VREF-
(Reference
voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on 28-pin devices.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 11-2. The maximum recommended
impedance for analog sources is 10 kΩ. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
DS30292B-page 114
1999 Microchip Technology Inc.
PIC16F87X
EQUATION 11-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2µS + TC + [(Temperature -25°C)(0.05µS/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
16.47µS
2µS + 16.47µS + [(50°C -25×C)(0.05µS/×C)
19.72µS
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leak-
age specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-2: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
CPIN
5 pF
= DAC capacitance
= 120 pF
VA
I LEAKAGE
VT = 0.6V
± 500 nA
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I LEAKAGE = leakage current at the pin due to
VDD 4V
3V
various junctions
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 1011
Sampling Switch
( kΩ )
1999 Microchip Technology Inc.
DS30292B-page 115
PIC16F87X
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
11.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
Table 11-1shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
• 2TOSC
• 8TOSC
• 32TOSC
• Internal RC oscillator
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
ADCS1:ADCS0
Maximum Device Frequency
Max.
Operation
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
Note 1
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for sleep
operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
11.3
Configuring Analog Port Pins
The ADCON1, and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
DS30292B-page 116
1999 Microchip Technology Inc.
PIC16F87X
required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
11.4
A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
In Figure 11-3, after the GO bit is set, the first time seg-
mant has a minimum of TCY and a maximum of TAD.
A/D
conversion
sample.
That
is,
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is aborted, a 2TAD wait is
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 11-3: A/D CONVERSION TAD CYCLES
TCY to TAD
TAD1
TAD3
b8
TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b6 b5 b4 b3 b2 b1 b0
TAD2
b9
TAD4
b7
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
1999 Microchip Technology Inc.
DS30292B-page 117
PIC16F87X
11.4.1 A/D RESULT REGISTERS
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits
wide. The A/D module gives the flexibility to left or right
justify the 10-bit result in the 16-bit result register. The
A/D Format Select bit (ADFM) controls this justifica-
tion. Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ’0’s’. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEPinstruction immediately follows the
instruction that sets the GO/DONE bit.
11.5
A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
11.6
Effects of a Reset
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
FIGURE 11-4: A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
ADFM = 1
0
7
7
2 1 0 7
0 7 6 5
0
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
10-bit Result
Left Justified
Right Justified
DS30292B-page 118
1999 Microchip Technology Inc.
PIC16F87X
TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D
POR,
BOR
MCLR,
WDT
Addr
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh
0Ch
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0000 000x
0000 0000
0000 000u
0000 0000
PSPIF(1)
PSPIE(1)
CCP1IF
CCP1IE
TMR2IF
TMR1IF
8Ch
1Eh
9Eh
1Fh
9Fh
85h
05h
PIE1
TMR2IE TMR1IE
0000 0000
xxxx xxxx
xxxx xxxx
0000 00-0
--0- 0000
--11 1111
--0x 0000
0000 -111
0000 0000
uuuu uuuu
uuuu uuuu
0000 00-0
--0- 0000
--11 1111
--0u 0000
0000 -111
ADRESH
ADRESL
ADCON0
ADCON1
TRISA
A/D Result Register High Byte
A/D Result Register Low Byte
ADCS1
ADFM
—
ADCS0
—
CHS2
CHS1
CHS0
GO/DONE
—
ADON
—
—
PCFG3
PCFG2
PCFG1
PCFG0
—
PORTA Data Direction Register
PORTA Data Latch when written: PORTA pins when read
PORTA
TRISE
—
—
89h(1)
IBF
OBF
IBOV
—
PSPMODE
—
—
—
PORTE Data Direction Bits
RE2 RE1
09h(1)
PORTE
—
—
RE0
---- -xxx
---- -uuu
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers/bits are not available on the 28-pin devices.
1999 Microchip Technology Inc.
DS30292B-page 119
PIC16F87X
NOTES:
DS30292B-page 120
1999 Microchip Technology Inc.
PIC16F87X
12.1
Configuration Bits
12.0 SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes and offer code protection. These are:
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-Circuit Serial Programming
• Low Voltage In-Circuit Serial Programming
• In-Circuit Debugger
These devices have a watchdog timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. It is
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional information on special features is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
1999 Microchip Technology Inc.
DS30292B-page 121
PIC16F87X
REGISTER 12-1: CONFIGURATION WORD
CP1 CP0 DEBUG
bit13
—
WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0
bit0
Register: CONFIG
Address 2007h
bit 13-12:
(2)
bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits
11= Code protection off
10= 1F00h to 1FFFh code protected (PIC16F877, 876)
10= 0F00h to 0FFFh code protected (PIC16F874, 873)
01= 1000h to 1FFFh code protected (PIC16F877, 876)
01= 0800h to 0FFFh code protected (PIC16F874, 873)
00= 0000h to 1FFFh code protected (PIC16F877, 876)
00= 0000h to 0FFFh code protected (PIC16F874, 873)
bit 11:
DEBUG: In-Circuit Debugger Mode
1= In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins.
0= In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10:
bit 9:
Unimplemented: Read as ‘1’
WRT: Flash Program Memory Write Enable
1= Unprotected program memory may be written to by EECON control
0= Unprotected program memory may not be written to by EECON control
bit 8:
bit 7:
bit 6:
bit 3:
bit 2:
CPD: Data EE Memory Code Protection
1= Code protection off
0= Data EEPROM memory code protected
LVP: Low Voltage In-Circuit Serial Programming Enable bit
1= RB3/PGM pin has PGM function, low voltage programming enabled
0= RB3 is digital I/O, HV on MCLR must be used for programming
(1)
BODEN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
(1)
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the
Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS30292B-page 122
1999 Microchip Technology Inc.
PIC16F87X
12.2
Oscillator Configurations
TABLE 12-1: CERAMIC RESONATORS
Ranges Tested:
12.2.1
OSCILLATOR TYPES
Mode
Freq
OSC1
OSC2
The PIC16F87X can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• RC
Low Power Crystal
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Crystal/Resonator
These values are for design guidance only. See
notes at bottom of page.
High Speed Crystal/Resonator
Resistor/Capacitor
Resonators Used:
12.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
455 kHz Panasonic EFO-A455K04B
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16F87X oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 12-2).
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
FIGURE 12-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
(1)
C1
OSC1
To
internal
logic
XTAL
(3)
RF
OSC2
SLEEP
PIC16F87X
(2)
RS
(1)
C2
Note 1: See Table 12-1 and Table 12-2 for rec-
ommended values of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
3: RF varies with the crystal chosen.
FIGURE 12-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC16F87X
Open
1999 Microchip Technology Inc.
DS30292B-page 123
PIC16F87X
12.2.3 RC OSCILLATOR
TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 12-3 shows how the R/C combina-
tion is connected to the PIC16F87X.
Cap.
Range
C2
Crystal
Freq
Cap. Range
C1
Osc Type
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
HS
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
20 MHz
FIGURE 12-3: RC OSCILLATOR MODE
These values are for design guidance only.
See notes at bottom of page.
VDD
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
Rext
Internal
OSC1
200 kHz STD XTL 200.000KHz
± 20 PPM
± 50 PPM
± 50 PPM
± 30 PPM
Clock
1 MHz
4 MHz
8 MHz
20 MHz
ECS ECS-10-13-1
Cext
VSS
PIC16F87X
ECS ECS-40-20-1
EPSON CA-301 8.000M-C
OSC2/CLKOUT
FOSC/4
Recommended values:
EPSON CA-301 20.000M-C ± 30 PPM
3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.
DS30292B-page 124
1999 Microchip Technology Inc.
PIC16F87X
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in
Table 12-4. These bits are used in software to deter-
mine the nature of the reset. See Table 12-6 for a full
description of reset states of all registers.
12.3
Reset
The PIC16F87X differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
A simplified block diagram of the on-chip reset circuit is
shown in Figure 12-4.
These devices have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BODEN
OST/PWRT
OST
Chip_Reset
Q
10-bit Ripple counter
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1999 Microchip Technology Inc.
DS30292B-page 125
PIC16F87X
12.4
Power-On Reset (POR)
12.8
Time-out Sequence
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16CXX device operating in
parallel.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the start-up con-
ditions. For additional information, refer to Application
Note, AN007, “Power-up Trouble Shooting”,
(DS00007).
Table 12-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 12-6 shows the
reset conditions for all the registers.
12.9
Power Control/Status Register
(PCON)
12.5
Power-up Timer (PWRT)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "don’t care" bit and is not necessarily predictable if
the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
12.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
12.7
Brown-Out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situa-
tion will reset the device. If VDD falls below VBOR for
less than TBOR, a reset may not occur.
Once the brown-out occurs, the device will remain in
brown-out reset until VDD rises above VBOR. The
power-up timer then keeps the device in reset for
TPWRT (parameter #33, about 72mS). If VDD should
fall below VBOR during TPWRT, the brown-out reset
process will restart when VDD rises above VBOR with
the power-up timer reset. The power-up timer is
always enabled when the brown-out reset circuit is
enabled regardless of the state of the PWRT configu-
ration bit.
DS30292B-page 126
1999 Microchip Technology Inc.
PIC16F87X
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
PWRTE = 0
Brown-out
Wake-up from
SLEEP
PWRTE = 1
1024TOSC
—
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
72 ms + 1024TOSC
1024TOSC
72 ms
—
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
1999 Microchip Technology Inc.
DS30292B-page 127
PIC16F87X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
uuuu uuuu(1)
ruuu uuuu(1)
uuuu uuuu(1)
-r-u u--u(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
ruuu uuuu
uuuu uuuu
-r-u u--u
PCL
STATUS
FSR
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
r000 0000
0000 0000
-r-0 0--0
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
-r-0 0--0
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
r000 0000
0000 0000
-r-0 0--0
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 000x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
-r-0 0--0
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for reset value for specific condition.
DS30292B-page 128
1999 Microchip Technology Inc.
PIC16F87X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
PCON
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
---- --qq
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
xxxx xxxx
0--- 0000
0--- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
---- ----
---- --uu
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
uuuu uuuu
0--- 0000
0--- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- u000
---- ----
---- --uu
1111 1111
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
u--- uuuu
u--- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- uuuu
---- ----
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADRESL
ADCON1
EEDATA
EEADR
EEDATH
EEADRH
EECON1
EECON2
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for reset value for specific condition.
FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1999 Microchip Technology Inc.
DS30292B-page 129
PIC16F87X
FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-8: SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
VDD
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30292B-page 130
1999 Microchip Technology Inc.
PIC16F87X
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
12.10 Interrupts
The PIC16F87X family has up to 14 sources of inter-
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi-
vidual and global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-9: INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
RCIF
RCIE
INTF
INTE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF
PIC16F876/873 Yes Yes Yes
PIC16F877/874 Yes Yes Yes
-
Yes
Yes
Yes Yes
Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1999 Microchip Technology Inc.
DS30292B-page 131
PIC16F87X
12.10.1 INT INTERRUPT
12.11 Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 12.13 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
For the PIC16F873/874 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 0x20 in bank 0, it must
also be defined at 0xA0 in bank 1.). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F876/877 devices, temporary holding regis-
ters W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same basic code in
Example 12-1 can be used.
12.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 5.0)
12.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
:(ISR)
:
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS30292B-page 132
1999 Microchip Technology Inc.
PIC16F87X
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
12.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEPinstruction.
Note: The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 12.1).
FIGURE 12-10: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
FIGURE 12-11: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
2007h
Config. bits
(1)
BODEN
CP1
CP0
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
81h,181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
1999 Microchip Technology Inc.
DS30292B-page 133
PIC16F87X
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
12.13.2 WAKE-UP USING INTERRUPTS
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1 WAKE-UP FROM SLEEP
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake up from sleep. The SLEEPinstruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
3. Interrupt from INT pin, RB port change or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP capture mode interrupt.
4. Special event trigger (Timer1 in asynchronous
mode using an external clock).
5. SSP (Start/Stop) bit detect interrupt.
6. SSP transmit or receive in slave mode (SPI/I2C).
7. USART RX or TX (synchronous slave mode).
8. A/D conversion (when A/D clock source is RC).
9. EEPROM write operation completion
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
DS30292B-page 134
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 12-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
CLKOUT(4)
INT pin
INTF flag
Interrupt Latency
(Note 2)
(INTCON<1>)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
12.14 In-Circuit Debugger
12.16 ID Locations
When the DEBUG bit in the configuration word is pro-
grammed to a ’0’, the In-Circuit Debugger functionality
is enabled. This function allows simple debugging func-
tions when used with MPLAB. When the microcontrol-
ler has this feature enabled, some of the resources are
not available for general use. Table 12-7 shows which
features are consumed by the background debugger.
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
TABLE 12-7: DEBUGGER RESOURCES
I/O pins
RB6, RB7
Stack
1 level
Program Memory
Address 0000h must be NOP
Last 100h words
Data Memory
0x070(0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
12.15 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
1999 Microchip Technology Inc.
DS30292B-page 135
PIC16F87X
12.17 In-Circuit Serial Programming
12.18 Low Voltage ICSP Programming
PIC16F87X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
The LVP bit of the configuration word enables low volt-
age ICSP programming. This mode allows the micro-
controller to be programmed via ICSP using a VDD
source in the operating voltage range. This only means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the program-
ming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter programming mode, VDD must be applied
to the RB3/PGM provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factory.
When using ICSP, the part must be supplied 4.5V to
5.5V if a bulk erase will be executed. This includes
reprogramming of the code protect both from an on-
state to off-state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This means calibration values, unique user IDs or user
code can be reprogrammed or added.
Note 1: The high voltage programming mode is
always available, regardless of the state of
the LVP bit, by applying VIHH to the MCLR
pin.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277B).
2: While in low voltage ICSP mode, the RB3
pin can no longer be used as a general
purpose I/O pin.
3: When using low voltage ICSP program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
If low-voltage programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to 0, only the high voltage programming mode is avail-
able and only high voltage programming mode can be
used to program the device.
When using low voltage ICSP, the part must be sup-
plied 4.5V to 5.5V if a bulk erase will be executed. This
includes reprogramming of the code protect bits from
an on-state to off-state. For all other cases of low volt-
age ICSP, the part may be programmed at the normal
operating voltage. This means calibration values,
unique user IDs or user code can be reprogrammed or
added.
DS30292B-page 136
1999 Microchip Technology Inc.
PIC16F87X
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
13.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 13-1
shows the opcode field descriptions.
Table 13-2 lists the instructions recognized by the
MPASM assembler.
Figure 13-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
All examples use the following format to represent a
hexadecimal number:
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
0xhh
where h signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Byte-oriented file register operations
13
8
7
6
0
0
OPCODE
d
f (FILE #)
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
Bit-oriented file register operations
13 10 9
b (BIT #)
Field
Description
7
6
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Bit address within an 8-bit file register
Literal field, constant data or label
Literal and control operations
General
Don't care location (= 0or 1)
The assembler will generate code with x = 0. It
is the recommended form of use for compati-
bility with all Microchip software tools.
13
8
7
0
0
OPCODE
k (literal)
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
k = 8-bit immediate value
PC
TO
PD
Program Counter
Time-out bit
CALL and GOTO instructions only
13 11 10
OPCODE
k = 11-bit immediate value
k (literal)
Power-down bit
The instruction set is highly orthogonal and is grouped
into three basic categories:
A description of each instruction is available in the
• Byte-oriented operations
• Bit-oriented operations
PICmicro™
(DS33023).
Mid-Range
Reference
Manual,
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
1999 Microchip Technology Inc.
DS30292B-page 137
PIC16F87X
TABLE 13-2: PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles 14-Bit Opcode
MSb
Status
Affected
Notes
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
0010 dfff ffff
1110 dfff ffff
0110 dfff ffff
C,DC,Z
1,2
1,2
2
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
Z
Z
Z
Move W to f
No Operation
-
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
C,DC,Z
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
DS30292B-page 138
1999 Microchip Technology Inc.
PIC16F87X
13.1
Instruction Descriptions
Add Literal and W
ADDLW
ANDWF
Syntax:
AND W with f
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
[label] ANDWF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d
[0,1]
(W) + k → (W)
Operation:
(W) .AND. (f) → (destination)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
The contents of the W register
are added to the eight bit literal ’k’
and the result is placed in the W
register.
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
BCF
Bit Clear f
ADDWF
Syntax:
Add W and f
Syntax:
Operands:
[label] BCF f,b
[label] ADDWF f,d
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d
[0,1]
Operation:
0 → (f<b>)
Operation:
(W) + (f) → (destination)
Status Affected: None
Status Affected: C, DC, Z
Description:
Bit 'b' in register 'f' is cleared.
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
BSF
Bit Set f
Syntax:
Operands:
[label] BSF f,b
ANDLW
AND Literal with W
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Syntax:
[label] ANDLW
k
Operands:
Operation:
Status Affected:
Description:
0 ≤ k ≤ 255
Operation:
1 → (f<b>)
(W) .AND. (k) → (W)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
Z
The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
1999 Microchip Technology Inc.
DS30292B-page 139
PIC16F87X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
The contents of register ’f’ are
cleared and the Z bit is set.
instruction is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOPis exe-
cuted instead making this a 2TCY
instruction.
CLRW
Clear W
Syntax:
[ label ] CLRW
None
BTFSC
Bit Test, Skip if Clear
Operands:
Operation:
Syntax:
[label] BTFSC f,b
00h → (W)
1 → Z
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Status Affected:
Description:
Z
Operation:
skip if (f<b>) = 0
W register is cleared. Zero bit (Z)
is set.
Status Affected: None
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
Operands:
Operation:
Syntax:
00h → WDT
0 → WDT prescaler,
1 → TO
Operands:
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
1 → PD
(PCLATH<4:3>) → PC<12:11>
Status Affected: TO, PD
Status Affected: None
Description: CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two cycle instruction.
DS30292B-page 140
1999 Microchip Technology Inc.
PIC16F87X
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
GOTO
Unconditional Branch
Syntax:
Operands:
Syntax:
[ label ] GOTO k
Operands:
Operation:
0 ≤ k ≤ 2047
d
[0,1]
k → PC<10:0>
Operation:
(f) → (destination)
PCLATH<4:3> → PC<12:11>
Status Affected:
Description:
Z
Status Affected: None
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
GOTOis an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two
cycle instruction.
DECF
Decrement f
[label] DECF f,d
0 ≤ f ≤ 127
INCF
Increment f
Syntax:
Operands:
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operands:
Operation:
(f) - 1 → (destination);
skip if result = 0
d
[0,1]
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
Status Affected: None
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead
making it a 2TCY instruction.
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0, a
NOPis executed instead making it
a 2TCY instruction.
1999 Microchip Technology Inc.
DS30292B-page 141
PIC16F87X
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .OR. k → (W)
Z
k → (W)
Status Affected: None
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
Description:
The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF
Syntax:
Move W to f
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 127
[ label ] MOVWF
0 ≤ f ≤ 127
f
Syntax:
Operands:
Operation:
Operands:
(W) → (f)
d
[0,1]
Status Affected: None
Operation:
(W) .OR. (f) → (destination)
Description:
Move data from W register to reg-
ister 'f'.
Status Affected:
Description:
Z
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
NOP
No Operation
[ label ] NOP
None
Syntax:
MOVF
Move f
Operands:
Operation:
Syntax:
Operands:
[ label ] MOVF f,d
No operation
0 ≤ f ≤ 127
Status Affected: None
Description: No operation.
d
[0,1]
Operation:
(f) → (destination)
Status Affected:
Description:
Z
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
DS30292B-page 142
1999 Microchip Technology Inc.
PIC16F87X
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RLF
Rotate Left f through Carry
[ label ] RLF f,d
0 ≤ f ≤ 127
Syntax:
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
TOS → PC,
1 → GIE
Operation:
See description below
C
Status Affected: None
Status Affected:
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
C
Register f
RETLW
Return with Literal in W
Syntax:
[ label ] RETLW k
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Operands:
Operation:
0 ≤ k ≤ 255
Syntax:
Operands:
k → (W);
TOS → PC
d
[0,1]
Status Affected: None
Operation:
See description below
C
Description:
The W register is loaded with the
Status Affected:
Description:
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
C
Register f
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN
None
SLEEP
Operands:
Operation:
Syntax:
[ label
]
TOS → PC
SLEEP
Status Affected: None
Operands:
Operation:
None
Description: Return from subroutine. The stack
00h → WDT,
0 → WDT prescaler,
1 → TO,
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
0 → PD
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
1999 Microchip Technology Inc.
DS30292B-page 143
PIC16F87X
SUBLW
Subtract W from Literal
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[label]
SUBLW k
XORLW k
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
k - (W) → (W)
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
The W register is subtracted (2’s
The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
complement method) from the
eight bit literal 'k'. The result is
placed in the W register.
XORWF
Syntax:
Exclusive OR W with f
[label] XORWF f,d
0 ≤ f ≤ 127
SUBWF
Subtract W from f
Syntax:
[ label ]
SUBWF f,d
Operands:
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .XOR. (f) → (destination)
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Z
Status Affected: C, DC, Z
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is placed in
register 'f'.
DS30292B-page 144
1999 Microchip Technology Inc.
PIC16F87X
MPLAB allows you to:
14.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
14.2
MPASM Assembler
Emulator
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
MPASM features include:
- PICDEM-17
- SEEVAL
• MPASM and MPLINK are integrated into MPLAB
projects.
- KEELOQ
• MPASM allows user defined macros to be created
for streamlined assembly.
14.1
MPLAB Integrated Development
Environment Software
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directives allow complete control over the
assembly process.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows -based applica-
tion which contains:
14.3
MPLAB-C17 and MPLAB-C18
C Compilers
• Multiple functionality
- editor
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• On-line help
1999 Microchip Technology Inc.
DS30292B-page 145
PIC16F87X
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
14.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
14.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
14.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
14.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
14.9
MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
14.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30292B-page 146
1999 Microchip Technology Inc.
PIC16F87X
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
14.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
14.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
14.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
14.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
14.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
14.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
1999 Microchip Technology Inc.
DS30292B-page 147
PIC16F87X
14.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
14.17 SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
14.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS30292B-page 148
1999 Microchip Technology Inc.
PIC16F87X
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
5 1 2 0 P M C
X X X C R M F
X X
H C S X
X X C 9 3
C 5 X 2 X /
C 4 X 2 X /
X X C 8 2 C 1 P I
X X 7 C 7 C 1 P I
X 4 C 7 C 1 P I
X X 9 C 6 C 1 P I
X 8 X 1 6 C I F P
X 8 C 6 C 1 P I
X X 7 C 6 C 1 P I
X 7 C 6 C 1 P I
X 6 2 6 1 F C I P
X X C 6 X C 1 P I
X 6 C 6 C 1 P I
X 5 C 6 C 1 P I
0 0 4 1 0 C I P
X X C 2 X C 1 P I
s l o o e T a r f t o w S s o r a t u l E m e r g g b e u D s r e m a m r g o P r
t i s K v a l E d a n d s a r o B o m e D
1999 Microchip Technology Inc.
DS30292B-page 149
PIC16F87X
NOTES:
DS30292B-page 150
1999 Microchip Technology Inc.
PIC16F87X
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than pulling
this pin directly to VSS.
3: PORTD and PORTE are not implemented on the 28-pin devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1999 Microchip Technology Inc.
DS30292B-page 151
PIC16F87X
FIGURE 15-1: PIC16FXXX-20 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz
20 MHz
Frequency
FIGURE 15-2: PIC16LFXXX-04 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
10 MHz
Frequency
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS30292B-page 152
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 15-3: PIC16FXXX-04 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
PIC16CXXX-04
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
Frequency
1999 Microchip Technology Inc.
DS30292B-page 153
PIC16F87X
15.1
DC Characteristics:
PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
D001 Supply Voltage
D001A
VDD
4.0
4.5
VBOR*
-
-
-
5.5
5.5
5.5
V
V
V
XT, RC and LP osc configuration
HS osc configuration
BOR enabled, Fmax = 14MHz (Note 7)
D002* RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage VBOR
3.7
-
4.0 4.35
V
BODEN bit in configuration word enabled
D010
D013
Supply Current (Note 2,5) IDD
1.6
4
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
-
7
15
mA HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D015* Brown-out Reset Current ∆IBOR
85 200 µA BOR enabled VDD = 5.0V
(Note 6)
D020 Power-down Current
D021 (Note 3,5)
D021A
IPD
-
-
-
10.5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C
1.5
1.5
16
19
µA VDD = 4.0V, WDT disabled, -0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current ∆IBOR
-
85 200 µA BOR enabled VDD = 5.0V
(Note 6)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30292B-page 154
1999 Microchip Technology Inc.
PIC16F87X
15.2
DC Characteristics: PIC16LF873/874/876/877-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C
≤ TA ≤ +70°C for commercial
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
Supply Voltage
VDD
VDR
2.0
-
-
5.5
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
See section on Power-on Reset for details
D002* RAM Data Retention
Voltage (Note 1)
1.5
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
-
-
V
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05
V/ms See section on Power-on Reset for details
D005
D010
Brown-out Reset Voltage VBOR
3.7
4.0 4.35
V
BODEN bit in configuration word enabled
Supply Current (Note 2,5) IDD
-
0.6
2.0
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
-
-
20
85
35
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D015* Brown-out Reset Current ∆IBOR
200
µA BOR enabled VDD = 5.0V
(Note 6)
D020
D021
D021A
Power-down Current
(Note 3,5)
IPD
-
-
-
7.5
0.9
0.9
30
5
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current ∆IBOR
-
85
200
µA BOR enabled VDD = 5.0V
(Note 6)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1999 Microchip Technology Inc.
DS30292B-page 155
PIC16F87X
15.3
DC Characteristics:
PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
PIC16LF873/874/876/877-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 15.1 and
Section 15.2.
Param
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
D030A
D031
D032
D033
with TTL buffer
VSS
VSS
VSS
VSS
VSS
-
-
-
-
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
Ports RC3 and RC4
with Schmitt Trigger buffer
with SMBus
Note1
D034
D034A
VSS
-0.5
-
-
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
Input High Voltage
I/O ports
VIH
-
-
-
D040
D040A
with TTL buffer
2.0
0.25VDD
+ 0.8V
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
D041
D042
with Schmitt Trigger buffer
MCLR
0.8VDD
0.8VDD
0.7VDD
0.9VDD
-
-
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
Note1
D042A OSC1 (XT, HS and LP)
D043
OSC1 (in RC mode)
Ports RC3 and RC4
with Schmitt Trigger buffer
with SMBus
PORTB weak pull-up current
Input Leakage Current
(Notes 2, 3)
D044
D044A
D070
0.7VDD
1.4
50
-
-
VDD
5.5
400
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
IPURB
IIL
250
µA VDD = 5V, VPIN = VSS
D060
I/O ports
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080
D083
I/O ports
VOL
-
-
-
-
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30292B-page 156
1999 Microchip Technology Inc.
PIC16F87X
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 15.1 and
Section 15.2.
Param
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
Output High Voltage
D090
D092
I/O ports (Note 3)
VOH VDD - 0.7
VDD - 0.7
-
-
-
-
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
D150* Open-Drain High Voltage
VOD
-
-
-
-
8.5
RA4 pin
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
-
-
15
pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102
All I/O pins and OSC2 (in RC
CIO
CB
-
-
-
-
50
400
pF
pF
mode) SCL, SDA in I2C mode
Data EEPROM Memory
Endurance
D120
D121
ED
100K
-
-
-
E/W 25°C at 5V
V
VDD for read/write
VDRW Vmin
5.5
Using EECON to read/write
Vmin = min operating voltage
D122
Erase/write cycle time
Program FLASH Memory
Endurance
TDEW
-
4
8
ms
D130
D131
EP
VPR
1000
Vmin
Vmin
-
-
-
-
E/W 25°C at 5V
V
V
VDD for read
5.5
5.5
Vmin = min operating voltage
using EECON to read/write,
Vmin = min operating voltage
D132a VDD for erase/write
D133 Erase/Write cycle time
TPEW
-
4
8
ms
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1999 Microchip Technology Inc.
DS30292B-page 157
PIC16F87X
15.4
Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
(I2C specifications only)
(I2C specifications only)
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 15-4: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2, but including PORTD and PORTE outputs as ports
for OSC2 output
Note: PORTD and PORTE are not implemented on the 28-pin devices.
DS30292B-page 158
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 15-5: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
3
4
2
CLKOUT
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic
No.
Min Typ†
Max
Units Conditions
FOSC External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
—
—
—
—
—
—
4
4
MHz XT and RC osc mode
MHz HS osc mode (-04)
MHz HS osc mode (-20)
kHz LP osc mode
(Note 1)
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
4
5
—
—
20
200
MHz HS osc mode
kHz LP osc mode
1
TOSC External CLKIN Period
250
250
50
—
—
—
—
ns XT and RC osc mode
ns HS osc mode (-04)
ns HS osc mode (-20)
µs LP osc mode
(Note 1)
—
—
5
—
—
Oscillator Period
(Note 1)
250
250
250
50
—
—
ns RC osc mode
—
10,000
250
250
—
ns XT osc mode
—
ns HS osc mode (-04)
ns HS osc mode (-20)
µs LP osc mode
—
5
—
2
3
TCY Instruction Cycle Time
200
TCY
DC
ns TCY = 4/FOSC
(Note 1)
TosL, External Clock in (OSC1) High 100
TosH or Low Time
—
—
—
—
—
—
—
—
—
25
50
15
ns XT oscillator
µs LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
2.5
15
—
4
TosR, External Clock in (OSC1) Rise
TosF or Fall Time
—
—
Legend: † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is
"DC" (no clock) for all devices.
1999 Microchip Technology Inc.
DS30292B-page 159
PIC16F87X
FIGURE 15-6: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
200
200
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
—
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
100
—
100
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
TckH2ioI Port in hold after CLKOUT ↑
—
0.5TCY + 20
—
TOSC + 200
—
0
—
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
100
255
Port out valid
18*
TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F)
Extended (LF)
100
200
—
—
—
—
ns
ns
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
10
—
10
—
—
—
—
40
ns
ns
ns
ns
ns
ns
ns
TioR
TioF
Port output rise time
Port output fall time
INT pin high or low time
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
—
145
40
21*
—
—
145
—
22††* Tinp
23††* Trbp
TCY
TCY
RB7:RB4 change INT high or low time
—
Legend:
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30292B-page 160
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-4 for load conditions.
FIGURE 15-8: BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +85°C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms VDD = 5V, -40°C to +85°C
32
Tost
Oscillation Start-up Timer Period
Power up Timer Period
—
28
—
1024 TOSC
—
132
2.1
—
TOSC = OSC1 period
33*
34
Tpwrt
TIOZ
72
—
ms VDD = 5V, -40°C to +85°C
µs
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
100
—
—
µs
VDD ≤ VBOR (D005)
Legend:
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
1999 Microchip Technology Inc.
DS30292B-page 161
PIC16F87X
FIGURE 15-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
0.5TCY + 20
—
—
ns Must also meet
parameter 42
With Prescaler
No Prescaler
With Prescaler
No Prescaler
10
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
ns Must also meet
parameter 42
ns
ns
TCY + 40
With Prescaler Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4, ..., 256)
N
0.5TCY + 20
15
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, Prescaler = 1
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous, Standard(F)
ns
ns
Prescaler =
2,4,8
Extended(LF)
25
Asynchronous Standard(F)
Extended(LF)
30
—
—
—
—
—
—
—
—
—
—
ns
ns
50
T1CKI Low Time
Synchronous, Prescaler = 1
Synchronous, Standard(F)
0.5TCY + 20
ns Must also meet
parameter 47
15
25
ns
ns
Prescaler =
2,4,8
Extended(LF)
Asynchronous Standard(F)
Extended(LF)
30
50
—
—
—
—
—
—
ns
ns
T1CKI input period Synchronous
Standard(F)
Greater of:
30 OR TCY + 40
ns N = prescale value
(1, 2, 4, 8)
N
Extended(LF) Greater of:
50 OR TCY + 40
N = prescale value
(1, 2, 4, 8)
N
Asynchronous Standard(F)
Extended(LF)
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
60
—
—
—
—
—
ns
ns
100
DC
Ft1
200
kHz
48
*
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
—
7Tosc
—
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30292B-page 162
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 15-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
Note: Refer to Figure 15-4 for load conditions.
54
TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param Sym Characteristic
No.
Min
Typ† Max Units Conditions
50*
TccL CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20
—
—
ns
Standard(F)
10
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
Extended(LF)
20
51*
TccH
No Prescaler
0.5TCY + 20
CCP1 and CCP2
input high time
Standard(F)
10
20
With Prescaler
Extended(LF)
52*
53*
TccP
3TCY + 40
ns N = prescale
value (1,4 or 16)
CCP1 and CCP2 input period
N
TccR CCP1 and CCP2 output rise time Standard(F)
Extended(LF)
—
—
—
—
10
25
10
25
25
50
25
45
ns
ns
ns
ns
54*
TccF CCP1 and CCP2 output fall time
Standard(F)
Extended(LF)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
These parameters are for design guidance only and are not tested.
1999 Microchip Technology Inc.
DS30292B-page 163
PIC16F87X
FIGURE 15-11: PARALLEL SLAVE PORT TIMING (40-PIN DEVICES ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-6: PARALLEL SLAVE PORT REQUIREMENTS (40-PIN DEVICES ONLY)
Parameter
No.
Sym
Characteristic
Min Typ† Max Units Conditions
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
25
—
—
—
—
ns
ns
Extended
Range Only
63*
64
TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) Standard(F)
Extended(LF)
20
35
—
—
—
—
ns
ns
TrdL2dtV RD↓ and CS↓ to data–out valid
—
—
—
—
80
90
ns
ns
Extended
Range Only
65
TrdH2dtI RD↑ or CS↓ to data–out invalid
10
—
30
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30292B-page 164
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 15-12: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
BIT6 - - - - - -1
MSb
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-4 for load conditions.
FIGURE 15-13: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 15-4 for load conditions.
1999 Microchip Technology Inc.
DS30292B-page 165
PIC16F87X
FIGURE 15-14: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-4 for load conditions.
FIGURE 15-15: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 15-4 for load conditions.
DS30292B-page 166
1999 Microchip Technology Inc.
PIC16F87X
TABLE 15-7: SPI MODE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max Units Conditions
Param
No.
70*
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
71*
72*
73*
TscH
TscL
SCK input high time (slave mode)
SCK input low time (slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
74*
75*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
TdoR
SDO data output rise time
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
76*
77*
78*
TdoF
SDO data output fall time
—
10
—
25
50
ns
ns
TssH2doZ
TscR
SS↑ to SDO output hi-impedance
10
SCK output rise time (master mode) Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79*
80*
TscF
SCK output fall time (master mode)
—
10
25
ns
ns
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
81*
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
TCY
—
—
ns
82*
83*
TssL2doV
SDO data output valid after SS↓ edge
SS ↑ after SCK edge
—
—
—
50
—
ns
ns
TscH2ssH,
TscL2ssH
1.5TCY + 40
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 15-16: I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-8: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min Typ Max Units
Conditions
90
91
92
93
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated START
condition
ns
ns
ns
ns
THD:STA START condition
Hold time
4000
600
After this period the first clock
pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
1999 Microchip Technology Inc.
DS30292B-page 167
PIC16F87X
FIGURE 15-17: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-9: I2C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
—
—
µs
µs
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
—
101
TLOW
Clock low time
100 kHz mode
4.7
µs
µs
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
TSU:STA START condition
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
setup time
THD:STA START condition hold 100 kHz mode
—
After this period the first clock
pulse is generated
time
400 kHz mode
100 kHz mode
400 kHz mode
—
106
107
92
THD:DAT Data input hold time
—
0
0.9
—
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
TSU:STO STOP condition setup 100 kHz mode
—
time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
109
110
TAA
Output valid from
clock
3500
—
Note 1
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast-mode (400 kHz) I C-bus device can be used in a standard-mode (100 kHz) I C-bus system, but the requirement tsu;
DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line is
released.
DS30292B-page 168
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 15-18: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
Pin
121
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ† Max Units Conditions
Standard(F)
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
Clock high to data out valid
Extended(LF)
121
122
Tckrf
Tdtrf
Clock out rise time and fall time Standard(F)
(Master Mode)
Extended(LF)
50
Data out rise time and fall time Standard(F)
Extended(LF)
45
50
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 15-19: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
TckL2dtl
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
—
—
ns
ns
126
Data hold after CK ↓ (DT hold time)
15
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1999 Microchip Technology Inc.
DS30292B-page 169
PIC16F87X
TABLE 15-12: PIC16F873/874/876/877-04 (COMMERCIAL, INDUSTRIAL)
PIC16F873/874/876/877-20 (COMMERCIAL, INDUSTRIAL)
PIC16LF873/874/876/877-04 (COMMERCIAL, INDUSTRIAL)
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
A01
A03
A04
A06
A07
NR
Resolution
—
—
—
—
—
—
—
—
—
—
10-bits
bit
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EIL
Integral linearity error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
< ± 1
< ± 1
< ± 2
< ± 1
LSb
LSb
LSb
LSb
EDL Differential linearity error
EOFF Offset error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EGN Gain error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
(3)
A10
A20
—
—
guaranteed
—
—
—
V
VSS ≤ VAIN ≤ VREF
Monotonicity
VREF Reference voltage (VREF+ - VREF-)
2.0V
VDD + 0.3
Absolute minimum electrical
spec. To ensure 10-bit
accuracy.
A21 VREF+ Reference voltage High
AVDD - 2.5V
AVSS - 0.3V
VSS - 0.3
—
AVDD + 0.3V
VREF+ - 2.0V
VREF + 0.3
10.0
V
V
A22
A25
A30
VREF- Reference voltage low
VAIN Analog input voltage
—
—
V
ZAIN Recommended impedance of
kΩ
analog voltage source
A40
A50
IAD
A/D conversion cur-
rent (VDD)
Standard
Extended
—
—
220
90
—
—
µA Average current consumption
when A/D is on.
(Note 1)
µA
IREF VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of VHOLD
to VAIN to charge CHOLD, see
Section 11.1.
—
—
10
µA During A/D Conversion cycle
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
DS30292B-page 170
1999 Microchip Technology Inc.
PIC16F87X
FIGURE 15-20: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
130
TAD A/D clock period
1.6
3.0
2.0
3.0
—
—
—
—
µs
µs
TOSC based, VREF ≥ 3.0V
TOSC based, VREF ≥ 2.0V
4.0
6.0
—
6.0
9.0
12
µs A/D RC Mode
µs A/D RC Mode
TAD
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
Note 2
10*
40
—
—
—
µs
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134
TGO Q4 to A/D clock start
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 for min conditions.
1999 Microchip Technology Inc.
DS30292B-page 171
PIC16F87X
NOTES:
DS30292B-page 172
1999 Microchip Technology Inc.
PIC16F87X
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are out-
side specified operating range (i.e., outside specified
VDD range). This is for information only and devices
are ensured to operate properly only within the speci-
fied range.
The data presented in this section is a statistical sum-
mary of data collected on units from different lots over
a period of time and matrix samples. ’Typical’ repre-
sents the mean of the distribution at 25°C. ’Max’ or ’min’
represents (mean + 3σ) or (mean - 3σ) respectively,
where σ is standard deviation, over the whole temper-
ature range.
Graphs and Tables not available at this time.
1999 Microchip Technology Inc.
DS30292B-page 173
PIC16F87X
NOTES:
DS30292B-page 174
1999 Microchip Technology Inc.
PIC16F87X
17.0 PACKAGING INFORMATION
17.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
PIC16F876-20/SP
XXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXX
9917HAT
AABBCDE
28-Lead SOIC
Example
PIC16F876-04/SO
9910SAA
XXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXX
AABBCDE
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
DS30292B-page 175
PIC16F87X
Package Marking Information (Cont’d)
40-Lead PDIP
Example
PIC16F877-04/P
9912SAA
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
AABBCDE
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC16F877
-04/PT
9911HAT
AABBCDE
44-Lead MQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC16F877
-20/PQ
9904SAT
AABBCDE
44-Lead PLCC
Example
PIC16F877
-20/L
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
9903SAT
AABBCDE
DS30292B-page 176
1999 Microchip Technology Inc.
PIC16F87X
17.2
K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil
E
D
2
α
n
1
E1
A1
A
R
L
c
B1
β
A2
p
eB
B
Units
INCHES*
NOM
0.300
28
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
MAX
MIN
NOM
7.62
MAX
n
p
B
B1
R
c
28
2.54
0.48
1.33
0.13
0.25
3.81
2.29
0.51
3.30
34.67
7.30
7.18
8.89
10
0.100
0.019
0.053
0.005
0.010
0.150
0.090
0.020
0.130
1.365
0.288
0.283
0.350
10
0.016
0.022
0.41
0.56
†
0.040
0.000
0.008
0.140
0.070
0.015
0.125
1.345
0.280
0.270
0.320
5
0.065
0.010
0.012
0.160
0.110
0.025
0.135
1.385
0.295
0.295
0.380
15
1.02
0.00
0.20
3.56
1.78
0.38
3.18
34.16
7.11
6.86
8.13
5
1.65
0.25
0.30
4.06
2.79
0.64
3.43
35.18
7.49
7.49
9.65
15
A
A1
A2
L
D
E
E1
eB
α
‡
‡
β
5
10
15
5
10
15
*
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1999 Microchip Technology Inc.
DS30292B-page 177
PIC16F87X
17.3
K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
E
p
D
B
2
1
n
X
α
45°
L
R2
c
A
A1
φ
R1
β
L1
A2
Units
Dimension Limits
Pitch
INCHES*
NOM
0.050
28
MILLIMETERS
MIN
MAX
MIN
NOM
1.27
28
MAX
p
n
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
A
A1
A2
0.093
0.099
0.058
0.008
0.706
0.296
0.407
0.020
0.005
0.005
0.016
4
0.104
2.36
1.22
2.50
1.47
0.19
17.93
7.51
10.33
0.50
0.13
0.13
0.41
4
2.64
0.048
0.004
0.700
0.292
0.394
0.010
0.005
0.005
0.011
0
0.068
0.011
0.712
0.299
0.419
0.029
0.010
0.010
0.021
8
1.73
0.28
18.08
7.59
10.64
0.74
0.25
0.25
0.53
8
0.10
17.78
7.42
10.01
0.25
0.13
0.13
0.28
0
‡
D
‡
E
E1
X
R1
R2
L
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
α
β
0.010
0.009
0.014
0
0.015
0.011
0.017
12
0.020
0.012
0.019
15
0.25
0.23
0.36
0
0.38
0.27
0.42
12
0.51
0.30
0.48
15
†
0
12
15
0
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30292B-page 178
1999 Microchip Technology Inc.
PIC16F87X
17.4
K04-016 40-Lead Plastic Dual In-line (P) – 600 mil
E
D
α
2
n
1
A1
L
E1
A
R
c
B1
B
β
A2
p
eB
Units
INCHES*
NOM
0.600
40
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
MAX
MIN
NOM
15.24
MAX
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
α
40
2.54
0.46
1.27
0.13
0.25
4.06
2.36
0.51
3.30
51.26
13.59
14.35
15.49
10
0.100
0.018
0.050
0.005
0.010
0.160
0.093
0.020
0.130
2.018
0.535
0.565
0.610
10
0.016
0.020
0.41
0.51
†
0.045
0.000
0.009
0.110
0.073
0.020
0.125
2.013
0.530
0.545
0.630
5
0.055
0.010
0.011
0.160
0.113
0.040
0.135
2.023
0.540
0.585
0.670
15
1.14
0.00
0.23
2.79
1.85
0.51
3.18
51.13
13.46
13.84
16.00
5
1.40
0.25
0.28
4.06
2.87
1.02
3.43
51.38
13.72
14.86
17.02
15
‡
‡
β
5
10
15
5
10
15
*
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1999 Microchip Technology Inc.
DS30292B-page 179
PIC16F87X
17.5
K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form
E1
E
# leads = n1
p
D
D1
2
1
B
n
X x 45°
L
α
A
R2
c
φ
R1
A1
β
A2
L1
Units
Dimension Limits
Pitch
INCHES
NOM
0.031
44
MILLIMETERS*
MIN
MAX
MIN
NOM
0.80
44
MAX
p
n
n1
A
A1
A2
R1
R2
L
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
11
11
0.039
0.015
0.002
0.003
0.003
0.005
0
0.043
0.025
0.004
0.003
0.006
0.010
3.5
0.047
1.00
0.38
1.10
0.64
0.10
0.08
0.14
0.25
3.5
1.20
0.035
0.006
0.010
0.008
0.015
7
0.89
0.15
0.25
0.20
0.38
7
0.05
0.08
0.08
0.13
0
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
c
B
0.003
0.004
0.012
0.463
0.463
0.390
0.390
0.025
5
0.008
0.006
0.015
0.472
0.472
0.394
0.394
0.035
10
0.013
0.008
0.018
0.482
0.482
0.398
0.398
0.045
15
0.08
0.09
0.30
11.75
11.75
9.90
9.90
0.64
5
0.20
0.15
0.38
12.00
12.00
10.00
10.00
0.89
10
0.33
0.20
0.45
12.25
12.25
10.10
10.10
1.14
15
†
D1
E1
‡
D
E
‡
X
α
β
5
12
15
5
12
15
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MS-026 ACB
DS30292B-page 180
1999 Microchip Technology Inc.
PIC16F87X
17.6
K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form
E1
E
# leads = n1
p
D
D1
2
1
B
n
X x 45°
α
L
R2
c
A
R1
φ
A1
β
L1
A2
Units
Dimension Limits
Pitch
INCHES
NOM
0.031
MILLIMETERS*
MIN
MAX
MIN
NOM
0.80
44
MAX
p
n
n1
A
A1
A2
R1
R2
L
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
44
11
11
0.079
0.086
0.044
0.006
0.005
0.012
0.020
3.5
0.093
2.00
0.81
2.18
1.11
0.15
0.13
0.30
0.51
3.5
2.35
0.032
0.002
0.005
0.005
0.015
0.056
0.010
0.010
0.015
0.025
1.41
0.25
0.25
0.38
0.64
7
0.05
0.13
0.13
0.38
0
Foot Angle
φ
0
7
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
c
B
0.011
0.005
0.012
0.510
0.510
0.390
0.390
0.025
0.016
0.007
0.015
0.520
0.520
0.394
0.394
0.035
10
0.021
0.009
0.018
0.530
0.530
0.398
0.398
0.045
15
0.28
0.13
0.30
12.95
12.95
9.90
9.90
0.635
5
0.41
0.18
0.37
13.20
13.20
10.00
10.00
0.89
10
0.53
0.23
0.45
13.45
13.45
10.10
10.10
1.143
15
†
D1
E1
‡
D
E
‡
X
α
β
5
5
12
15
5
12
15
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MS-022 AB
1999 Microchip Technology Inc.
DS30292B-page 181
PIC16F87X
17.7
K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square
E1
E
# leads = n1
D1
D
n 1 2
α
A3
CH2 x 45°
CH1 x 45°
R1
c
L
A
35°
A1
B1
B
R2
β
A2
p
E2
D2
Units
Dimension Limits
Number of Pins
INCHES*
NOM
44
MILLIMETERS
MIN
MAX
MIN
NOM
44
MAX
n
Pitch
p
A
0.050
0.173
0.103
0.023
0.029
0.045
0.005
0.690
0.690
0.653
0.653
0.620
0.620
11
0.010
0.029
0.018
0.058
0.005
0.025
5
1.27
Overall Pack. Height
Shoulder Height
Standoff
0.165
0.180
4.19
2.41
0.38
0.61
1.02
0.00
17.40
17.40
16.51
16.51
15.49
15.49
4.38
2.60
0.57
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
11
0.25
0.74
0.46
1.46
0.13
0.64
5
4.57
2.79
0.76
0.86
1.27
A1
A2
A3
CH1
CH2
E1
D1
E
D
E2
D2
n1
c
B1
B
0.095
0.015
0.024
0.040
0.000
0.685
0.685
0.650
0.650
0.610
0.610
0.110
0.030
0.034
0.050
0.010
0.695
0.695
0.656
0.656
0.630
0.630
Side 1 Chamfer Dim.
Corner Chamfer (1)
Corner Chamfer (other)
Overall Pack. Width
Overall Pack. Length
Molded Pack. Width
Molded Pack. Length
Footprint Width
Footprint Length
Pins along Width
Lead Thickness
Upper Lead Width
Lower Lead Width
Upper Lead Length
Shoulder Inside Radius
J-Bend Inside Radius
Mold Draft Angle Top
0.25
17.65
17.65
16.66
16.66
16.00
16.00
‡
‡
0.008
0.026
0.015
0.050
0.003
0.015
0
0.012
0.032
0.021
0.065
0.010
0.035
10
0.20
0.66
0.38
1.27
0.08
0.38
0
0.30
0.81
0.53
1.65
0.25
0.89
10
†
L
R1
R2
α
Mold Draft Angle Bottom
β
0
5
10
0
5
10
*
Controlling Parameter.
†
‡
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MO-047 AC
DS30292B-page 182
1999 Microchip Technology Inc.
PIC16F87X
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
1998
This is a new data sheet. However, these devices are similar to the PIC16C7X
devices found in the PIC16C7X Data Sheet (DS30390). Data Memory Map for
PIC16F873/874, moved ADFM bit from ADCON1<5> to ADCON1<7>
B
1999
FLASH EEPROM access information.
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
PIC16F876/873
5 channels, 10bits
no
Difference
PIC16F877/874
8 channels, 10bits
A/D
Parallel Slave Port
Packages
yes
28-pin PDIP, 28-pin windowed CERDIP,
28-pin SOIC
40-pin PDIP, 44-pin TQFP,
44-pin MQFP, 44-pin PLCC
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of
devices to the ones listed in this data sheet are listed in
Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
PIC16C7X
Characteristic
PIC16F87X
Pins
28/40
3
28/40
3
Timers
Interrupts
Communication
Frequency
A/D
11 or 12
13 or 14
PSP, USART, SSP (SPI, I2C Slave)
PSP, USART, SSP (SPI, I2C Master/Slave)
20 MHz
8-bit
20 MHz
10-bit
CCP
2
2
Program Memory
RAM
4K, 8K EPROM
192, 368 bytes
None
4K, 8K FLASH
192, 368 bytes
128, 256 bytes
EEPROM data
Other
In-Circuit Debugger, Low Voltage
Programming
1999 Microchip Technology Inc.
DS30292B-page 183
PIC16F87X
NOTES:
DS30292B-page 184
1999 Microchip Technology Inc.
PIC16F87X
Buffer Full bit, BF ............................................................... 72
Buffer Full Status bit, BF .................................................... 64
Bus Arbitration ................................................................... 88
Bus Collision Section ......................................................... 88
Bus Collision During a RESTART Condition ..................... 91
Bus Collision During a Start Condition ............................... 89
Bus Collision During a Stop Condition ............................... 92
Bus Collision Interrupt Flag bit, BCLIF ............................... 24
INDEX
A
A/D ................................................................................... 111
ADCON0 Register .................................................... 111
ADCON1 Register .................................................... 112
ADIF bit .................................................................... 113
Analog Input Model Block Diagram .......................... 115
Analog Port Pins ...................................... 7, 8, 9, 37, 38
Block Diagram .......................................................... 114
Configuring Analog Port Pins ................................... 116
Configuring the Interrupt .......................................... 113
Configuring the Module ............................................ 113
Conversion Clock ..................................................... 116
Conversions ............................................................. 117
Delays ...................................................................... 115
Effects of a Reset ..................................................... 118
GO/DONE bit ........................................................... 113
Internal Sampling Switch (Rss) Impedence ............. 114
Operation During Sleep ........................................... 118
Sampling Requirements ........................................... 114
Source Impedence ................................................... 114
Time Delays ............................................................. 115
Absolute Maximum Ratings ............................................. 151
ACK .................................................................................... 72
Acknowledge Data bit ........................................................ 66
Acknowledge Pulse ............................................................ 72
Acknowledge Sequence Enable bit ................................... 66
Acknowledge Status bit ...................................................... 66
ADRES Register ........................................................ 15, 111
Application Note AN578, "Use of the SSP Module
in the I2C Multi-Master Environment." ............................... 71
Application Notes
C
Capture/Compare/PWM
Capture
Block Diagram ................................................... 59
CCP1CON Register ........................................... 58
CCP1IF .............................................................. 59
Mode ................................................................. 59
Prescaler ........................................................... 59
CCP Timer Resources ............................................... 57
Compare
Block Diagram ................................................... 60
Mode ................................................................. 60
Software Interrupt Mode .................................... 60
Special Event Trigger ........................................ 60
Special Trigger Output of CCP1 ........................ 60
Special Trigger Output of CCP2 ........................ 60
Interaction of Two CCP Modules ............................... 57
Section ....................................................................... 57
Special Event Trigger and A/D Conversions ............. 60
Capture/Compare/PWM (CCP)
CCP1
RC2/CCP1 Pin ................................................. 7, 8
CCP2
RC1/T1OSI/CCP2 Pin ..................................... 7, 8
PWM Block Diagram ................................................. 60
PWM Mode ................................................................ 60
CCP1CON ......................................................................... 17
CCP2CON ......................................................................... 17
CCPR1H Register .................................................. 15, 17, 57
CCPR1L Register ........................................................ 17, 57
CCPR2H Register ........................................................ 15, 17
CCPR2L Register ........................................................ 15, 17
CCPxM0 bit ........................................................................ 58
CCPxM1 bit ........................................................................ 58
CCPxM2 bit ........................................................................ 58
CCPxM3 bit ........................................................................ 58
CCPxX bit .......................................................................... 58
CCPxY bit .......................................................................... 58
CKE ................................................................................... 64
CKP ................................................................................... 65
Clock Polarity Select bit, CKP ............................................ 65
Code Examples
AN552 (Implementing Wake-up on Key
Strokes Using PIC16CXXX) ....................................... 31
AN556 (Table Reading Using PIC16CXX) ................. 26
Architecture
PIC16F873/PIC16F876 Block Diagram ....................... 5
PIC16F874/PIC16F877 Block Diagram ....................... 6
Assembler
MPASM Assembler .................................................. 145
B
Banking, Data Memory ................................................ 12, 18
Baud Rate Generator ......................................................... 78
BCLIF ................................................................................. 24
BF .................................................................... 64, 72, 81, 83
Block Diagrams
A/D ........................................................................... 114
Analog Input Model .................................................. 115
Baud Rate Generator ................................................. 78
Capture ...................................................................... 59
Compare .................................................................... 60
Call of a Subroutine in Page 1 from Page 0 .............. 26
Indirect Addressing .................................................... 27
Code Protection ....................................................... 121, 135
Computed GOTO ............................................................... 26
Configuration Bits ............................................................ 121
Conversion Considerations .............................................. 183
2
I C Master Mode ........................................................ 76
2
I C Module ................................................................. 71
PWM .......................................................................... 60
SSP (I C Mode) ......................................................... 71
2
SSP (SPI Mode) ......................................................... 67
Timer0/WDT Prescaler .............................................. 47
Timer2 ........................................................................ 55
USART Receive ....................................................... 101
USART Transmit ........................................................ 99
BRG ................................................................................... 78
BRGH bit ............................................................................ 97
Brown-out Reset (BOR) ........................... 121, 125, 127, 128
BOR Status (BOR Bit) ................................................ 25
D
D/A ..................................................................................... 64
Data Memory ..................................................................... 12
Bank Select (RP1:RP0 Bits) ................................ 12, 18
General Purpose Registers ....................................... 12
Register File Map ................................................ 13, 14
Special Function Registers ........................................ 15
Data/Address bit, D/A ........................................................ 64
DC Characteristics ........................................................... 154
1999 Microchip Technology Inc.
DS30292B-page 185
PIC16F87X
2
Development Support ......................................................145
Device Differences ...........................................................183
Device Overview ..................................................................5
Direct Addressing ......................................................... 27, 28
I C Module Address Register, SSPADD ........................... 72
I C Slave Mode .................................................................. 72
2
ID Locations ............................................................. 121, 135
In-Circuit Serial Programming (ICSP) ...................... 121, 136
INDF .................................................................................. 17
INDF Register ........................................................ 15, 16, 27
Indirect Addressing ...................................................... 27, 28
FSR Register ............................................................. 12
Instruction Format ............................................................ 137
Instruction Set .................................................................. 137
ADDLW .................................................................... 139
ADDWF .................................................................... 139
ANDLW .................................................................... 139
ANDWF .................................................................... 139
BCF ......................................................................... 139
BSF .......................................................................... 139
BTFSC ..................................................................... 140
BTFSS ..................................................................... 140
CALL ........................................................................ 140
CLRF ....................................................................... 140
CLRW ...................................................................... 140
CLRWDT ................................................................. 140
COMF ...................................................................... 141
DECF ....................................................................... 141
DECFSZ .................................................................. 141
GOTO ...................................................................... 141
INCF ........................................................................ 141
INCFSZ .................................................................... 141
IORLW ..................................................................... 142
IORWF ..................................................................... 142
MOVF ...................................................................... 142
MOVLW ................................................................... 142
MOVWF ................................................................... 142
NOP ......................................................................... 142
RETFIE .................................................................... 143
RETLW .................................................................... 143
RETURN .................................................................. 143
RLF .......................................................................... 143
RRF ......................................................................... 143
SLEEP ..................................................................... 143
SUBLW .................................................................... 144
SUBWF .................................................................... 144
SWAPF .................................................................... 144
XORLW ................................................................... 144
XORWF ................................................................... 144
Summary Table ....................................................... 138
INTCON ............................................................................. 17
INTCON Register ............................................................... 20
GIE Bit ....................................................................... 20
INTE Bit ..................................................................... 20
INTF Bit ..................................................................... 20
PEIE Bit ..................................................................... 20
RBIE Bit ..................................................................... 20
RBIF Bit ............................................................... 20, 31
T0IE Bit ...................................................................... 20
T0IF Bit ...................................................................... 20
E
Electrical Characteristics ..................................................151
Errata ...................................................................................4
F
Firmware Instructions .......................................................137
FSR Register ....................................................15, 16, 17, 27
G
General Call Address Sequence ........................................74
General Call Address Support ...........................................74
General Call Enable bit ......................................................66
I
I/O Ports .............................................................................29
2
I C ......................................................................................71
2
I C Master Mode Reception ...............................................83
2
I C Master Mode Restart Condition ...................................80
2
I C Mode Selection ............................................................71
2
I C Module
Acknowledge Sequence timing ..................................85
Addressing .................................................................72
Baud Rate Generator .................................................78
Block Diagram ............................................................76
BRG Block Diagram ...................................................78
BRG Reset due to SDA Collision ...............................90
BRG Timing ...............................................................78
Bus Arbitration ...........................................................88
Bus Collision ..............................................................88
Acknowledge ......................................................88
Restart Condition ...............................................91
Restart Condition Timing (Case1) ......................91
Restart Condition Timing (Case2) ......................91
Start Condition ...................................................89
Start Condition Timing ................................. 89, 90
Stop Condition ...................................................92
Stop Condition Timing (Case1) ..........................92
Stop Condition Timing (Case2) ..........................92
Transmit Timing .................................................88
Bus Collision timing ....................................................88
Clock Arbitration .........................................................87
Clock Arbitration Timing (Master Transmit) ................87
Conditions to not give ACK Pulse ..............................72
General Call Address Support ...................................74
Master Mode ..............................................................76
Master Mode 7-bit Reception timing ..........................84
Master Mode Operation .............................................77
Master Mode Start Condition .....................................79
Master Mode Transmission ........................................81
Master Mode Transmit Sequence ..............................77
Multi-Master Communication .....................................88
Multi-master Mode .....................................................77
Operation ...................................................................71
Repeat Start Condition timing ....................................80
Slave Mode ................................................................72
Slave Reception .........................................................73
Slave Transmission ....................................................73
SSPBUF .....................................................................72
Stop Condition Receive or Transmit timing ................86
Stop Condition timing .................................................86
Waveforms for 7-bit Reception ..................................73
Waveforms for 7-bit Transmission .............................74
2
Inter-Integrated Circuit (I C) .............................................. 63
Internal Sampling Switch (Rss) Impedence ..................... 114
Interrupt Sources ..................................................... 121, 131
Block Diagram ......................................................... 131
Interrupt on Change (RB7:RB4 ) ............................... 31
RB0/INT Pin, External ...................................... 7, 8, 132
TMR0 Overflow ........................................................ 132
USART Receive/Transmit Complete ......................... 95
DS30292B-page 186
1999 Microchip Technology Inc.
PIC16F87X
Interrupts
Bus Collision Interrupt ................................................ 24
Synchronous Serial Port Interrupt .............................. 22
Interrupts, Context Saving During .................................... 132
Interrupts, Enable Bits
PCLATH Register ............................................ 15, 16, 17, 26
PCON Register .................................................... 17, 25, 126
BOR Bit ...................................................................... 25
POR Bit ...................................................................... 25
PIC16F876 Pinout Description ............................................ 7
PICDEM-1 Low-Cost PICmicro Demo Board .................. 147
PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 147
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 147
PICSTART Plus Entry Level Development System ...... 147
PIE1 Register .............................................................. 17, 21
PIE2 Register .............................................................. 17, 23
Pinout Descriptions
Global Interrupt Enable (GIE Bit) ....................... 20, 131
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) .......................................................... 20, 132
Peripheral Interrupt Enable (PEIE Bit) ....................... 20
RB0/INT Enable (INTE Bit) ........................................ 20
TMR0 Overflow Enable (T0IE Bit) .............................. 20
Interrupts, Flag Bits
Interrupt on Change (RB7:RB4) Flag
PIC16F873/PIC16F876 ............................................... 7
PIC16F874/PIC16F877 ............................................... 8
PIR1 Register .................................................................... 22
PIR2 Register .................................................................... 24
POP ................................................................................... 26
PORTA ...................................................................... 7, 8, 17
Analog Port Pins ...................................................... 7, 8
Initialization ................................................................ 29
PORTA Register ........................................................ 29
RA3, RA0 and RA5 Port Pins .................................... 29
RA4/T0CKI Pin .................................................. 7, 8, 29
RA5/SS/AN4 Pin ...................................................... 7, 8
TRISA Register .......................................................... 29
PORTA Register ................................................................ 15
PORTB ...................................................................... 7, 8, 17
PORTB Register ........................................................ 31
Pull-up Enable (RBPU Bit) ......................................... 19
RB0/INT Edge Select (INTEDG Bit) .......................... 19
RB0/INT Pin, External ..................................... 7, 8, 132
RB3:RB0 Port Pins .................................................... 31
RB7:RB4 Interrupt on Change ................................. 132
RB7:RB4 Interrupt on Change Enable
(RBIF Bit) ..................................................... 20, 31, 132
RB0/INT Flag (INTF Bit) ............................................. 20
TMR0 Overflow Flag (T0IF Bit) .......................... 20, 132
K
KeeLoq Evaluation and Programming Tools ................. 148
L
Loading of PC .................................................................... 26
M
Master Clear (MCLR) ....................................................... 7, 8
MCLR Reset, Normal Operation .............. 125, 127, 128
MCLR Reset, SLEEP ............................... 125, 127, 128
Memory Organization
Data Memory ............................................................. 12
Program Memory ....................................................... 11
MPLAB Integrated Development Environment Software . 145
Multi-Master Communication ............................................. 88
Multi-Master Mode ............................................................. 77
O
(RBIE Bit) ........................................................... 20, 132
RB7:RB4 Interrupt on Change Flag
OPCODE Field Descriptions ............................................ 137
OPTION ............................................................................. 17
OPTION_REG Register ..................................................... 19
INTEDG Bit ................................................................ 19
PS2:PS0 Bits ............................................................. 19
PSA Bit ....................................................................... 19
RBPU Bit .................................................................... 19
T0CS Bit ..................................................................... 19
T0SE Bit ..................................................................... 19
OSC1/CLKIN Pin ............................................................. 7, 8
OSC2/CLKOUT Pin ......................................................... 7, 8
Oscillator Configuration ............................................ 121, 123
HS .................................................................... 123, 127
LP ..................................................................... 123, 127
RC ............................................................ 123, 124, 127
XT .................................................................... 123, 127
Oscillator, WDT ................................................................ 133
Output of TMR2 ................................................................. 55
(RBIF Bit) ..................................................... 20, 31, 132
RB7:RB4 Port Pins .................................................... 31
TRISB Register .......................................................... 31
PORTB Register ................................................................ 15
PORTC ...................................................................... 7, 8, 17
Block Diagram ........................................................... 33
PORTC Register ........................................................ 33
RC0/T1OSO/T1CKI Pin ........................................... 7, 8
RC1/T1OSI/CCP2 Pin ............................................. 7, 8
RC2/CCP1 Pin ......................................................... 7, 8
RC3/SCK/SCL Pin ................................................... 7, 8
RC4/SDI/SDA Pin .................................................... 7, 8
RC5/SDO Pin .......................................................... 7, 8
RC6/TX/CK Pin .................................................. 7, 8, 96
RC7/RX/DT Pin ........................................... 7, 8, 96, 97
TRISC Register ................................................... 33, 95
PORTC Register ................................................................ 15
PORTD .................................................................... 9, 17, 38
Block Diagram ........................................................... 35
Parallel Slave Port (PSP) Function ............................ 35
PORTD Register ........................................................ 35
TRISD Register ......................................................... 35
PORTD Register ................................................................ 15
PORTE .......................................................................... 9, 17
Analog Port Pins .............................................. 9, 37, 38
Block Diagram ........................................................... 36
Input Buffer Full Status (IBF Bit) ................................ 36
Input Buffer Overflow (IBOV Bit) ................................ 36
Output Buffer Full Status (OBF Bit) ........................... 36
PORTE Register ........................................................ 36
P
P ......................................................................................... 64
Packaging ........................................................................ 175
Paging, Program Memory ............................................ 11, 26
Parallel Slave Port (PSP) ......................................... 9, 35, 38
Block Diagram ............................................................ 38
RE0/RD/AN5 Pin .............................................. 9, 37, 38
RE1/WR/AN6 Pin ............................................. 9, 37, 38
RE2/CS/AN7 Pin .............................................. 9, 37, 38
Read Waveforms ....................................................... 39
Select (PSPMODE Bit) .................................. 35, 36, 38
Write Waveforms ....................................................... 39
PCL Register .................................................... 15, 16, 17, 26
1999 Microchip Technology Inc.
DS30292B-page 187
PIC16F87X
PSP Mode Select (PSPMODE Bit) ................35, 36, 38
RE0/RD/AN5 Pin .............................................. 9, 37, 38
RE1/WR/AN6 Pin ............................................. 9, 37, 38
RE2/CS/AN7 Pin .............................................. 9, 37, 38
TRISE Register ..........................................................36
PORTE Register ................................................................15
Postscaler, WDT
Assignment (PSA Bit) ................................................19
Rate Select (PS2:PS0 Bits) .......................................19
Power-on Reset (POR) ....................121, 125, 126, 127, 128
Oscillator Start-up Timer (OST) ....................... 121, 126
POR Status (POR Bit) ................................................25
Power Control (PCON) Register ..............................126
Power-down (PD Bit) .........................................18, 125
Power-up Timer (PWRT) ................................. 121, 126
Time-out (TO Bit) ............................................... 18, 125
Time-out Sequence on Power-up ....................129, 130
PR2 ....................................................................................17
PR2 Register ................................................................16, 55
Prescaler, Timer0
Assignment (PSA Bit) ................................................19
Rate Select (PS2:PS0 Bits) .......................................19
PRO MATE II Universal Programmer ............................147
Product Identification System ...........................................191
Program Counter
Reset Conditions ......................................................127
Program Memory ...............................................................11
Interrupt Vector ..........................................................11
Paging ..................................................................11, 26
Program Memory Map ...............................................11
Reset Vector ..............................................................11
Program Verification .........................................................135
Programming Pin (VPP) ....................................................7, 8
Programming, Device Instructions ...................................137
PUSH .................................................................................26
Reset ....................................................................... 121, 125
Block Diagram ......................................................... 125
Reset Conditions for All Registers ........................... 128
Reset Conditions for PCON Register ...................... 127
Reset Conditions for Program Counter .................... 127
Reset Conditions for STATUS Register ................... 127
Restart Condition Enabled bit ............................................ 66
Revision History ............................................................... 183
S
SCK ................................................................................... 67
SCL .................................................................................... 72
SDA ................................................................................... 72
SDI ..................................................................................... 67
SDO ................................................................................... 67
SEEVAL Evaluation and Programming System ............ 148
Serial Clock, SCK .............................................................. 67
Serial Clock, SCL ............................................................... 72
Serial Data Address, SDA ................................................. 72
Serial Data In, SDI ............................................................. 67
Serial Data Out, SDO ........................................................ 67
Slave Select, SS ................................................................ 67
SLEEP ............................................................. 121, 125, 134
SMP ................................................................................... 64
Software Simulator (MPLAB-SIM) ................................... 146
SPBRG .............................................................................. 17
SPBRG Register ................................................................ 16
Special Features of the CPU ........................................... 121
Special Function Registers ................................................ 15
Speed, Operating ................................................................. 1
SPI
Master Mode .............................................................. 68
Master Mode Timing .................................................. 68
Serial Clock ................................................................ 67
Serial Data In ............................................................. 67
Serial Data Out .......................................................... 67
Serial Peripheral Interface (SPI) ................................ 63
Slave Mode Timing .................................................... 69
Slave Mode Timing Diagram ..................................... 69
Slave Select ............................................................... 67
SPI clock .................................................................... 68
SPI Mode ................................................................... 67
SPI Clock Edge Select, CKE ............................................. 64
SPI Data Input Sample Phase Select, SMP ...................... 64
SPI Module
R
R/W ....................................................................................64
R/W bit ...............................................................................72
R/W bit ...............................................................................73
RCREG ..............................................................................17
RCSTA Register ........................................................... 17, 96
CREN Bit ....................................................................96
FERR Bit ....................................................................96
OERR Bit ...................................................................96
RX9 Bit .......................................................................96
RX9D Bit ....................................................................96
SPEN Bit .............................................................. 95, 96
SREN Bit ....................................................................96
Read/Write bit, R/W ...........................................................64
Receive Enable bit .............................................................66
Receive Overflow Indicator bit, SSPOV .............................65
Register File .......................................................................12
Register File Map ......................................................... 13, 14
Registers
Slave Mode ................................................................ 69
SS ...................................................................................... 67
SSP .................................................................................... 63
Block Diagram (SPI Mode) ........................................ 67
RA5/SS/AN4 Pin ...................................................... 7, 8
RC3/SCK/SCL Pin ................................................... 7, 8
RC4/SDI/SDA Pin .................................................... 7, 8
RC5/SDO Pin ........................................................... 7, 8
SPI Mode ................................................................... 67
SSPADD .................................................................... 72
SSPBUF .............................................................. 68, 72
SSPCON1 ................................................................. 65
SSPCON2 ................................................................. 66
SSPSR ................................................................ 68, 72
SSPSTAT ............................................................ 64, 72
FSR Summary ...........................................................17
INDF Summary ..........................................................17
INTCON Summary .....................................................17
OPTION Summary .....................................................17
PCL Summary ............................................................17
PCLATH Summary ....................................................17
PORTB Summary ......................................................17
SSPSTAT ...................................................................64
STATUS Summary ....................................................17
TMR0 Summary .........................................................17
TRISB Summary ........................................................17
2
SSP I C
2
SSP I C Operation .................................................... 71
DS30292B-page 188
1999 Microchip Technology Inc.
PIC16F87X
SSP Module
SPI Master Mode ....................................................... 68
Timers
Timer0
SPI Slave Mode ......................................................... 69
SSPCON1 Register ................................................... 71
SSP Overflow Detect bit, SSPOV ...................................... 72
SSPADD Register ........................................................ 16, 17
SSPBUF ....................................................................... 17, 72
SSPBUF Register .............................................................. 15
SSPCON Register ............................................................. 15
SSPCON1 .................................................................... 65, 71
SSPCON2 .......................................................................... 66
SSPEN ............................................................................... 65
SSPIF ........................................................................... 22, 73
SSPM3:SSPM0 .................................................................. 65
SSPOV ................................................................... 65, 72, 83
SSPSTAT ..................................................................... 64, 72
SSPSTAT Register ...................................................... 16, 17
Stack .................................................................................. 26
Overflows ................................................................... 26
Underflow ................................................................... 26
Start bit (S) ......................................................................... 64
Start Condition Enabled bit ................................................ 66
STATUS Register ........................................................ 17, 18
C Bit ........................................................................... 18
DC Bit ......................................................................... 18
IRP Bit ........................................................................ 18
PD Bit ................................................................. 18, 125
RP1:RP0 Bits ............................................................. 18
TO Bit ................................................................. 18, 125
Z Bit ............................................................................ 18
Stop bit (P) ......................................................................... 64
Stop Condition Enable bit .................................................. 66
Synchronous Serial Port .................................................... 63
Synchronous Serial Port Enable bit, SSPEN ..................... 65
Synchronous Serial Port Interrupt ...................................... 22
Synchronous Serial Port Mode Select bits,
External Clock ................................................... 48
Interrupt ............................................................. 47
Prescaler ........................................................... 48
Prescaler Block Diagram ................................... 47
Section .............................................................. 47
T0CKI ................................................................ 48
Timer1
Asynchronous Counter Mode ............................ 53
Capacitor Selection ........................................... 53
Operation in Timer Mode ................................... 52
Oscillator ............................................................ 53
Prescaler ........................................................... 53
Resetting of Timer1 Registers ........................... 53
Resetting Timer1 using a CCP Trigger Output .. 53
Synchronized Counter Mode ............................. 52
T1CON .............................................................. 51
TMR1H .............................................................. 53
TMR1L ............................................................... 53
Timer2
Block Diagram ................................................... 55
Postscaler .......................................................... 55
Prescaler ........................................................... 55
T2CON .............................................................. 55
Timing Diagrams
A/D Conversion ....................................................... 172
Acknowledge Sequence Timing ................................ 85
Baud Rate Generator with Clock Arbitration .............. 78
BRG Reset Due to SDA Collision .............................. 90
Brown-out Reset ...................................................... 162
Bus Collision
Start Condition Timing ....................................... 89
Bus Collision During a Restart Condition (Case 1) .... 91
Bus Collision During a Restart Condition (Case2) ..... 91
Bus Collision During a Start Condition (SCL = 0) ...... 90
Bus Collision During a Stop Condition ....................... 92
Bus Collision for Transmit and Acknowledge ............ 88
Capture/Compare/PWM .......................................... 164
CLKOUT and I/O ..................................................... 161
SSPM3:SSPM0 .................................................................. 65
T
T1CKPS0 bit ...................................................................... 51
T1CKPS1 bit ...................................................................... 51
T1CON ............................................................................... 17
T1CON Register .......................................................... 17, 51
T1OSCEN bit ..................................................................... 51
T1SYNC bit ........................................................................ 51
T2CKPS0 bit ...................................................................... 55
T2CKPS1 bit ...................................................................... 55
T2CON Register .......................................................... 17, 55
TAD ................................................................................... 116
Timer0
Clock Source Edge Select (T0SE Bit) ........................ 19
Clock Source Select (T0CS Bit) ................................. 19
Overflow Enable (T0IE Bit) ........................................ 20
Overflow Flag (T0IF Bit) ..................................... 20, 132
Overflow Interrupt .................................................... 132
RA4/T0CKI Pin, External Clock ............................... 7, 8
Timer1 ................................................................................ 51
RC0/T1OSO/T1CKI Pin ........................................... 7, 8
RC1/T1OSI/CCP2 Pin .............................................. 7, 8
2
I C Bus Data ............................................................ 169
I C Bus Start/Stop bits ............................................. 168
I C Master Mode First Start bit timing ....................... 79
I C Master Mode Reception timing ............................ 84
2
2
2
2
I C Master Mode Transmission timing ...................... 82
Master Mode Transmit Clock Arbitration ................... 87
Power-up Timer ....................................................... 162
Repeat Start Condition .............................................. 80
Reset ....................................................................... 162
SPI Master Mode ....................................................... 68
SPI Slave Mode (CKE = 1) ........................................ 69
SPI Slave Mode Timing (CKE = 0) ............................ 69
Start-up Timer .......................................................... 162
Stop Condition Receive or Transmit .......................... 86
Time-out Sequence on Power-up .................... 129, 130
Timer0 ..................................................................... 163
Timer1 ..................................................................... 163
USART Asynchronous Master Transmission .......... 100
USART Asynchronous Reception ........................... 101
USART Synchronous Receive ................................ 170
USART Synchronous Reception ............................. 107
USART Synchronous Transmission ................ 106, 170
USART, Asynchronous Reception .......................... 104
Wake-up from SLEEP via Interrupt ......................... 135
Watchdog Timer ...................................................... 162
1999 Microchip Technology Inc.
DS30292B-page 189
PIC16F87X
TMR0 .................................................................................17
TMR0 Register ...................................................................15
TMR1CS bit ........................................................................51
TMR1H ...............................................................................17
TMR1H Register ................................................................15
TMR1L ...............................................................................17
TMR1L Register .................................................................15
TMR1ON bit .......................................................................51
TMR2 .................................................................................17
TMR2 Register ...................................................................15
TMR2ON bit .......................................................................55
TOUTPS0 bit ......................................................................55
TOUTPS1 bit ......................................................................55
TOUTPS2 bit ......................................................................55
TOUTPS3 bit ......................................................................55
TRISA .................................................................................17
TRISA Register ..................................................................16
TRISB .................................................................................17
TRISB Register ..................................................................16
TRISC ................................................................................17
TRISC Register ..................................................................16
TRISD ................................................................................17
TRISD Register ..................................................................16
TRISE .................................................................................17
TRISE Register ............................................................ 16, 36
IBF Bit ........................................................................36
IBOV Bit .....................................................................36
OBF Bit ......................................................................36
PSPMODE Bit ................................................ 35, 36, 38
TXREG ...............................................................................17
TXSTA ................................................................................17
TXSTA Register .................................................................95
BRGH Bit ...................................................................95
CSRC Bit ....................................................................95
SYNC Bit ....................................................................95
TRMT Bit ....................................................................95
TX9 Bit .......................................................................95
TX9D Bit .....................................................................95
TXEN Bit ....................................................................95
RCSTA Register ........................................................ 96
Receive Block Diagram ........................................... 101
Receive Data, 9th bit (RX9D Bit) ............................... 96
Receive Enable, 9-bit (RX9 Bit) ................................. 96
Serial Port Enable (SPEN Bit) ............................. 95, 96
Single Receive Enable (SREN Bit) ............................ 96
Synchronous Master Mode ...................................... 105
Synchronous Master Reception ............................... 107
Synchronous Master Transmission ......................... 105
Synchronous Slave Mode ........................................ 108
Transmit Block Diagram ............................................ 99
Transmit Data, 9th Bit (TX9D) ................................... 95
Transmit Enable (TXEN Bit) ...................................... 95
Transmit Enable, Nine-bit (TX9 Bit) ........................... 95
Transmit Shift Register Status (TRMT Bit) ................ 95
TXSTA Register ......................................................... 95
W
Wake-up from SLEEP .............................................. 121, 134
Interrupts ......................................................... 127, 128
MCLR Reset ............................................................ 128
Timing Diagram ....................................................... 135
WDT Reset .............................................................. 128
Watchdog Timer (WDT) ........................................... 121, 133
Block Diagram ......................................................... 133
Enable (WDTE Bit) .................................................. 133
Programming Considerations .................................. 133
RC Oscillator ............................................................ 133
Time-out Period ....................................................... 133
WDT Reset, Normal Operation ................ 125, 127, 128
WDT Reset, SLEEP ................................. 125, 127, 128
Waveform for General Call Address Sequence ................. 74
WCOL .................................................. 65, 79, 81, 83, 85, 86
WCOL Status Flag ............................................................. 79
Write Collision Detect bit, WCOL ....................................... 65
WWW, On-Line Support ...................................................... 4
U
UA ......................................................................................64
Universal Synchronous Asynchronous Receiver
Transmitter (USART)
Asynchronous Receiver
Setting Up Reception .......................................103
Timing Diagram ................................................104
Update Address, UA ..........................................................64
USART ...............................................................................95
Asynchronous Mode ..................................................99
Receive Block Diagram ....................................103
Asynchronous Receiver ...........................................101
Asynchronous Reception .........................................102
Asynchronous Transmitter .........................................99
Baud Rate Generator (BRG) ......................................97
Baud Rate Formula ............................................97
Baud Rates, Asynchronous Mode (BRGH=0) ...98
High Baud Rate Select (BRGH Bit) ....................95
Sampling ............................................................97
Clock Source Select (CSRC Bit) ................................95
Continuous Receive Enable (CREN Bit) ....................96
Framing Error (FERR Bit) ..........................................96
Mode Select (SYNC Bit) ............................................95
Overrun Error (OERR Bit) ..........................................96
RC6/TX/CK Pin ........................................................7, 8
RC7/RX/DT Pin ........................................................7, 8
DS30292B-page 190
1999 Microchip Technology Inc.
PIC16F87X
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
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Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
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Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
ConnectingtotheMicrochipInternetWebSite
981103
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
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ety of Microchip specific business information is also
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Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLAB are regis-
tered trademarks of Microchip Technology Incorporated in
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U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
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All other trademarks mentioned herein are the property of
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• Job Postings
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• Listing of seminars and events
1999 Microchip Technology Inc.
DS30292B-page 191
PIC16F87X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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Literature Number:
DS30292B
Device:
PIC16F87X
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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DS30292B-page 192
1999 Microchip Technology Inc.
PIC16F87X
PIC16F87X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Examples:
Frequency Temperature Package
Range Range
Pattern
f)
PIC16F877 -20/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
g)
h)
PIC16F876 - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
Device
PIC16F87X(1), PIC16F87XT(2) ;VDD range 4.0V to 5.5V
PIC16LF87X(1), PIC16LF87XT(2 );VDD range 2.0V to 5.5V
PIC16F877 - 04I/P = Industrial temp., PDIP
package, 10MHz, normal VDD limits.
Frequency Range
04
20
= 4 MHz
= 20 MHz
Note 1:
F
= CMOS FLASH
LF = Low Power CMOS FLASH
Temperature Range
b(3)
I
=
=
0°C to
70°C (Commercial)
T
= in tape and reel - SOIC, PLCC,
MQFP, TQFP packages only.
-40°C to +85°C (Industrial)
Package
PQ
PT
SO
SP
P
=
=
=
=
=
=
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
PLCC
L
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
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2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
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Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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1999 Microchip Technology Inc.
DS30292B-page 193
PIC16F87X
NOTES:
DS30292B-page 194
1999 Microchip Technology Inc.
PIC16F87X
NOTES:
1999 Microchip Technology Inc.
DS30292B-page 195
PIC16F87X
NOTES:
DS30292B-page 196
1999 Microchip Technology Inc.
PIC16F87X
NOTES:
1999 Microchip Technology Inc.
DS30292B-page 197
PIC16F87X
NOTES:
DS30292B-page 198
1999 Microchip Technology Inc.
PIC16F87X
NOTES:
1999 Microchip Technology Inc.
DS30292B-page 199
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Singapore Pte Ltd.
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#07-02 Prime Centre
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Microchip Technology Inc.
Microchip Technology Inc.
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Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
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Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
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Taiwan, R.O.C
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Italy
Los Angeles
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Microchip Technology Inc.
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Microchip Technology Inc.
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Tel: 631-273-5305 Fax: 631-273-5335
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30292B-page 200
1999 Microchip Technology Inc.
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