PJ3842BCD [ETC]
High Performance Current Mode Controller; 高性能电流模式控制器
| 型号： | PJ3842BCD |
| 厂家： | 
ETC |
| 描述： | High Performance Current Mode Controller |
| 文件： | 总15页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PJ3842B
High Performance Current Mode Controller
he PJ3842B series is high performance fixed frequency
Also included are protective features consisting of input
and reference undervoltage lockouts each with hysteresis,
Tcurrent mode controllers. This is specifically designed
for Off-Line and DC-to-DC converter applications offering
the designer a cost effective solution with minimal external
cycle-by-cycle current limiting , programmable output
deadtime, and a latch for single pulse metering.
This device is available in 8-pin dual-in-line plastic
packages as well as the 8-pin plastic surface mount (SOP-8).
The SOP-8 package has separate power and ground pins for
the totem pole output stage.
components.This integrated circuits feature
a trimmed
oscillator for precise duty cycle control, a temperature
compensated reference, high gain error amplifier, current
sensing comparator,and a high current totem pole output
ideally suited for driving a power MOSFET.
The PJ3842B has UVLO thresholds of 16V (on) and
10V (off), ideally suited for off-line converters.
FEATURES
DIP-8
SOP-8
•
Trimmed Oscillator Discharge Current for Precise Duty
Cycle Control
•
•
•
•
Current Mode Operation to 500KHz
Automatic Feed Forward Compensation
Latching PWM for Cycle-By-Cycle Current Limiting
Internally Trimmed Reference with Undervoltage
Lockout
Pin: 1. Compensation
2. Voltage Feedback
3. Current Sense
5. Gnd
6. Output
7. Vcc
4. RT/CT
8. Vref
ORDERING INFORMATION
•
•
•
High Current Totem Pole Output
Device
PJ3842BCD
PJ3842BCS
Operating Temperature
-20℃ TO +85℃
Package
DIP-8
Input Undervoltage Lockout with Hystersis
Low Start-Up and Operating Current
SOP-8
SIMPLIFIED BLOCK DIAGRAM
The document contains information on a new product.Specifications and information herein are subject to change without notice.
1-15
2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
MAXIMUM RATING
Rating
Symbol
Value
Unit
Total Power Supply and Zener Current
Output Current Source or Sink (Note 1)
Output Energy (Capacitive Load per Cycle)
Current Sense and Voltage Feedback Inputs
Error Amp Output Sink Current
Power Dissipation and Thermal Characteristics
Plastic Dip
(ICC+IZ)
Io
30
1.0
mA
A
W
5.0
μJ
V
Vin
Io
-0.3 to +5.5
10
mA
Maximum Power Dissipation @ TA=25℃
Thermal Resistance Junction to Air
Plastic Dip
PD
RθJA
862
145
mW
℃/W
Maximum Power Dissipation @ TA=25℃
Thermal Resistance Junction to Air
Operating Junction Temperature
Operature Ambient Temperature
Storage Temperature Range
PD
RθJA
TJ
1.25
100
W
℃/W
℃
℃
℃
+150
TA
0 to +70
-65 to +150
Tstg
ELECTRICAL CHARACTERISTICS (VCC = 15V (Note 2), RT =10K, CT=3.3nF, TA=Tlow to Thigh(Note 3) unless otherwise
PJ3842B
Characteristic
REFERENCE SECTION
Symbol
Min
Typ
Max
Unit
Reference Output Voltage (Io=1.0mA,TJ = 25℃)
Line Regulation (VCC =12V to 25V)
Vref
Regline
Regload
Ts
Vref
Vn
5.0
5.0
2.0
3.0
0.2
-
5.0
20
25
-
5.18
-
V
mV
mV
mV/℃
V
-
Load Regulation (Io =1.0mA to 20mA)
Temperature Stability
Total Output Variation over Line,Load ,and Temperature
Output Noise Voltage (f = 10Hz to 10kHz, TJ=25℃)
Long Term Stability ( TA=125.℃ for 1000 Hours)
Output Short Circuit Current
-
-
4.82
-
50
µV
S
-
5.0
-85
-
mV
mA
Isc
-30
180
OSCILLATOR SECTION
Frequency
Fosc
KHz
TJ=25℃
TA=Tlow toThigh
47
46
-
52
-
57
60
1.0
-
Frequency Change with Voltage (VCC =12V to 25V)
Frequency Change with Temperature
TA=Tlow toThigh
Δfos c/ ΔV
Δfos c/ ΔT
0.2
5.0
%
%
-
Oscillator Voltage Swing ( Peak-to-Peak)
Discharge Current (Vosc=2.0V)
TJ=25℃
Vosc
-
1.6
-
V
Idischg
mA
7.5
7.2
8.4
-
9.3
9.5
TA=Tlow toThigh
Note: 1. Maximum Package power dissipation limits must be observed.
2. Adjust VCC above the Start-Up threshold before setting to 15V.
3. Low duty cycle pulse technique are used during test to maintain junction temperature as close to ambient as possible.
Tlow = -20℃ Thigh = +85℃
4. This parameter is measured at the latch trip point with VFB = 0V.
ΔV Output Compensation
5. Comparator gain is defined as : Av =
ΔV Current Sense Input
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2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
ELECTRICAL CHARACTERISTICS (VCC =15V(Note 2) , RT=10K CT=3.3nF TA=T lo w to Thigh ( Note 3) unless otherwise
Characteristic
Symbol
PJ3842B
Typ
Unit
Min
Max
ERROR AMPLIFIER SECTION
Voltage Feedback Input (Vo=2.5V)
Input Bias Current (VFB =5.0V)
Open-Loop Voltage Gain (Vo=2.0V to 4.0V)
Unity Gain Bandwidth (TJ=25℃)
Power Supply Rejection Radio (VCC=12V to 25V)
Output Current
VFB
IIB
2.42
-
2.5
-0.1
90
2.58
V
-2.0
μΑ
dB
AVOL
BW
65
0.7
60
-
-
-
1.0
70
MHz
dB
PSRR
mA
Sink (Vo=1.1V, VFB =2.7V)
Isink
2.0
12
-
-
Source ( Vo=5.0V, VFB =2.3V)
ISource
-0.5
-1.0
Output Voltage Swing
V
High State (RL=15K to ground, VFB =2.3V)
Low State (RL=15K to Vref, VFB=2.7V)
VOH
VOL
5.0
-
6.2
0.8
-
1.1
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Note 4&5)
Maximum Current Sense Input Threshold(Note 4)
Power Supply Rejection Radio
VCC=12V to 25V,Note 4
Input Bias Current
Av
Vth
2.85
0.9
-
3.0
1.0
70
3.15
1.1
-
V/V
V
PSRR
dB
IIB
-
-
-2.0
150
-10
μΑ
Propagation Delay(Current Sense Input to Output)
OUTPUT SECTION
tPLH(IN/OUT)
300
ns
Output Voltage
V
Low State (Isink=20mA)
(Isink=200mA)
VOL
VOH
-
-
0.1
1.6
0.4
2.2
-
High State (Isource=20mA)
(Isource=200mA)
13
12
-
13.5
13.4
0.1
-
Output Voltage with UVLO Activated
VCC=6.0V,Isink=1.0mA
VOL(UVLO)
1.1
V
Output Voltage Rise Time (CL=1.0nF,TJ=25℃)
Output Voltage Fall Time (CL=1.0nF,TJ=25℃)
UNDERVOLTAGE LOCKOUT SECTION
Start-Up Threshold
tr
tf
-
-
50
50
150
150
ns
ns
Vth
V
V
PJ3842B
14.5
8.5
16
10
17.5
11.5
Minimum Operating Voltage After Turn-On
PJ3842B
VCC(min)
PWM SECTION
Duty Cycle
%
Maximum
DCmax
DCmin
94
-
96
-
-
Minimum
0
TOTAL DEVICE
Power Supply Current
ICC
Vz
mA
V
Start-Up, VCC= 14V
-
-
0.25
12
0.5
17
-
Operating (Note 2)
Power Supply Zener Voltage (ICC=25mA)
30
36
3-15
2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
FIGURE 1- OUTPUT DEAD TIME versus
FIGURE 2- TIMING RESISTOR versus
OSCILLATOR FREQUENCY
OSCILLATOR FREQUENCY
FIGURE 3-OSCILLATOR DISCHARGE CURRENT
versus TEMPERATURE
FIGURE 4-MAXIMUM OUTPUT DUTY CYCLE
versus TIMING RESISTOR
FIGURE 5-ERROR AMP SMALL SIGNAL
TRANSIENT RESPONSE
FIGURE 6-ERROR AMP LARGE SIGNAL
TRANSIENT RESPONSE
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PJ3842B
High Performance Current Mode Controller
FIGURE 7-ERROR AMP OPEN-LOOP GAIN AND
FIGURE 8-CURRENT SENSE INPUT THRESHOLD
versus ERROR AMP OUTPUT VOLTAGE
PHASE versus FREQUENCY
FIGURE 9-REFERENCE VOLTAGE CHANGE
versus SOURCE CURRENT
FIGURE 10-REFERENCE SHORT CIRCUIT
CURRENT versus TEMPERATURE
FIGURE 11- REFERENCE LOAD REGULATION
FIGURE 12-REFERENCE LINE REGULATION
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PJ3842B
High Performance Current Mode Controller
FIGURE 13-OUTPUT SATURATION VOLTAGE
FIGURE 14-OUTPUT WAVEFORM
versus LOAD CURRENT
FIGURE 15-OUTPUT CROSS CONDUCTION
FIGURE 16-SUPPLY CURRENT versus SUPPLY
VOLTAGE
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2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
FIGURE 17-REPRESENTATIVE BLOCK DIAGRAM
Pin numbers adjacent to terminals are for the 8 pin dual-in-line package.
Pin numbers in parenthesis are for the SOP-14 package.
FIGURE 18-TIMING DIAGRAM
UNDERVOLTAGE LOCKOUT
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators.Each has built-in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The large hysteresis and
low start-up current of the PJ3842B makes it ideally suited in
off-line converter applications where efficient bootstrap start-
up technique (Figure 33). 36 V zener is connected as a shunt
regulator from VCC to ground.Its purpose is to protect the IC
from excessive voltage that can occur during system start-up.
The minimum operating voltage for the PJ3842B is 11V.
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2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
Output
These devices contain a single totem pole output stage
FIGURE 19-CONTINUOUS CURRENT WAVEFROMS
that was specifically designed for direct drive of power
MOSFET’s. It is capable of up to ±1.0A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active.This characteristic eliminates the need for an
external pull-down resistor.
The SOP-8 surface mount package provides separate pins
for Vc(output supply) and Power Ground.Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level.The separate Vc supply input allows the designer
added fiexlbility in tailoring the drive voltage independent of
Vcc.A zener clamp is typically connected to this input when
driving power MOSFETs in systems where Vcc is greater
than 20V. Figure 25 shows proper power and control ground
connections in a current sensing power MOSFET application.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current,This instability is
independent of the regulators closed loop characteristics and
is caused by the simultaneous operating conditions of fixed
frequency and peak current detecting. Figure 19A shows the
phenomenon graphically, At t0 , switch conduction begins ,
causing the inductor current to rise at a slope of m1. This
slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2,
until the next oscillator cycle. This unstable condition can be
shown if a perturbation is added to the control voltage ,
resulting in a small Δl (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn-on(t2) is increased by Δl+Δl m2/m1.
The minimum current at the next cycl e (t3) decreases to (Δ
l+ Δ l m2/m1)(m2/m1). This perturbation is multiplied by
m2/m1 on each succeeding cycle , alternat ely increasing and
decreasing the inductor current at switch turn-on, Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If m2/m1
is greater than 1, the converter will be unstable . Figure 19B
shows that by adding an artificial ramp that is synchronized
with the PWM clock to the control voltage . the Δ l
perturbation will decrease to zero on succeeding cycles. This
compensating ramp (m3) must have a slope equal to or
slightly greater than m2/2 for stability . With m2/2 slope
compensation , the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense inputs
(Figure 32).
Reference
The 5.0V bandgap reference is trimmed to±2.0% on the
PJ3842B.Its promary purpose to supply charging current to
the oscillator timing capacitor.The reference has short circuit
protection and is capable of providing in excess of 20mA for
powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on wirewrap or
plug-in prototype boards. High frequency circuit layout
techniques are imperative to prevent pulsewidth jitter.This is
usually caused by excessive noise pick-up imposed on the
Current Sense or Voltage Feedback inputs.Noise immunity
can be improved by lowering circuit impedances at these
points.The printed circuit layout should contain a ground
plane with lowcurrent signal and high-current switch and
output grounds returning separate paths back to the input
filter capacitor.Ceramic bypass capacitors(0.1μF) connect ed
directly to Vcc,Vc, and Vref may be required depending upon
circuit layout . This provides a low impedance path for
filtering the high frequency noised. All high current loops
should be kept as short as possible using heavy copper runs to
minimize radiated EMI. The Error Amp compensation
circuitry and the converter output voltage divider should be
located close to the IC and as far as possible from the power
switch and other noise generating components.
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2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
FIGURE 20-EXTERNAL CLOCK
FIGURE 21-EXTERNAL DUTY CYCLE CLAMP AND
MULTI UNIT SYNCHRONIZATION
SYNCHRONIZATION
1.44
RB
The diode clamp is required ifthe Sync amplitude is large enough to
the cause the bottomside ofCT to go more than 300mV below
ground.
f=
DMAX=
(RA+RB)
RA+2RB
FIGURE 22-ADJUSTABLE REDUCTION OF CLAMP
LEVEL
FIGURE 23-SOFT-START CIRCUIT
Isoft-Start=3600c in µF
FIGURE 24-ADJUSTABLE BUFFERED REDUCTION
OF CLAMP LEVEL WITH SOFT-STAR
FIGURE 25-CURRENT SENSING POWER MOSFET
Virtually lossless current sensing can be achieved with the
implementation of a SENSEFET power switch.For proper operation
during over current conditions.a reduction of the Ipk(max) clamp
level must be implemented.Refer to Figure 22 and 24
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PJ3842B
High Performance Current Mode Controller
FIGURE 26-CURRENT WAVEFORM SPIKE
FIGURE 27-MOSFET PARASITIC OSCILLATIONS
SUPPRESSION
The addition ofRC filter will eliminate instability caused
by the leading edge splik on the current waveform.
FIGURE 29-ISOLATED MOSFET DRIVE
FIGURE 28-BIPOLAR TRANSISTOR DRIVE
The totem-pole output can furnish negativebase current for
enhanced transistorturn-off,with the additions ofcapacitor C1.
FIGURE 30-LATCHED SHUTDOWN
FIGURE 31-ERROR AMPLIFIER COMPENSATION
Error Amp compensation circuit for stabilizing any currentmode topology
except for boost and flyback converters operating with continuous inductor
current.
Error Amp compensation circuit for stabilizing any currentmode topology
except for boost and flyback converters operating with continuous inductor
current.
The MCR101 SCR must be selected for a holding of less than 0.5mA at TA
(min).The simple two transistor circuit can be used in place of the SCR as
shown.All resistors are 10K.
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2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
FIGURE 32-SLOPE COMPENSATION
The buffered oscillator ramp can resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
FIGURE 33-27 WATT OFF-LINE REGULATION
T1-Primary:45 Turns #26 AWG
Secondary ±12V :9 Turns #30 AWG (2 strands ) Bifiliar Wound
Secondary 5.0V: 4Turns (six strands) #26 Hexfiliar Wound
L1-15μH at 5.0A, Coilcraft 27156.
L2.L3-25μH at 1.0A, Coilcraft 27157.
Secondary Feedback : 10 Turns #30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35-3C8
Bobbin : Ferroxcube EC35PCB1
Gap : 0.10” for a primary inductance of 1.0mH
≌
Line Regulation:5.0V
±12V
Vin=95 to 130 Vac
=50mV or ±0.5%
=24mV or ±0.1%
Load Regulation: 5.0V
±12V
Vin=115Vac, Iout =1.0A to 4.0A
=300mV or ±3.0%
=60mV or ±0.25%
40mVp-p
Vin=115Vac,Iout=100mA to 300mA
Vin=115Vac
Output Ripple: 5.0V
±12V
80 Vp-p
Efficiency
Vin=115Vac
70%
All outputs are at nominal load currents unless otherwise noted.
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PJ3842B
High Performance Current Mode Controller
FIGURE 21-33 WATT OFF-LINE FLYBACK CONVERTER
WITH SOFT-START AND PRIMARY POWER LIMITING
T1
Coilcraft 11-464-16, 0.025” gap
in each leg
Baobbin :
Coilcraft 37-573
Windings:
Primary, 2each:
75 turns #26 Awg Bifilar wound
TEST
CONDITIONS
Vin=95 to 135 Vac, Io=3.0A
Vin=95 to 135 Vac, Io=±0.75A
Vin=115 Vac, Io=1.0 to 4.0A
Vin=115 Vac, Io=±0.4 to ±0.9A
Vin=115 Vac, Io=3.0A
RESULTS
20mV 0.40%
52mV 0.26%
476mV 9.5%
300mV 2.5%
45 mVp-p
Line Regulation 5.0V
Line Regulation± 12V
Line Regulation 5.0V
Line Regulation± 12V
Line Regulation 5.0V
Feedback:
15 turns #26 Awg
Secondary , 5.0V:
6 turns #22 Awg Bifiar wound
Secondary , 5.0V:
P.A.R.D.
14 turns #24 Awg Bifiar wound
Line Regulation± 12V
Efficiency
Vin=115 Vac, Io=±0.75A
75 mV p-p
P.A.R.D.
L1
Coilcraft Z7156. 15μF @ 5.0A
Vin=115 Vac, Io 5.0V=3.0A
Io ±12=±0.75A
74%
L2,L3
Coilcraft Z7157. 25μF @ 1.0A
12-15
2002/01.ver.A
PJ3842B
High Performance Current Mode Controller
PIN FUNCTION DESCRIPTION
Pin No.
8-Pin
Function
Description
1
Compensation
This pin is the Error Amplifier output and is made available for loop
compensation
2
Voltage Feedback
This is the inverting input of the Error Amplifier. It is normally
connected to the switching power supply output through a resistor
divider.
3
4
Current Sense
RT/CT
A voltage proportional to inductor current is connected to this input.
The PWM uses this information to terminate the output switch
conduction.
The Oscillator Frequency and maximum Output duty are
programmed by connecting resistor RT to Vref and capacitor CT to
ground operation to 500kHz is possible.
5
6
Gnd
This pin is the combined control circuitry and power ground (8-pin
package only).
Output
This output directly drives the gate of a power MOSFET.Peak current
up to 1.0A are soured and sunk by this pin.
7
8
Vcc
This pin is the positive supply of the control IC.
Vref
This pin is the reference output . It provides charging current for
capacitor CT through resistor RT.
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PJ3842B
High Performance Current Mode Controller
OPERATING DESCRIPTION
The PJ3842B series are high performance, fixed frequency, current mode controllers, They are specifically designed for Off-Line
and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components . A
representative block diagram is shown in Figure 17.
OSCILLATOR
The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged
from the 5.0V reference through resistor RT to approximately 2.8V and discharge to 1.2V by an internal current sink.During the
discharge of CT , the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes
the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator
Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT . Note that many values of RT and C T
will give the same oscillator frequency but only onne combination will yield a specific output deadtime at a given frequency. The
oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at TJ
=25℃. These internal circuit refinements minimum variations of oscillator frequency and maximum output duty cycle. The
results are shown in Figure 3 and 4.
In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be
accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking. The free-running oscillator
frequency should be set about 10% less than the clock frequency . A method for multi unit synchronization is shown in Figure 21.
By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.
ERROR AMPLIFIER
A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage
gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees of phase margin (Figure 7). The non-inverting input is
internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the
inverting input. The maximum input bias current is -2.0μA which can cause an output voltage error that is equal to the product of
the input bias current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 31). The output voltage is offset by two diode
drops (≈1.4V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that
no drive pulses appear at the Output(Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is
operating and the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum
feedback resistance is limited by the amplifier's source current (0.5mA) and the required output voltage (VOH) to reach the
comparator’s 1.0V clamp level:
Rf(MIN) = [3.0 (1.0V)+1.4V] / 0.5mA = 8800Ω
CURRENT SENSE COMPARATOR AND PWM LATCH
The PJ3842B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated
when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus
the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch
configuration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is
converted to a voltageby inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This
voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak
inductor current under normal operating conditions is controlled by the voltage at pin 1 where:
IPK = [V(Pin 1) - 1.4V] / 3RS
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost, Under these
conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch
current is:
IPK (MAX) = 1.0V / RS
When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the
power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external
diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to
noise pickup can result if there is an excessive reduction of the IPK (max) clamp voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit
an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output
rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike
duration will usually eliminate the instability: refer to Figure 26.
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PJ3842B
High Performance Current Mode Controller
MILLIMETERS
INCHES
MIN
0.357
0.245
0.125
0.019
DIM
A
B
C
D
MIN
9.07
6.22
3.18
0.35
MAX
9.32
6.48
4.43
0.55
MAX
0.367
0.255
0.135
0.020
G
2.54BSC
0.10BSC
J
K
L
M
0.29
3.25
7.75
-
0.31
3.35
8.00
10°
0.011
0.128
0.305
-
0.012
0.132
0.315
10°
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
4.80
3.80
1.35
0.35
0.40
MAX
5.00
4.00
1.75
0.49
1.25
MIN
0.189
0.150
0.054
0.014
0.016
MAX
0.196
0.157
0.068
0.019
0.049
F
G
1.27BSC
0.05BSC
K
M
P
0.10
0°
5.80
0.25
0.25
7°
6.20
0.50
0.004
0°
0.229
0.010
0.009
7°
0.244
0.019
R
15-15
2002/01.ver.A
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