PLL2026X [ETC]
PLL2026X 25MHz ~ 300MHz FSPLL PLL2026X|Data Sheet ; PLL2026X为25MHz 〜 300MHz的FSPLL PLL2026X |数据表\n
| 型号： | PLL2026X |
| 厂家： | 
ETC |
| 描述： | PLL2026X 25MHz ~ 300MHz FSPLL PLL2026X|Data Sheet
|
| 文件： | 总6页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
25MHz ~ 300MHz FSPLL
PLL2026X
February 2000 V2.0
General Description
Features
The PLL2026X is a Phase-Locked Loop (PLL) frequency synthesizer
constructed in CMOS process technology. The PLL macrofunctions
provide frequency multiplication capabilities.The output clock frequency
Fout is related to the reference input clock frequency, by the follwing
equation:
• 0.25um CMOS process technology
• 2.5 Volt Single power supply
• Output frequency range: 25MHz~300 MHz
• Cycle-to-cycle jitter: ±…100ps
• Output Duty ratio: 40% to 60%
• Input Duty ratio: 30% to 70%
• Frequency changed by programmable divider
• Power down mode
Fout=( m*Fin ) / ( p*s )
where Fout is the output clock frequency. Fin is the reference input
clock frequency. m,p and s are the values for programmable dividers.
PLL2026X consists of a Phase/Frequency Detector(PFD), a Charge
Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO),
a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as
shown in Figure 1.
• Lock Detector mode
FUNCTIONAL BLOCK DIAGRAM
LDT
LD
FIN
FOUT
Pre Divider
P
Charge
Pump
Post Scaler
VCO
PFD
S
FILTER
Main Divider
M
PWRDN
P[5]~P[0]
M[7]~M[0]
S[1],S[0]
AVSS25A
AVSS25D
AVDD25A
AVDD25D
AVBB25
Figure 1. Functional Block Diagram
1 / 6
PLL2026X
25MHz~300MHz FSPLL
SYMBOL PIN DESCRIPTION
NAME
AVDD25D
AVSS25D
AVDD25A
AVSS25A
AVBB25
FIN
I/O TYPE
PIN DESCRIPTION
DP
Digital power supply
I/O TYPE ABBR.
DG
Digital ground
¡ ¤
AI : Analog Input
¡ ¤
DI : Digital Input
¡ ¤
AO : Analog Output
¡ ¤
DO : Analog Output
AP
Analog power supply
Analog ground
AG
AG
Substrate ground
External Clock input
DI
. Pump out is connected to Filter
. A capacitor and 2 resistor are connected
between the pin and analog ground
¡ ¤
AP : Analog Power
¡ ¤
AG : Analog Ground
FILTER
AO
¡ ¤
AB : Analog Sub Bias
¡ ¤
DP : Digital Power
¡ ¤
DG : Digital Ground
¡ ¤
DB : Digital Sub Vias
LDT
DO
DO
Lock Detector output. High(locking state)
25MHz~300MHz clock output
FOUT
FSPLL clock power down.
-If PWRDN is High, PLL does not operate
under this condition.
PWRDN
DI
-If not used, tie it to VSS.
¡ ¤
BD : Bidirectional Port
P[5:0]
M[7:0]
S[1:0]
DI
DI
DI
The values for 6bit programmable pre-divider.
The values for 8bit programmable main divider.
The values for 2bit programmable post scaler.
SYMBOL CONFIGURATION
AVDD25D
AVSS25D
FIN
Ž
PWRDN
Ž
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
Ž
Ž
LDT
Ž
Ž
Ž
Ž
FOUT
Ž
Ž
PLL2026X
Ž
Ž
FILTER
Ž
P[0]
P[1]
P[2]
Ž
Ž
Ž
P[3]
P[4]
P[5]
Ž
Ž
Ž
S[0]
S[1]
Ž
Ž
AVDD25A
AVDD25A
AVBB25
Figure 2. Symbol Configuration
2 / 6
SEC ASIC
ANALOG
PLL2026X
25MHz~300MHz FSPLL
(Ta=25°C)
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
AVDD25D
AVDD25A
Value
Unit
Applicable pin
AVDD25A,AVSS25A,AVDD25D
AVSS25D,AVBB25
DC Supply Voltage
-0.3 to +3.0
V
P[5:0],M[7:0]S[1:0]
PWRDN,LDT
DC Input Voltage
VIN
Vss-0.25 to Vdd+0.25
-40 to 125
V
Storage Temperature
TSTG
°C
-
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged
permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect
reliability. Each condition value is applied with the other values kept within the following operating
conditions and function operation under any of these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
§Ú
3. 100pF capacitor is discharged through a 1.5 resistor (Human body model)
Recommended Operating Conditions
Characteristics
Symbol
AVDD25D
AVDD25A
FIN
Min
Typ
2.5
Max
Unit
V
Supply Voltage
2.375
2.625
Oscillator Frequency
14.318
680
MHz
pF
*External Loop Filter Capacitance-1
(Refer to Board Application Methodology)
C1
C2
*External Loop Filter Capacitance-2
39
8
pF
(Refer to Board Application Methodology)
*External Loop Filter Resistance
R1
Kilo-ohm
(Refer to Board Application Methodology)
Operating Temperature
NOTES
TOPR
0
70
°C
1. It is strongly recommended that all the supply pins (AVDD25A, AVDD25D) be powered from the same source
to avoid power latch-up.
Filter Pin Board Application Methodology
External Pin
PLL Core
§Ú
8
R1
C2
C1
39pF
680pF
Custom Chip
VSSA
Figure 3. Board Application of Filter pin
3 / 6
SEC ASIC
ANALOG
PLL2026X
25MHz~300MHz FSPLL
DC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
DC Supply Voltage
DC Input Voltage High
DC Input Voltage Low
Dynamic Current @300MHz
Power Down Current
AVDD25D/AVDD25A
2.2
1.6
2.5
3.0
V
V
VIH
VIL
IDD
IPD
0.6
3.1
V
mA
uA
100
AC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Input Frequency
Output Clock Frequency
Output Clock Duty Ratio
Input Clock Duty Ratio
Lock-in Time
FIN
FOUT
TOD
TID
8
14.318
40
300
60
MHz
MHz
%
25
40
30
50
70
%
TLT
100
us
Cycle to Cycle Jitter
TJCC
-100
+100
ps
Functional Description
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference
signal in frequency as well as in phase. In this application, it includes the following basic blocks.
. The voltage-controlled oscillator to generate the output frequency.
. The divider P to divide the reference frequency by p.
. The divider M to divide the VCO output frequency by m.
. The divider S to divide the VCO output frequency by s.
. The phase frequency detector to detect the phase difference between the reference frequency
and the output frequency (after division) and to control the charge pump voltage.
. The loop filter to filter out high frequency components in charge pump voltage and give
smooth and clean control to VCO.
The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL
can be locked onto the desired frequency.
Fout = ( m * Fin ) / ( p*s )
Fin = 14.318MHz,
Digital data format:
m=M+8 , p=P+2, s=2^S
Main Divider
Pre Divider
Post Scaler
M[7],M[6],M[5],M[4],M[3],M[2],M[1],M[0]
P[5],P[4],P[3],P[2],P[1],P[0]
S[0],S[1]
NOTES
. S[1] - S[0] : Output Frequency Scaler
. M[7] - M[0] : VCO Frequency Divider
. P[5] - P[0] : Reference Frequency Input Divider
SEC ASIC
ANALOG
4 / 6
PLL2026X
25MHz~300MHz FSPLL
DESIGN and CORE LAYOUT GUIDE
• Dedicated power pins, guard bars
• Neighboring circuitry pads
• Created white space between the PLL and all other circuits
• Don't place noisy, high frequency and high power cells near the PLL
• Closely placed Loop Filter components
• Analog signals should not be crossed by digital signals and should not run next
to digital signals. This will minimize the capacitive coupling between the two signals
• Power cuts are required to provide on-chip isolation
=> between dedicated PLL power/ground and all other power/ground
• Use proper low jitter refernce clock
• The external loop filter pin is placed between the analog power to avoid stray coupling
outside the chip and magnetic coupling via board wires
• Solid Group plane
• Use proper power/ground de-coupling
• Use good power and ground source on the board
• Use wide PCB traces for analog power/ground connections to the PLL core
• Separate the traces from the chip's power/ground supplies
FOUT
FILTER
AVDD25A
AVSS25A
FILTER
LDT
LD
Divider
P
Scaler
S
PFD
&CP
FIN
FIN
LF
VCO
FOUT
Glue
Logics
PWRDN
Divider
M
P[5:0]
M[7:0]
S[1:0]
AVDD25D
MUX
PLL Core
AVSS25D
AVBB25
*Divider Bus
*Optional Test Pins
Figure 4. Example of PLL Embeddd Methodology
5 / 6
SEC ASIC
ANALOG
PLL2026X
25MHz~300MHz FSPLL
PLL Specification
We appreciate your interest in our products. If you have further questions, please specify in
the attached form. Thank you very much.
Parameter
Min
Typ
Max
Unit
Remarks
Supply Voltage
Output frequency range
Input frequency range
Cycle to Cycle Jitter
Lock up time
Dynamic current
Stand by current
Output clock duty ratio
Long term jitter
Output slew rate
- Do you need XTAL driver buffer in PLL Core?
If you need it, what's the crystal frequency range? If not, What's the input frequency range?
- Do you need the lock detector?
- Do you need the I/O cell of SEC?
- Do you need the external pin for PLL test?
- What's the main frequency & frequency range?
- How many FSPLLs do you use in your system?
- What's output loading?
- Could you external/internal pin configurations as required?
Specially requested function list :
SEC ASIC
ANALOG
6 / 6
相关型号：
©2020 ICPDF网 联系我们和版权申明