PUMA68F32006M-15 [ETC]
EEPROM ; EEPROM\n
| 型号： | PUMA68F32006M-15 |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总23页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1M x 32 FLASH MODULE
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
A version 'A' with four independant write enables
(WE1-4) is available.
Description
The PUMA 68F32006 is a high density 32Mbit
CMOS 5V Only FLASH memory organised as
1M x 32 in a JEDEC 68 pin surface mount
PLCC, with read access times of 90, 120, and
150ns.
The output width is user configurable as 8 , 16
or 32 bits using four Chip Selects (CE1~4) for
optimum application flexibility.
Features
• Fast Access Times of 90/120/150 ns.
• Output Configurable as 32 / 16 / 8 bit wide.
• Commercial, Industrial, or Military (Restricted) grade.
• AutomaticWrite/ErasebyEmbeddedAlgorithm-endof
The module incorporates Embedded Algorithms
for Program and Erase with Sector architecture
(64K sector) and supports full chip erase.
The device also features hardware sector
protection, which disables both program and
erase operations in any of the 64 sectors on the
module.
Write/Erase indicated by DATA Polling and Toggle Bit.
• Flexible Sector Erase Architecture - 64K byte sector
size, with hardware protection of sector groups.
• Single Byte Program of 7µs (Typ.)
• Erase/WriteCycleEndurance100,000(Min.)-Evariant.
Block Diagram (see page 24 for 'A' version)
Pin Definition (see page 24 for 'A' version)
64 63 62 61
8 7 6 5 4 3 2 1 68 67 66 65
9
10
D1 11
D0
60
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
A0~A19
OE
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
12
13
14
15
16
17
D2
D3
D4
D5
D6
D7
WE
1M x 8
1M x 8
1M x 8
PUMA 68F32006
1M x 8
FLASH
FLASH
FLASH
FLASH
VIEW
FROM
ABOVE
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
GND 18
19
D9 20
D8
21
22
23
24
D10
D11
D12
D13
D14 25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D15
Pin Functions
D0-D31
WE
Vcc
A0-A19
CE1-4
OE
Address Input
Chip Enables
Output Enable
Ground
Data Inputs/Outputs
Write Enable (WE1-4 for 'A' version)
Power (+5V)
GND
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Absolute Maximum Ratings (1)
max
-2.0 to +7
-2.0 to +7
unit
V
V
Voltage on any pin w.r.t. Gnd
Supply Voltage(2)
Voltage on A9 w.r.t. Gnd (3)
Storage Temperature
-2.0 to +13.5 V
-65 to +125 °C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operationof the device at those or any other conditions above those indicated in the operational sections of this
specification
is not implied.
(2) Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V
During transitions voltage may overshoot by +/-2V for upto 20ns
(3) Minimum DC input voltage on A9 is -0.5V during voltage transitions, A9 may overshoot Vss to -2V for periods of up to
20ns, maximum DC input voltage in A9 is 12.5V which may overshoot to 14.0V for periods up to 20ns
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
min
4.5
2.0
-0.5
0
typ
5.0
max
5.5
VCC+0.5
VCC+0.8
70
unit
V
V
V
°C
VCC
VIH
VIL
TA
TAI
TAM
-
-
-
-
-
-40
-55
85
115
OC (-I suffix)
OC (-M suffix)
Parameter
I/P Leakage CurrentAddress, OE, WE ILI1
A9 Input Leakage Current ILI2
Symbol Test Condition
min
typ max Unit
VCC=VCC max, VIN=0V or VCC
VCC=VCC max, A9=12V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4 µA
200 µA
±1 µA
±4 µA
120 mA
62 mA
33 mA
Other Pins ILI3
ILO
VCC=VCC max, VIN=0V or VCC
VCC=VCC max, VOUT=0V or VCC
Output Leakage Current
VCC Operating Current
32 bit ICCO32 CE=VIL(1), OE=VIH, IOUT=0mA, f=6MHz
16 bit ICCO16 As above
8 bit ICCO8
As above
VCC Program/Erase Current 32 bit ICCP32 Programming in Progress
16 bit ICCP16 As above
-
-
-
-
-
-
240 mA
122 mA
63 mA
8 bit ICCP8
As above
(1)
Standby Supply Current
ISB1
VCC=VCC max, CE=VIH OE = VIH
VCC = 5.0V
-
-
-
-
-
-
4
12.5
0.45
-
mA
V
Autoselect / Sector Protect Voltage
Output Low Voltage
VID
11.5
VOL
IOL=12mA. VCC = VCC min.
IOH=-2.5mA. VCC = VCC min.
-
2.4
3.2
V
Output High Voltage
VOH1
VLKO
V
Low VCC Lock-Out Voltage
4.2
V
Notes (1) CE above are accessed through CE1-4. These inputs must be operated simultaneoulsy for 32 bit operation,
in pairs in 16 bit mode and singly for 8 bit mode.
2
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Capacitance (TA=25°C,f=1MHz)
Parameter
Symbol
Test Condition
typ
max
Unit
Input CapacitanceAddress, OE, WE CIN1
VIN=0V
VIN=0V
-
-
35
14
pF
pF
Other pins
CIN2
Output Capacitance
32 bit
COUT32
VOUT=0V
-
54
pF
Note: These parameters are calculated, not measured.
AC Test Conditions
Ω
166
* Input pulse levels : 0.0V to 3.0V
* Input rise and fall times : 5 ns
* Input and output timing reference levels : 1.5V
* VCC = 5V +/- 10%
I/O Pin
1.76V
30pF
* Module tested in 32 bit mode
3
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
90
min typ max Unit
Read Cycle Time
tRC
tACC
tCE
90
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Address to output delay
Chip enable to output
Output enable to output
-
90
90
40
20
-
-
tOE
-
Output enable to output High Z tDF
Output hold time from address tOH
CE or OE whichever occurs first
-
0
Parameter
Symbol
120
150
min
120
typ max min typ max Unit
Read Cycle Time
tRC
tACC
tCE
-
-
-
-
-
-
-
150
-
-
-
-
-
-
-
ns
Address to output delay
Chip enable to output
Output enable to output
-
-
120
120
50
30
-
-
-
150 ns
150 ns
tOE
-
-
55
35
-
ns
ns
ns
Output enable to output High Z tDF
Output hold time from address tOH
CE or OE whichever occurs first
-
-
0
0
4
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Write/Erase/Program
Parameter
Symbol
90
min
typ
max
unit
Write Cycle time (2)
Address Setup time
Address Hold time
Data Setup Time
tWC
tAS
90
0
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
tAH
45
45
0
-
-
tDS
-
-
Data hold Time
tDH
-
-
Output Enable Setup Time
Read Recover before Write
CE setup time
tOES
tGHWL
tCE
0
-
-
0
-
-
0
-
-
CE hold time
tCH
0
-
-
WE Pulse Width
tWP
45
20
-
-
-
WE Pulse Width High
Byte Programming operation
Sector Erase operation (1)
Vcc setup time (2)
tWPH
tWHWH1
tWHWH2
tVCS
-
-
8
1
-
-
-
15
-
50
Parameter
Symbol
120
typ
150
typ
min
max
min
max
unit
Write Cycle time (2)
Address Setup time
Address Hold time
Data Setup Time
tWC
tAS
120
0
-
-
-
-
150
0
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
tAH
50
50
0
-
-
50
50
0
-
-
tDS
-
-
-
-
Data hold Time
tDH
-
-
-
-
Output Enable Setup Time
Read Recover before Write
CE setup time
tOES
tGHWL
tCE
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
CE hold time
tCH
0
-
-
0
-
-
WE Pulse Width
tWP
50
20
-
-
-
50
20
-
-
-
WE Pulse Width High
Byte Programming operation
Sector Erase operation (1)
Vcc setup time (2)
tWPH
tWHWH1
tWHWH2
tVCS
-
-
-
-
8
1
-
-
8
1
-
-
-
15
-
-
15
-
50
50
Notes: (1) This does not include the preprogramming time.
(2) Not 100% tested.
5
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Write/Erase/Program Alternate CE controlled Writes
Parameter
Symbol
90
min
typ
max
unit
Write Cycle time (2)
Address Setup time
tWC
tAS
90
0
-
-
-
-
ns
ns
Address Hold time
Data Setup Time
tAH
tDS
45
45
0
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
us
Data hold Time
tDH
-
-
Output Enable Setup Time
Read Recover before Write
WE setup time
tOES
tGHEL
tWS
0
-
-
0
-
-
0
-
-
WE hold time
tWH
0
-
-
CE Pulse Width
tCP
45
20
-
-
-
CE Pulse Width High
Programming operation
Sector Erase operation (1)
Vcc setup time (2)
tCPH
tWHWH1
tWHWH2
tVCS
-
-
8
1
50
-
-
15
-
-
Parameter
Symbol
120
typ
150
typ
min
max
min
max
unit
Write Cycle time (2)
Address Setup time
tWC
tAS
120
0
-
-
-
-
150
0
-
-
-
-
ns
ns
Address Hold time
Data Setup Time
tAH
tDS
50
50
0
-
-
-
-
50
50
0
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
us
Data hold Time
tDH
-
-
-
-
Output Enable Setup Time
Read Recover before Write
WE setup time
tOES
tGHEL
tWS
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
WE hold time
tWH
0
-
-
0
-
-
CE Pulse Width
tCP
50
20
-
-
-
50
20
-
-
-
CE Pulse Width High
Programming operation
Sector Erase operation (1)
Vcc setup time (2)
tCPH
tWHWH1
tWHWH2
tVCS
-
-
-
-
8
1
50
-
8
1
50
-
-
15
-
-
15
-
-
-
Note: (1) Does not include pre-programming time.
(2) Not 100% tested.
6
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
AC Waveforms for Read Operation
tRC
Addresses Stable
tACC
Addresses
CE
tDF
tOE
OE
tOH
tCE
WE
High Z
High Z
Output Valid
Outputs
AC Waveforms Program
Data Polling
5555H
tWC
PA
PA
Address
CE
tAH
tAS
tRC
tGHWL
OE
t
tWHP
tWHWH1
WP
WE
tDF
tOE
tCS
tDH
DATA
A0H
PD
DOUT
DQ7
tDS
tCE
tOH
VCC
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the out put of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
7
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
A.C Waveforms - Alternate CE controlled Program operation timings
Data Polling
5555H
tWC
PA
PA
Address
tAH
tAS
tRC
WE
tGHEL
OE
t
tCHP
tWHWH1
CP
CE
t
DF
tOE
tWS
tDH
DATA
A0H
PD
DOUT
DQ7
tDS
tCE
tOH
V
CC
NOTES:
1. PA is address of memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
AC Waveforms for Data Polling During Embedded Algorithm Operations
t
CH
CE
tDF
tOE
OE
tOEH
tCE
WE
t
OH
*
HIGH Z
HIGH Z
DQ7=
Valid Data
DQ7
DQ7
tWHWH
1 or 2
DQ0-DQ6
= Invalid
DQ0-DQ7=
Vaild Data
DQ0-DQ6
t
OE
8
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
CE
WE
tOEH
OE
*
DATA
(DQ0-DQ7)
DQ0-DQ7
Valid
DQ6=
Stop Toggling
DQ6=Toggle
DQ6=Toggle
tOE
* DQ6 stops toggling ( the device has completed the embedded operations)
AC Waveforms Chip / Sector Erase
tAH
tAS
Address
CE
5555H
2AAAH
5555H
5555H
2AAAH
SA
tGHWL
OE
tWP
WE
tWPH
tDH
tCS
10H/30H
80H
AAH
55H
55H
AAH
Data
tDS
Vcc
tVCS
NOTES:
1. SA is the address for sector erase. Addresses = don't care for Chip Erase.
9
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
EMBEDDED PROGRAMMING ALGORITHM
Start
Write Program Command
Sequence
(see below)
Data Poll Device
Last
Address
?
No
Increment Address
Yes
Programming
Completed
Program Command Sequence (Address /Command)
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program data
10
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
EMBEDDED ERASE ALGORITHM
START
Write Erase Command Sequence
(See below)
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
Individual Sector/Mulitiple Sector
Chip Erase Command Sequence
(Address/Command):
Erase Command Sequence
(Address/Command):
5555H/AAH
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/AAH
5555H/10H
2AAAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
}
11
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
DATA POLLING ALGORITHM
START
Read Byte
(DQ0-DQ7)
Addr =VA
YES
DQ7 = Data ?
NO
NO
DQ5 = 1 ?
YES
Read Byte
(DQ0-DQ7)
Addr =VA
YES
DQ7 = Data ?
PASS
NO
FAIL
NOTE:
1. DQ7 is rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
2. VA = Byte address for programming.
= Any of the sector addresses within the sector being erased during sector erase operation
= Valid address equals any Non-protected sector group address during chip erase.
TOGGLE BIT ALGORITHM
START
Read Byte
(DQ0-DQ7)
Addr=Don't Care
NO
DQ6=Toggle ?
YES
NO
DQ5 = 1 ?
YES
Read Byte
(DQ0-DQ7)
Addr=Don't Care
NO
DQ6=Toggle ?
PASS
YES
FAIL
NOTES:
1. DQ6 is rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time as DQ5 changing to "1".
12
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
DEVICE OPERATION
The following description deals with the device operating in 8 bit mode accessed through CE1,
however status flag definitions shown apply equally to the corresponding flag for each device in the module.
Read Mode
The device has two control functions which must be satisfied in order to obtain data at the outputs
CE1-4 is the power control and should be used for device selection
OE is the output control and should be used to gate data to the output pins if the device is selected.
Standby Mode
Two standby modes are available :
CMOS standby : CE1-4 held at Vcc +/- 0.3V
TTL standby : CE1-4 held at VIH
In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is
deselected during erasure or programming the device will draw active current until the operation is completed.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify the die manu-
facturer and type. This mode is intended for use by programming equipment. This mode is functional over the
full military temperature range. The autoselect codes for the first device are as follows :
Type
A17-A19
A6
A1
A0
Code
(HEX)
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacture
Code
X
VIL
VIL
VIL
01H
A4H
01H*
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
1
X
VIL
VIL
VIL
VIH
VIH
VIL
Device Code
Sector Group Sector Group
Protection Address
* Outputs 01H at protected sector address
To activate this mode the programming equipment must force VID on address A9 . Two identifier bytes may
then be sequenced from each die device outputs by toggling A0 from VIL to VIH. All addresses are dont care
apart from A0, A1, A6. All identifiers for manufacturer and device will exhibit odd parity with D7 defined as the
parity bit. In order to read the proper device codes when executing the autoselect A1 must be VIL.
Write
Device erasure and programming are accomplished via the command register. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The
register is a latch used to store the commands along with the address and data information required to execute
the command. The command register is written by bringing WE/WE1-4 to VIL while CE1-4 is at VIL and
OE is at VIH.Addresses are latched on the falling edge of WE/WE1-4 while data is latched on the rising edge.
13
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
The following table defines these register command sequences.
Bus
Write
Cycles
Req'd
Fourth Bus
Read/Write
Cycle
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Command
Sequence
Read/Reset
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
F0H
AAH
1
3
XXXXH
5555H
Read/Reset
Read/Reset
Autoselect
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
55H
55H
55H
55H
55H
5555H
5555H
5555H
5555H
5555H
F0H
90H
A0H
80H
80H
RA
RD
00H/
01H
3
4
5555H
5555H
5555H
5555H
AAH
AAH
AAH
AAH
01H/D5H
PD
Byte Program
Chip Erase
PA
2AAAH
2AAAH
5555H
5555H
AAH
AAH
55H
55H
5555H
SA
10H
30H
6
6
Sector Erase
Erase Suspend
Erase Resume
1
1
XXXXH B0H
30H
XXXXH
NOTES:
1. Address bit A15,A14,A13, A12, A11=X=Don't care.
2. RA=Address of the memory location to be read.
PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE pulse .
SA=Address of the sector to be erased. The combination of A19, A18, A17 and A16 will uniquely select any
sector.
3. RD=Data read from location RA during read operation.
PD=Data to be programmed at location PA. Data is latched on the falling edge of WE
Read / Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters.
14
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Sector Group Protection
The device features hardware sector group protection. This feature will disable both program and erase
operations in any combination of sector groups of memory. The sector protect feature is enabled using pro-
gramming equipment at the users site. The device is shipped with all sector groups unprotected.
It is also possible to determine if a sector is protected in the system by writing the autoselect command.
Performing a read operation at XX02H , where the higher order addresses (A17, A18, A19) is the desired
sector group address, will produce 01H data at DQ0 for a protected sector group.
Sector Address Table
A17
0
A19
0
A18
0
A16
0
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
SA0
SA1
SA2
SA3
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
SA4
0
1
0
SA5
1
SA6
0
1
1
0
0
1
1
1
SA7
070000h-07FFFFh
1
0
0
SA8
0
080000h-08FFFFh
090000h-09FFFFh
1
0
0
1
SA9
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
SA10
SA11
SA12
SA13
SA14
SA15
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0
1
0
1
0
1
0F0000h-0FFFFFh
Sector Group Address Table
Sectors
A17
0
A19
A18
0
0
0
0
1
1
1
1
0
0
1
1
SA0-SA1
SA2-SA3
SA4-SA5
SA6-SA7
SA8-SA9
SA10-SA11
SA12-SA13
SGA0
SGA1
SGA2
SGA3
1
0
1
0
0
0
1
1
SGA4
SGA5
SGA6
SGA7
1
0
SA14-SA15
1
15
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target systems. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally a desired system design practice.
The device contains an autoselect operation to supplement traditional PROM programming methodology. The
operation is initiated by writing the autoselect command sequence into the command register. Following the
command write, a read cycle from address XX00H retrieves the manufacture code of 01H. A read cycle from
address XX01H returns the device code D5H. Further, the write protect status of sectors can be read in this
mode. Scanning the sector group addresses (A17, A18, A19) while (A6,A1,A0)=(0, 1, 0) will produce a logical
'1' at device output DQ0 for a protected sector group.
To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycle. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of WE/WE1-4 or CE1-4, whichever happens later, while the data are latched on the
rising edge of WE/WE1-4 or CE1-4 whichever happens first. The rising edge of WE/WE1-4 or CE1-4 begins
programming. Upon executing the Embedded Program Algorithm Command sequence the system is not
required to provide further controls or timings. The device will automatically provide adequate internally gener-
ated program pulses and verify the programmed cell margin. The automatic programming operation is com-
pleted when the data on D7 is equivalent to data written to this bit (see written Operations Status) at which time
the device returns to read mode. Data Polling must be performed at the memory location which is being
programmed.
Programming is allowed in any address sequence and across sector boundaries.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings during
these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.
16
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing
the "Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The
sector address (any address location within the desired sector) is latched on the falling edge of WE, while the
command (30H) is latched on the rising edge of WE. A time-out of 50us from the rising edge of the last sector
erase command will initiate the sector erase command(s).
Multiple sectors may be erased sequentially by writing the six bus cycle operations as desribed above. This
sequence is followed with writes of the sector erase command to addresses in other sectors desired to be
sequentially erased. A time-out of 50us from the rising edge of the WE pulse for the last sector erase com-
mand will initiate the sector erase. If another sector erase command is wriiten within the 50us time-out window
the timer is reset. Any command other than sector erase within the time-out window will reset the device to the
read mode, ignoring the previous command string (refer to Write Operation Status section for Sector Erase
Timer operation). Loading the sector erase buffer may be done in any sequence and with any number of
sectors (0 to 7).
Sector erase doesn't require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors
the remaining unselected sectors are not affected. The system is not required to provide any controls or
timings during these operations.
The automatic sector erase begins after the 50us time-out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on D7 is "1" ( see Written Operation Status
Section) at which time the device returns to read mode. Data polling must be preformed at an address within
any of the sectors being erased.
Erase Suspend
Erase suspend allows the user to interrupt a sector erase operation and then perform data reads or programs
to a sector not being erased.
This command is only applicable during the sector erase operation which includes the time-out period for
sector erase. Writing the erase suspend command during the sector erase time-out results in immediate
termination of the time-out period & suspension of the erase operation. Writing the erase resume command
resumes the erase operation.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. After
entering the erase-suspend-read mode, the user can program the device by writing the appropriate command
sequence for Byte program. The end of the erase-suspend program operation is detected by data polling, or
by the toggle bit. Note that DQ7 must be read from the byte program address.
To resume the sector erase operation, the resume command (30H) should be written. Any further writes of the
resume command at this point will be ignored.
17
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Operating Modes
The following modes are used to control the device.
OPERATION
Auto-Select Manufacturer Code
Auto Select Device Code
Read(1)
CE
L
OE
L
WE
A0
A1
A6
A9
I /O
Code
Code
DOUT
H
L
L
L
VID
VID
L
L
H
H
A0
X
L
L
L
L
X
A1
X
A6
X
A9
Standby
H
L
X
H
H
L
X
H
L
X
High Z
High Z
Din
Output Disable
X
X
X
X
Write
L
A0
A1
A6
A9
VID
Verify Sector Group Protect
L
H
L
H
L
Code
1) L=VIL, H=VIH, X=Don't Care
NOTE:
1) WE can be VIL if OE is VIL , OE at VIH initiates write cycle.
WRITE OPERATIONS STATUS
Status
DQ7
DQ6 DQ5
DQ3 DQ2
Toggle
Toggle
0
1
0
DQ7
Byte Program in Embedded Program Algorithm
Embedded Erase Algorithm
0
1
Toggle
1
0
Toggle
Erase Suspend Read
1
0
Data
0
0
(Erase Suspend Sector)
(Note 1)
In Progress
Erase Suspend Read
Erase Suspended Mode
Data
DQ7
Data
Data
0
Data
(Non-Erase Suspend Sector)
Toggle
Erase Suspend Program
1
(Non-Erase Suspend Sector)
(Note 2)
(Note 3)
Toggle
Toggle
0
1
1
DQ7
0
1
Byte Program in Embedded Program Algorithm
Program/Erase in Embedded Erase Algorithm
1
1
Exceeded
N/A
Time Limits
Erase Suspend Program
(Non-Erase Suspend Sector)
DQ7
N/A
Toggle
1
Erase Suspended Mode
Notes:
1. Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.
2. Performing successive read operations from any address will cause DQ6 to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic '1' at the DQ2 bit.
However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
18
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
D7 Data Polling
The device features Data Polling as a method to indicate to the host system that the Embedded Algorithms
are in progress or completed.
During the Embedded Programming Algorithm, an attempt to read the device will produce the complement of
the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read the
device will produce the true data last written to D7.
During the Embedded Erase Algorithm, D7will be "0" until the erase operation is completed. Upon completion
data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, Data Polling is valid after the last rising edge of the sector erase WE
pulse.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, Erase-Suspend-Program, or sector erase time-out.
D6
Toggle Bit
The device also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device
will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is
completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the
Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For chip erase,
the Toggle bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector
Erase, the toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active
during the sector time-out.
D5 Exceeding Time Limits
D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will
produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only
operating function of the device under this condition. The CE circuit will partially power down the device under
these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions .
The D5 failure condition may also appear if the user tries to program a non blank location without erasing. In
this case the device locks out and never completes the embedded algorithm operation. Hence the system
never reads a valid data on D7 and D6 never stops toggling. Once the device has exceeded timing limits, the
D5 bit will indicate '1'
D3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may
be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase opera-
tion is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional
sector erase commands. To insure the command has been accepted, the software should check the status of
D3 prior to and following each subsequent sector erase command. If D3 were high on the second status
check, the command may not have been accepted.
19
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up
and power down transitions or system noise.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for
VCC<VLKO . If VCC<VLKO, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition the device will reset to read mode. Subsequent writes will be ignored until the VCC level is
greater than VLKO. It is usually correct to prevent unintentional writes when VCC>VLKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CE, WE will not initiate a write cycle
Logical Inhibit
Writing is inhibited by holding any one of OE=VIL, CE=VIH or WE=VIH. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
Power Up Write Inhibit
Power-up of the device with WE=CE=VIL and OE=VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Protect
Sectors of the device may be hardware protected at the users factory. The protection circuitry will disable both
program and erase functions for the protected sector(s). Requests to program or erase a protected sector will
be ignored by the device.
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Min
Typ
Max
Unit
Comments
Sector Erase Time
-
1
15
sec
Excludes 00H programming
prior to erasure.
(Note 1)
Byte Programming Time
Chip Programming Time
-
-
7
1000
50
us
Excludes System-level overhead.
(Note 1)
7.2
sec
Excludes system-level overhead.
(Note 1)
16
(Note 1)
Chip Erase Time
-
240
sec
Exclude 00H programming
prior to erase
Notes: (1) 25OC, 5V VCC, 100,000 cycles.
20
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Version 'A' Pin Definition
Version 'A' Block Diagram
64 63 62 61
8 7 6 5 4 3 2 1 68 67 66 65
9
A0~A19
10
D1 11
D0
60
D16
OE
59 D17
WE4
WE3
WE2
WE1
12
13
14
15
16
17
D2
D3
D4
D5
D6
D7
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
PUMA 68F32006A
1M x 8
1M x 8
1M x 8
FLASH
1M x 8
VIEW
FROM
ABOVE
FLASH
FLASH
FLASH
GND 18
D8 19
D9 20
D10 21
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
22
23
24
D11
D12
D13
D14 25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D15
21
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
Package Information
Dimensions in mm(inches)
Plastic 68 Pin JEDEC Surface mount PLCC
25.27 (0.995) sq.
5.08
(0.200) max
0.10 (0.004)
25.02 (0.985) sq.
1.27
(0.050) typ.
0.46
(0.018) typ.
0.90 (0.035) typ.
Ordering Information
PUMA 68F32006AM-90E
Speed
90 = 90 ns
12 = 120 ns
15 = 150 ns
Temperature range Blank = Commercial Temperature
I = Industrial Temperature
M = Military Temperature (Restricted)
Special Features
Organisation
Blank = Single WE
A = WE1-4
32006 = 1M x 32, user configurable
as 2M x 16 and 4M x 8
Memory Type
Package
F = FLASH
PUMA 68 = 68 pin "J" Leaded PLCC
NOTE: The E variant is designated to parts with extended Erase/Write Cycle Endurance (100,000 Min.). If not
specified when ordered only a Erase/Write Cycle Endurance of 10,000 Minimum can be
guaranteed.
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for aparticular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
ISSUE HISTORY
PUMA 68F32006-90/12/15
Issue 4.1 DCN3964 First issue based on AMD29F080.
Issue 4.2
Restricted military Operating temperature from 125OC to 115OC
23
相关型号：
©2020 ICPDF网 联系我们和版权申明