PW-82520N0-240 [ETC]

Industrial Control IC ; 工业控制IC\n


型号：	PW-82520N0-240
厂家：	ETC
描述：	Industrial Control IC 工业控制IC\n
文件：	总16页 (文件大小：193K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Make sure the next

Card you purchase

has...

PW-82520/21N

3-PHASE DC MOTOR

TORQUE CONTROLLER

FEATURES

• Self-Contained 3-Phase Motor

Controller

• Operates as Current or Voltage

Controller

• 1, 3 or 10 Amp Output Current

• 1.5% Linearity

• 3% Current Regulating Accuracy

• User-Programmable Compensation

• 10 KHz - 100 KHz PWM Frequency

• Complementary Four-Quadrant

Operation

• Holding Torque through Zero

Current

DESCRIPTION

• Cycle-by-Cycle Current Limit

The PW-82520N (100Vdc) and PW-82521N (200Vdc) are high per-

formance current regulating torque loop controllers designed to accu-

rately regulate the current in the motor windings of 3-phase brushless

DC and brush DC motors.

• Optional Radiation Tolerance to

100Krads (see PW-82520R data

sheet)

The PW-82520/21N is a completely self-contained motor controller

that converts an analog input command signal into motor current and

uses the signals from Hall-effect sensors in the motor to commutate

the current in the motor windings. The motor current is internally

sensed and processed into an analog signal. The current signal is

summed together with the command signal to produce an error sig-

nal that controls the pulse width modulation (PWM) duty cycle of the

output, thus controlling the motor current. The PW-82520/21N per-

formance can be tuned by utilizing the internal error amplifier and the

external Proportional/Integral (PI) regulator network components to

match motor characteristics.

APPLICATIONS

The PW-82520/21N is ideal for applications requiring current regula-

tion and/or holding torque at zero input command. System applica-

tions include: pumps, actuators, antenna position, environmental con-

trol, reaction/momentum wheel systems using brushless and brush

motors, flight surface control on aircrafts for horizontal stabilizers and

flaps, missile fin control, fuel and Hydraulic pumps, radar, and counter

measure systems.

Packaged in a small DIP-style hybrid package, the PW-82520/21N is

well suited for applications with limited printed circuit board area.

FOR MORE INFORMATION CONTACT:

Technical Support:

1-800-DDC-5757 ext. 7677 or 7381

Data Device Corporation

105 Wilbur Place

Bohemia, New York 11716

631-567-5600 Fax: 631-567-7358

www.ddc-web.com

2001 Data Device Corporation

5.0V

10K 10K 10K

100

HALL A

TACH OUT

DIR OUT

HALL B

HALL C

COMMUTATION

LOGIC

TACH

CIRCUIT

COMMAND OUT

50K

COMMAND IN -

100

VBUS+ A

PHASE A

COMMAND IN

DRIVE

PHASE A

COMMAND

BUFFER

50K

COMMAND GND

SYNC IN

+15V

VBUS+ B

PHASE B

VDR

VCC

+5V

+5V RTN

DRIVE

PWM

LOGIC

CIRCUITRY

PHASE B

VCC RTN

VDD

SUPPLY GND

VEE

VBUS+ C

PHASE C

DRIVE

5.0V

CASE

CASE GND

ENABLE

PHASE C

10.0K

PWM IN

PWM OUT

ERROR AMP OUT

ERROR AMP IN

470pF

RS+

100

Rsense

VBUS–

CURRENT

AMP

ERROR

AMPLIFIER

CURRENT

MONITOR OUT

FIGURE 1. PW-82520/21N BLOCK DIAGRAM

TABLE 1. PW-82520/21N ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED)

PARAMETER

SYMBOL

VALUE

UNITS

BUS VOLTAGE PW-82520N / (PW-82521N)

+15V SUPPLY

VBUS+ A,B,C

100.0 (200.0)

+17.5

Vdc

VDR

VDD

VCC

+5V TO +15V

+17.5

+5V SUPPLY

+5.5

-5V TO -15V

VEE

-17.5

VBUS- TO GND

Voltage Differential

VGNDDIF

0-VDD +1.0

Vdc

CONTINUOUS OUTPUT CURRENT

PW-82520N1

PW-82520N3

IOC

PW-82520N0 / PW-82521N0

PEAK OUTPUT CURRENT (PULSED t = 50µS)

PW-82520N1

PW-82520N3

IOP

PW-82520N0 / PW-82521N0

VCMD +

VCMD -

COMMAND INPUT +

COMMAND INPUT -

±15.0

Vdc

LOGIC INPUTS:

ENABLE, SYNC IN, HA, HB, HC, ERROR AMP IN, PWM IN

VIH

VOH

7.0

Vdc

TACH OUT / DIR OUT

IOL

TABLE 2. PW-82520/21N SPECIFICATIONS

(UNLESS OTHERWISE SPECIFIED, VBUS = 28VDC, VDR = +15V, VCC = +5V, VDD = +5V, VEE = -5V,TC = 25°C, LL = 500 µH,

PWM IN = PWM OUT AT ½ FREE RUNNING FREQUENCY)

PARAMETER

OUTPUT (PW-82520N1)

Output Current Continuous

Output Current Pulsed

Current Limit

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

IOC

IOP

ICL

IOFFSET

RON

1.8

+20

0.055

0.075

0.080

1.5

Pulse Width ≤ 50µsec

1.3

-20

1.5

Ω

Current Offset

Output On-Resistance

FIGURE 7, VCMD = 0V

+25°C

+85°C

ID = 1A

Ω

Output Conductor Resistance

Diode Forward Voltage Drop

OUTPUT (PW-82520N3)

Output Current Continuous

Output Current Pulsed

Current Limit

Current Offset

Output On-Resistance

IOC

IOP

ICL

IOFFSET

RON

4.5

+20

0.055

0.075

0.080

1.8

Pulse Width ≤ 50µsec

3.4

-20

FIGURE 7, VCMD = 0V

Ω

+25°C

+85°C

ID = 3A

Ω

Output Conductor Resistance

Diode Forward Voltage Drop

Ω

OUTPUT (PW-82520N0)

Output Current Continuous

Output Current Pulsed

Current Limit

Current Offset

Output On-Resistance

IOC

IOP

ICL

IOFFSET

RON

Pulse Width ≤ 50µsec

12.0

-100

14.0

15.4

+100

0.055

0.075

0.080

1.9

FIGURE 7, VCMD = 0V

+25°C

Ω

+85°C

ID = 10A

Ω

Output Conductor Resistance

Diode Forward Voltage Drop

Ω

OUTPUT PW-82521N0

Output Current Continuous

Output Current Pulsed

Current Limit

Current Offset

Output On-Resistance

IOC

IOP

ICL

IOFFSET

RON

Ω

Pulse Width ≤ 50µsec

12.0

-0.3

14.0

15.4

+0.3

0.100

0.140

0.080

1.9

FIGURE 7, VCMD = 0V

+25°C

+85°C

ID = 10A

Output Conductor Resistance

Diode Forward Voltage Drop

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

TABLE 2. PW-82520/21N SPECIFICATIONS (CONTINUED)

(UNLESS OTHERWISE SPECIFIED, VBUS = 28VDC, VDR = +15V, VCC = +5V, VDD = +5V, VEE = -5V,TC = 25°C, LL = 500 µH,

PWM IN = PWM OUT AT ½ FREE RUNNING FREQUENCY)

PARAMETER

PROPAGATION DELAY

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Td (on)

From 1.5V on ENABLE to

90% of VBUS

µs

Td (off)

From 3.5V on ENABLE to

10% of VBUS

µs

SWITCHING CHARACTERISTICS

PW-82520N1

Upper Drive

Turn-on Rise Time

Turn-off Fall Time

Lower Drive

Turn-on Rise Time

Turn-off Fall Time

PW-82520N3

Rise Time =

90% to 10% of VBUS

Fall Time =

10% to 90% of VBUS

IO = 1A

Upper Drive

Rise Time =

90% to 10% of VBUS

Fall Time =

10% to 90% of VBUS

IO = 3A

Turn-on Rise Time

Turn-off Fall Time

Lower Drive

Turn-on Rise Time

Turn-off Fall Time

PW-82520N0/21N0

Upper Drive

Turn-on Rise Time

Turn-off Fall Time

Lower Drive

Turn-on Rise Time

Turn-off Fall Time

150

160

130

Rise Time =

90% to 10% of VBUS

Fall Time =

10% to 90% of VBUS

IO = 10A

200

CURRENT MONITOR AMP

(ALL MODELS)

Current Monitor Offset

Output Current

IoC = 0A

-10

+10

mVdc

Ω

Output Resistance

ROUT

CURRENT MONITOR AMP

(PW-82520N1)

Current Monitor Gain

V/A

CURRENT MONITOR AMP

(PW-82520N3)

Current Monitor Gain

1.33

0.40

CURRENT MONITOR AMP

(PW-82520/82521N0)

Current Monitor Gain

CURRENT COMMAND

Transconductance Ratio

PW-82520N1

PW-82520N3

PW-82520/82521N0

Non-Linearity

FIGURE 7

Io = 1A

Io = 3A

Io = 10A

0.24

0.73

2.37

-1.5

0.25

0.75

2.50

0.26

0.76

2.63

+1.5

A/V

% FSR

Temperature Coefficient of G

PW-82520N1/N3

PW-82520/82521N0

0.038

0.05

%FSR/°C

VBUS+ SUPPLY

Nominal Operating Voltage

PW-82520N1/N3/N0

PW-82521N0

VNOM

140

Vdc

+15V SUPPLY

Voltage

Current

VDR

IDR

+13.5

+15.0

100

+16.5

Vdc

µA

ENABLE = high

IDR

ENABLE = low

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

TABLE 2. PW-82520/21N SPECIFICATIONS (CONTINUED)

(UNLESS OTHERWISE SPECIFIED, VBUS = 28VDC, VDR = +15V, VCC = +5V, VDD = +5V, VEE = -5V,TC = 25°C, LL = 500 µH,

PWM IN = PWM OUT AT ½ FREE RUNNING FREQUENCY)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

+5V SUPPLY

Voltage

Current

VCC

ICC

+4.5

+5.0

+5.5

Vdc

+5V TO +15V SUPPLY

Voltage

Current

VDD

IDD

+15V

+4.5

+16.5

Vdc

-5V TO -15V SUPPLY

Voltage

Current

VEE

IEE

-15V

-16.5

-4.5

Vdc

SYNC IN

Low

High

Duty Cycle

VIL

VIH

D.C.

1.5

Vdc

3.5

SYNC range as % of free-run frequency

100

120

PWM IN

+ Peak Voltage

- Peak Voltage

Frequency

Linearity Error

Duty Cycle

Vp+

Vp-

f_PWM

LIN

Vcc = 4.5 - 5.5V

2.3

-2.7

-2

2.5

-2.5

2.7

-2.3

110

KHz

D.C.

PWM OUT

Free Run Frequency

PW-82520N1/N3

PW-82520/82521N0

Stability, Temperature

f_PWM

47.5

100

0.5

105

52.5

2.0

KHz

Full Temp Range

HALL SIGNALS (HA, HB, HC)

Logic 0

Logic 1

VIL

VIH

1.5

Vdc

3.5

ENABLE

Enabled

Disabled

VIL

VIH

1.5

1.2

Vdc

TACH OUT/ DIR OUT

Current Sink

Open Collector

@ 1mA

VOL

0.7

Vdc

ISOLATION

Case to Ground

MΩ

500 Vdc HIPOT

-4

COMMAND IN+/-

Differential Input

Input Offset

VCMD

800

Vdc

µV

Input Offset Drift

µV/°C

COMMAND OUT

Internal Voltage Clamp

Slew Rate

VCLAMP

-5

Vdc

V/µs

µs to 0.1%

1.4

Settling Time

VO = 0.2 to 4.5V

THERMAL (ALL MODELS)

Junction Temperature

Case Operating Temperature

Case Storage Temperature

TCS

+150

+125

+150

°C

-55

-65

THERMAL (PW-82520N1)

Thermal Resistance

Junction-Case

θj-c

θc-a

°C/W

Case-Air

THERMAL (PW-82520N3)

Thermal Resistance

Junction-Case

θj-c

θc-a

°C/W

Case-Air

THERMAL (PW-82520N0/82521N0)

Thermal Resistance

Junction-Case

θj-c

θc-a

5.5

°C/W

Case-Air

WEIGHT

N0, N1, N3

1.7 (48)

oz (g)

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

INTRODUCTION

The complementary drive design produces a 50% PWM duty

cycle in response to a zero current command. During a zero cur-

rent command the benefit of a complementary 4 quadrant drive

over a standard 4 quadrant is as follows:

The PW-82520/21N is a 3-phase high performance current con-

trol (torque loop) motor controller hybrid, which provides true

four-quadrant control through zero current (Refer to FIGURE 1.

PW-82520/21N Block Diagram). Its high Pulse Width Modulation

(PWM) switching frequency makes it suitable for operation with

low inductance motors. The PW-82520/21N hybrids can accept

single-ended or differential mode command signals. The current

gain can be easily programmed to match the end user system

requirements. The addition of an externally wired compensation

network provides the user with optimum control of a wide range

of loads.

COMPLEMENTARY (FIGURES 2, 3A)

Complementary Drives produce a bi-directional holding torque

by driving a balanced bi-polar current into the motor that has an

average value of zero.

During the first quarter of the PWM cycle (starting at time zero

on FIGURE 3A) the MOSFET's, PHASE A UPPER (UA) and

PHASE B LOWER (LB) (FIGURE 2), are turned on. This allows

current flow from phase A to phase B to increase to +Imax.

The PW-82520/21N uses single point current sense technology

with an internal non-inductive hybrid sense resistor (Rsense),

which yields a highly linear current output over the full -55°C to

+125°C military temperature range. The output current non-lin-

earity is less than 1.5% and the total error due to all the factors

such as offset, initial component accuracy, etc., is maintained

well below 3% of the full-scale rated output current.

During the second quarter of the PWM cycle, the first pair of

transistors, UA and LB are turned off and a second pair PHASE

A LOWER (LA) & PHASE B UPPER (UB) (FIGURE 2) are turned

on. This allows the current in phase A & B from the previous

quarter cycle to decrease from Imax to zero. The average cur-

rent during the first two-quarter cycles is positive.

The Hall sensor interface for current commutation has built-in

decoder logic that ignores illegal codes and ensures that there is

no cross conduction. The Hall sensor inputs are internally pulled

up to +5V and they can be driven from open-collector outputs.

During the third quarter of the PWM cycle, the second pair of

switches UB & LA remain on allowing current to flow, in the neg-

ative direction, from phase B to phase A and increase to –Imax

as shown in FIGURE 3A.

The PWM frequency can be programmed externally by adding a

capacitor from PWM OUT to PWM GND. Multiple PW-82520N's

can be synchronized in two ways: 1) by using one device as a

master and connecting its PWM OUT pin to the PWM IN of all

the other slave devices, or 2) by applying a master SYNC pulse

from an external source to the PWM IN pins on all devices to be

synchronized.

During the fourth quarter of the PWM cycle, the first pair of

switches UA & LB are turned on while the second pair of switch-

es UB & LA are turned off, to allow the current in the inductor to

decrease to zero.

The average current in the phases for the third and fourth quar-

ter cycles is negative.

The ENABLE input signal provides quick start and shutdown of

the internal PWM. In addition, built-in under-voltage fault protec-

tion turns off the output in case of improper power supply voltages.

The hybrid features dual current limiting functions. The input

command amplifier output is limited to ±5V, limiting the motor

current under normal operation. In addition, there is a cycle-by-

cycle current limit which kicks in to protect the hybrid as well as

the load (see TABLE 2 for ICL limits).

The positive current (phase A to B) in the first two-quarter cycles

produces a torque in one direction and the negative current

(phase B to A) in the third and fourth quarter cycles produces a

torque in the opposite direction. The average of the two oppos-

ing torques results in a net zero or holding torque.

VBUS

BASIC OPERATION AND ADVANTAGES

PHASE A

UPPER

PHASE B

UPPER

OFF

The PW-82520/21N uses a complementary four-quadrant drive

technique to control current in the load. The complementary

drive has the following advantages over standard drives:

PHASE A

PHASE B

PHASE C

PHASE A

LOWER

PHASE B

LOWER

OFF

1. Holding torque in the motor at zero commanded current

2. Linear current control through zero

3. No deadband at zero

Rsense

FIGURE 2. COMPLEMENTARY 4-QUADRANT DRIVE

FIRST HALF OF PWM CYCLE

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

OFF

Time (half phase)

Time (quarter phase)

Drive Switches and Phase Current vs. Time

FIGURE 3B. STANDARD 4-QUADRANT DRIVE

PWM CYCLE

FIGURE 3A. COMPLEMENTARY 4-QUADRANT DRIVE

PWM CYCLE

NON-COMPLEMENTARY (FIGURES 2, 3B)

quadrant drive. The PW-82520N use of average current mode

control simplifies the control loop by eliminating the need for

slope compensation and by eliminating the pole created by the

motor inductance. Slope compensation and the pole created by

the motor inductance are two limitations normally associated

with implementing standard 4 quadrant current mode controls.

Non-Complementary Drives produce a unidirectional torque by

applying a unipolar current into the motor that has an average

positive value as shown in FIGURE 3B.

During the first half of the PWM cycle the MOSFET's, Phase A

upper and Phase B lower, are turned on to provide current into

the phases.

FUNCTIONAL AND PIN DESCRIPTIONS

During the second half of the PWM cycle the drive is in dead

time, all transistors are turned off, the motor current continues to

flow in the same direction through the device diodes, until it

decays to zero.

VBUS+A, VBUS+B, VBUS+C

The VBUS+ supply is the power source for the motor phases. For

the PW-82520 (PW-82521) series device, the normal operating

voltage is 28Vdc (100Vdc) and may vary from +18 (+36) to

+70Vdc (+140Vdc) with respect to VBUS-. The power-stage

MOSFETs in the hybrid have an absolute maximum VBUS+ sup-

ply voltage rating of 100V (200V).The user must supply sufficient

external capacitance or circuitry to prevent the bus supply from

exceeding the maximum recommended voltages at the hybrid

power terminals under any condition.

Current flowing in to and out of the phases produces a net torque

in one direction.

MAJOR ADVANTAGES

The advantage of a complementary 4-quadrant drive over a

standard 4-quadrant drive is that it provides holding torque dur-

ing a zero current command. The motor current at 50% duty

cycle is simply the magnetizing current of the motor winding.

Using the complementary 4-quadrant technique allows the motor

direction to be defined by the duty cycle.

POWER-ON SEQUENCE (IMPORTANT!)

The VBUS+ should be applied at least 50ms after VDD and VEE

to allow the internal analog circuitry to stabilize. If this is not pos-

sible, the hybrid must be powered up in the "disabled" mode.

Relative to a given switch pair, i.e. Phase A upper and Phase B

lower, a duty cycle greater than 50% will result in a clockwise

rotation whereas a duty cycle less than 50% will result in a

counter clockwise rotation. Therefore, with the use of average

current mode control, direction can be controlled without the use

of a direction bit and the current can be controlled through zero

in a very precise and linear fashion.

VBUS-

This is the high current ground return for VBUS+.This point must

be closely connected to SUPPLY GND for proper operation of

the current loop.

VCC (+5V SUPPLY) AND VCC RTN

These inputs are used to power the digital circuitry of the hybrid.

The PW-82520N contains all the circuitry required to close an

average current mode control loop around a complementary 4-

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

VDR (+15V SUPPLY)

“1” (or HIGH ) is defined by an input greater than 3.5Vdc or an

open circuit to the controller; Logic “0”(or LOW) is defined as any

Hall voltage input less than 1.5Vdc. Internal to the PW-

82520/21N are 10K pull-up resistors tied to +5Vdc on each Hall

input.

This input is used to power the gate driver circuitry for the output

MOSFETs. There is no power consumption from VDR when the

hybrid is disabled.

VDD (+5V TO +15V SUPPLY), VEE (-5V TO -15V SUPPLY)

These inputs can vary from ±5V to ±15V as long as they are

symmetrical. VDD and VEE are used to power the small signal

analog circuitry of the hybrid. Please note that using ±5V supply

will reduce the quiescent power consumption by approximately

60% when compared to ±15V operation.

The PW-82520/21N will alternately operate with Hall phasing of

60° electrical spacing. If 60° commutation is used, then the out-

put of HC must be inverted as shown in FIGURES 4 and 5.

FIGURE 4 illustrates the Hall sensor outputs along with the cor-

responding back emf voltage they are in phase with.

SUPPLY GND

HALL INPUT SIGNAL CONDITIONING

This pin is the return for the VDR, VEE, VDD supplies. The phase

current sensing technique of the PW-82520N/21N requires that

VBUS- and SUPPLY GND (see FIGURES 6 and 7) be connect-

ed together externally (see VBUS- supply).

When the motor is located more than two feet away from the PW-

82520/21N controller or is in a noisy electrical environment the

Hall inputs require filtering from noise. It is recommended to use

a 1KΩ resistor in series with the Hall signal and a 2000 pF

capacitor from the Hall input pin to the Hall supply ground pin as

shown in FIGURES 6 and 7.

CASE GND

This pin is internally connected to the hybrid case. In some applica-

tions the user may want to tie this to Ground for EMI considerations.

PHASE A, B, C

These are the power drive outputs to the motor and switch

between VBUS+ Input and VBUS- Input or become high imped-

ance (see TABLE 3).

HALL A, B, C SIGNALS

These are logic signals from the motor Hall-effect sensors. They

use a phasing convention referred to as 120 degree spacing; that

is, the output of HA is in phase with motor back EMF voltage

VAB, HB is in phase VBC, and HC is in phase with VCA. Logic

HALL-EFFECT SENSOR PHASING vs.

MOTOR BACK EMF FOR CW ROTATION (120° Commutations)

300°

180°

0°

60°

120°

240°

300° 360°/0°

60°

120°

V_AB

V_BC

V_CA

BACK EMF

OF MOTOR

ROTATING

REMOTE POSITION SENSOR (HALL) SPACING FOR

120 DEGREE COMMUTATION

In Phase

with V_AB

60°

120°

In Phase

with V_BC

60°

In Phase

with V_CA

In Phase

with V_AC

(60˚)

REMOTE POSITION SENSOR (HALL) SPACING FOR

60 DEGREE COMMUTATION

FIGURE 4. HALL PHASING

FIGURE 5. HALL SENSOR SPACING

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

OPTIONAL

Cext

CASE GND

PWM IN

VBUS+ A

VBUS+ B

VBUS+ C

{

+28V

PWM OUT

+15V

PW-82520/21N

VDR

+15V SUPPLY

+5V SUPPLY

VCC

VDD

PHASE

{

+5V to +15V

PHASE

GND

VEE

SUPPLY GND

-5V to -15V

{

PHASE C

MOTOR BLDC

COMMAND GND

GND

VBUS-

COMMAND IN

COMMAND

SIGNAL

HALL A

HALL B

HALL C

ERROR AMP OUT

COMMAND OUT

10K

ERROR AMP INPUT

CURRENT

MONITOR

OUT

2000pF

10K

CURRENT MONITOR OUT

ENABLE

Sync In

FIGURE 6. VOLTAGE CONTROL HOOK-UP

OPTIONAL

Cext

CASE GND

PWM IN

PWM OUT

VBUS+ A

VBUS+ B

VBUS+ C

{

+28V

+15V

PW-82520/21N

VDR

+15V SUPPLY

SUPPLY

+5V

VCC

VDD

PHASE

+5V to +15V

PHASE

VBUS-

{

GND

VEE

SUPPLY GND

-5V to -15V

PHASE C

COMMAND GND

MOTOR BLDC

COMMAND IN

GND

COMMAND

SIGNAL

ERROR AMP OUT

COMMAND OUT

R2A

HALL A

HALL B

HALL C

10K, 0.5%

R2B

ERROR AMP INPUT

10K

4700pF

CURRENT MONITOR OUT

ENABLE

R7 1MEG

10K, 0.5%

ENABLE

2000pF

10K

100

TACH OUT

TACH

10K

100

DIR OUT

DIR

Sync In

FIGURE 7. TORQUE (CURRENT) CONTROL HOOK-UP

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

ENABLE

PWM IN

The ENABLE input is an active low (L) logic signal that enables

or disables the internal PWM. In the disable mode (H), the PWM

is shut down and the outputs, Phase A, Phase B and Phase C,

are in an "off" state and no voltage is applied to the motor.

The PWM comparator inputs are used to control the PWM pulse

width. PWM out or an external triangular waveform is connected

to this pin.

TACH OUT

WARNING: Never apply power to the hybrid without connecting

either PWM OUT or an external triangular waveform to PWM IN!

Failure to do so may result in one or more outputs latching on.

The TACH OUT provides a tachometer signal that is a square

wave with a frequency relative to motor speed and is derived

from the three Hall inputs HA, HB, HC. The tachometer circuitry

combines these three signals into a single pulse train as a 50%-

duty-cycle pulse. There are three pulses that occur every 360

electrical degree. The number of pulses per motor revolution is

formulated below:

PWM FREQUENCY

The PWM frequency from the PW-82520N1/N3 (PW-

82520N0/21N0) PWM OUT pin will free-run at a frequency of

100KHz ± 5KHz (50KHz ± 2.5KHz). The PWM frequency is user

adjustable from 100KHz (50KHz) down to 10KHz through the

addition of an external capacitor. The PWM triangular waveform

generated internally is brought out to the PWM OUT pin. This

output, or an external triangular waveform generated by the user,

may be connected to PWM IN on the hybrid.

Pr =

x 3 (e.g., 6 pulses/revolution for a 4 pole motor)

The motor RPM is:

Tf x 60

RPM =

where:

P = number of motor poles

Pr = number of pulses per revolution

Tf = Tach output frequency cycles/second

PWM OUT

This is the output of the internally generated PWM triangle wave-

form. It is normally connected to PWM IN. The frequency of this

output may be lowered by connecting an NPO capacitor (CEXT)

between PWM OUT and COMMAND GND. The PWM frequency

is determined by the following formula:

DIR OUT

The DIR OUT indicates the direction the motor is rotating, clock-

wise (CW) for a HI (open collector), or counterclockwise (CCW),

indicated as a logic LOW (ground).

PW-82520/21N0:

PW-82520N1/N3:

CURRENT MONITOR OUT

16.5E-6

33.0E-6

This is a bipolar analog output voltage representative of motor

current.The CURRENT MONITOR OUT will have the same scal-

ing as the COMMAND IN inputs.

330pF + CEXTpF

ERROR AMP INPUT, ERROR AMP OUT

These are the input and output pins for the error amplifier and

are used for compensation.

SYNC IN

This input, as shown in FIGURE 9, is used to synchronize the

PWM switching frequency with an external clocking device. The

PWM switching frequency can be pulled to up-to 20% faster than

its free running frequency.

EXTERNAL PI REGULATOR

10.0 K

4700 pF

SYNC PERIOD

1 MEG

ERROR

AMP INPUT

ERROR

AMP OUT

470 pf

100

R2B

R2A

10.0 K

50% DUTY CYCLE

COMMAND

OUT

CURRENT

MONITOR OUT

FIGURE 8. STANDARD PI CURRENT LOOP

FIGURE 9. SYNC INPUT SIGNAL

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

COMPENSATION

duty cycle range of the output voltage is limited to approximate-

ly 5-95% in both current and voltage modes.

The PI regulator in the PW-82520/21N can be tuned to a specif-

ic load for optimum performance. FIGURE 8 shows the standard

current loop configuration and tuning components. By adjusting

R1, R2 and C1, the amplifier can be tuned. The value of R1, C1

will vary, depending on the loop bandwidth requirement.

COMMAND GND

This pin is used when the command buffer is used single-ended and

the COMMAND IN- or COMMAND IN+ are tied to COMMAND GND.

COMMAND IN+, COMMAND IN- ,

TRANSCONDUCTANCE RATIO AND OFFSET

COMMAND GROUND, COMMAND OUT

When the PW-82520/21N is used in the current mode, the com-

mand inputs (COMMAND IN+ and COMMAND IN-) are designed

such that ±4Vdc on either input, with the other input connected

to ground will result in ± full-scale current (Continuous Output

Current: (Ioc) - Refer to TABLE 2) flow into the load. The dc cur-

rent transfer ratio accuracy is ±5% of the rated current including

offset and initial component accuracy. The initial output dc cur-

rent offset with both COMMAND IN+ and COMMAND IN- tied to

the ground will be as shown in TABLE 2 (Ioffset) when measured

using a load of 0.5mH and 1.0W at ambient room temperature

with standard current loop compensation (see FIGURE 8). The

winding phase current error shall be within the cumulative limits

of the transconductance ratio error and the offset error.

These are the connection pins for the command amplifier. The

command amplifier has a differential input that operates from a

±4Vdc full-scale analog current command. The command ampli-

fier output signal is internally limited to approximately ±5Vdc to

prevent the amplifier from saturating. The input impedance of the

command amplifier is 50KΩ.

The PW-82520/21N can be used either as a current or voltage

mode controller. When used as a torque controller (current

mode), the input command signal is processed through the com-

mand buffer, which is internally limited to ±5Vdc. The output of

the buffer (command out) is summed with the current monitor

output into the error amplifier. External compensation is used on

the error amp, so the response time can be adjusted to meet the

application.

RS+

Rs+ is the high side of the sense resistor used for non-scaled

test purposes only. Accuracy is not a guaranteed parameter.

When used in the voltage mode, the voltage command signal is

applied to the command amplifier, to control the voltage applied

to the motor. The command amplifier output is coupled into the

error amplifier. The error amplifier directly varies the PWM duty

cycle to control the voltage applied to the motor phase. The

nominal PWM frequency in the voltage mode is 50% with zero

volts applied to the command input. The PWM duty cycle is var-

ied by the voltage applied to the command input according to the

transfer function, 12% per volt applied to the command input.The

OUTPUT CURRENT

Output current derating as a function of the hybrid case temper-

ature is provided in FIGURES 11 and 12. The hybrid contains

internal pulse by pulse current limit circuitry to limit the output

current during fault conditions (See TABLE 2). Current Limit

accuracy is +10/-15%.

WARNING! The PW-82520/(21)N does not have short cir-

cuit protection. The PW-82520/(21)N must see a minimum of

100µH (400µH) inductive load phase-to-phase or enough

phase-to-phase line-to-line resistance to limit the continuous

output current to less than Ioc at all times. Operation into a

short or a condition that requires excessive output current will

damage the hybrid.

TABLE 3. COMMUTATION TRUTH TABLE

INPUTS

OUTPUTS

PHASE PHASE PHASE

ENABLE

DIR*

HA HB HC

TABLE 4. HALL INPUTS FOR

H-BRIDGE CONTROLLER

CCW

INPUTS

OUTPUTS

ENABLE COMMAND IN HA HB HC PH A PH B PH C

Positive

Negative

1=Logic Voltage >3.5Vdc, 0=Logic voltage < 1.5Vdc

* DIR is based on the convention shown in FIGURE 4.

Actual motor set up might be different.

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

THERMAL OPERATION

All other connections are as shown in either FIGURES 6 or 7

depending on voltage or current mode operation. The Hall inputs

are wired per TABLE 4. A positive input command will result in

positive current to the motor out of Phase A.

It is necessary that the base (heat sink surface - FIGURE 13) of

the PW-82520/21N be mounted to a heat sink. This heat sink

shall have the capacity to dissipate heat generated by the hybrid

at all levels of current output, up to the peak limit, while main-

taining the case temperature limit as per FIGURE 11.

OPTIONAL FEATURES

BRUSH MOTOR OPERATION

EXTERNAL SENSING RESISTOR

An external sense resistor can be connected to replace the inter-

nal resistor if this option is required. Please contact factory for

this option.

The PW-82520/21N can also be used as a brush motor controller

for current or voltage control in an H-Bridge configuration.The PW-

82520/21N would be connected as shown in FIGURE 10.

VBUS+ A

{

+28V

VBUS+ B

{

VBUS+ C

{

PHASE

PHASE A

{

PHASE

{

PHASE C

VBUS-

GND

HALL A

HALL B

HALL C

+5V

FIGURE 10. BRUSH MOTOR HOOK-UP

PW-82521N0

PW-82520N0

-50

-25

100

125

-25

100

125

Case Temperature (˚C)

(VBUS+ = 100V)

(VBUS+ = 28V)

(HSW = 20KHz)

FIGURE 11. OUTPUT CURRENT FOR CONTINUOUS COMMUTATION (ELECTRICAL > 600RPM, PWM = 50KHZ)

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

PW-82520/21N POWER DISSIPATION

2. SWITCHING LOSSES (PS)

Ps = [ VBUS ( IOA (ts1) + IOB (ts2) ) fo] / 2

There are two major contributors to power dissipation in the motor driver:

conduction losses, and switching losses.

-9

Ps = [ 28 ( 3 (200 x10 ) + 7 (400 x10 ) ) 25x10 ] / 2

An example calculation is shown below:

Ps = 1.19 Watts

VBUS = +28 V (Bus Voltage)

TRANSISTOR POWER DISSIPATION ( PQ )

Pq = PT + PS

IOA = 3 A, IOB = 7 A (see FIGURE 12)

= 25 KHz (switching frequency)

Pq = 1.30 + 1.19 = 2.49 Watts

PWM

ton = 36 µs, T = 40 µs (90% duty cycle) (see FIGURE 12)

Ron = 0.055 Ω (on-resistance, see TABLE 2)

OUTPUT CONDUCTOR DISSIPATION

PC = (Imotor rms) x (Rc)

PC = (4.87) x (0.080)

Rc = 0.080 Ω (conductor resistance, see TABLE 2)

ts1 = tf = 200 ns, ts2 = 2tr = 400 ns (see TABLE 2, FIGURE 12)

PC = 1.90 Watts

3. TRANSISTOR POWER DISSIPATION FOR

CONTINUOUS COMMUTATION

(ELECTRICAL > 600RPM)

(IOB - IOA)²

ton

Imotor rms =

IOBIOA +

(

)

(

Pqc = Pq (0.33)

(7 - 3)

7 x 3 +

(

)

(

Pqc = (2.49) x (0.33)

Pqc = 0.82 Watts

= 4.87 amps

motor rms

1. TRANSISTOR CONDUCTION LOSSES (PT)

PT = (Imotor rms) x (Ron)

4. TOTAL HYBRID POWER DISSIPATION

PTOTAL = (Pq + Pc) x 2

PT = (4.87) x (0.055)

PTOTAL = (2.49 + 1.90) x 2

PTOTAL = 8.78 Watts

PT = 1.30 Watts

VBUS

I_OB

I_OA

I_O

t_s1

t_s2

FIGURE 12. OUTPUT CHARACTERISTICS

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

PIN NO.1

CONTRASTING

COLOR BEAD

1.400 ±0.005

(35.58 ±0.127)

TABLE 5. PW-82520/21N PIN FUNC-

TIONS

1.150 ±0.005

(29.21 ±0.127)

FUNCTION

VBUS+ A

FUNCTION

41 TACH OUT

40 DIR OUT

39 HALL C

38 HALL B

37 HALL A

36 ENABLE

35 VCC

VBUS+ A

PHASE A

VBUS+ B

PHASE B

VBUS-

2.600 ±0.005

(66.04 ±0.127)

0.100 ±0.005 TYP

(2.54 ±0.127)

0.150 ±0.005 TYP

(3.81 ±0.127)

24 EQ. SP.

@ 0.100 = 2.400 ±0.010

(@ 2.54 = 60.96 ±0.254)

15 EQ. SP.

@ 0.150 = 2.250 ±0.010

(@ 3.81 = 57.15 ±0.254)

34 VCC RTN

33 VDR

10 VBUS-

11 RS+

32 SYNC IN

31 VDD

12 RS+

30 SUPPLY GND

29 VEE

13 VBUS+ C

14 VBUS+ C

15 PHASE C

BOTTOM VIEW

SIDE VIEW

28 N/C

0.250 MAX

(6.35)

27 N/C

CURRENT MONI-

TOR OUT

16 PHASE C

Heat

Sink

Surface

25 ERROR AMP IN

24 ERROR AMP OUT

23 COMMAND OUT

22 COMMAND IN -

21 COMMAND IN +

20 COMMAND GND

19 PWM OUT

0.250 ±0.010

(6.35 ±0.254)

0.030 ±0.002 DIA TYP

(0.762 ±0.051)

0.018 ±0.002 DIA TYP

(0.457 ±0.051)

NOTES:

1. DIMENSIONS IN INCHES (MM).

2. LEAD IDENTIFICATION NUMBERS ARE FOR REFERENCE ONLY.

18 PWM IN

FIGURE 13. MECHANICAL OUTLINE

17 CASE GND

* N/C pins have internal connections for factory test purposes.

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

ORDERING INFORMATION

PW-8252XNX- X X 0

Reliability Grade:

0 = Standard DDC Processing, no Burn-In (See table below.)

1 = MIL-PRF-38534 Compliant

2 = B*

3 = MIL-PRF-38534 Compliant with PIND Testing

4 = MIL-PRF-38534 Compliant with Solder Dip

5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip

6 = B* with PIND Testing

7 = B* with Solder Dip

8 = B* with PIND Testing and Solder Dip

9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.)

Temperature Range:

1 = -55°C to +125°C

2 = -40°C to +85°C

3 = 0°C to +70°C

4 = -55°C to +125°C with Variables Test Data

5 = -40°C to +85°C with Variables Test Data

8 = 0°C to +70°C with Variables Test Data

Rating:

1 = 1A

3 = 3A

0 = 10A

Voltage

0 = 100V

1 = 200V (available with N0 Rating only)

*Standard DDC Processing with burn-in and full temperature test — see table below.

STANDARD DDC PROCESSING

MIL-STD-883

TEST

METHOD(S)

CONDITION(S)

INSPECTION

SEAL

2009, 2010, 2017, and 2032

—

1014

1010

A and C

TEMPERATURE CYCLE

CONSTANT ACCELERATION

BURN-IN

2001

1015, TABLE 1

—

Data Device Corporation

www.ddc-web.com

PW-82520/21N

A-11/01-1000

The information in this data sheet is believed to be accurate; however, no responsibility is

assumed by Data Device Corporation for its use, and no license or rights are

granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482

For Technical Support - 1-800-DDC-5757 ext. 7677 or 7381

Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358

Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610

West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988

United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264

Ireland - Tel: +353-21-341065, Fax: +353-21-341568

France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425

Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089

Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689

World Wide Web - http://www.ddc-web.com

DATA DEVICE CORPORATION

REGISTERED TO ISO 9001

FILE NO. A5976

A-11/01-1000

PRINTED IN THE U.S.A.

PW-82520N0-240 [ETC]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E