QL3040-1PQ208C [ETC]
FPGA|1008-CELL|CMOS|QFP|208PIN|PLASTIC ;型号: | QL3040-1PQ208C |
厂家: | ETC |
描述: | FPGA|1008-CELL|CMOS|QFP|208PIN|PLASTIC |
文件: | 总19页 (文件大小:446K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
QL3040 pASIC 3 FPGA Data Sheet
40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
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Eight Low-Skew Distributed
Networks
Device Highlights
• Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
High Performance & High Density
• 40,000 Usable PLD Gates with 252 I/Os
• 300 MHz 16-bit Counters,
• Six global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control — each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
400 MHz Datapaths
• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
• 100% routable with 100% utilization and
High Performance
complete pin-out stability
• Input + logic cell + output total delays
• Variable-grain logic cells provide high
under 6 ns
performance and 100% utilization
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
• Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 252 I/O Pins
• 244 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
• Eight high-drive input/distributed
network pins
Figure 1: 1,008 pASIC 3 Logic Cells
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© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Architecture Overview
The QL3040 is a 40,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC
3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic's patented
ViaLink technology to provide a unique combination of high performance, high density,
low cost, and extreme ease-of-use.
The QL3040 contains 1,008 logic cells. With a maximum of 252 I/Os, the QL3040 is
available in 208-PQFP and 456-pin PBGA packages.
Software support for the complete pASIC 3 family, including the QL3040, is available
through three basic packages. The turnkey QuickWorks package provides the most
complete FPGA software solution from design entry to logic synthesis, to place and route,
to simulation. The QuickToolsTM for Workstations package provides a solution for designers
who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM,
or other third-party tools for design entry, synthesis, or simulation.
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Electrical Specifications
AC Characteristics at VCC = 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided
in Table 1 through Table 5.
Table 1: Logic Cells
Symbol
Parameter
Propagation Delays (ns) Fanouta
1
2
3
4
8
tPD
tSU
Combinatorial Delay b
Setup Time b
Hold Time
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
1.9
1.8
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
tRW
Reset Width
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in Table 7.
b. These limits are derived from a representative selection of the slowest paths through the pASIC
3 logic cell including typical net delays. Worst case delay values for specific paths should be de-
termined from timing analysis of your particular design.
Table 2: Input-Only/Clock Cells
Symbol
Parameter
Propagation Delays (ns) Fanout a
1
2
3
4
8
12 24
tIN
tINI
tISU
tIH
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
1.5 1.6 1.8 1.9 2.4 2.9 4.4
1.6 1.7 1.9 2.0 2.5 3.0 4.5
3.1 3.1 3.1 3.1 3.1 3.1 3.1
0.0 0.0 0.0 0.0 0.0 0.0 0.0
0.7 0.8 1.0 1.1 1.6 2.1 3.6
0.6 0.7 0.9 1.0 1.5 2.0 3.5
tlCLK
tlRST
tlESU
tlEH
Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and tempera-
ture settings as specified in Table 7.
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Table 3: Clock Cells
Symbol
Parameter
Propagation Delays (ns) Loads per Half Column a
1
2
3
4
8
10
11
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1.2
0.7
0.8
1.2
0.7
0.8
1.3
0.7
0.9
1.3
0.7
0.9
1.5
0.7
1.1
1.6
0.7
1.2
1.7
0.7
1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to eight loads per half column. The glo-
bal clock has up to 11 loads per half column.
Table 4: Input-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Fanout a
1
2
3
4
8
10
tI/O
tISU
Input Delay (bidirectional pad)
Input Register Set-Up Time
1.3
3.1
0.0
0.7
0.6
2.3
0.0
1.6
3.1
0.0
1.0
0.9
2.3
0.0
1.8
3.1
0.0
1.2
1.1
2.3
0.0
2.1
3.1
0.0
1.5
1.4
2.3
0.0
3.1
3.1
0.0
2.5
2.4
2.3
0.0
3.6
3.1
0.0
3.0
2.9
2.3
0.0
tIH
Input Register Hold Time
tlOCLK
tlORST
tlESU
tlEH
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA =
25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature set-
tings as specified in Table 7.
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Table 5: Output-Only I/O Cells
Propagation Delays (ns) Output Load
Symbol
Parameter
Capacitance (pF)
30
50
2.5
2.6
1.7
2.0
-
75
3.1
3.2
2.2
2.6
-
100
3.6
3.7
2.8
3.1
-
150
4.7
4.8
3.9
4.2
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tOUTLH
tOUTHL
tPZH
Output Delay Low to High
Output Delay High to Low
2.1
2.2
1.2
1.6
2.0
1.2
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State a
Output Delay Low to Tri-State
tPZL
tPHZ
tPLZ
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-
-
-
a. The loads presented in Figure 2 are used for tPXZ
:
tPHZ
1ΚΩ
5 pF
1ΚΩ
tPLZ
5 pF
Figure 2: Loads used for tPXZ
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QL3040 pASIC 3 FPGA Data Sheet Rev E
DC Characteristics
The DC specifications are provided in Table 6 through Table 8.
Table 6: Absolute Maximum Ratings
Parameter
VCC Voltage
Value
-0.5 V to 4.6 V
-0.5 V to 7.0 V
-0.5 V to VCCIO +0.5 V
200 mA
Parameter
Value
20 mA
DC Input Current
ESD Pad Protection
Storage Temperature
Lead Temperature
VCCIO Voltage
Input Voltage
Latch-up Immunity
2000 V
-65°C to +150°C
300°C
Table 7: Operating Range
Military
Symbol
Parameter
Industrial
Commercial
Unit
Min
Max
3.6
5.5
-
Min
Max
3.6
Min
3.0
3.0
0
Max
3.6
VCC
VCCIO
TA
Supply Voltage
3.0
3.0
-55
-
3.0
3.0
V
I/O Input Tolerance Voltage
Ambient Temperature
Case Temperature
5.5
5.25
70
V
-40
85
°C
TC
125
-
-
-
-
-
°C
-0 Speed Grade
-
0.43
0.43
0.43
0.43
0.43
1.90
1.54
1.28
0.90
0.82
0.46
0.46
0.46
0.46
0.46
1.85
1.50
1.25
0.88
0.80
n/a
n/a
n/a
n/a
n/a
-1 Speed Grade 0.42
-2 Speed Grade 0.42
-3 Speed Grade
1.64
1.37
K
Delay Factor
-4 Speed Grade
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Table 8: DC Characteristics
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Conditions
Min
Max
Units
V
0.5 VCC VCCIO+0.5
VIL
-0.5
2.4
0.3 VCC
V
IOH = -12 mA
IOH = -500 µA
IOL = 16 mAa
IOL = 1.5 mA
V
VOH
Output HIGH Voltage
Output LOW Voltage
0.9 VCC
V
0.45
0.1 VCC
10
V
VOL
V
II
I or I/O Input Leakage Current
3-State Output Leakage Current
Input Capacitanceb
VI = VCCIO or GND
VI = VCCIO or GND
-10
-10
µA
µA
pF
mA
mA
mA
µA
IOZ
CI
10
10
VO = GND
VO = VCC
-15
40
-180
210
2
IOS
Output Short Circuit Currentc
D.C. Supply Currentd
ICC
VI, VIO = VCCIO or GND 0.50 (typ)
0
ICCIO D.C. Supply Current on VCCIO
100
a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All
other devices have 8 mA IOL specifications.
b. Capacitance is sample tested only. Clock pins are 12 pF maximum.
c. Only one output at a time. Duration should not exceed 30 seconds.
d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all
industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLog-
ic customer applications group (see Contact Information).
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Kv and Kt Graphs
Voltage Factor vs. Supply Voltage
1.1000
1.0800
1.0600
1.0400
1.0200
1.0000
0.9800
0.9600
0.9400
0.9200
3
3.1
3.2
3.3
3.4
3.5
3.6
Supply Voltage (V)
Figure 3: Voltage Factor vs. Supply Voltage
Temperature Factor vs. Operating Temperature
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-60
-40
-20
0
20
40
60
80
Junction Temperature C
Figure 4: Temperature Factor vs. Operating Temperature
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Power-up Sequencing
VCCIO
VCC
(VCCIO -VCC MAX
)
VCC
400 us
Time
Figure 5: Power-up Requirements
The following requirements must be met when powering up the device (refer to Figure 5):
• When ramping up the power supplies keep (VCCIO -VCC)MAX
≤ 500 mV. Deviation from
this recommendation can cause permanent damage to the device.
• VCCIO must lead VCC when ramping the device.
• The power supply must take greater than or equal to 400 µs to reach VCC. Ramping to
VCC/VCCIO earlier than 400 µs can cause the device to behave improperly.
An internal diode is present in-between VCC and VCCIO, as shown in Figure 6.
V
V
CCIO
CC
Internal Logic
Cells, RAM
blocks, etc
IO Cells
Figure 6: Internal Diode Between VCC and VCCIO
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
JTAG
TCK
TAp Controller
State Machine
(16 States)
Instruction Decode
&
Control Logic
TMS
TRSTB
Instruction Register
Mux
RDI
TDO
Mux
Boundary-Scan Register
(Data Register)
Bypass
Register
Internal
Register
I/O Registers
User Defined Data Register
Figure 7: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design
challenges, not the least of which concerns the accessibility of test points. The Joint Test
Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard
1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the
boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port
(TAP) controller works in concert with the Instruction Register (IR); these allow users to run
three required tests, along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse
subsystem tests for fuller verification of higher level system elements.
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
The 1149.1 standard requires the following three tests:
• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan
register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)
pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload
Instruction), and input boundary cells capture the input data for analysis.
• Sample/Preload Instruction. This instruction allows a device to remain in its
functional mode, while selecting the boundary scan register to be connected between
the TDI and TDO pins. For this test, the boundary scan register can be accessed via a
data scan operation, allowing users to sample the functional data entering and leaving
the device.
• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary
scan entirely, so the data passes through the bypass register. The Bypass instruction
allows users to test a device without passing through other devices. The bypass register
is connected between the TDI and TDO pins, allowing serial data to be transferred
through a device without affecting the operation of the device.
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Pin Descriptions
Table 9: Pin Descriptions
Pin
Function
Description
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TDI
Test Data In for JTAG
Hold LOW during normal operation. Connect to
ground if not used for JTAG.
TRSTB
TMS
Active low Reset for JTAG
Test Mode Select for JTAG
Test Clock for JTAG
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
Hold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.
TCK
Output that must be left unconnected if not used for
JTAG.
TDO
STM
Test data out for JTAG
Special Test Mode
Must be grounded during normal operation.
Can be configured as either or both.
High-drive input and/or array
network driver
I/ACLK
High-drive input and/or global
network driver
I/GCLK
Can be configured as either or both.
I
High-drive input
Input/Output pin
Power supply pin
Use for input signals with high fanout.
Can be configured as an input and/or output.
Connect to 3.3 V supply.
I/O
VCC
Connect to 5.0 V supply if 5 V input tolerance is
required, otherwise connect to 3.3 V supply.
VCCIO
GND
Input voltage tolerance pin
Ground pin
Connect to ground.
Ordering Information
QL 3040 - 1 PQ208 C
QuickLogic device
pASIC 3 device
part number
Operating Range
C = Commercial
I = Industrial
M = Military
Speed Grade
0 = Quick
1 = Fast
2 = Faster
3 = Faster
*4 = Wow
Package Code
PQ208 = 208-pin PQFP
PB456 = 456-pin PBGA
* Contact QuickLogic regarding availability (see Contact Information)
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© 2002 QuickLogic Corporation
12
QL3040 pASIC 3 FPGA Data Sheet Rev E
208 PQFP Pinout Diagram
Pin 157
Pin 1
pASIC 3
QL3040-1PQ208C
Pin 53
Pin 105
Figure 8: Top View of 208 Pin PQFP
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QL3040 pASIC 3 FPGA Data Sheet Rev E
208 PQFP Pinout Table
Table 10: 208 PQFP Pinout Table
208 PQFP Function 208 PQFP Function 208 PQFP Function 208 PQFP Function 208 PQFP Function
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TRSTB
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
TDO
208
1
43
44
45
46
47
48
NC
49
50
51
52
53
54
NC
NC
55
56
NC
57
58
59
60
61
62
63
64
NC
65
66
67
NC
68
69
70
NC
71
NC
72
73
74
NC
75
76
77
78
79
80
81
82
83
84
85
125
126
127
128
NC
168
169
NC
I/O
GND
I/O
2
86
I/O
3
87
170
171
172
173
174
175
NC
I/O
I/O
4
88
I/O
GCLK/I
ACLK/I
VCC
GCLK/I
GCLK/I
VCC
I/O
5
89
129
130
131
132
133
134
135
136
NC
NC
6
I/O
90
I/O
91
I/O
7
92
I/O
8
NC
93
I/O
9
176
177
178
179
NC
VCC
I/O
10
11
12
13
14
NC
15
16
17
18
19
20
NC
21
22
23
24
25
26
27
28
29
30
31
32
NC
33
NC
34
35
36
NC
37
38
39
NC
40
41
42
94
95
I/O
GND
I/O
I/O
96
I/O
97
137
NC
I/O
GND
I/O
98
180
181
182
NC
I/O
99
138
139
140
141
142
NC
I/O
I/O
100
NC
101
NC
102
NC
NC
103
104
105
NC
106
107
108
109
NC
110
111
112
113
114
115
116
117
NC
118
119
120
121
NC
122
123
124
I/O
I/O
I/O
I/O
183
184
185
186
187
188
NC
I/O
I/O
I/O
I/O
I/O
I/O
143
144
145
NC
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
146
147
148
149
150
151
152
153
154
155
156
157
158
NC
189
190
191
192
193
194
NC
GND
I/O
GCLK/I
GCLK/I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
195
196
197
198
NC
I/O
I/O
I/O
GND
I/O
I/O
TCK
STM
I/O
I/O
199
200
201
202
203
204
205
206
207
I/O
I/O
I/O
159
160
161
162
163
164
165
166
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCC
I/O
I/O
VCC
I/O
I/O
I/O
167
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www.quicklogic.com
© 2002 QuickLogic Corporation
14
QL3040 pASIC 3 FPGA Data Sheet Rev E
456 PBGA Pinout Diagram
pASIC 3
QL3040-1PB456C
BOTTOM View
PIN A1
CORNER
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Figure 9: 456-Pin PBGA Pinout Diagram
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© 2002 QuickLogic Corporation
www.quicklogic.com
15
QL3040 pASIC 3 FPGA Data Sheet Rev E
456 PBGA Pinout Table
Table 11: 456 PBGA Pinout Table
456
A1
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
456
B26
C1
Function
STM
I/O
456
D25
D26
E1
Function
I/O
456
H4
Function
456
M14
M15
M16
M22
M23
M24
M25
M26
N1
Function
GND/THERM
GND/THERM
GND/THERM
NC
I/O
I/O
NC
A2
H5
I/O
I/O
NC
A3
C2
H22
H23
H24
H25
H26
J1
A4
C3
I/O
E2
I/O
I/O
TDO
I/O
I/O
I/O
NC
A5
C4
E3
I/O
I/O
I/O
A6
C5
E4
I/O
GND
VCC
GND
NC
I/O
I/O
A7
C6
E5
I/O
I/O
I/O
A8
C7
E6
A9
C8
I/O
E7
J2
I/O
GCLK/I
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
C9
I/O
E8
J3
I/O
N2
I/O
GND
I/O
NC
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
E9
J4
N3
I/O
GND
GCLK/I
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
J5
N4
I/O
GND
GND
VCC
GND
GND
GND
NC
NC
J22
J23
J24
J25
J26
K1
N5
I/O
NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26
P1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K2
I/O
GND
NC
I/O
K3
I/O
K4
I/O
I/O
I/O
GND
VCC
GND
I/O
VCC
I/O
K5
I/O
GND
I/O
K22
K23
K24
K25
K26
L1
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
I/O
I/O
I/O
P2
I/O
I/O
I/O
P3
I/O
I/O
I/O
I/O
B2
P4
I/O
I/O
I/O
NC
B3
D2
L2
P5
I/O
I/O
I/O
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
NC
B4
D3
F2
L3
P11
P12
P13
P14
P15
P16
P22
P23
P24
P25
P26
R1
GND
I/O
I/O
I/O
B5
D4
F3
L4
B6
D5
F4
NC
L5
NC
B7
D6
NC
I/O
F5
VCC
VCC
NC
L11
L12
L13
L14
L15
L16
L22
L23
L24
L25
L26
M1
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
NC
B8
D7
F22
F23
F24
F25
F26
G1
I/O
B9
D8
GND
I/O
I/O
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
D9
I/O
GCLK / I
GCLK / I
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
I/O
I/O
GND
I/O
I/O
I/O
I/O
ACLK / I
I/O
G2
I/O
I/O
I/O
G3
GND
I/O
I/O
I/O
I/O
G4
R2
NC
I/O
I/O
G5
R3
I/O
G22
G23
G24
G25
G26
H1
GND
I/O
ACLK / I
GCLK/I
I/O
R4
NC
GND
I/O
NC
M2
R5
I/O
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
M3
R11
R12
R13
R14
R15
R16
I/O
I/O
NC
M4
NC
I/O
I/O
GND
M5
I/O
GND/THERM
GND/THERM
GND/THERM
M11
M12
M13
GND
I/O
H2
I/O
I/O
H3
(Sheet 1 of 2)
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© 2002 QuickLogic Corporation
16
QL3040 pASIC 3 FPGA Data Sheet Rev E
Table 11: 456 PBGA Pinout Table (Continued)
456
R22
R23
R24
R25
R26
T1
Function
456
W1
Function
I/O
456
Function
NC
456
AD1
Function
I/O
456
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
NC
I/O
I/O
NC
I/O
W2
AD2
I/O
I/O
GND
VCC
I/O
W3
AD3
I/O
I/O
I/O
W4
AD4
GCLK / I
NC
NC
I/O
I/O
W5
AD5
I/O
W22
W23
W24
W25
W26
Y1
NC
AD6
I/O
I/O
VCC
GND
NC
I/O
T2
AD7
I/O
I/O
I/O
T3
AD8
I/O
I/O
I/O
T4
AD9
VCC
I/O
VCC
GND
I/O
I/O
T5
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
T11
T12
T13
T14
T15
T16
T22
T23
T24
T25
T26
U1
GND/THERMAL
I/O
I/O
GND/THERMAL
Y2
I/O
I/O
GND/THERMAL
I/O
I/O
I/O
Y3
AF2
GND/THERMAL
I/O
I/O
I/O
Y4
AF3
GND/THERMAL
I/O
I/O
I/O
Y5
AF4
GND/THERMAL
GND
I/O
I/O
I/O
Y22
Y23
Y24
Y25
Y26
AA1
AA2
AA3
AA4
AA5
AA22
AA23
AA24
AA25
AA26
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AF5
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
GND
NC
I/O
I/O
I/O
AC2
I/O
I/O
AF6
I/O
NC
I/O
AC3
AF7
I/O
GND
I/O
I/O
AC4
AF8
I/O
I/O
AC5
AF9
I/O
NC
I/O
AC6
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
I/O
I/O
I/O
AC7
U2
NC
NC
VCC
VCC
NC
I/O
AC8
I/O
TRSTB
I/O
NC
U3
AC9
I/O
I/O
U4
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
I/O
I/O
U5
NC
TDI
I/O
U22
U23
U24
U25
U26
V1
I/O
AE2
I/O
VCCIO
NC
AE3
I/O
I/O
I/O
AE4
I/O
I/O
I/O
AE5
I/O
I/O
I/O
AE6
I/O
NC
I/O
V2
AE7
V3
I/O
I/O
AE8
I/O
V4
GND
VCC
NC
NC
NC
VCC
GND
I/O
AE9
I/O
I/O
I/O
V5
AE10
AE11
AE12
AE13
AE14
AE15
NC
I/O
V22
V23
V24
V25
V26
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(Sheet 2 of 2)
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© 2002 QuickLogic Corporation
www.quicklogic.com
17
QL3040 pASIC 3 FPGA Data Sheet Rev E
456 PBGA Mechanical Drawing
Figure 10: 456 PBGA Mechanical Drawing
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© 2002 QuickLogic Corporation
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QL3040 pASIC 3 FPGA Data Sheet Rev E
Contact Information
Telephone: 408 990 4000 (US)
416 497 8884 (Canada)
44 1932 57 9011 (Europe)
49 89 930 86 170 (Germany)
852 8106 9091 (Asia)
81 45 470 5525 (Japan)
info@quicklogic.com
E-mail:
Support:
Web site:
support@quicklogic.com
http://www.quicklogic.com/
Revision History
Table 12: Revision History
Revision
Date
Comments
First release.
A
B
C
D
not avail.
not avail.
not avail
May 2001
Update of AC/DC Specs and reformat
Added Kfactor, Power-up, JTAG, and mechanical
drawing information. Reformatted.
E
June 2002
Copyright Information
Copyright © 2002 QuickLogic Corporation.
All Rights Reserved.
The information contained in this product brief, and the accompanying software programs
are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic
Corporation reserves the right to make periodic modifications of this product without
obligation to notify any person or entity of such revision. Copying, duplicating, selling, or
otherwise distributing any part of this product without the prior written consent of an
authorized representative of QuickLogic is prohibited.
QuickLogic, QuickWorks, pASIC, and ViaLink are registered trademarks of QuickLogic
Corporation.
Verilog is a registered trademark of Cadence Design Systems, Inc.
All trademarks and registered trademarks are the property of their respective owners.
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© 2002 QuickLogic Corporation
www.quicklogic.com
19
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