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QL4009-2PL68I [ETC]

9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM; 9000可以使用的PLD门QuickRAM ESP相结合的性能，密度和嵌入式RAM
QL4009-2PL68I
型号： QL4009-2PL68I
厂家： ETC    ETC
描述：

9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
9000可以使用的PLD门QuickRAM ESP相结合的性能，密度和嵌入式RAM

可编程逻辑 栅
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QL4009 QuickRAM Data Sheet  
9,000 Usable PLD Gate QuickRAM ESP Combining Performance,  
Density and Embedded RAM  
• • • • • •  
Advanced I/O Capabilities  
Device Highlights  
• Interfaces with both 3.3 V and 5.0 V devices  
• PCI compliant with 3.3 V and 5.0 V busses  
High Performance & High Density  
for -1/-2/-3/-4 speed grades  
• 9,000 Usable PLD Gates with 82 I/Os  
• Full JTAG boundary scan  
• 300 MHz 16-bit Counters, 400 MHz  
• I/O Cells with individually controlled  
Datapaths, 160+ MHz FIFOs  
Registered Input Path and Output Enables  
• 0.35 µm four-layer metal non-volatile  
CMOS process for smallest die sizes  
High Speed Embedded SRAM  
• 8 dual-port RAM modules, organized in  
user-configurable 1,152 bit blocks  
• 5 ns access times, each port independently  
8
RAM  
Blocks  
160  
High Speed  
Logic Cells  
accessible  
• Fast and efficient for FIFO, RAM, and ROM  
functions  
Easy to Use / Fast Development  
Cycles  
Interface  
• 100% routable with 100% utilization and  
Figure 1: QuickRAM Block Diagram  
complete pin-out stability  
• Variable-grain logic cells provide high  
performance and 100% utilization  
• Comprehensive design tools include high  
quality Verilog/VHDL synthesis  
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© 2002 QuickLogic Corporation  
www.quicklogic.com  
1
QL4009 QuickRAM Data Sheet Rev B  
Architecture Overview  
The QuickRAMTM family of ESPs (Embedded Standard Products) offers FPGA logic in  
combination with Dual-Port SRAM modules. The QL4009 is a 9,000 usable PLD gate  
member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35µm  
four-layer metal process using QuickLogic's patented ViaLinkTM technology to provide a  
unique combination of high performance, high density, low cost, and extreme ease-of-use.  
The QL4009 contains 160 logic cells and 8 Dual Port RAM modules (see Figure 1). Each  
RAM module has 1,152 RAM bits, for a total of 9,216 bits. RAM Modules are Dual Port  
(one read port, one write port) and can be configured into one of four modes: 64 (deep) x18  
(wide), 128x9, 256x4, or 512x2 (see Figure 4). With a maximum of 82 I/Os, the QL4009  
is available in 68-pin PLCC, 84-pin PLCC and 100-pin TQFP packages.  
Designers can cascade multiple RAM modules to increase the depth or width allowed in  
single modules by connecting corresponding address lines together and dividing the words  
between modules (see Figure 2). This approach allows up to 512-deep configurations as  
large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.  
Software support for the complete QuickRAM family, including the QL4009, is available  
through two basic packages. The turnkey QuickWorksTM package provides the most  
complete ESP software solution from design entry to logic synthesis, to place and route, to  
simulation. The QuickToolsTM packages provides a solution for designers who use Cadence,  
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for  
design entry, synthesis, or simulation.  
The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outputs  
within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29  
including register and control lines (see Figure 3).  
WDATA  
WADDR  
RDATA  
RADDR  
RAM  
Module  
(1,152 bits)  
RAM  
Module  
(1,152 bits)  
WDATA  
RDATA  
Figure 2: QuickRAM Module Bits  
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© 2002 QuickLogic Corporation  
2
QL4009 QuickRAM Data Sheet Rev B  
Product Summary  
Total of 82 I/O Pins  
• 74 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for  
-1/-2/-3/-4 speed grades  
• 8 high-drive input/distributed network pins  
Eight Low-Skew Distributed Networks  
• Two array clock/control networks available to the logic cell flip-flop clock, set and reset  
inputs - each driven by an input-only pin  
• Six global clock/control networks available to the logic cell F1, clock, set and reset inputs  
and the input and I/O register clock, reset and enable inputs as well as the output enable  
control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell  
feedback  
High Performance Silicon  
• Input + logic cell + output total delays under 6 ns  
• Data path speeds over 400 MHz  
• Counter speeds over 300 MHz  
• FIFO speeds over 160+ MHz  
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© 2002 QuickLogic Corporation  
www.quicklogic.com  
3
QL4009 QuickRAM Data Sheet Rev B  
AC Characteristics at VCC = 3.3 V, TA = 25° C (K = 1.00)  
To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the  
following numbers in the tables provided.  
QS  
A1  
A2  
A3  
AZ  
A4  
A5  
A6  
QS  
OP  
B1  
B2  
OZ  
C1  
C2  
MP  
QZ  
MS  
D1  
D2  
E1  
E2  
NP  
NS  
NZ  
FZ  
F1  
F2  
F3  
F4  
F5  
F6  
QC  
QR  
Figure 3: QuickRAM Logic Cell  
Table 1: Logic Cell  
Propagation Delays (ns)  
Symbol  
Parameter  
Fanout (5)  
1
2
3
4
5
tPD  
Combinatorial Delaya  
Setup Timea  
1.4  
1.7  
0.0  
0.7  
1.2  
1.2  
1.0  
0.8  
1.9  
1.8  
1.7  
1.7  
0.0  
1.0  
1.2  
1.2  
1.3  
1.1  
1.9  
1.8  
1.9  
2.2  
1.7  
0.0  
1.5  
1.2  
1.2  
1.8  
1.6  
1.9  
1.8  
3.2  
1.7  
0.0  
2.5  
1.2  
1.2  
2.8  
2.6  
1.9  
1.8  
tSU  
1.7  
tH  
Hold Time  
0.0  
tCLK  
tCWHI  
tCWLO  
tSET  
tRESET  
tSW  
Clock to Q Delay  
Clock High Time  
Clock Low Time  
Set Delay  
1.2  
1.2  
1.2  
1.5  
Reset Delay  
1.3  
Set Width  
1.9  
tRW  
Reset Width  
1.8  
a. These limits are derived from a representative selection of the slowest paths through the Quick-  
RAM logic cell including typical net delays. Worst case delay values for specific paths should be  
determined from timing analysis of your particular design.  
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© 2002 QuickLogic Corporation  
4
QL4009 QuickRAM Data Sheet Rev B  
[8:0]  
WA  
RE  
RCLK  
[17:0]  
WD  
WE  
[8:0]  
RA  
RD  
[17:0]  
WCLK  
MODE  
[1:0]  
ASYNCRD  
Figure 4: QuickRAM Module  
Table 2: RAM Cell Synchronous Write Timing  
Propagation Delays (ns)  
Symbol  
Parameter  
Fanout  
1
2
3
4
5
tSWA  
tHWA  
tSWD  
tHWD  
tSWE  
WA Setup Time to WCLK  
WA Hold Time to WCLK  
WD Setup Time to WCLK  
WD Hold Time to WCLK  
WE Setup Time to WCLK  
WE Hold Time to WCLK  
WCLK to RD (WA=RA)a  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.0  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.3  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.6  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.9  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
7.1  
tHWE  
tWCRD  
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and  
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature  
settings as specified in the Operating Range.  
Table 3: RAM Cell Synchronous Read Timing  
Propagation Delays (ns)  
Symbol  
Parameter  
Fanout  
Logic Cells  
tSRA  
1
2
3
4
5
RA Setup Time to RCLK  
RA Hold Time to RCLK  
RE Setup Time to RCLK  
RE Hold Time to RCLK  
RCLK to RDa  
1.0  
0.0  
1.0  
0.0  
4.0  
1.0  
0.0  
1.0  
0.0  
4.3  
1.0  
0.0  
1.0  
0.0  
4.6  
1.0  
0.0  
1.0  
0.0  
4.9  
1.0  
0.0  
1.0  
0.0  
6.1  
tHRA  
tSRE  
tHRE  
tRCRD  
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and  
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature  
settings as specified in the Operating Range.  
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© 2002 QuickLogic Corporation  
www.quicklogic.com  
5
QL4009 QuickRAM Data Sheet Rev B  
Table 4: RAM Cell Asynchronous Read Timing  
Propagation Delays (ns)  
Fanout  
Symbol  
Parameter  
1
2
3
4
5
RPDRD  
RA to RDa  
3.0  
3.3  
3.6  
3.9  
5.1  
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and  
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature  
settings as specified in the Operating Range.  
Table 5: Input-Only / Clock Cells  
Propagation Delays (ns)  
Symbol  
Parameter  
Fanout  
1
2
3
4
8
12 24  
tIN  
High Drive Input Delay  
1.5 1.6 1.8 1.9 2.4 2.9 4.4  
1.6 1.7 .19 2.0 2.5 3.0 4.5  
3.1 3.1 3.1 3.1 3.1 3.1 3.1  
0.0 0.0 0.0 0.0 0.0 0.0 0.0  
0.7 0.8 1.0 1.1 1.6 2.1 3.6  
0.6 0.7 0.9 1.0 1.5 2.0 3.5  
2.3 2.3 2.3 2.3 2.3 2.3 2.3  
0.0 0.0 0.0 0.0 0.0 0.0 0.0  
tINI  
High Drive Input, Inverting Delay  
Input Register Set-Up Time  
tISU  
tIH  
Input Register Hold Time  
tICLK  
tIRST  
tIESU  
tIEH  
Input Register Clock To Q  
Input Register Reset Delay  
Input Register Clock Enable Setup Time  
Input Register Clock Enable Hold Time  
Table 6: Clock Cells  
Propagation Delays (ns)  
Fanouta  
Symbol  
Parameter  
1
2
3
4
8
10 11  
tACK  
Array Clock Delay  
1.2 1.2 1.3 1.3 1.5 1.6 1.7  
0.7 0.7 0.7 0.7 0.7 0.7 0.7  
0.8 0.8 0.9 0.9 1.1 1.2 1.3  
tGCKP  
tGCKB  
Global Clock Pin Delay  
Global Clock Buffer Delay  
a. The array distributed networks consist of 40 half columns and the global distributed networks con-  
sist of 44 half columns, each driven by an independent buffer. The number of half columns used  
does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global  
clock has up to 11 loads per half column.  
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www.quicklogic.com  
© 2002 QuickLogic Corporation  
6
QL4009 QuickRAM Data Sheet Rev B  
Table 7: I/O Cell Input Delays  
Propagation Delays (ns)  
Fanouta  
Symbol  
Parameter  
1
2
3
4
8
10  
tI/O  
tISU  
tIH  
Input Delay (bidirectional pad)  
1.3 1.6 1.8 2.1 3.1 3.6  
3.1 3.1 3.1 3.1 3.1 3.1  
0.0 0.0 0.0 0.0 0.0 0.0  
0.7 1.0 1.2 1.5 2.5 3.0  
0.6 0.9 1.1 1.4 2.4 2.9  
2.3 2.3 2.3 2.3 2.3 2.3  
0.0 0.0 0.0 0.0 0.0 0.0  
Input Register Set-Up Time  
Input Register Hold Time  
tIOCLK  
tIORST  
tIESU  
tIEH  
Input Register Clock to Q  
Input Register Reset Delay  
Input Register Clock Enable Set-Up Time  
Input Register Clock Enable Hold Time  
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and  
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature  
settings as specified in the Operating Range.  
Table 8: I/O Cell Output Delays  
Propagation Delays (ns)  
Output Load Capacitance (pF)  
Symbol  
Parameter  
3
50  
2.5  
2.6  
1.7  
2.0  
-
75  
3.1  
3.2  
2.2  
2.6  
-
100  
3.6  
3.7  
2.8  
3.1  
-
150  
4.7  
4.8  
3.9  
4.2  
-
tOUTLH  
Output Delay Low to High  
Output Delay High to Low  
Output Delay Tri-state to High  
Output Delay Tri-state to Low  
Output Delay High to Tri-statea  
Output Delay High to Tri-statea  
2.1  
2.2  
1.2  
1.6  
2.0  
1.2  
tOUTHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
-
-
-
-
a. The following loads are used for tPXZ  
tPHZ  
5 pF  
1ΚΩ  
1ΚΩ  
tPLZ  
5 pF  
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© 2002 QuickLogic Corporation  
www.quicklogic.com  
7
QL4009 QuickRAM Data Sheet Rev B  
DC Characteristics  
The DC specifications are provided in the tables below.  
Table 9: Absolute Maximum Ratings  
Parameter  
VCC Voltage  
Value  
-0.5 to 4.6 V  
Parameter  
Value  
20 mA  
DC Input Current  
ESD Pad Protection  
Storage Temperature  
Lead Temperature  
VCCIO Voltage  
Input Voltage  
Latch-up Immunity  
-0.5 to 7.0 V  
2000V  
-0.5 V to VCCIO +0.5 V  
200 mA  
-65° C to +150° C  
300° C  
Table 10: Operating Range  
Military Industrial  
Min Max  
Symbol  
Parameter  
Commercial  
Unit  
Min  
Max  
3.6  
Min  
3.0  
3.0  
0
Max  
3.6  
VCC  
VCCIO  
TA  
Supply Voltage  
3.0  
3.0  
-55  
-
3.0  
3.0  
3.6  
5.5  
V
I/O Input Tolerance Voltage  
Ambient Temperature  
Case Temperature  
5.5  
5.25  
70  
V
-
-40  
85  
° C  
° C  
n/a  
n/a  
n/a  
n/a  
n/a  
TC  
125  
2.03  
1.64  
1.37  
-
-
-
-
-0 Speed Grade 0.42  
-1 Speed Grade 0.42  
-2 Speed Grade 0.42  
-3 Speed Grade  
0.43  
0.43  
0.43  
0.43  
0.43  
1.90  
1.54  
1.28  
0.90  
0.82  
0.46  
0.46  
0.46  
0.46  
0.46  
1.85  
1.50  
1.25  
0.88  
0.80  
K
Delay Factor  
-4 Speed Grade  
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© 2002 QuickLogic Corporation  
8
QL4009 QuickRAM Data Sheet Rev B  
Table 11: DC Characteristics  
Symbol  
VIH  
Parameter  
Input HIGH Voltage  
Input LOW Voltage  
Conditions  
Min  
0.5VCC  
-0.5  
Max  
Units  
V
VCCIO+0.5  
0.3VCC  
VIL  
V
IOH = -12 mA  
IOH = -500 µA  
IOL = 16 mAa  
IOL = 1.5 mA  
2.4  
V
VOH  
Output HIGH Voltage  
Output LOW Voltage  
0.9VCC  
V
0.45  
0.1VCC  
10  
V
VOL  
V
II  
I or I/O Input Leakage Current  
3-State Output Leakage Current  
Input Capacitanceb  
VI = VCCIO or GND  
VI = VCCIO or GND  
-10  
-10  
µA  
µA  
pF  
mA  
mA  
mA  
µA  
IOZ  
CI  
10  
10  
VO = GND  
VO = VCC  
-15  
40  
-180  
210  
2
IOS  
Output Short Circuit Currentc  
ICC  
D.C. Supply Currentd  
VI, VIO = VCCIO or GND 0.50 (typ)  
0
ICCIO  
D.C. Supply Current on VCCIO  
100  
a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All  
other devices have 8 mA IOL specifications.  
b. Capacitance is sample tested only. Clock pins are 12 pF maximum.  
c. Only one output at a time. Duration should not exceed 30 seconds.  
d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all  
industrial grade devices. and 5 mA for all military grade devices. For AC conditions, contact QuickLog-  
ic customer applications group.  
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© 2002 QuickLogic Corporation  
www.quicklogic.com  
9
QL4009 QuickRAM Data Sheet Rev B  
Kv and Kt Graphs  
Voltage Factor vs. Supply Voltage  
1.1000  
1.0800  
1.0600  
1.0400  
1.0200  
1.0000  
0.9800  
0.9600  
0.9400  
0.9200  
3
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
Supply Voltage (V)  
Figure 5: Voltage Factor vs. Supply Voltage  
Temperature Factor vs. Operating Temperature  
1.15  
1.10  
1.05  
1.00  
0.95  
0.90  
0.85  
-60  
-40  
-20  
0
20  
40  
60  
80  
Junction Temperature C  
Figure 6: Temperature Factor vs. Operating Temperature  
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© 2002 QuickLogic Corporation  
10  
QL4009 QuickRAM Data Sheet Rev B  
Power-up Sequencing  
VCCIO  
VCC  
(VCCIO -VCC MAX  
)
VCC  
400 us  
Time  
Figure 7: Power-up Requirements  
The following requirements must be met when powering up the device:  
(Refer to Figure 7 above)  
• When ramping up the power supplies keep (VCCIO -VCC)MAX  
≤ 500 mV. Deviation from  
this recommendation can cause permanent damage to the device.  
• VCCIO must lead VCC when ramping the device.  
• The power supply must take greater than or equal to 400 µs to reach VCC. Ramping to  
VCC/VCCIO earlier than 400 µs can cause the device to behave improperly.  
An internal diode is present in-between VCC and VCCIO, as shown in Figure 8.  
V
V
CCIO  
CC  
Internal Logic  
Cells, RAM  
blocks, etc  
IO Cells  
Figure 8: Internal Diode Between VCC and VCCIO  
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© 2002 QuickLogic Corporation  
www.quicklogic.com  
11  
QL4009 QuickRAM Data Sheet Rev B  
JTAG  
TCK  
TAp Controller  
State Machine  
(16 States)  
Instruction Decode  
&
Control Logic  
TMS  
TRSTB  
Instruction Register  
Mux  
RDI  
TDO  
Mux  
Boundary-Scan Register  
(Data Register)  
Bypass  
Register  
Internal  
Register  
I/O Registers  
User Defined Data Register  
Figure 9: JTAG Block Diagram  
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design  
challenges, not the least of which concerns the accessibility of test points. The Joint Test  
Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard  
1149.1, the Standard Test Access Port and Boundary Scan Architecture.  
The JTAG boundary scan test methodology allows complete observation and control of the  
boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port  
(TAP) controller works in concert with the Instruction Register (IR); these allow users to run  
three required tests, along with several user-defined tests.  
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse  
subsystem tests for fuller verification of higher level system elements.  
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© 2002 QuickLogic Corporation  
12  
QL4009 QuickRAM Data Sheet Rev B  
The 1149.1 standard requires the following three tests:  
• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test  
places a device into an external boundary test mode, selecting the boundary scan  
register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)  
pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload  
Instruction), and input boundary cells capture the input data for analysis.  
• Sample/Preload Instruction. This instruction allows a device to remain in its  
functional mode, while selecting the boundary scan register to be connected between  
the TDI and TDO pins. For this test, the boundary scan register can be accessed via a  
data scan operation, allowing users to sample the functional data entering and leaving  
the device.  
• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary  
scan entirely, so the data passes through the bypass register. The Bypass instruction  
allows users to test a device without passing through other devices. The bypass register  
is connected between the TDI and TDO pins, allowing serial data to be transferred  
through a device without affecting the operation of the device.  
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© 2002 QuickLogic Corporation  
www.quicklogic.com  
13  
QL4009 QuickRAM Data Sheet Rev B  
Pin Descriptions  
Table 12: Pin Descriptions  
Pin  
Function  
Description  
Hold HIGH during normal operation. Connects to serial  
PROM data in for RAM initialization. Connect to VCC if  
unused.  
Test Data In for JTAG /RAM init.  
Serial Data In  
TDI/RSI  
Hold LOW during normal operation. Connects to serial  
PROM reset for RAM initialization. Connect to GND if  
unused.  
Active low Reset for JTAG /RAM  
init. reset out  
TRSTB/RRO  
Hold HIGH during normal operation. Connect to VCC if  
not used for JTAG.  
TMS  
TCK  
Test Mode Select for JTAG  
Test Clock for JTAG  
Hold HIGH or LOW during normal operation. Connect to  
VCC or ground if not used for JTAG.  
Connect to serial PROM clock for RAM initialization. Must  
be left unconnected if not used for JTAG or RAM  
initialization.  
Test data out for JTAG /RAM init.  
clock out  
TDO/RCO  
STM  
Special Test Mode  
Must be grounded during normal operation.  
Can be configured as either or both.  
High-drive input and/or array  
network driver  
I/ACLK  
High-drive input and/or global  
network driver  
I/GCLK  
Can be configured as either or both.  
I
High-drive input  
Input/Output pin  
Power supply pin  
Use for input signals with high fanout.  
Can be configured as an input and/or output.  
Connect to 3.3 V supply.  
I/O  
VCC  
Connect to 5.0 V supply if 5 V input tolerance is required,  
otherwise connect to 3.3 V supply.  
VCCIO  
GND  
Input voltage tolerance pin  
Ground pin  
Connect to ground.  
Available on 456-PBGA only. Connect to ground plane on  
PCB if heat sinking desired. Otherwise may be left  
unconnected.  
GND/THERM Ground/Thermal pin  
Ordering Information  
QL 4009 - 1 PF100 C  
QuickLogic device  
QuickRAM device  
part number  
Operating Range  
C = Commercial  
I = Industrial  
M = Military  
Speed Grade  
0 = Quick  
1 = Fast  
2 = Faster  
3 = Faster  
*4 = Wow  
Package Code  
PL68 = 68-pin PLCC  
PF84 = 84-pin PLCC  
PF100 = 100-pin TQFP  
* Contact QuickLogic regarding availabliity  
•
•
•
•
•
•
www.quicklogic.com  
© 2002 QuickLogic Corporation  
14  
QL4009 QuickRAM Data Sheet Rev B  
68 PLCC Pinout Diagram  
9
8
7
6
5
4
3
2 1 68 67 66 65 64 63 62 61  
IO  
IO  
IO  
IO  
IO  
IO  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
IO  
IO  
IO  
IO  
GND  
IO  
GCLK/I  
ACLK/I  
VCC  
GCLK/I  
GCLK/I  
IO  
GCLK/I  
GCLK/I  
VCC  
ACLK/I  
GCLK/I  
IO  
GND  
IO  
IO  
QuickRAM  
QL4009-1PL68C  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
Figure 10: Top View of 68 Pin PLCC  
68 PLCC Pinout Table  
Table 13: 68 PLCC Pinout Table  
68 PLCC  
Function  
GND  
68 PLCC  
18  
Function  
68 PLCC  
35  
Function  
GND  
I/O  
68 PLCC  
52  
Function  
1
2
V
V
CC  
CC  
I/O  
19  
GCLK/I  
GCLK/I  
I/O  
36  
53  
GCLK/I  
GCLK/I  
I/O  
I/O  
I/O  
3
20  
37  
54  
4
V
21  
38  
I/O  
55  
CCIO  
I/O  
I/O  
V
I/O  
5
22  
39  
56  
CCIO  
6
I/O  
23  
I/O  
40  
I/O  
57  
I/O  
7
I/O  
24  
I/O  
41  
I/O  
58  
I/O  
I/O  
I/O  
TRSTB  
TMS  
I/O  
I/O  
8
25  
42  
58  
9
TDO  
I/O  
26  
I/O  
43  
60  
I/O  
TDI  
I/O  
TCK  
STM  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
27  
44  
61  
I/O  
28  
45  
I/O  
62  
I/O  
I/O  
I/O  
29  
46  
63  
I/O  
30  
I/O  
47  
I/O  
64  
I/O  
GND  
I/O  
31  
I/O  
48  
GND  
I/O  
65  
I/O  
I/O  
I/O  
32  
49  
66  
GCLK/I  
ACLK/I  
33  
I/O  
50  
GCLK/I  
ACLK/I  
67  
I/O  
I/O  
I/O  
34  
51  
68  
•
•
•
•
•
•
© 2002 QuickLogic Corporation  
www.quicklogic.com  
15  
QL4009 QuickRAM Data Sheet Rev B  
84 PLCC Pinout Diagram  
11 10  
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
GND  
IO  
GCLK/I  
ACLK/I  
GCLK/I  
GCLK/I  
VCC  
IO  
IO  
IO  
IO  
IO  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
VCC  
GCLK/I  
GCLK/I  
ACLK/I  
GCLK/I  
IO  
GND  
IO  
IO  
QuickRAM  
QL4009-1PL84C  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  
Figure 11: Top View of 84 Pin PLCC  
84 PLCC Pinout Table  
Table 14: 84 PLCC Pinout Table  
84 PLCC  
Function  
84 PLCC  
22  
Function  
ACLK/I  
84 PLCC  
43  
Function  
84 PLCC  
64  
Function  
ACLK/I  
1
2
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
23  
GCLK/I  
44  
65  
GCLK/I  
GCLK/I  
GCLK/I  
3
24  
45  
66  
4
V
25  
V
46  
V
67  
V
CCIO  
CC  
CCIO  
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDI  
I/O  
I/O  
I/O  
I/O  
I/O  
5
26  
47  
68  
6
I/O  
27  
48  
I/O  
69  
I/O  
I/O  
I/O  
7
28  
49  
70  
8
I/O  
29  
50  
I/O  
71  
I/O  
9
I/O  
30  
51  
I/O  
72  
I/O  
I/O  
TRSTB  
TMS  
I/O  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
31  
52  
73  
TDO  
I/O  
32  
53  
74  
I/O  
TCK  
STM  
I/O  
33  
54  
75  
I/O  
34  
55  
I/O  
76  
I/O  
35  
56  
I/O  
77  
I/O  
V
I/O  
I/O  
36  
57  
78  
CC  
I/O  
37  
I/O  
58  
I/O  
79  
V
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
38  
59  
80  
I/O  
39  
I/O  
60  
I/O  
81  
GND  
I/O  
40  
GND  
I/O  
61  
GND  
I/O  
82  
GND  
I/O  
41  
62  
83  
GCLK/I  
42  
I/O  
63  
GCLK/I  
84  
I/O  
•
•
•
•
•
•
www.quicklogic.com  
© 2002 QuickLogic Corporation  
16  
QL4009 QuickRAM Data Sheet Rev B  
100 TQFP Pinout Diagram  
Pin 76  
Pin 1  
QuickRAM  
QL4009-1PF100C  
Pin 26  
Pin 51  
Figure 12: Top View of 100 Pin TQFP  
Table 15: 100 TQFP Pinout Table  
100 TQFP Pinout Table  
100TQFP  
Function  
100TQFP  
26  
Function  
TDI  
I/O  
100TQFP  
51  
Function  
100TQFP  
76  
Function  
TCK  
STM  
I/O  
1
I/O  
I/O  
I/O  
I/O  
2
27  
52  
77  
3
I/O  
28  
I/O  
53  
I/O  
78  
4
I/O  
29  
I/O  
54  
I/O  
79  
I/O  
I/O  
I/O  
I/O  
I/O  
5
30  
55  
80  
6
I/O  
31  
I/O  
56  
I/O  
81  
I/O  
I/O  
I/O  
I/O  
I/O  
7
32  
57  
82  
8
I/O  
33  
I/O  
58  
I/O  
83  
I/O  
9
GND  
I/O  
34  
I/O  
59  
GND  
I/O  
84  
I/O  
GND  
I/O  
GND  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
35  
60  
85  
I
36  
61  
I
86  
ACLK / I  
I/O  
ACLK / I  
I/O  
37  
62  
87  
V
38  
GND  
I/O  
63  
V
88  
GND  
I/O  
CC  
CC  
I
39  
64  
I
89  
GCLK / I  
I/O  
GCLK / I  
I/O  
40  
65  
90  
V
41  
I/O  
66  
V
91  
I/O  
CC  
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
42  
67  
92  
CCIO  
CCIO  
43  
I/O  
68  
93  
I/O  
I/O  
I/O  
44  
69  
94  
45  
I/O  
70  
95  
I/O  
46  
I/O  
71  
96  
I/O  
I/O  
I/O  
47  
72  
97  
48  
I/O  
73  
98  
I/O  
TRSTB  
TMS  
I/O  
49  
74  
99  
50  
75  
100  
TDO  
•
•
•
•
•
•
© 2002 QuickLogic Corporation  
www.quicklogic.com  
17  
QL4009 QuickRAM Data Sheet Rev B  
Contact Information  
Telephone: 408 990 4000 (US)  
416 497 8884 (Canada)  
44 1932 57 9011 (Europe)  
49 89 930 86 170 (Germany)  
852 8106 9091 (Asia)  
81 45 470 5525 (Japan)  
info@quicklogic.com  
E-mail:  
Support:  
Web site:  
support@quicklogic.com  
http://www.quicklogic.com/  
Revision History  
Table 16: Revision History  
Revision  
Date  
Comments  
First release.  
A
B
5/2000  
Added Kfactor, Power-up, JTAG and mechanical  
drawing information. Reformatted.  
5/2002  
Copyright Information  
Copyright © 2002 QuickLogic Corporation. All Rights Reserved.  
The information contained in this product brief, and the accompanying software programs  
are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic  
Corporation reserves the right to make periodic modifications of this product without  
obligation to notify any person or entity of such revision. Copying, duplicating, selling, or  
otherwise distributing any part of this product without the prior written consent of an  
authorized representative of QuickLogic is prohibited.  
QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are  
trademarks of QuickLogic Corporation.  
Verilog is a registered trademark of Cadence Design Systems, Inc.  
•
•
•
•
•
•
© 2002 QuickLogic Corporation  
www.quicklogic.com  
18  

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