QS5919Q [ETC]


型号：	QS5919Q
厂家：	ETC
描述：	EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER\|CMOS\|SSOP\|28PIN\|PLASTIC 8个分散输出时钟驱动器\| CMOS \| SSOP \| 28PIN \|塑料\n 时钟驱动器输出元件
文件：	总9页 (文件大小：165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

LOW SKEW CMOS PLL

CLOCK DRIVER WITH

QS5919

INTEGRATED LOOP FILTER

FEATURES:

DESCRIPTION

•

5Voperation

Low noise CMOS level outputs

<500ps outputskew, Q0–Q4

2xQoutput, Qoutputs, Q output, Q/2output

Outputs 3-state andresetwhile OE/RST low

PLLdisable feature forlowfrequencytesting

InternalloopfilterRCnetwork

FunctionalequivalenttoMotorola MC88915

Positive ornegative edge synchronization(PE)

Balanceddrive outputs ±36mA

The QS5919 Clock Driver uses an internal phase locked loop (PLL)

tolocklowskewoutputstooneoftworeferenceclockinputs.Eightoutputs

are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

<500ps skewbetweentheQ0-Q4,andQ/2outputs.TheQS5919includes

an internal RC filter which provides excellent jitter characteristics and

eliminates the needforexternalcomponents. Various combinations of

feedback and a divide-by-2 in the VCO path allow applications to be

customized for linear VCO operation over a wide range of input SYNC

frequencies.ThePLLcanalsobedisabledbythePLL_ENsignaltoallow

lowfrequencyorDCtesting.The LOCKoutputasserts toindicate when

phase lockhas beenachieved.The QS5919is designedforuse inhigh-

performance workstations, multi-board computers, networking hard-

ware, and mainframe systems. Several can be used in parallel or

scatteredthroughouta systemforguaranteedlowskew, system-wide

clockdistributionnetworks.

160MHzmaximumfrequency(2xQoutput)

Available in QSOP and PLCC packages

For more information on PLL clock driver products, see Application

Note AN-227.

FUNCTIONALBLOCKDIAGRAM

REF_SEL

LOCK

FEEDBACK

PLL_EN

FREQ_SEL

SYNC0

SYNC

PHASE

LOOP

FILTER

VCO

DETECTOR

OE/RST

2xQ

INDUSTRIAL TEMPERATURE RANGE

JULY 2000

2000 Integrated Device Technology, Inc.

DSC-5823/-

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

PINCONFIGURATION

GND

VDD

2xQ

Q/2

FEEDBACK

REF_SEL

SYNC0

AVDD

OE/RST

FEEDBACK

REF_SEL

SYNC0

GND

VDD

J28-1

SO28-9

AVDD

GND

LOCK

AGND

LOCK

PLL_EN

GND

AGND

SYNC1

14 15

FREQ_SEL

GND

VDD

PLCC

QSOP

TOP VIEW

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Symbol

Rating

Max.

Unit

AVDD/VDD Supply Voltage to Ground

–0.5 to +7

VIN

DC Input Voltage VIN

–0.5 to +7

Maximum Power

QSOP

PLCC

655

770

°C

Dissipation (TA = 85°C)

Storage Temperature Range

TSTG

–65 to +150

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

CAPACITANCE _{(T = 25 C, f = 1MHz, V = 0V)}

QSOP

PLCC

Parameter

Typ.

Max.

Typ.

Max.

Unit

CIN

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

PIN DESCRIPTION

Pin Name

I/O

Description

SYNC0

Reference clock input

SYNC1

REF_SEL

FREQ_SEL

FEEDBACK

Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0.

VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.

PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output

frequency relationships. See the Frequency Selection Table for more information.

Clock outputs

Q0 -Q4

Clock output. Matched in frequency, but inverted with respect to Q.

Clock output. Matched in phase, but frequency is double the Q frequency.

Clock output. Matched in phase, but frequency is half the Q frequency.

2xQ

Q/2

LOCK

PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to

the inputs.

OE/RST

Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,

outputs are enabled.

PLL_EN

PLL enable. Enables and disables the PLL. Useful for testing purposes.

When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the

negative edge of SYNC.

VDD

—

Power supply for output buffers.

AVDD

GND

AGND

Power supply for phase lock loop and other internal circuitries.

Ground supply for output buffers.

Ground supply for phase lock loop and other internal circuitries.

OUTPUT FREQUENCY SPECIFICATIONS

Industrial: T^A= –40°C to +85°C, AV^DD/V^DD= 5.0V ± 10%

Symbol

FMAX_2XQ

FMAX_Q

Description

– 55

– 70

– 100

100

– 133

133

66.5

33.25

– 160

160

Units

MHz

Max Frequency, 2xQ

Max Frequency, Q0 - Q4, Q5

Max Frequency, Q/2

Min Frequency, 2xQ

Min Frequency, Q0 - Q4, Q5

Min Frequency, Q/2

27.5

13.75

FMAX_Q/2

FMIN_2XQ

FMIN_Q

17.5

FMIN_Q/2

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

FREQUENCY SELECTION TABLE

SYNC (MHz)

(allowable range) ⁽¹⁾

Output Used for

Feedback

Output Frequency Relationships ⁽²⁾

FREQ_SEL

HIGH

LOW

Min.

Max

Q/2

Q0 - Q4

SYNC X 2

SYNC

2XQ

Q/2

Q0 -Q4

FMIN_Q/2

FMIN_Q

FMAX _Q/2

FMAX _Q

SYNC

– SYNC X 2

– SYNC

SYNC X 4

SYNC X 2

– SYNC X 2

SYNC

SYNC / 2

– SYNC / 2

SYNC / 4

SYNC

FMIN_Q

FMAX _Q

SYNC

– SYNC

SYNC / 2

SYNC X 2

SYNC

2xQ

Q/2

FMIN_2XQ

FMIN_Q/2 /2

FMIN_Q /2

F_{MIN_Q}/2

FMIN_2XQ /2

FMAX _2XQ

FMAX _Q/2 /2

FMAX _Q /2

F_{MAX _Q}/2

FMAX _2XQ /2

– SYNC / 2

– SYNC X 2

– SYNC

SYNC X 4

SYNC X 2

– SYNC X 2

SYNC

LOW

Q0 -Q4

Q₅

SYNC / 2

– SYNC / 2

SYNC / 4

LOW

SYNC

– SYNC

SYNC / 2

LOW

2xQ

– SYNC / 2

NOTES:

1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2XQ. Operation with

Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect

output frequencies.

2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Industrial: T^A= –40°C to +85°C, AV^DD/V^DD= 5.0V ± 10%

Symbol

Parameter

Input HIGH Voltage

Conditions

Min.

Typ.

Max.

Unit

VIH

Guaranteed Logic HIGH Level

—

VIL

Input LOW Voltage

Guaranteed Logic LOW Level

IOH = −36mA

—

100

—

0.8

—

0.45

0.2

—

VOH

Output HIGH Voltage

VDD – 0.75

IOH = −100µA

_DD– 0.2

VOL

Output LOW Voltage

VDD = Min., IOL = 36mA

VDD = Min., IOL = 100µA

—

IOZ

IIN

Input Hysteresis

µA

Output Leakage Current

Input Leakage Current

Input Pull-Down Current (PE)

VOUT = VDD or GND, VDD = Max.

VIN = AVDD or GND, AVDD = Max.

AVDD = Max., VIN = AVDD

IPD

100

POWER SUPPLY CHARACTERISTICS

Symbol

Parameter

Test Conditions

VDD = Max., OE/RST = LOW,

SYNC = LOW, All outputs unloaded

Typ.

Max.

Unit

IDDQ

Quiescent Power Supply Current

1.5

∆IDD

Power Supply Current per Input HIGH

Dynamic Power Supply Current ⁽¹⁾

_DD= Max., V = 3.4V

0.4

0.2

1.5

0.4

IDDD

VDD = Max., CL = 0pF

mA/MHz

NOTE:

1. Relative to the frequency of Q outputs.

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

INPUT TIMING REQUIREMENTS

Symbol

Description ⁽¹⁾

Min.

Max.

Unit

tR, tF

Maximum input rise and fall times, 0.8V to 2V

—

(1)

tPWC

Input Clock Frequency, SYNC0, SYNC1

Input clock pulse, HIGH or LOW ⁽²⁾

2.5

FMAX _2XQ

MHz

—

(2)

Duty cycle, SYNC0, SYNC1

NOTES:

1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with

different FEEDBACK and FREQ_SEL combinations.

2. Where pulse witdh implied by D^His less than t^WPClimit, t^WPClimit applies

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter ⁽¹⁾

Min.

Max.

Unit

tSKR

Output Skew Between Rising Edges, Q0-Q4 and Q/2 ⁽²⁾

—

500

tSKF

tSKALL

tPW

Output Skew Between Falling Edges, Q0-Q4 and Q/2 ⁽²⁾

Output Skew, All Outputs ^(2,5)

—

500

750

Pulse Width, 2xQ output, >40MHz

Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz

Cycle-to-Cycle Jitter ⁽⁴⁾

TCY/2 − 0.4

− 0.15

− 500

—

TCY/2 + 0.4

0.15

tPD

SYNC Input to Feedback Delay ⁽⁶⁾

tLOCK

SYNC to Phase Lock

tPZH

tPZL

tPHZ

tPLZ

tR, tF

Output Enable Time, OE/RST LOW to HIGH ⁽³⁾

Output Disable Time, OE/RST HIGH to LOW ⁽³⁾

Output Rise/Fall Times, 0.2VDD 0.8VDD

0.3

2.5

NOTES:

1. See Test Loads and Waveforms for test load and termination.

2. Skew specifications apply under identical environments (loading, temperature, V^DD, device speed grade).

3. Measured in open loop mode PLL_EN = 0.

4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.

5. Skew measured at selected synchronization edge.

6. tPD measured at device inputs at 1.5V, Q output at 80MHz.

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

AC TEST LOADS AND WAVEFORMS

VDD

300Ω

100Ω

7.0V

OUTPUT

300Ω

30pF

100

Ω

TEST CIRCUIT 1

TEST CIRCUIT 2

1.0ns

VDD

0.8VDD

3.0V

2.0V

Vth = 1.5V

tPW

0.5VDD

0.2VDD

0.8V

TTL INPUT TEST WAVEFORM

CMOSOUTPUTWAVEFORM

ENABLE

DISABLE

1.5V

CONTROL

INPUT

tPLZ

tPZL

OUTPUT

NORMALLY

LOW

3.5V

VOL

SWITCH

CLOSED

1.5VDD

0.3V

tPHZ

tPZH

VOH

SWITCH

OPEN

1.5VDD

OUTPUT

NORMALLY

HIGH

ENABLE AND DISABLE TIMES

TEST CIRCUIT 1 is used for output enable/disable parameters.

TEST CIRCUIT 2 is used for all other timing parameters.

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

AC TIMING DIAGRAM

SYNC

t^PD

FEEDBACK

t^J

t^SKF

Q -Q

t^SKR

Q/2

2xQ

t_SKALL

NOTES:

1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the

negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC.

2. All parameters except tPD are measured at 0.5VDD; tPD is measured at 1.5V.

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

PLLOPERATION

ThePhaseLockedLoop(PLL)circuitincludedintheQS5919provides

forreplicationofincomingSYNCclocksignals.Anymanipulationofthat

signal,suchas frequencymultiplyingorinversionis performedbydigital

logicfollowingthePLL(seetheblockdiagram).Thekeyadvantageofthe

PLLcircuitis toprovide aneffective zeropropagationdelaybetweenthe

outputandinputsignals.Infact,addingdelaycircuitsinthefeedbackpath,

‘propagationdelay’canevenbe negative!Asimplifiedschematicofthe

QS5919 PLL circuit is shown below.

SIMPLIFIEDDIAGRAMOFQS5919FEEDBACK

2xQ

Q/2

INPUT

VCO

PHASE

DETECTOR

The phase difference between the output and the input frequencies

feeds the VCOwhichdrives the outputs.Whicheveroutputis fedback,it

will stabilize at the same frequency as the input. Hence, this is a true

negativefeedbackclosedloopsystem.Inmostapplications,theoutputwill

optimallyhavezerophaseshiftwithrespecttotheinput.Infact,theinternal

loop filter on the QS5919 typically provides within 150ps of phase shift

betweeninputandoutput.

Iftheuserwishes tovarythephasedifference(typicallytocompensate

forbackplane delays), this is mosteasilyaccomplishedbyaddingdelay

circuits tothefeedbackpath.Therespectiveoutputusedforfeedbackwill

beadvancedbytheamountofdelayinthefeedbackpath.Allotheroutputs

willretaintheirproperrelationships tothatoutput.

QS5919

INDUSTRIALTEMPERATURERANGE

LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

ORDERINGINFORMATION

XXXX

Device Type

Package

Quarter Size Outline Package (SO28-9)

Plastic Leaded Chip Carrier (J28-1)

Low Skew CMOS PLL Clock Driver with Integrated

Loop Filter

5919

CORPORATE HEADQUARTERS

for SALES:

2975StenderWay

Santa Clara, CA 95054

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Turboclock is a registered trademark of Integrated Device Technology, Inc.

QS5919Q [ETC]

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