QT0081411TUE [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n
| 型号： | QT0081411TUE |
| 厂家： | 
ETC |
| 描述： | Controller Miscellaneous - Datasheet Reference
|
| 文件： | 总62页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPTi
®
FireBridge II
82C814
Docking Station Controller
Data Book
Revision: 1.0
912-3000-047
January 08, 1998
Copyright
Copyright © 1997, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored
in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechani-
cal, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Incorporated, 888 Tasman
Drive, Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and espe-
cially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the
right to revise the design and associated documentation and to make changes from time to time in the content without obligation
of OPTi Inc. to notify any person of such revisions or changes.
Note: Before designing contact OPTi for latest Product Alerts, Applications Notes, and Errata for this product line.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of their respec-
tive holders.
OPTi Inc.
888 Tasman Drive
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
www.opti.com
ii
82C814
Table of Contents
1.0 Features ............................................................................................................................ 1
2.0 Overview ........................................................................................................................... 1
3.0 Signal Definitions............................................................................................................. 2
3.1
3.2
Terminology/Nomenclature Conventions ........................................................................................2
Signal Descriptions ............................................................................................................................6
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
Host Interface PCI Signals .....................................................................................................6
Docking Control and Sense Signals.......................................................................................7
PCI Docking Interface Pins.....................................................................................................7
Interrupt Interface Pins ...........................................................................................................9
Power and Ground Pins .........................................................................................................9
3.3
3.4
Strap-Selected Interface Options ....................................................................................................10
Internal Resistors .............................................................................................................................11
4.0 Functional Description .................................................................................................. 13
4.1
4.2
4.3
4.4
4.5
4.6
OPTi Docking Station Controller Chipset.......................................................................................13
Chipset Compatibility.......................................................................................................................13
Interface Overview............................................................................................................................13
Device Type Detection Logic...........................................................................................................14
Primary PCI Bus................................................................................................................................15
PCI-to-CardBus Bridge.....................................................................................................................15
4.6.1
Configuration Cycle ..............................................................................................................15
4.6.1.1 Translation Between Type 0 and Type 1 Configuration Cycles ............................15
4.6.2
4.6.3
4.6.4
4.6.5
Cycle from Host to Docking Interface...................................................................................16
Master Cycle from Docking Interface ...................................................................................16
Inability to Complete a Posted Write ....................................................................................16
Cycle Termination by Target ................................................................................................16
4.6.5.1 Posted Write Termination .....................................................................................16
4.6.5.2 Non-Posted Write Termination..............................................................................16
4.6.5.3 Read (Prefetched or Non-Prefetched) Termination ..............................................16
OPTi
®
912-3000-047
Revision: 1.0
Page iii
January 08, 1998
82C814
Table of Contents (cont.)
4.7
PCI Docking Station Operation .......................................................................................................17
4.7.1
4.7.2
4.7.3
4.7.4
Introduction...........................................................................................................................17
Procedure.............................................................................................................................17
Initial Setup...........................................................................................................................17
Action Upon Attachment of Dock..........................................................................................18
4.8
Status Change Service Routine ......................................................................................................19
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
Docking Event ......................................................................................................................19
Undocking Event ..................................................................................................................19
Notes on Undocking .............................................................................................................19
Retest ...................................................................................................................................19
PCI Clock Buffering ..............................................................................................................20
4.9
Interrupt Support ..............................................................................................................................20
4.9.1
4.9.2
4.9.3
PCI INTx# Implementation ...................................................................................................20
IRQ Driveback Logic.............................................................................................................20
Compaq Serial IRQ Implementation.....................................................................................21
4.9.3.1 Operation ..............................................................................................................21
5.0 82C814 Register Set ...................................................................................................... 23
5.1
5.2
5.3
Register State on Device Removal..................................................................................................23
Base Register Group........................................................................................................................23
82C814-Specific Register Group.....................................................................................................31
5.3.1
5.3.2
5.3.3
CLKRUN#.............................................................................................................................31
Slot Buffer Enable, Slew Rate, and Threshold Control.........................................................31
Dual ISA Buses ....................................................................................................................31
5.4
5.5
CardBus Register Group..................................................................................................................34
5.4.1 Power Control.......................................................................................................................34
Docking Station Window Selection Group.....................................................................................36
5.5.1
Docking Station Window Registers ......................................................................................36
5.5.1.1 Cycle Decoding.....................................................................................................37
5.5.1.2 Cycle Trapping......................................................................................................37
5.5.1.3 ISA Window Selection...........................................................................................37
5.6
PCI Power Management Register Group........................................................................................41
OPTi
®
Page iv
912-3000-047
January 08, 1998
Revision: 1.0
82C814
Table of Contents (cont.)
6.0 Electrical Ratings ........................................................................................................... 43
6.1
6.2
6.3
6.4
Absolute Maximum Ratings.............................................................................................................43
DC Characteristics: VCC = 3.3V or 5.0V ±5%, TA = 0°C to +70°C.................................................43
AC Characteristics............................................................................................................................44
AC Timing Diagrams ........................................................................................................................45
7.0 Mechanical Package Outline......................................................................................... 47
Appendix A IRQ Driveback Protocol ................................................................................. 49
A.1 Driveback Cycle Format...................................................................................................................49
A.2 Edge vs Level Mode, IRQ Polarity...................................................................................................50
A.3 Host Handling of IRQ Driveback Information.................................................................................50
OPTi
®
912-3000-047
Revision: 1.0
Page v
January 08, 1998
82C814
Table of Contents (cont.)
OPTi
®
Page vi
912-3000-047
Revision: 1.0
January 08, 1998
82C814
List of Figures
Figure 2-1
Figure 3-1
Figure 3-2
Figure 4-1
Figure 6-1
Figure 6-2
Figure 6-3
Figure 7-1
Figure A-1
Multiple ISA Bus Support and Cascadeable Docking......................................................................1
Pin Diagram.....................................................................................................................................3
Power-Up Timing...........................................................................................................................11
82C814 Organization.....................................................................................................................13
Setup Timing Waveform ................................................................................................................45
Hold Timing Waveform..................................................................................................................45
Output Delay Timing Waveform.....................................................................................................45
144-Pin LQFP, Low-Profile Quad Flat Pack ..................................................................................47
IRQ Driveback Cycle High-Priority Request ..................................................................................49
OPTi
®
912-3000-047
Revision: 1.0
Page vii
January 08, 1998
82C814
OPTi
®
Page viii
912-3000-047
Revision: 1.0
January 08, 1998
82C814
List of Tables
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 4-6
Table 4-7
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 5-7
Table A-1
Table A-2
Signal Definitions Legend................................................................................................................2
Numerical Pin Cross-Reference List................................................................................................4
Alphabetical Pin Cross-Reference List ............................................................................................5
Strap Options for 82C814 Configurations......................................................................................10
Internal Keeper Resistor Scheme..................................................................................................11
Device Detection (CardBus Rules)................................................................................................14
CLKRUN# Control Bits ..................................................................................................................15
Translation Feature Configuration Bit............................................................................................15
Write Posting Associated Registers...............................................................................................16
Summary of Typical Settings (using IRQ5 for SMI).......................................................................18
Register used to Delay Internal PCICLK to Compensate for Trace Delays...................................20
Compaq SIRQ Control Bits............................................................................................................21
Base Register Group - PCICFG 00h-4Fh......................................................................................23
Specific Register Group - PCICFG 50h-5Fh..................................................................................32
CardBus Register Set in System Memory .....................................................................................34
CardBus Register Group - PCICFG 60h-74h / MEMOFST 00h-7Fh.............................................35
Docking Station Access Windows .................................................................................................37
Docking Station Window Registers - PCICFG 80h-EFh................................................................37
PCI Power Management Registers - PCICFG F0h-FFh................................................................41
Information Provided on a Driveback Cycle...................................................................................49
Information Provided on a Optional Data Phase 2 of IRQ Driveback Cycle..................................50
OPTi
®
912-3000-047
Revision: 1.0
Page ix
January 08, 1998
82C814
OPTi
®
Page x
912-3000-047
Revision: 1.0
January 08, 1998
OPTi
®
82C814
Docking Station Controller
1.0 Features
2.0 Overview
• Provides true hot docking and undocking
• PCI Power Management Compliant
• Supports 3.3V or 5.0V PCI dock
• Host PCI bus can be 3.3V or 5.0V
This document describes the OPTi 82C814 Docking Station
Controller, a true bridge docking solution that allows software
to treat the docking station like a dynamically insertable/
removable CardBus card.
• Host and Docking PCI buses can be asynchronous
• Works in conjunction with OPTi PCI-to-ISA bridge to pro-
vide reliable ISA support on the dock
The PCI software interface conforms to the CardBus header
layout, instead of the PCI-to-PCI bridge header layout, to
overcome the limitations of PCI-to-PCI bridges.
• Provides eight windows, selectable for memory or I/O
• Offers additional fixed window for VGA
• Supports INTA#, INTB#, INTC#, INTD#
• Supports four bus masters
• Generates PCI clocks for four devices
• Supports cascadeable docking with multiple 82C814 con-
trollers
The docking controller implements a true PCI-PCI bridge with
full buffering and synchronous or asynchronous operation.
Figure 2-1 illustrates the flexibility of the device, including its
ability to support multiple ISA buses when used with an OPTi
PCI-to-ISA Bridge.
Note: This document describes Revision 1.0 of the 82C814
• Bridge solution increases primary PCI bus bandwidth by
off-loading transactions into buffers
chip.
• Supports external bus arbiter for secondary PCI bus
• Packaged in 144-pin LQFP (Low-profile Quad Flat Pack)
Figure 2-1
Multiple ISA Bus Support and Cascadeable Docking
Host
Chipset
CPU
Local ISA Bus
PCI Bus 0
82C814
Docking
Station
PCI
LCD/SVGA
Controller
Sound
Chip
Controller
(Ports 340-35Fh)
PCI Bus 1
OPTi
PCI-ISA
Bridge
PCI
Device
82C814
Docking
Station
Controller
Docking ISA Bus
PCI Bus 2
Sound
Card
Network
Controller
(Ports 340-35Fh)
912-3000-047
Revision: 1.0
Page 1
January08,1998
82C814
3.0 Signal Definitions
The 82C814 chip provides a primary interface which is PCI-
based. It also provides an independent attachment interface,
which can be switched on and off dynamically.
Table 3-1
Mnemonic
Signal Definitions Legend
Description
CMOS
Dcdr
Ext
G
CMOS-level compatible
Decoder
3.1
Terminology/Nomenclature
Conventions
External
The “#” symbol at the end of a signal name indicates that the
active, or asserted state occurs when the signal is at a low
voltage level. When “#” is not present after the signal name,
the signal is asserted when at the high voltage level.
Ground
I
Input
I/O
Int
Input/Output
Internal
The terms “assertion” and “negation” are used extensively.
This is done to avoid confusion when working with a mixture
of “active low” and “active high” signals. The term “assert”, or
“assertion” indicates that a signal is active, independent of
whether that level is represented by a high or low voltage.
The term “negate”, or “negation” indicates that a signal is
inactive.
Mux
O
Multiplexer
Output
OD
Open drain (open-collector) CMOS-
level compatible
P
Power
The 82C814 has some pins that have multiple functions
(denoted by “+” in the pin name). These functions are either:
PD
PU
S
Pull-down resistor
Pull-up resistor
• cycle-multiplexed (always enabled and available when a
particular cycle is in progress),
Schmitt-trigger TTL-level compatible
TTL-level compatible
• a strap option (configured at reset),
• or selected via register programming.
TTL
The tables in this section use several common abbreviations.
Table 3-1 lists the mnemonics and their meanings.
OPTi
®
Page 2
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Figure 3-1
Pin Diagram
AD7
1
108
107
106
105
104
103
102
101
100
99
C/BE3#
AD24
AD6
2
AD5
3
AD25
AD4
AD3
4
AD26
5
AD27
AD2
6
AD28
GND
7
AD29
AD1
8
GND
AD0
9
AD30
CLKRUN#
IRQLATCH+INTA#
INTB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AD31
98
REQ#
97
GNT#
VENID+EXTCLK+INTC#
VCC
96
VCC
95
PCIRST#
CCD2#
CVS2
ENVCC3+INTD#
ENVCC5
CCD1#
94
93
92
CIRQSER
CCLKRUN#
PCIRQ3#
PCIRQ2#
GND
CVS1
91
CCLK0
90
82C814
GND
89
CAD0
88
CAD1
87
PCIRQ1#
PCIRQ0#
CGNT3#
CREQ3#
CGNT2#
CREQ2#
CGNT1#
CREQ1#
CGNT0#
CREQ0#
CRST#
CAD31
GND
CAD2
86
CAD3
85
CAD4
84
CAD5
83
CAD6
82
CAD7
81
CC/BE0#
CAD8
80
79
CAD9
78
CAD10
77
GND
76
CCLK1
75
C_VCC
CAD11
74
CCLK3
C_VCC
73
OPTi
®
912-3000-047
Revision: 1.0
Page 3
January 08, 1998
82C814
Table 3-2
Numerical Pin Cross-Reference List
Pin
No.
Pin
Type
Pin
No.
Pin
Type
Pin
No.
Pin
Type
Pin
No.
Pin
Type
Pin Name
Pin Name
Pin Name
Pin Name
1 AD7
I/O
I/O
I/O
I/O
I/O
I/O
G
35 C_VCC
P
73 C_VCC
P
O
G
I/O
O
I
111 AD23
112 AD22
113 AD21
114 AD20
115 AD19
116 GND
I/O
I/O
I/O
I/O
I/O
G
2 AD6
36 CAD11
37 CAD12
38 CAD13
39 CAD14
40 CAD15
41 CC/BE1#
42 CAD16
43 CPAR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
74 CCLK3
75 GND
3 AD5
4 AD4
76 CAD31
77 CRST#
78 CREQ0#
79 CGNT0#
80 CREQ1#
81 CGNT1#
82 CREQ2#
83 CGNT2#
84 CREQ3#
85 CGNT3#
86 PCIRQ0#
87 PCIRQ1#
88 GND
5 AD3
6 AD2
7 GND
O
I
117 AD18
118 AD17
119 AD16
120 C/BE2#
121 FRAME#
122 IRDY#
123 TRDY#
124 GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
8 AD1
I/O
I/O
I/O
I/O
I/O
I/O
O
9 AD0
O
I
10 CLKRUN#
11 IRQLATCH
INTA#
44 GND
45 CSERR#
46 CPERR#
47 CBLOCK#
48 CSTOP#
49 CDEVSEL#
50 CTRDY#
51 CIRDY#
52 GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
O
I
12 INTB#
13 VENID
EXTCLK
O
I
I
I
125 PCICLK
126 VCC
I
INTC#
I/O
P
G
I
P
14 VCC
89 PCIRQ2#
90 PCIRQ3#
91 CCLKRUN#
92 CIRQSER
93 CVS2
127 DEVSEL#
128 STOP#
129 LOCK#
130 PERR#
131 SERR#
132 PAR
I/O
I/O
I/O
I/O
O/OD
I/O
I/O
I/O
I/O
G
15 ENVCC3
INTD#
O
I
I/O
O
53 CCLK2
54 C_VCC
55 CFRAME#
56 CC/BE2#
57 CAD17
58 CAD18
59 CAD19
60 CAD20
61 CAD21
62 CAD22
63 CAD23
64 GND
O
I
16 ENVCC5
17 CCD1#
18 CVS1
19 CCLK0
20 GND
21 CAD0
22 CAD1
23 CAD2
24 CAD3
25 CAD4
26 CAD5
27 CAD6
28 CAD7
29 CC/BE0#
30 CAD8
31 CAD9
32 CAD10
33 GND
34 CCLK1
P
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
I
94 CCD2#
95 PCIRST#
96 VCC
I
O
I
133 C/BE1#
134 AD15
135 AD14
136 GND
G
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
97 GNT#
I
98 REQ#
O
I/O
I/O
G
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
99 AD31
137 AD13
138 AD12
139 AD11
140 AD10
141 AD9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
100 AD30
101 GND
102 AD29
103 AD28
104 AD27
105 AD26
106 AD25
107 AD24
108 C/BE3#
109 VCC
65 CC/BE3#
66 CAD24
67 CAD25
68 CAD26
69 CAD27
70 CAD28
71 CAD29
72 CAD30
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
142 AD8
143 C/BE0#
144 VCC
O
110 IDSEL
I
OPTi
®
Page 4
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 3-3
Alphabetical Pin Cross-Reference List
Pin
No.
Pin
Type
Pin
No.
Pin
Type
Pin
No.
Pin
Type
Pin
No.
Pin
Type
Pin Name
Pin Name
Pin Name
Pin Name
9 AD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
27 CAD6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
34 CCLK1
O
O
64 GND
G
8 AD1
6 AD2
28 CAD7
30 CAD8
53 CCLK2
74 CCLK3
75 GND
88 GND
G
O
G
5 AD3
31 CAD9
91 CCLKRUN#
49 CDEVSEL#
55 CFRAME#
79 CGNT0#
81 CGNT1#
83 CGNT2#
85 CGNT3#
10 CLKRUN#
51 CIRDY#
92 CIRQSER
43 CPAR
I
101 GND
116 GND
124 GND
136 GND
97 GNT#
110 IDSEL
12 INTB#
122 IRDY#
G
4 AD4
32 CAD10
36 CAD11
37 CAD12
38 CAD13
39 CAD14
40 CAD15
42 CAD16
57 CAD17
58 CAD18
59 CAD19
60 CAD20
61 CAD21
62 CAD22
63 CAD23
66 CAD24
67 CAD25
68 CAD26
69 CAD27
70 CAD28
71 CAD29
72 CAD30
76 CAD31
143 C/BE0#
133 C/BE1#
120 C/BE2#
108 C/BE3#
47 CBLOCK#
29 CC/BE0#
41 CC/BE1#
56 CC/BE2#
65 CC/BE3#
17 CCD1#
94 CCD2#
19 CCLK0
I/O
I/O
O
G
3 AD5
G
2 AD6
G
1 AD7
O
I
142 AD8
141 AD9
140 AD10
139 AD11
138 AD12
137 AD13
135 AD14
134 AD15
119 AD16
118 AD17
117 AD18
115 AD19
114 AD20
113 AD21
112 AD22
111 AD23
107 AD24
106 AD25
105 AD26
104 AD27
103 AD28
102 AD29
100 AD30
99 AD31
21 CAD0
22 CAD1
23 CAD2
24 CAD3
25 CAD4
26 CAD5
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
11 IRQLATCH+
INTA#
129 LOCK#
132 PAR
I/O
I/O
46 CPERR#
78 CREQ0#
80 CREQ1#
82 CREQ2#
84 CREQ3#
77 CRST#
125 PCICLK
86 PCIRQ0#
87 PCIRQ1#
89 PCIRQ2#
90 PCIRQ3#
95 PCIRST#
130 PERR#
98 REQ#
I
I
I
I
I
I
I
I
O
I
45 CSERR#
48 CSTOP#
50 CTRDY#
35 C_VCC
I/O
I/O
I/O
P
I/O
O
131 SERR#
128 STOP#
123 TRDY#
14 VCC
O/OD
I/O
I/O
P
54 C_VCC
P
73 C_VCC
P
18 CVS1
I
96 VCC
P
93 CVS2
I
109 VCC
P
127 DEVSEL#
I/O
O
126 VCC
P
15 ENVCC3+
INTD#
144 VCC
P
16 ENVCC5
121 FRAME#
7 GND
O
I/O
G
13 VENID+
EXTCLK+
INTC#
I/O
20 GND
G
33 GND
G
44 GND
G
I
52 GND
G
O
OPTi
®
912-3000-047
Revision: 1.0
Page 5
January 08, 1998
82C814
3.2
Signal Descriptions
3.2.1 Host Interface PCI Signals
Pin
No.
Signal
Type
Signal Name
Signal Description
AD[31:0]
99, 100,
102:107,
111:115,
117:119,
134, 135,
137:142,
1:6, 8, 9
I/O
Address and Data Lines 31 through 0: This bus carries the address during the
address phase and the data during the data phase of a PCI cycle. During the
address phase these pins are inputs only and during the data phase they are
I/Os.
C/BE[3:0]#
PAR
108,
120,
133, 143
I/O
I/O
I
Bus Command and Byte Enables 3 through 0: These inputs provide the com-
mand type information during the address phase and carry the byte enable infor-
mation during the data phase.
132
125
13
Parity: This bit carries parity information for both the address and data phases of
PCI cycles. During the address or data write phase of a PCI cycle this pin is an
input only. During the data read phase it acts as an output only.
PCICLK
VENID#
EXTCLK
PCI Clock: Provides timing for all transactions on the host PCI bus; normally
33MHz. This same clock can be used for timing the slot interfaces, or can be
divided. The slot interfaces can also run from the alternative EXTCLK input.
O
I
Drive Vendor ID: This pin can be used to enable an external tristate buffer to
drive vendor ID bits onto the PCI bus. This feature allows system card designers
to drive a unique PCI card ID for identification by software.
External Clock: Provides alternative clock source for transactions on the slot
interface PCI bus. The frequency can be any value but is usually 20MHz or
25MHz. It should be tied low if not used. This pin is automatically sensed just after
reset time to determine whether an external clock frequency is being applied. If
not, the function defaults to VENID#.
INTC#
I/O
I/O
See Section 3.2.4 for interrupt information.
CLKRUN#
10
11
Clock Run: Pulled low by any device needing to use the PCI bus. If no devices
pull this pin low, the host PCI bus controller is allowed to stop the PCICLK signal.
The interrupt logic of the 82C814 uses this signal to request a restart of PCICLK
in order to send an interrupt request.
IRQLATCH
I/O
Interrupt Latch: For use on chipsets without IRQ driveback capability, the
82C814 logic can drive this line low to drive ISA IRQ lines using an external latch.
This pin is also a strap option, refer to Section 5.3
INTA#
I/O
I/O
See Section 3.2.4 for interrupt information.
FRAME#
121
122
123
Cycle Frame: Driven by PCI bus masters to indicate the beginning and duration
of an access.
IRDY#
I/O
I/O
Initiator Ready: Asserted by the PCI bus master to indicate that it is ready to
complete the current data phase of the transaction.
TRDY#
Target Ready: Asserted by the PCI bus target (when the 82C814 is a slave) to
indicate that it is ready to complete the current data phase of the transaction. PCI-
type devices on the slot interfaces return CTRDY# to the 82C814, which in turn
drives TRDY# to the host. The 82C814 logic drives TRDY# directly for 82C814
configuration register accesses.
OPTi
®
Page 6
912-3000-047
Revision: 1.0
January 08, 1998
82C814
3.2.1 Host Interface PCI Signals (cont.)
Pin
No.
Signal
Type
Signal Name
Signal Description
STOP#
128
129
I/O
I/O
Stop: Used by the target to request that the master stop the current transaction
and retry it later. The 82C814 logic uses this mechanism to back-off from a
claimed cycle and generate, for example, an SMI through the IRQ driveback
cycle.
LOCK#
Lock: Indicates an atomic operation that may require multiple transactions to
complete. The signal can be asserted to the 82C814 by any host bus PCI master,
and is driven by the 82C814 logic in response to the current slot interface bus
master driving its CBLOCK# signal.
DEVSEL#
PERR#
127
130
131
I/O
I/O
Device Select: Driven by the 82C814 logic when it decodes its address as the
target of the current access via either positive or subtractive decoding.
Parity Error: All devices use this signal to report data parity errors during any PCI
transaction except a Special Cycle.
SERR#
O/OD
System Error: The 82C814 logic uses this line to report address parity errors,
data parity errors on the Special Cycle command, or any other system error
where the result will be catastrophic. This pin has an open drain output.
REQ#
98
O
Bus Request: The 82C814 logic uses this signal to gain control of the PCI bus.
The logic also uses this pin to generate an interrupt driveback request.
GNT#
IDSEL
97
I
I
Bus Grant: The system grants the bus to the 82C814 chip using this signal.
110
ID Select: This signal is the "chip select" for the controller. This input simply con-
nects to one of the upper address lines to select the controller for configuration
cycles.
PCIRST#
95
I
Reset: Main chip reset input.
3.2.2 Docking Control and Sense Signals
Pin
No.
Signal
Type
Signal Name
Signal Description
CCD1#
CCD2#
CVS1
17
94
18
93
16
15
I
I
Connection Detect 1 and 2, Voltage Sense 1 and 2: CCD1-2# and CVS1-2
are used to determine proper dock attachment and to sense its voltage.
I
CVS2
I
ENVCC5
ENVCC3
INTD#
O
O
I/O
5.0V VCC Enable: Used to turn on power to 5.0V dock.
3.3V VCC Enable: Used to turn on power to 3.3V dock.
See Section 3.2.4 for interrupt information.
3.2.3 PCI Docking Interface Pins
Pin
No.
Signal
Type
Signal Name
Signal Description
CAD[31:0]
76, 72:66,
63:57, 42,
40:36,
32:30,
28:21
I/O
Multiplexed Address and Data Lines 31 through 0: These pins are the multi-
plexed PCI address and data lines. During the address phase, these pins are
outputs for PCI slave cycles and inputs for PCI master cycles. During the data
phase, these pins are outputs during PCI write cycles and inputs during PCI
reads.
OPTi
®
912-3000-047
Revision: 1.0
Page 7
January 08, 1998
82C814
3.2.3 PCI Docking Interface Pins (cont.)
Pin
No.
Signal
Type
Signal Name
Signal Description
CRST#
77
O
Reset: Used to reset the docking station PCI bus. This signal defaults to
“asserted” until specifically programmed to go high.
CC/BE[3:0]#
CPAR
65, 56, 41,
29
I/O
Bus Command and Byte Enables 3 through 0: These pins are the multi-
plexed PCI command and byte enable lines. Normally outputs, these pins are
inputs during master cycles.
43
I/O
Parity: This signal is an input either during PCI slave cycles for address and
write data phases or during PCI master cycle for read data phase; otherwise it is
an output.
CCLK[3:0]
CFRAME#
CIRDY#
74, 53, 34,
19
O
Clock 3 through 0: These pins generate individual clocks to each PCI device
on the dock.
55
51
50
I/O
I/O
I/O
Cycle Frame: The 82C814 drives this signal to indicate the beginning and dura-
tion of an access.
Initiator Ready: The 82C814 drives this signal to indicate its ability to complete
the current data phase of the transaction.
CTRDY#
Target Ready: The 82C814 monitors this input from the slot interface slave
device to determine when it can complete the cycle. PCI devices on the slots
return CTRDY# to the 82C814 which in turn drives host TRDY#.
CSTOP#
48
47
49
46
45
I/O
I/O
I/O
I/O
I/O
Stop: This signal is used by the target to request the master to stop the current
transaction. The 82C814 will back-off the current cycle and retry it later.
CBLOCK#
CDEVSEL#
CPERR#
CSERR#
Bus Lock: The 82C814 uses this signal to indicate an atomic operation that
may require multiple transactions to complete.
Device Select: This signal is normally an input from the slot interface device
claiming the cycle. The 82C814 claims the cycle ahead of time on the host side.
Parity Error: All slot interface devices use this signal to report data parity
errors, during any PCI transaction except a Special Cycle.
System Error: All slot interface devices use this signal to report address parity
errors, data parity errors on the Special Cycle command, or any other system
error where the result will be catastrophic.
CEXT_GNT#
84
I
External Arbiter Grant Input: This signal is asserted by an external arbiter to
grant the secondary PCI bus to the 82C814. When using an external arbiter
CREQ[2:0]# and CGNT[2:0]# are not functional and should be pulled high.
CREQ3#
I
I
Bus Master Request Line 3: Request/grant signal pairs are provided to
accommodate up to four PCI bus masters on the docking station.
CREQ[2:0]#
CEXT_REQ#
82, 80, 78
85
Bus Master Request Lines 2 through 0: Request/grant signal pairs are pro-
vided to accommodate up to four PCI bus masters on the docking station.
O
External Arbiter Request Output: The 82C814 asserts this signal to request
the secondary PCI bus from an external arbiter. When using an external arbiter
CREQ[2:0]# and CGNT[2:0]# are not functional and should be pulled high.
CGNT3#
O
O
Bus Grant Line 3: Request/grant signal pairs are provided to accommodate up
to four PCI bus masters on the docking station.
CGNT[2:0]#
83, 81, 79
Bus Grant Lines 2 through 0: Request/grant signal pairs are provided to
accommodate up to four PCI bus masters on the docking station.
OPTi
®
Page 8
912-3000-047
Revision: 1.0
January 08, 1998
82C814
3.2.3 PCI Docking Interface Pins (cont.)
Pin
No.
Signal
Type
Signal Name
Signal Description
CCLKRUN#
91
I/O
CLKRUN signal for docking PCI devices: Pulled low by any device needing the
PCI bus. If no devices pull this pin low, the 82C814 logic is allowed to stop its
CCLK0-3 outputs.
3.2.4 Interrupt Interface Pins
Signal
Signal Name
Pin No.
Type
Signal Description
PCIRQ0#
PCIRQ1#
PCIRQ2#
PCIRQ3#
CIRQSER
INTA#
86
87
89
90
92
11
I
PCI Interrupt 0: From docking station, routed according to PCICFG 48h
PCI Interrupt 1: From docking station, routed according to PCICFG 49h
PCI Interrupt 2: From docking station, routed according to PCICFG 4Ah
PCI Interrupt 3: From docking station, routed according to PCICFG 4Bh
IRQ Serial: Single-wire Serial IRQ for docking station devices using serial IRQs
I
I
I
I/O
I/O
INTA#: IRQLATCH reassigned as Primary PCI INTA#. See Table 3-4 for strap
options.
INTB#
INTC#
INTD#
IRQSER
12
13
15
I/O
I/O
I/O
INTB#: NC pin reassigned as Primary PCI INTB#. See Table 3-4 for strap
options.
INTC#: VENID# pin reassigned as Primary PCI INTC#. See Table 3-4 for strap
options.
INTD#: ENVCC3 pin reassigned as Primary PCI INTD#. See Table 3-4 for strap
options.
IRQ Serial: INTD# reassigned as IRQSER - provides serial IRQ connection to
host bus core logic. Enabled in PCICFG 4Eh.
3.2.5 Power and Ground Pins
Signal
Signal Name
Pin No.
Type
Signal Description
Ground Connection
GND
7, 20, 33,
44, 52,
G
64,75, 88,
101, 116,
124, 136
VCC
14, 96,
109, 126,
144
P
P
Power Connection: For Host Interface
Power Connection: For Docking Interface
C_VCC
35, 54, 73
OPTi
®
912-3000-047
Revision: 1.0
Page 9
January 08, 1998
82C814
3.3
Strap-Selected Interface Options
The 82C814 CardBus Controller can be strapped to operate
in one of several different modes depending on its implemen-
tation in the system.
Note: For 5.0V core and PCI host interface designs that
use host PCI interrupts INTA#-D#, it may not be pos-
sible to strap the 82C814 into 5.0V mode if there is
an external pull-up on the host INTA# signal. For
these designs it is necessary to program the core
voltage to 5.0V by writing PCICFG 5Eh[4] = 1.
Strap options are registered at chip reset time. The selection
straps are normally 10k ohm resistors engaged full-time.
The strapping possibilities are listed in Table 3-4.
Table 3-4
Strap Options for 82C814 Configurations
Pulled by 10k ohm
Resistor at Reset
Strap Selection
Feature
No Strap
IRQLATCH
(PCI INTA#) Pin 11
Core Voltage Select
3.3V Core and PCI host interface
(internal pull up)
5.0V Core and PCI host interface
(external 10k ohm pull down)
PCI INTB#
Pin 12
PCI Interrupts
Use IRQ Driveback or IRQLATCH#
(internal pull down)
Provide INTA#-D#
(external 10k ohm pull up)
OPTi
®
Page 10
912-3000-047
Revision: 1.0
January 08, 1998
82C814
3.4
Internal Resistors
The 82C814 slot interfaces are provided with pull-up and pull-down resistors internal to the chip. The resistors are active at the
times indicated in Table 3-5.
Table 3-5 refers to the chip state with no card inserted, a powered-down card inserted, or a docking station attached.
Figure 3-2 shows the functional timing relationships of software power-up and reset commands to the signals output by the
power cycle state machine.
Table 3-5
Internal Keeper Resistor Scheme
82C814 Action with
82C814 Action after
Signal Group
No Attachment
Detecting Docking Station
Dock Detect:
CCD1-2#
Pull up to core VCC to detect dock
insertion/removal
Pull up to core VCC
Address/Data:
CAD[31:0]
CC/BE[3:0]#
CPAR
Pull down
Pull down until interface is powered up
Reset:
CRST#
Driven low
Pull down
Pull down
Driven according to PCICFG 3Eh[6]
Frame:
CFRAME#
None
None
PCI Control/Status:
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPERR#
CBLOCK#
Clock:
CCLK[3:0]
Pull down
Disable pull-down (clock input is
always driven)
Request:
CREQ[3:0]#
CSERR#
Pull up to card VCC
Pull up to card VCC
None
None
Open Drain:
Figure 3-2
Power-Up Timing
Software writes CardBus 010h[5:4] = 11 (3.3V select)
Pull-downs disabled
VCC3 output signal
CardBus 000h[3] = 1 (power cycle complete)
Pull-ups enabled, Output signals are driven
Software sees power cycle complete,
writes PCICFG 3Eh = 0 (deassert CRST#)
CRST#
OPTi
®
912-3000-047
Revision: 1.0
Page 11
January 08, 1998
82C814
OPTi
®
Page 12
912-3000-047
Revision: 1.0
January 08, 1998
82C814
4.0 Functional Description
compliant system. ISA DMA may require special software
support on non-OPTi systems.
4.1
OPTi Docking Station Controller
Chipset
The OPTi Docking Station solution is comprised of two
devices. The minimum configuration requires one chip, the
82C814 part.
4.3
Interface Overview
The OPTi 82C814 Docking Station Controller Chipset uses
two independent external interfaces. The terms host interface
and docking interface are used throughout this document to
describe these interfaces.
• The 144-pin 82C814 Docking Controller handles the signal
transfer for a complete PCI bus, including interrupts and
clock generation.
• The host interface provides industry standard PCI signals
to the host system. The interface also can be programmed
to return interrupt requests from the docking interfaces.
• The OPTi PCI-ISA Bridge converts PCI signals back into
ISA signals. No OPTi PCI-ISA Bridge is required in the
system, but one can be added as an option to support ISA
peripherals in an attached docking station that connects
through the PCI bus interface. The OPTi PCI-ISA Bridges
are discussed in a separate document.
• The docking interface duplicates the primary PCI signal
set. It is completely isolated from the primary PCI bus.
The interface signal groups used to integrate the OPTi Dock-
ing Station Controller Chipset into the standard system are
described in the following sections. Figure 4-1 illustrates the
interaction of the logic modules of the OPTi Docking Station
Controller Chipset.
The multiple interface arrangement offers the maximum in
system design flexibility.
4.2
Chipset Compatibility
Because the OPTi Docking Station Controller Chipset is
based on a PCI host interface, it can be used with any PCI-
Figure 4-1
82C814 Organization
PCI-to-CardBus
Bridge #0
PCI Ctrl, Address, Data
PCI
P
r
PCI Function #0
Cfg. Registers
S
e
c
o
n
d
a
r
i
m
a
r
Master Req
Bus Arbiter
Logic
IRQs
y
REQ#
D
o
c
k
i
H
o
s
t
GNT#
P
C
I
y
B
u
s
PCI Slots
ISA Slots
IRQ Driveback
Logic
P
C
I
n
g
P
C
I
OPTi
PCI-to-ISA
Bridge
PCICLK
B
u
s
Clock
PCIRQ[3:0]#
CCLK[3:0]
S
t
a
t
i
o
n
Generation
Logic
External
Clock
Source
OPTi
®
912-3000-047
Revision: 1.0
Page 13
January 08, 1998
82C814
The logic implements several functional blocks that interact
as indicated. The functional blocks shown in the diagram are
briefly described below.
• Devices connected to the docking interface can transmit
interrupts to the host system directly or through serial
IRQs. Docking station PCI devices can generate INTA#,
INTB#, INTC#, and INTD# which the 82C814 logic con-
verts to an interrupt.
• The 82C814 takes its control, address, and data informa-
tion from its primary PCI bus, which is usually controlled
by the host PCI interface but can also be controlled by a
master on the docking interface.
• Clock generation logic is provided to use either the pri-
mary PCICLK input for synchronous operation, or an
external clock input for asynchronous operation. Four sep-
arate output clocks are provided, and can be skew-com-
pensated to adjust for varying board trace lengths.
• The 82C814 logic implements a PCI-to-PCI (Card Bus)
bridge controlled by PCI Configuration Registers. These
configuration registers are accessed from the primary PCI
bus. Any bus master, including a master on the docking
interface, can program these registers. The PCI Configura-
tion Registers consist of standard CardBus registers at
indexes 00h-47h and OPTi 82C814 architecture-specific
registers at indexes 48h-FFh. Settings in these registers
control host interface operations, select architecture-spe-
cific settings such as interrupt routing to the host, and pro-
vide PCI status to the host on request. The register set is
accessed as PCI Function 0 of the 82C814 device.
The logic subsystems of the 82C814 Docking Station Con-
troller are described in detail in the following sections.
4.4
Device Type Detection Logic
The 82C814 logic includes attachment detection logic and a
power control state machine to determine what type of dock
has been attached to the docking interface.
The power control state machine follows the algorithm pro-
vided by the CardBus specification, with a slight modification
for docking station detection. Table 4-1 lists the device deter-
mination rules. Although the state machine follows the rules
for CardBus device detection, only docking stations are con-
sidered valid attachments.
• The PCI-to-PCI bridge serves to connect the primary PCI
bus to an independent secondary PCI bus. It is this sec-
ondary bus that interfaces externally to a docking station. If
no dock is attached, software can still access the configu-
ration registers for the bridge.
• The bus arbiter logic takes master requests for bus own-
ership for the purpose of giving PCI master control to one
of the secondary PCI buses.
Table 4-1
CCD2#
Device Detection (CardBus Rules)
CCD1#
CVS2
CVS1
Key
Card Type
GND
Short to CVS2
Short to CVS1
Short to CVS2
GND
Short to CVS1
GND
Open
Short to CCD2#
GND
Short to CCD1#
GND
LV
LV
3.3V CardBus
3.3/x.xV CardBus
3.3/x.x/y.yV CardBus
x.xV CardBus
GND
Short to CCD2#
Open
LV
GND
Short to CCD2#
Short to CCD1#
Open
LV
Short to CVS2
GND
Open
LV
x.x/y.yV CardBus
y.yV CardBus
Short to CVS1
GND
Short to CCD2#
Short to CCD1#
GND
LV
Short to CVS1
Short to CVS2
GND
GND
--
3.3V Docking Station
5.0V Docking Station
5.0V PCMCIA
GND
Short to CCD1#
Open
--
GND
Open
5.0V
LV
GND
GND
Open
GND
3.3V PCMCIA
GND
GND
Open
GND
5.0V
LV
3.3/5.0V PCMCIA
x.xV PCMCIA
GND
GND
GND
Open
GND
GND
GND
GND
LV
x.x/3.3V PCMCIA
x.x/3.3/5.0V PCMCIA
GND
GND
GND
GND
5.0V
OPTi
®
Page 14
912-3000-047
Revision: 1.0
January 08, 1998
82C814
4.5
Primary PCI Bus
The host interfaces to the 82C814 chip through the primary
PCI bus. This bus operates according to PCI standards,
including the later addition of the CLKRUN# signal. CLK-
RUN# is normally controlled by the host, but at certain times
can be driven low by the 82C814 chip when the chip is
requesting that PCICLK be restarted or sped up. Refer to the
PCI Mobile Design Guide for the requirements of CLKRUN#.
4.6.1.1 Translation Between Type 0 and Type 1
Configuration Cycles
The 82C814 logic converts Type 1 configuration cycles on
the host PCI bus to Type 1, Type 0, or a Special Cycle as is
typically required of a PCI-to-PCI bridge. However, in a PCI-
to-PCI bridge, Type 1 configuration cycles on the secondary
PCI bus can be converted only to Type 1 or Special Cycles
on the primary bus, never to Type 0.
CLKRUN# is controlled by PCICFG 50h[2].
The 82C814 logic is different from the standard PCI-to-PCI
bridge in this regard. The 82C814 allows the secondary to act
as a primary. PCICFG 52h[0] is used to enable this feature.
4.6
PCI-to-CardBus Bridge
The PCI-to-CardBus bridge circuit of the 82C814 chip recog-
nizes the cycle being performed by the current system bus
master and responds as required.
With this feature selected, master devices on the docking sta-
tion interface can program the PCI configuration registers of
the 82C814 (and any other PCI device on the host PCI bus).
To do so, the secondary bus master must generate a Type 1
configuration cycle. The 82C814 logic will pass this to the pri-
mary as a Type 0 configuration cycle. Since the 82C814 PCI
configuration registers sit on the primary, they are also acces-
sible this way. Thus, on the primary the 82C814 acts as both
initiator by generating the configuration cycle, and as target
by claiming the cycle it just generated.
4.6.1 Configuration Cycle
If the access is a configuration cycle, the PCI bridge simply
accesses the local PCI Configuration Register set directly.
The PCI cycle controller claims all configuration accesses to
PCI Function 0 of the 82C814 chip.
Note that secondary bus masters can access PCI configura-
tion registers on any primary bus device, not just the 82C814.
Table 4-2
7
CLKRUN# Control Bits
6
5
4
3
2
1
0
PCICFG 50h
PCI Host Feature Control Register
Default = 01h
CLKRUN# (on
host interface):
0 = Enabled
per PCI
1 = Disabled,
CLKRUN#
tristated
Table 4-3
7
Translation Feature Configuration Bit
6
5
4
3
2
1
0
PCICFG 52h
Docking Feature Control Register 2
Default = 0Fh
Type 1 to Type
0 conversion
blocked from
secondary to
primary:
0 = No
1 = Yes
(Default)
OPTi
®
912-3000-047
Revision: 1.0
Page 15
January 08, 1998
82C814
The 82C814 PCI configuration register set provides a register
to program the number of retries before the logic gives up
and generates SERR#, as shown in Table 4-4.
4.6.2 Cycle from Host to Docking Interface
For a cycle from the host to a docking interface with a dock-
ing station attached, the PCI bridge resynchronizes the cycle
and passes it to the external PCI device. Docking PCI
devices can run either synchronously at the host PCI fre-
quency, or asynchronously at any speed using an external
clock. The bridge claims the cycle if it falls into one of the
ranges programmed in the Window Registers of the PCI Con-
figuration Register set.
4.6.5 Cycle Termination by Target
The PCI-to-CardBus bridge logic responds to cycle termina-
tion by target devices in various ways for each transaction
type being terminated.
4.6.5.1 Posted Write Termination
Retry or Disconnect - The 82C814 logic retries the write cycle
at least 256 times, and may continue trying indefinitely,
according to the setting of PCICFG 5Eh[2:0]. When the logic
reaches the retry limit, it generates SERR# on the master
interface. No target abort will be signalled in the PCI Status
Register, but software can read 82C814-Specific Register
5Fh to determine whether the retry limit was exceeded.
4.6.3 Master Cycle from Docking Interface
For a master cycle from the docking interface, the 82C814
logic presents the cycle on the host PCI bus as master.
If the cycle is directed to a device on the other docking inter-
face, the 82C814 logic claims the cycle immediately, as a
slave, since the address ranges are already programmed into
the Base Address Registers for that docking station.
Target Abort or No Response - The logic generates
SERR#+CSERR# on the master interface. Software reads
the PCI Status Register to determine that a target abort
occurred.
If the cycle is not claimed by the other docking station and no
host device claims it, the 82C814 generates a master abort.
4.6.4 Inability to Complete a Posted Write
The 82C814 logic provides write posting in both the down-
stream and upstream PCI directions. There is a special situa-
tion that arises when the target of posted write data is unable
to complete the transaction. Normally, a target retry or a dis-
connect will result in the 82C814 logic retrying the access
until it has completed the transfer of posted data.
4.6.5.2 Non-Posted Write Termination
Retry, Disconnect, or Target Abort - The logic simply conveys
the target response to the initiator.
No Response - If PCICFG 3Eh[5] = 0, the 82C814 logic termi-
nates the cycle to the initiator normally. If bit 3Eh[5] = 1, the
logic generates target abort to the initiator.
However, after the programmed number of retries has been
attempted, the logic must report the error condition back to
the host. The 82C814 provides only one mechanism to return
the error: the SERR# pin. The host must then decide how to
handle the SERR# generation, either by generation of an
NMI or some other means.
4.6.5.3 Read (Prefetched or Non-Prefetched)
Termination
Retry, Disconnect, or Target Abort - The logic simply conveys
the target response to the initiator.
No Response - If PCICFG 3Eh[5] = 0, the 82C814 logic termi-
nates the cycle to the initiator normally and returns
FFFFFFFFh as the data read. If bit 3Eh[5] = 1, the logic gen-
erates target abort to the initiator.
Table 4-4
7
Write Posting Associated Registers
6
5
4
3
2
1
0
PCICFG 5Eh
Primary Retry Limit Register
Default = 07h
Retry Limit:
These bits relate to the number of times that the
82C814, as a slave, will retry accesses on the pri-
mary. If this limit is exceeded, the 82C814 gener-
ates SERR# to the host.
8
16
20
24
000=2
001=2
010=2
011=2
100=2
101=2
110=2
10
12
14
111= Infinite retries (Default)
OPTi
®
Page 16
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 4-4
7
Write Posting Associated Registers (cont.)
6
5
4
3
2
1
0
PCICFG 5Fh
82C814 Retry Count Readback Register (RO)
Default = 00h
-
-
-
-
This register returns the number of retry attempts made.
More than 256 retries are indicated by FFh.
Used for diagnostic purposes. Read-only.
Separate counts are maintained for primary and secondary. Bit 5Eh[3] selects the count being read back.
PCICFG 3Eh
Bridge Control Register - Byte 0
Default = 40h
Response to
master abort
on slot
interface:
0 = Ignore
1 = Signal with
target abort
or SERR#
4.7
PCI Docking Station Operation
OPTi docking is based on the CardBus concept: the docking
station can be treated like a CardBus card being plugged into
or removed from the system at any time. The docking inter-
face is fully isolated and allows the host system to recover in
case of problems on the dock.
4.7.2 Procedure
The docking concept follows the Yenta specification. How-
ever, a more flexible set of registers is available for docking
that allows eight windows instead of the four offered by
Yenta. Either the Yenta window registers (PCICFG 1C-3Bh)
or the docking registers (PCICFG 80-BFh) can be used. The
docking window registers also allow finer control over window
sizes than do the Yenta window registers.
Windows 98 and NT 5.0 fully supports 82C814 docking.
When using other operating systems, BIOS support software
is required. The rest of this section describes the basics of
the support software needed.
4.7.3 Initial Setup
The following programming should be performed at system
initialization time, and does not need to be repeated.
4.7.1 Introduction
The 82C814 register set follows the Yenta standard; the reg-
isters are virtually the same whether in CardBus mode or in
Docking mode. However, there are two differences from a
programming point of view.
• Enable Host Chipset Bus Preemption. Write SYSCFG
1Eh[3] = 1 on the Viper-N+ and FireStar chipsets.
• Establish Status Change Interrupt. Write PCICFG 4Ch
with the IRQ that should be generated when the dock is
attached or removed. Any available IRQ can be used. On
FireStar, selecting IRQ2 will generate an SMI and IRQ13
will generate an NMI. These selections are not available
on Viper-N+. However, normal IRQs can be programmed
on the Viper-N+ chipset to generate an SMI or NMI if
desired, through the following approach:
• A CardBus card can be identified as PCICFG 68h[5:4] =
10. A Docking Station is identified by PCICFG 68h[5:4] =
11.
• A CardBus card has only one interrupt, mapped to
PCIRQ0#. A Docking Station has four interrupt pins,
mapped through PCIRQ[3:0]#.
When a docking station is attached to the interface, the
power control state machine of the 82C814 recognizes the
docking station. A docking station is the only valid attachment
to the 82C814 chip.
1. Use SYSCFG 64h and A4h to select the IRQ to use for
SMI generation.
2. Write SYSCFG 57h[6] = 1 to enable INTRGRP to gener-
ate PMI#6 when the selected IRQ goes active.
3. Write SYSCFG 59h[5:4] = 11 to enable PMI#6 to gener-
ate SMI.
OPTi
®
912-3000-047
Revision: 1.0
Page 17
January 08, 1998
82C814
• Establish IRQ Driveback Address. Write PCICFG 54-
57h with an I/O address to use for IRQ driveback. The
default value is 33333330h, but any unused value is fine.
Ideally the address should be greater than FFFFh to pre-
vent conflicts with ISA I/O address space.
quate. Also write PCICFG 60h = 0Fh to clear any pending
events.
Table 4-5 summarizes the typical settings for system initial-
ization.
4.7.4 Action Upon Attachment of Dock
Write the same value to the IRQ Driveback registers in the
host chipset (Viper-N+ or FireStar). The registers are at
the same PCI offset, but different PCI device: PCIDV1 54-
57h.
At idle, with no device attached, the CD1-2# pins are pulled
high internal to the 82C814 chip. CVS1-2 are driven low. All
other interface lines are pulled low at this time; the docking
interface itself can remain unpowered. The 82C814 monitors
the CD1-2 lines to determine a docking event.
• Select PCI Bus Number of Docking Station. PCICFG
19h selects the PCI bus number on the secondary side of
the bridge. A value of 01h is typical.
When a docking station is attached, the 82C814 sees CD1#
and CD2# go low, because the docking station connector has
these lines hard-wired as follows:
• Select Total Number of Downstream Buses. PCICFG
1Ah selects the number of the last downstream PCI bus. A
value of 01h is typical.
• CD1# is connected to CVS1 for a 3.3V docking station, or
to CVS2 for a 5.0V docking station.
• Program the Time-out Value. PCICFG 1Bh should be set
• CD2# is connected to ground.
to FFh.
The 82C814 card detection sequencer waits for the time set
in PCICFG 50h[3], then performs a test on these lines to
determine the type of device attached. Once the test is com-
plete, the 82C814 generates an interrupt to the IRQ config-
ured in PCICFG 4Ch.
• Program the Latency Timer. PCICFG 0Dh should be set
to FFh.
• Select the Status Change Events. PCICFG 64h[3:0]
select the events that will cause a status change interrupt
in the future. Typically writing PCICFG 64h = 06h is ade-
Table 4-5
Register
Summary of Typical Settings (using IRQ5 for SMI)
Byte 3 Byte 2
Byte 1
Byte 0
82C814 Register
PCICFG 4Ch
PCICFG 54h
PCICFG 0Ch
PCICFG 18h
PCICFG 64h
PCICFG 60h
--
--
--
15h (IRQ5)
33h
--
33h
--
33h
FFh
01h
--
30h
--
FFh
--
01h
--
00h
06h
0Fh
--
--
--
Viper N+ Register (assuming IRQ5)
PCIDV1 54h
SYSCFG 64h
SYSCFG 57h
SYSCFG 59h
SYSCFG 1Eh
33h
--
33h
--
33h
--
30h
****1***b(IRQ5)
01**0000b
**11****b
****1***b
--
--
--
--
--
--
--
--
--
* These bits should be read first, then written to the same value.
OPTi
®
Page 18
912-3000-047
Revision: 1.0
January 08, 1998
82C814
4.8
Status Change Service Routine
Interrupt or SMI service software should perform the following
steps:
4. Select PCICLK skew through PCICFG 52h[7:4]. This
value will have to be determined according to the design
of the docking station. Depending on the type of PCICLK
routing used on the docking station, the internal clock
may need to be skewed 1-15ns.
1. Read PCICFG 68h[7, 5:4] to determine whether a dock-
ing station has been recognized.
Test: PCICFG 68h[7] = 0?
Yes - Device recognized.
No - Device not recognized. Go to “Retest” section.
5. Write PCICFG 3Eh[6] = 0 to deassert PCIRST# to the
dock.
The Docking Station devices can now be configured in the
usual manner for PCI devices.
Test: PCICFG 68[5:4] = 11?
Yes - Docking station recognized.
No - Not a docking station. Exit procedure so that Card-
Bus software can handle event.
4.8.2 Undocking Event
The following step should be followed if an undock event has
been detected.
2. Read PCICFG 68h[2:1]. The card detection sequencer
drives CVS1 and CVS2 low after detection, so CD1-2#
will stay low.
1. Test whether PCICFG 69h[0] = 1. If so, data may have
been lost in the undocking event.
Test: PCICFG 68h[2:1] = 00?
Yes - Docking confirmed.
No - A non zero value indicates that the connection is not
valid or that an undock event has taken place.
On an undock event, no other steps are necessary. The con-
troller automatically powers down the dock, tristates the inter-
face, and asserts the CRST# line.
4.8.3 Notes on Undocking
3. Read PCICFG 60h to determine the event that caused
the interrupt. Write this same value back to the register to
clear these events, and cause the IRQ line that was
active to go inactive. Also clear PMI event on host chipset
if this was an SMI.
When undocking, the user can notify the system software
(Windows 95) first so that the system software can turn off
the 82C814 docking side to make a graceful undock. This is
the safest scheme to implement but is not always practical in
a real system because of cost.
4. Test: Was docking confirmed in step 2?
If hot undocking is required without notifying the system soft-
ware, shorter CD1-2# pins are required on the docking con-
nector. The CD1-2# pins will change first. The 82C814 will
complete the current cycle on the secondary, and will not
attempt to start another.
Yes - Go to “Docking Event” section.
No - Force a retest by writing PCICFG 6Dh[6] = 1, and go
to step 1. If this is the second time through, then proceed
to “Undocking Event” section.
The undocking event generates an interrupt to the system, so
that software can check to determine if any posted write data
was left in the FIFO. PCICFG 5Fh returns the number of
retries attempted in flushing the FIFO, which can be used to
determine whether any data was left after the hot undock.
4.8.1 Docking Event
1. Read PCICFG 69h to determine the docking station volt-
age.
2. Power up the interface by writing PCICFG 70h[6:4] with
the correct VCC value. PCICFG 70h is typically written to
20h for a 5.0V docking station.
4.8.4 Retest
Whenever the result of a test is ambiguous, software should
force the controller to retest the detection pins. Force a retest
by writing PCICFG 6Dh[6] = 1, then start the full service rou-
tine over again. If after several times through this retest
sequence the status cannot be determined, assume an
“undocked” state.
3. Read PCICFG 68h again to check power cycling.
Test: PCICFG 68h[3] = 1?
Yes - Continue to next step.
No - There is a problem. Check PCICFG 69h[1] to see if
the VCC value chosen is allowable. If necessary, force a
retest and then start over at step 1.
OPTi
®
912-3000-047
Revision: 1.0
Page 19
January 08, 1998
82C814
4.8.5 PCI Clock Buffering
The 82C814 logic provides register settings PCICFG 52h[7:4]
to compensate for trace delays. Some compensation is gen-
erally required. Table 4-6 highlights the register used for com-
pensating trace delays.
Table 4-6
7
Register used to Delay Internal PCICLK to Compensate for Trace Delays
6
5
4
3
2
1
0
PCICFG 52h
Docking Feature Control Register 2
Default = 0Fh
Secondary PCICLK Skew:
This value selects the approximate delay, in nanoseconds, that the
internal secondary PCICLK must be skewed in order to compensate
for external buffer delays.
0000 = No delay
.....
0001 = 1ns
0010 = 2ns
1101 = 13ns
1110 = 14ns
1111 = 15ns
4.9
Interrupt Support
The 82C814 supports a total of three interrupt schemes from
the secondary PCI bus.
4.9.1 PCI INTx# Implementation
The PCI INTA#, INTB#, INTC#, and INTD# lines can be
mapped to any of the primary side PCIRQ[3:0]# lines.
PCICFG 48-4Ch provide controls for this mapping.
1. PCI interrupts INTA#, INTB#, INTC#, and INTD# can be
mapped internally to system PCIRQ[3:0]# lines.
4.9.2 IRQ Driveback Logic
2. PCI IRQ driveback cycles can generate any ISA inter-
rupt. The OPTi PCI-ISA Bridge uses this scheme to gen-
erate interrupts in a parallel format back to the host
controller via the 82C814 chip.
A detailed overview of the IRQ driveback cycle is provided in
Appendix A. The logic used to implement this mechanism is
relatively simple. The trigger events for a driveback cycle are
any transition on an interrupt line, or an SMI event as enabled
by the 82C814 configuration registers. The request goes to
the Request Arbiter logic, which always gives the driveback
cycle top priority. Once the REQ# pin is available, the
Request Arbiter asserts REQ# on behalf of the IRQ Drive-
back logic and toggles REQ# according to the driveback pro-
tocol discussed in Appendix A.
3. The Compaq Serial IRQ scheme uses a single wire,
IRQSER, along with the PCICLK to transmit interrupts in
a serial format.
The available schemes are described below.
Once the host PCI controller returns GNT#, the driveback
logic writes to the IRQ driveback address location specified in
the PCI configuration registers as shown in Appendix A.
OPTi
®
Page 20
912-3000-047
Revision: 1.0
January 08, 1998
82C814
high on the clock that immediately follows. Because of this
contention, OPTi cannot guarantee against chip hardware
failure if interrupts are shared in this mode.
4.9.3 Compaq Serial IRQ Implementation
The 82C814 chip supports the Compaq standard of Serial
IRQs. This one wire approach is very compact compared to
the Intel two-wire approach, but if two devices on the line
want to share the same interrupt, there may be brief conten-
tion since both devices drive the line low on one clock and
The Compaq Serial IRQ scheme requires the register bits.
shown in Table 4-7.
Table 4-7
7
Compaq SIRQ Control Bits
6
5
4
3
2
1
0
PCICFG 4Eh
Serial IRQ Control Register 1
Compaq SIRQ Compaq SIRQ Start frame width
Default = 00h
Compaq SIRQ Compaq SIRQ
HALT mode
request:
Compaq SIRQ
(Compaq Serial
IRQ scheme):
QUIET mode
request:
data frame
slots. Change
only when the
Serial IRQ logic
is disabled or in
Halt state.
in PCI clocks. Change this setting
only when Serial IRQ is disabled
or in Halt state.
0 = Active
1 = Halt
0 = Continuous
1 = Quiet
0 = Disable
1 = Enable
00 = 4 PCI clocks
01 = 6 PCI clocks
10 = 8 PCI clocks
11 = Reserved
0 = 17 slots
1 = 21 slots
PCICFG 4Fh
Serial IRQ Control Register 2
Default = 00h
Compaq SIRQ Compaq SIRQ
in HALT state
(RO)?
in QUIET state
(RO)?
0 = No
0 = No
1 = Yes
1 = Yes
QUIET - PCICFG 4Eh[6] requests the next Serial IRQ cycle
to be Continuous or Quiet mode. In mobile applications, use
Continuous mode only. This is to guarantee that the host
gains control of the Serial IRQ for suspend and APM stop
clock. In application where the PCI clock never stops, use
either mode. PCICFG 4Fh[6] can be read to determine the
current state of the logic.
At the end of the Data frame, the CSIRQ controller will sam-
ple the QUIET and HALT bits to determine whether the next
Compaq Serial IRQ cycle will be Continuous mode, Quiet
mode, or a temporary Halt state.
• If the next cycle is sampled to be Continuous mode,
IRQSER is asserted for three PCI clocks. Once the logic
enters Idle state, it checks whether the PMU stop PCI
clock request is pending. If so, the CSIRQ logic will stay in
the Idle state until the PMU request is removed.
HALT - PCICFG 4Eh[7] requests a temporary halt of the
Serial IRQ controller as soon as the current cycle has
returned to Idle state. Once in Halt state, the Serial IRQ con-
figuration can be changed. After the logic has been put in
Halt state, upon clearing this bit the logic will return to Contin-
uous mode. PCICFG 4Fh[7] can be read to determine the
current state of the logic.
• If the next cycle is sampled to be Quiet mode, IRQSER is
asserted for two PCI clocks. Once the logic enters Idle
state, it samples the IRQSER input to begin the Quiet
mode cycle. Since the 82C814 has no control of the Start
frame, this mode is not recommended for mobile applica-
tion.
4.9.3.1 Operation
The Compaq Serial IRQ protocol requires one additional PCI
sustained Tri-State pin, the IRQSER signal. For detailed
Serial IRQ operation, refer to the “Serialized IRQ for PCI Sys-
tems” specification.
• If the HALT bit is sampled active, then the CSIRQ logic
asserts IRQSER for three PCI clocks to tell all the Serial
IRQ devices that next cycle will be Continuous mode; the
logic then enters Halt state. In Halt state, CSIRQ configu-
ration can be changed. Clearing the HALT bit will immedi-
ately cause a Continuous mode Start frame to be
generated.
After setting PCICFG 4Eh[0] = 1 to enable Compaq Serial
IRQ (CSIRQ) mode, the CSIRQ controller initiates a Continu-
ous mode Start frame. During the Data frame, the CSIRQ
logic samples the IRQSER input for the corresponding SMI,
IOCHCK#, and IRQ values, and then passes the sampled
values to the primary.
Once enabled, the Compaq Serial IRQ logic operates all the
time when docked; no clock stop synchronization is needed.
OPTi
®
912-3000-047
Revision: 1.0
Page 21
January 08, 1998
82C814
OPTi
®
Page 22
912-3000-047
Revision: 1.0
January 08, 1998
82C814
5.0 82C814 Register Set
The 82C814 Docking Controller chip provides a single group
of programming registers, PCI-to-CardBus Bridge 0 Register
Group, accessed through a PCI Configuration Cycle to Func-
tion 0 of the chip. Consists of CardBus Controller Base Reg-
ister Group at PCICFG 00h-4Fh, 82C814-specific registers at
50h-5Fh, CardBus Control and Status Register Group at 60h-
7Fh, and Docking Station Window Register Group at 80h-
FFh. Note that the CardBus Control and Status Register
Group can also be accessed in system memory space.
disconnected from the interface (CCD1# and CCD2# both
high). However, the 82C814-specific registers at PCICFG
48h-5Fh control global configuration and remain set to their
programmed values even after a device is removed.
5.2
Base Register Group
The registers below represent the standard group required
for PCI peripheral device identification and configuration for a
PCI-to-CardBus bridge.
This register group is defined in the following subsections.
Note: In the tables that follow, all bits are R/W and their
default value is zero, unless otherwise specified.
R/W = Read/Write, RO = Read-only, and
WO = Write-only
5.1
Register State on Device Removal
As a general rule, all PCI configuration registers default to
their power-on reset value when the card or docking station is
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh
6
5
4
3
2
1
0
PCICFG 00h
PCICFG 01h
Vendor Identification Register (RO) - Byte 0
Vendor Identification Register (RO) Byte 1
Default = 45h
Default = 10h
PCICFG 02h
PCICFG 03h
Device ID (RO) - Byte 0
Device ID (RO) - Byte 1
Default = 14h
Default = C8h
PCICFG 04h
PCI Command Register - Byte 0
Default = 04h
Address/data
stepping:
PERR#
generation:
VGA palette
snoop:
Mem write and
Invalidate (RO):
Special Cycle
(RO):
Bus master by
docking inter-
faces:
Respond to
PCI mem
accesses:
Respond to
PCI I/O
accesses:
0 = Disable
(always)
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
(always)
0 = Disable
(always)
1 = Enable
(always)
0 = No
1 = Yes
0 = No
1 = Yes
PCICFG 05h
PCI Command Register - Byte 1
Reserved: Write bits as read.
Default = 00h
Fast back-to-
back (RO):
SERR#
generation:
0 = Disable
(always)
0 = Disable
1 = Enable
PCICFG 06h
PCI Status Register - Byte 0
Default = 10h
Fast back-to-
back capability
(RO):
Reserved (RO)
PCI Power
Management
Capability (RO)
Reserved (RO)
0 = No (always)
1 = Yes
(always)
PCICFG 07h
PCI Status Register - Byte 1
Default = 02h
Parity
error:
System
error:
Received
master abort:
Received
target abort:
Signalled
target abort:
DEVSEL# timing (RO):
PERR# active
as master:
00 = Fast
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
01 = Medium (always)
10 = Slow
0 = No
1 = Yes
11 = Reserved
Write 1 to clear Write 1 to clear Write 1 to clear Write 1 to clear Write 1 to clear
Write 1 to clear
OPTi
®
912-3000-047
Revision: 1.0
Page 23
January 08, 1998
82C814
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh (cont.)
6
5
4
3
2
1
0
PCICFG 08h
Revision Register (RO) Revision 1.0
Default = 10h
PCICFG 09h
PCICFG 0Ah
Programming Interface Class Code Register (RO)
Default = 00h
Default = 07h
Class Code Register (RO) - Byte 0
Subclass Code bits: = 07h (PCI-to-Cardbus Bridge)
PCICFG 0Bh
PCICFG 0Ch
PCICFG 0Dh
PCICFG 0Eh
Class Code Register (RO) - Byte 1
Default = 06h
Default = 00h
Default = 00h
Default = 02h
Base Class Code bits: = 06h (Bus Bridge)
Cache Line Size Register
Not implemented
Latency Timer Register
Indicates the time-out value for the primary PCI interface.
Header Type Register
Multi-function
device (RO):
Layout type for 10-3Fh bytes bits [6:0] = 02h (PCI-to-CardBus Header Layout)
0 = No (always)
PCICFG 0Fh
BIST Register
Default = 00h
Default = 00h
Not implemented
PCICFG 10h
CardBus Base Address Register - Byte 0: Address Bits [7:0]
CardBus Socket Status and Control Base Address Bits:
-
The 32-bit Cardbus Base Address Register selects the starting address in memory space of the CardBus socket status and
control registers.
-
-
Actual register addresses are calculated by adding the MEMOFST of the register to this base address.
Bits [11:0] are read-only and are always 0, to indicate that the registers occupy 4KB of non prefetchable system memory space and
starts on a 4KB boundary.
PCICFG 11h
PCICFG 12h
PCICFG 13h
CardBus Base Address Register - Byte 1: Address Bits [15:8]
CardBus Base Address Register - Byte 2: Address Bits [23:16]
CardBus Base Address Register - Byte 3: Address Bits [31:24]
Default = 00h
Default = 00h
Default = 00h
PCICFG 14h
Capabilities Pointer (RO)
Default = F0h
Indicates the offset in the PCICFG space for the location of the first item in the Capabilities Linked List. This location is PCICFG F0h.
PCICFG 15h
Reserved
Default = 00h
OPTi
®
Page 24
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh (cont.)
6
5
4
3
2
1
0
PCICFG 16h
PCI Secondary Bus Status Register - Byte 0
Default = 00h
Fast back-to-
back capability
on docking
Reserved (RO)
interface PCI
bus (RO):
0 = No (always)
PCICFG 17h
PCI Secondary Bus Status Register - Byte 1
Default = 02h
Parity error
on docking
interface
Received
system error on
docking inter-
face PCI bus:
Received mas-
ter abort on
docking inter-
face PCI bus
(RO):
Received
target abort on target abort on
docking inter-
face PCI bus
(RO):
Signalled
DEVSEL# timing on docking inter- PERR# active
face PCI bus (RO):
as master on
docking inter-
face PCI bus
(RO):
docking inter-
face PCI bus:
00 = Fast
PCI bus:
01 =Medium (always)
10 = Slow
0 = No
0 = No
0 = No
1 = Yes
1 = Yes
0 = No
0 = No
1 = Yes
11 = Reserved
0 = No
1 = Yes
1 = Yes
1 = Yes
Write 1 to clear Write 1 to clear
Write 1 to clear
PCICFG 18h
Primary PCI Bus Number Register
Default = 00h
-
-
-
Indicates the number of the PCI bus to which the host interface of the 82C814 chip is connected.
Defaults to 0.
The logic uses this value to determine whether Type 1 configuration transactions on the docking interface should be converted to Spe-
cial Cycle transactions on the host interface.
PCICFG 19h
Secondary PCI Bus Number Register
Default = 00h
-
-
-
Indicates the number of the PCI bus to which the docking interface of the 82C814 chip is connected.
Defaults to 0.
The logic uses this value to determine whether Type 1 configuration transactions on the host interface should be converted to Type 0
transactions on the docking interface.
PCICFG 1Ah
Subordinate Bus Number Register
Default = 00h
-
-
Indicates the number of the highest-numbered PCI bus on the docking interface side.
The 82C814 logic uses this value in conjunction with the Secondary Bus Number to determine when to respond to Type 1 configuration
transactions on the host interface and pass them onto the docking interface.
Defaults to 0.
-
PCICFG 1Bh
Latency Timer Register
Default = 00h
Default = 00h
Indicates the time-out value for the docking interface.
PCICFG 1Ch
Memory Window 0 Base Address Register - Byte 0: Address Bits [7:0]
Memory Window 0 Base Address Bits:
-
The 32-bit Memory Window 0 Base Address Register selects the start address of one of two possible CardBus memory windows to the
slot interface.
-
-
-
-
Bits [11:0] are read-only and are always 0.
The memory windows are globally enabled by bit 04h[1] (Command Register).
Prefetching is enabled by bit 3Fh[0] (Bridge Control Register) and defaults to "enabled."
The Limit address can be set below the Base address to individually disable a window.
PCICFG 1Dh
PCICFG 1Eh
PCICFG 1Fh
Memory Window 0 Base Address Register - Byte 1: Address Bits [15:8]
Memory Window 0 Base Address Register - Byte 2: Address Bits [23:16]
Memory Window 0 Base Address Register - Byte 3: Address Bits [31:24]
Default = F0h
Default = FFh
Default = FFh
OPTi
®
912-3000-047
Revision: 1.0
Page 25
January 08, 1998
82C814
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh (cont.)
6
5
4
3
2
1
0
PCICFG 20h
Memory Window 0 Limit Address Register - Byte 0: Address Bits [7:0
Default = 00h
Memory Window 0 Limit Address Bits:
-
-
-
The 32-bit Memory Window 0 Limit Address Register selects the end address of Memory Window 0.
Bits [11:0] are read-only and are always 0.
The minimum window size is always 4KB.
PCICFG 21h
PCICFG 22h
PCICFG 23h
Memory Window 0 Limit Address Register - Byte 1: Address Bits [15:8]
Memory Window 0 Limit Address Register - Byte 2: Address Bits [23:16]
Memory Window 0 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
Default = 00h
Default = 00h
PCICFG 24h
Memory Window 1 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Memory Window 1 Base Address Bits:
-
The 32-bit Memory Window 1 Base Address Register selects the start address of one of two possible CardBus memory windows to the
slot interface.
-
-
-
-
Bits [11:0] are read-only and are always 0.
The memory windows are globally enabled by bit 04h[1] (Command Register).
Prefetching is enabled by bit 3Fh[1] (Bridge Control Register) and defaults to "enabled."
The Limit address can be set below the Base address to individually disable a window.
PCICFG 25h
PCICFG 26h
PCICFG 27h
Memory Window 1 Base Address Register - Byte 1: Address Bits [15:8]
Memory Window 1 Base Address Register - Byte 2: Address Bits [23:16]
Memory Window 1 Base Address Register - Byte 3: Address Bits [31:24]
Default = F0h
Default = FFh
Default = FFh
PCICFG 28h
Memory Window 1 Limit Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Memory Window 1 Limit Address Bits:
-
-
-
The 32-bit Memory Window 1 Limit Address Register selects the end address of Memory Window 1.
Bits [11:0] are read-only and are always 0.
The minimum window size is always 4KB.
PCICFG 29h
PCICFG 2Ah
PCICFG 2Bh
Memory Window 1 Limit Address Register - Byte 1: Address Bits [15:8]
Memory Window 1 Limit Address Register - Byte 2: Address Bits [23:16]
Memory Window 1 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
Default = 00h
Default = 00h
PCICFG 2Ch
I/O Window 0 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 0 Base Address Bits:
RO:
Decoding:
-
The 32-bit I/O Window 0 Base Address Register selects the start address of one of two possible
CardBus I/O windows to the slot interface.
Always returns 0 = 16-bit
0. (AD[31:16] = 0)
-
The I/O windows are globally enabled by bit 04h[0] (Command Register).
1 = 32-bit
PCICFG 2Dh
PCICFG 2Eh
PCICFG 2Fh
I/O Window 0 Base Address Register - Byte 1: Address Bits [15:8]
I/O Window 0 Base Address Register - Byte 2: Address Bits [23:16]
I/O Window 0 Base Address Register - Byte 3: Address Bits [31:24]
Default = F0h
Default = FFh
Default = FFh
OPTi
®
Page 26
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh (cont.)
6
5
4
3
2
1
0
PCICFG 30h
I/O Window 0 Limit Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 0 Limit Address Bits:
RO:
Always returns 0.
-
-
The 32-bit I/O Window 0 Limit Address Register selects the end address of I/O Window 0.
The minimum window size is always 4 bytes.
PCICFG 31h
PCICFG 32h
PCICFG 33h
I/O Window 0 Limit Address Register - Byte 1: Address Bits [15:8]
I/O Window 0 Limit Address Register - Byte 2: Address Bits [23:16]
I/O Window 0 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
Default = 00h
Default = 00h
PCICFG 34h
I/O Window 1 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 1 Base Address Bits:
RO:
Decoding:
-
The 32-bit I/O Window 1 Base Address Register selects the start address of one of two possible
CardBus I/O windows to the slot interface.
Always returns
0.
0 = 16-bit
(AD[31:16] = 0)
-
The I/O windows are globally enabled by bit 04h[0] (Command Register).
1 = 32-bit
PCICFG 35h
PCICFG 36h
PCICFG 37h
I/O Window 1 Base Address Register - Byte 1: Address Bits [15:8]
I/O Window 1 Base Address Register - Byte 2: Address Bits [23:16]
I/O Window 1 Base Address Register - Byte 3: Address Bits [31:24]
Default = F0h
Default = FFh
Default = FFh
PCICFG 38h
I/O Window 1 Limit Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 1 Limit Address Bits:
RO:
Always returns 0.
-
-
The 32-bit I/O Window 1 Limit Address Register selects the end address of I/O Window 1.
The minimum window size is always 4 bytes.
PCICFG 39h
PCICFG 3Ah
PCICFG 3Bh
I/O Window 1 Limit Address Register - Byte 1: Address Bits [15:8]
I/O Window 1 Limit Address Register - Byte 2: Address Bits [23:16]
I/O Window 1 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
Default = 00h
Default = 00h
PCICFG 3Ch
Interrupt Line Register for Status Change
Default = 00h
-
-
This register is readable and writable per the PCI specification.
The logic does not use the value written to this register.
PCICFG 3Dh
Interrupt Pin Register for Status Change
Default = 01h
RO:
-
-
-
This register reflects the value written to PCICFG 4Ch.
It defaults to 01h, selecting PCIRQ0# for the status change (docking station attach/detach) interrupt.
If PCICFG 4Ch is written to select an ISA interrupt or no interrupt, this register returns 00h.
PCICFG 3Eh
Bridge Control Register - Byte 0
Default = 40h
Reserved
Force CRST#
cycling
on slot
interface:
Response to
master abort
on slot
Reserved:
Pass VGA
addresses
A0000-BFFFFh,
3B0-3BBh,
Reserved
Forwarding of
SERR# from
slot interface to
primary PCI
bus:
Response to
parity errors on
slot interface:
Write as read.
interface:
0 = Ignore
1 = Enable
3C0-3DFh:
0 = CRST# high 0 = Ignore
0 = No
1 = Yes
0 = Disable
1 = Enable
1 = Assert
CRST#
1 = Signal with
target abort
or SERR#
(Default)
OPTi
®
912-3000-047
Revision: 1.0
Page 27
January 08, 1998
82C814
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh (cont.)
6
5
4
3
2
1
0
PCICFG 3Fh
Bridge Control Register - Byte 1
Reserved. Write as read.
Default = 03h
Write posting:
Memory Win-
Memory Win-
dow 1 prefetch: dow 0 prefetch:
0 = Disable
1 = Enable
0 = Disable
0 = Disable
1 = Enable
(Default)
1 = Enable
(Default)
PCICFG 40h
Subsystem Vendor Register - Byte 0: Bits [7:0]
Default = 00h
Subsystem Vendor Bits:
-
-
The chipset responds to reads of this register with the first value written. The register can be written only once, then becomes read only.
If the option is selected, the EXTCLK pin can be used as DRVVENID# to enable external logic to drive this data onto the bus. In this
case, the chipset claims the access but does not drive any data.
PCICFG 41h
Subsystem Vendor Register - Byte 1: Bits [15:8]
Subsystem ID Register - Byte 0: Bits [7:0]:
Default = 00h
Default = 00h
PCICFG 42h
Subsystem ID
-
-
The chipset responds to reads of this register with the first value written. The register can be written only once, then becomes read only.
If the option is selected, the EXTCLK pin can be used as DRVVENID# to enable external logic to drive this data onto the bus. In this
case, the chipset claims the access but does not drive any data.
PCICFG 43h
Subsystem ID Register - Byte 1: Bits [15:8]
Reserved
Default = 00h
Default = 00h
Default = 01h
PCICFG 44h - 47h
PCICFG 48h
Docking PCIRQ0# Interrupt Assignment Register
Reserved
Using OPTi IRQ driveback mechanism:
Docking Interrupt Assignment (PCIRQ0# Default) - Interrupts from the docking
PCIRQ0# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode interrupt)
is selected, this IRQ must be programmed to Level mode on the host chipset.
Level Mode:
00000 = Disabled
00010 = PCIRQ1#
00100 = PCIRQ3#
00001 = PCIRQ0# (Default) 00011 = PCIRQ2#
00101-01111 = Rsrvd
Edge Mode: (Viper-N+)
10000 = IRQ0
10001 = IRQ1
10010 = IRQ2
10011 = IRQ3
10100 = IRQ4
10101 = IRQ5
10110 = IRQ6
10111 = IRQ7
11000 = IRQ8
11001 = IRQ9
11010 = IRQ10
11011 = IRQ11
11100 = IRQ12
11101 = IRQ13
11110 = IRQ14
11111 = IRQ15
Reserved
Using Host PCI INTA#-D# (PCICFG 50h[6]=1)
000 = Disabled
001 = INTA# (default)
010 = INTB#
011 = INTC#
100 = INTD#
101-111 = Reserved
OPTi
®
Page 28
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh (cont.)
6
5
4
3
2
1
0
PCICFG 49h
Docking PCIRQ1# Interrupt Assignment Register
Default = 02h
Reserved
Using OPTi IRQ driveback mechanism:
Docking PCIRQ1# Interrupt Assignment (PCIRQ1# Default) - Interrupts from the dock-
ing PCIRQ1# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode inter-
rupt) is selected, this IRQ must be programmed to Level mode on the host chipset.
Level Mode:
00000 = Disabled
00001 = PCIRQ0#
00010 = PCIRQ1# (Default) 00100 = PCIRQ3#
00011 = PCIRQ2#
00101-01111 = Rsrvd
Edge Mode: (Viper-N+)
10000 = IRQ0
10001 = IRQ1
10010 = IRQ2
10011 = IRQ3
10110 = IRQ6
10111 = IRQ7
11000 = IRQ8
11001 = IRQ9
11010 = IRQ10
11011 = IRQ11
11100 = IRQ12
11101 = IRQ13
11110 = IRQ14
11111 = IRQ15
10100 = IRQ4
10101 = IRQ5
Reserved
Using Host PCI INTA#-D# (PCICFG 50h[6]=1)
000 = Disabled
001 = INTA#
011 = INTC#
100 = INTD#
010 = INTB# (default)
101-111 = Reserved
PCICFG 4Ah
Docking PCIRQ2# Interrupt Assignment Register
Default = 03h
Reserved
Using OPTi IRQ driveback mechanism:
Docking PCIRQ2# Interrupt Assignment (PCIRQ2# Default) - Interrupts from the dock-
ing PCIRQ2# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode inter-
rupt) is selected, this IRQ must be programmed to Level mode on the host chipset.
Level Mode:
00000 = Disabled
00001 = PCIRQ0#
00010 = PCIRQ1#
00011 = PCIRQ2# (Default) 00101-01111 = Rsrvd
00100 = PCIRQ3#
Edge Mode: (Viper-N+)
10000 = IRQ0
10001 = IRQ1
10010 = IRQ2
10011 = IRQ3
10110 = IRQ6
10111 = IRQ7
11000 = IRQ8
11001 = IRQ9
11010 = IRQ10
11011 = IRQ11
11100 = IRQ12
11101 = IRQ13
11110 = IRQ14
11111 = IRQ15
10100 = IRQ4
10101 = IRQ5
Reserved
Using Host PCI INTA#-D# (PCICFG 50h[6]=1)
000 = Disabled
001 = INTA#
010 = INTB#
011 = INTC# (default)
100 = INTD#
101-111 = Reserved
OPTi
®
912-3000-047
Revision: 1.0
Page 29
January 08, 1998
82C814
Table 5-1
7
Base Register Group - PCICFG 00h-4Fh (cont.)
6
5
4
3
2
1
0
PCICFG 4Bh
Docking PCIRQ3# Interrupt Assignment Register
Default = 04h
Reserved
Using OPTi IRQ driveback mechanism:
Docking PCIRQ3# Interrupt Assignment (PCIRQ3# Default) - Interrupts from the dock-
ing PCIRQ3# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode inter-
rupt) is selected, this IRQ must be programmed to Level mode on the host chipset.
Level Mode:
00000 = Disabled
00001 = PCIRQ0#
00010 = PCIRQ1#
00011 = PCIRQ2#
00100 = PCIRQ3# (Default)
00101-01111 = Rsrvd
Edge Mode: (Viper-N+)
10000 = IRQ0
10001 = IRQ1
10010 = IRQ2
10011 = IRQ3
10110 = IRQ6
10111 = IRQ7
11000 = IRQ8
11001 = IRQ9
11010 = IRQ10
11011 = IRQ11
11100 = IRQ12
11101 = IRQ13
11110 = IRQ14
11111 = IRQ15
10100 = IRQ4
10101 = IRQ5
Reserved
Using Host PCI INTA#-D# (PCICFG 50h[6]=1)
000 = Disabled
001 = INTA#
010 = INTB#
011 = INTC#
100 = INTD# (default)
101-111 = Reserved
PCICFG 4Ch
Docking Detect Interrupt Assignment Register
Reserved Using OPTi IRQ driveback mechanism:
Default = 01h
Host controller
type:
Interrupt Pin
Requested in
PCICFG 3Dh
Docking Detect Interrupt Assignment - If attachment of a docking station is detected, or
if the device attached could not be determined, this interrupt will be generated. This
same interrupt will be generated when the docking station is removed.
0 = FireStar
(burst two data
phases)
0 = equal to
Level Mode
selections in
PCICFG
Level Mode:
1 = Viper-N+
(send single
data phase on
IRQ driveback)
00000 = Disabled
00001 = PCIRQ0# (Default)
00010 = PCIRQ1#
00100 = PCIRQ3#
00101 = ACPI0
00110 = ACPI1
00111 = ACPI2
01000 = ACPI3
01001-01111 = Rsrvd
4Ch[4:0]
1 = Always 01
00011 = PCIRQ2#
Edge Mode: (Viper-N+)
10000 = IRQ0
10001 = IRQ1
10010 = IRQ2
10011 = IRQ3
10110 = IRQ6
10111 = IRQ7
11000 = IRQ8
11001 = IRQ9
11010 = IRQ10
11011 = IRQ11
11100 = IRQ12
11101 = IRQ13
11110 = IRQ14
11111 = IRQ15
10100 = IRQ4
10101 = IRQ5
Reserved
Using Host PCI INTA#-D# (PCICFG 50h[6]=1)
000 = Disabled
001 = INTA# (default)
010 = INTB#
011 = INTC#
100 = INTD#
101-111 = Reserved
PCICFG 4Dh
PCICFG 4Eh
Serial IRQ Enable Register
Default = 00h
Test Bits (for factory use only)
Reserved
IRQSER on pin
15
0 = Disabled
1 = Enabled
Serial IRQ Control Register 1
Default = 00h
OPTi
®
Page 30
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-1
Base Register Group - PCICFG 00h-4Fh (cont.)
7
6
5
4
3
2
1
0
Compaq SIRQ Compaq SIRQ
Reserved
Compaq SIRQ Compaq SIRQ Start frame width
Reserved
Compaq SIRQ
(Compaq Serial
IRQ scheme):
HALT mode
request:
QUIET mode
request:
data frame
slots. Change
only when the
Serial IRQ logic
is disabled or in
Halt state.
in PCI clocks. Change this setting
only when Serial IRQ is disabled
or in Halt state.
0 = Active
1 = Halt
0 = Continuous
1 = Quiet
0 = Disable
1 = Enable
00 = 4 PCI clocks
01 = 6 PCI clocks
10 = 8 PCI clocks
11 = Reserved
0 = 17 slots
1 = 21 slots
PCICFG 4Fh
Serial IRQ Control Register 2 And External Arbiter Enable
Default = 00h
Compaq SIRQ Compaq SIRQ
Reserved
External Arbiter
on secondary
PCI:
in HALT state
(RO)?
in QUIET state
(RO)?
0 = No
1 = Yes
0 = No
1 = Yes
0 = Disable
1 = Enable
5.3.3 Dual ISA Buses
5.3
82C814-Specific Register Group
Dual ISA buses are possible with the 82C814 chip used in
conjunction with the OPTi PCI-ISA Bridge chips. This feature
depends on the ISA Windows feature of the 82C814 chip,
which allows cycles destined for the remote docking ISA bus
to be claimed with positive decoding from the primary PCI
bus and then retried. If the cycle turns out not to be destined
for the docking ISA bus, the 82C814 chip ignores the next
retry so that the cycle will be claimed using subtractive
decode by the host chipset.
The 82C814 defines many special functions that require
enabling and monitoring through a dedicated register set.
The 82C814-specific registers at PCICFG 50h-5Fh remain
set to their programmed values even after a device is
removed from the slot. Also, PCICFG 50h is common to both
slot interfaces (i.e. changing the bit in one PCI register set
changes it in the other).
The following subsections discuss some of the special func-
tions located in the 82C814-Specific Register Group.
The FireStar chip provides an additional feature that allows
positive decode of cycles to known local ISA devices. This
feature would conflict with the positive decode used by the
82C814 chip. Therefore, the 82C814 chip has the option of
decoding on the slow clock instead of on the medium clock.
This feature is enabled by writing PCICFG 5Eh[7] = 1.
5.3.1 CLKRUN#
PCICFG 50h[2] selects whether the CLKRUN# signal to the
host will toggle. Normally it will be set for automatic operation.
In this mode, the 82C814 logic asserts CLKRUN# only when
it wants bus ownership for master cycles, or when it has an
interrupt it must send to the host. At all other times, it leaves
CLKRUN# tristated and depends on the current PCI bus
master to assert CLKRUN# and keep the clock running.
When the feature is selected, the 82C814 logic will monitor
the DEVSEL# line to determine whether FireStar (or anyone
else) has claimed the cycle by fast or medium decode. Only if
DEVSEL# remains high through the medium decode clock
will the 82C814 chip claim the cycle.
5.3.2 Slot Buffer Enable, Slew Rate, and
Threshold Control
The slow decode feature works only for windows enabled as
ISA windows. Other windows will continue to use a medium
decode.
PCICFG 51h[2:0] are automatically updated by the card
insertion state machine according to whether a 5.0V or 3.3V
dock has been detected using CD1-2# and VS1-2. Once the
card has been inserted and detected, and the interface auto-
matically set appropriately, software can still override the
automatic settings by reading and then writing PCICFG
51h[2:0] as desired.
OPTi
®
912-3000-047
Revision: 1.0
Page 31
January 08, 1998
82C814
Table 5-2
Specific Register Group - PCICFG 50h-5Fh
7
6
5
4
3
2
1
0
PCICFG 50h
PCI Host Feature Control Register
Default = 00h
Reserved
Primary INTA#-
INTD# Select
Vendor ID
feature
IRQLATCH
function
Docking detect CLKRUN# (on
CRST# and
MEMOFST 010
bits [2:0]
debounce:
host interface): ENVCC5 Con-
selected:
trol
0 = No (pin 12
pulled down)
0 = Disable
(default)
0 = 1.0 sec
1 = 0.25 sec
0 = Enabled
per PCI
0 = Read/Write
1 = Read only
0 = No
0 = Normal
1 = Yes
1 = Yes (pin 12
pulled up)
1 = Enable
1 = Disabled,
CLKRUN#
tristated
1 = Force both
signals high,
ignore PCICFG
3Eh[6] and
MEMOFST
070h
PCICFG 51h
Docking Feature Control Register 1
Default = 04h
Dock Interface clock divisor:
Dock Interface-
clock source:
Mode
select:
CCLKRUN# on Dock Interface
Output Drive Select:
dock interface
0 = Disabled
1 = Enabled
threshold
voltage:
00 = 1 (Default)
01 = 2
10 = 3
00 = Reserved
01 = Reserved
10 = 3.3V PCI dock
11 = 5.0V PCI dock
0 = PCICLK
1 = EXTCLK
0 = Automatic
1 = Force async
0 = 3.3V
1 = 5.0V
11 = 4
These bits retain their previously written value
regardless of dock attachment/removal.
PCICFG 52h
Docking Feature Control Register 2
Default = 4Fh
Secondary PCICLK Skew:
Block Prefetch
Block Posted
Writes on
Downstream
Transactions
Enabled
delayed Trans-
actions
Type 1 to Type
0 conversion
blocked from
secondary to
primary:
on Down-
stream Trans-
actions
This value selects the approximate delay, in nanoseconds, that the
internal secondary PCICLK must be skewed in order to compensate
for external buffer delays.
0 = Only when
window
selected as
ISA window
0 = No
0 = No
0000 = No delay
.....
1101 = 13ns
0001 = 1ns
0010 = 2ns
0 = No
1 = Yes
(default)
1 = Yes
(default)
1110 = 14ns
1111 = 15ns
1 = Yes
1 = On all win-
dows when-
ever retry
(Default)
Controls mem- Controls mem-
ory windows 0
& 1 only
ory windows 0
& 1 only
count exceeds
50% of retry
limit (PCICFG
5Eh[2:0]).
(default)
PCICFG 53h
Docking Feature Control Register 3
Default = 00h
Event signalled when PCICFG
3Eh[6] is changed
Event signalled when CD1-2#
change states
Event signalled on read of
MEMOFST 0-FFFh
Event signalled on write of
MEMOFST 0-FFFh
00 = None
00 = None
01 = SMI#
00 = None
00 = None
01 = SMI#
01 = SMI#
01 = SMI#
10 = ACPI1 (DOCK#)
11 = ACPI2 (STSCHG#)
10 = ACPI1 (DOCK#)
10 = ACPI1 (DOCK#)
11 = ACPI2 (STSCHG#)
10 = ACPI1 (DOCK#)
11 = ACPI2 (STSCHG#)
11 = ACPI2 (STSCHG#)
Note: SMI# is available through IRQ Driveback or Serial IRQ; ACPI1 and ACPI2 are available only through IRQ Driveback
OPTi
®
Page 32
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-2
7
Specific Register Group - PCICFG 50h-5Fh (cont.)
6
5
4
3
2
1
0
PCICFG 54h
IRQ Driveback Address Register - Byte 0: Address Bits [7:0]
Default = 30h
IRQ Driveback Protocol Address Bits:
-
When the 82C814 logic must generate an interrupt from any source, it follows the IRQ Driveback Protocol and toggles the REQ# line to
the host. Once it has the bus, it writes the changed IRQ information to the 32-bit I/O address specified in this register. The host interrupt
controller claims this cycle and latches the new IRQ values.
-
-
Bits 2:0 are reserved to be 000 and are read-only.
This register defaults to a value of 33333330h.
PCICFG 55h
PCICFG 56h
PCICFG 57h
IRQ Driveback Address Register - Byte 1: Address Bits [15:8]
IRQ Driveback Address Register - Byte 2: Address Bits [23:16]
IRQ Driveback Address Register - Byte 3: Address Bits [31:24]
Default = 33h
Default = 33h
Default = 33h
PCICFG 58h
DRQ Remap Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
DRQ Remap Base Address Bits:
-
The distributed DMA protocol requires DMA controller registers for each DMA channel to be individually mapped into I/O space outside
the range claimed by ISA devices. Bits A[31:0] of this register specify that base; bits 7:0 are reserved (write 0) because the base
address can fall only on 256 byte boundaries.
-
The 82C814 logic uses this base address to forward accesses across the bridge to remote devices specified in the DMA Channel Selec-
tor Register.
PCICFG 59h
PCICFG 5Ah
PCICFG 5Bh
DRQ Remap Base Address Register - Byte 1: Address Bits [15:8]
DRQ Remap Base Address Register - Byte 2: Address Bits [23:16]
DRQ Remap Base Address Register - Byte 3: Address Bits [31:24]
Default = 00h
Default = 00h
Default = 00h
PCICFG 5Ch
DMA Channel Selector Register
Default = 00h
Channel 7
(DMAC2):
Channel 6
(DMAC2):
Channel 5
(DMAC2):
DMAC respon-
sibility (RO):
Channel 3
(DMAC1):
Channel 2
(DMAC1):
Channel 1
(DMAC1):
Channel 0
(DMAC1):
0 = Not claimed 0 = Not claimed 0 = Not claimed 0 = Secondary 0 = Not claimed 0 = Not claimed 0 = Not claimed 0 = Not claimed
(always)
1 = On slot
interface
1 = On slot
interface
1 = On slot
interface
1 = On slot
interface
1 = On slot
interface
1 = On slot
interface
1 = On slot
interface
1 = Master
PCICFG 5Dh
SMI Status Register (Write 1 to clear bit)
Default = 00h
Toggling of
PCICFG 3Eh[6]
Generated SMI
Dock/Undock
Event Gener-
ated SMI
Read of Card-
Bus Registers
(MEMOFST
0=FFFh) Gen-
erated SMI
Write of Card-
Bus Registers
(MEMOFST
0=FFFh) Gen-
erated SMI
Docking Win-
dow 3
Docking Win-
dow 2
Docking Win-
dow 1
Docking Win-
dow 0
generated SMI: generated SMI: generated SMI: generated SMI:
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
0 = No
1 = Yes
1 = Yes
OPTi
®
912-3000-047
Revision: 1.0
Page 33
January 08, 1998
82C814
Table 5-2
7
Specific Register Group - PCICFG 50h-5Fh (cont.)
6
5
4
3
2
1
0
PCICFG 5Eh
Primary Retry Limit Register
Default = 00h
Slow decode for
ISA windows:
Prefetch on
upstream
transactions:
Posted writes
on upstream
transactions:
Core voltage:
Retry count
readback
control:
Retry Limit:
0 = 3.3V
1 = 5.0V
These bits relate to the number of times that the
82C814, as a slave, will retry accesses on the pri-
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Write post- mary. If this limit is exceeded, the 82C814 gener-
ing retries
on second-
ary
ates SERR# to the host.
8
16
20
24
000=2
001=2
010=2
011=2
100=2
10
12
14
101=2
110=2
1 = Retries on
primary
111= Infinite retries (Default)
PCICFG 5Fh
82C814 Retry Count Readback Register (RO)
Default = 00h
-
-
-
-
This register returns the number of retry attempts made.
More than 256 retries are indicated by FFh.
Used for diagnostic purposes. Read-only.
Separate counts are maintained for primary and secondary. Bit 5Eh[3] selects the count being read back.
Write-Only: This register is also writable, for factory diagnostic purposes only.
Status Change Initialization
When PCICFG PCI Retry Test
Prototype test
mode:
Force FIFO
clear
Retry test
times:
Power-up and
detect timer:
51h[3]=1
0 = Disable
1 = Enable
0 = Old scheme
1 = New
0 = Original
1 = Variation
0 = Automatic
Mode
0 = Disable
1 = Enable
0 = Normal
1 = Quick*
0 = Normal
1 = Quick
1 = Sync mode
*
Quick Mode will not function unless PCICFG 5Eh[2:0] is zero.
5.4
CardBus Register Group
The CardBus-style control and status register group is acces-
sible through two different means. It is always accessible as
part of the PCI configuration space at the indexes shown in
Table 5-4. In addition, when the CardBus register base
address at PCICFG 14h is written to any value other than
zero, these same registers can be accessed through the sys-
tem memory space selected (see Table 5-3).
5.4.1 Power Control
PCICFG 70h[6:4] set the external VCC5 and VCC3 pin lev-
els. Because only these two pins are available on the 82C814
interface, the system must be designed to interpret these sig-
nals properly and select the correct voltage for the applica-
tion.
Note that when accessing these registers in PCI memory
space, they start from an offset of 00h, not 60h, from the reg-
ister base address programmed.
Table 5-3
CardBus Register Set in System
Memory
CardBus Base
Address plus:
Name
000h
Socket Event Register
Socket Mask Register
Socket Present State Register
Force Event Register
Control Register
004h
008h
00Ch
010h
014-7FFh
Reserved
OPTi
®
Page 34
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-4
CardBus Register Group - PCICFG 60h-74h / MEMOFST 00h-7Fh
7
6
5
4
3
2
1
0
PCICFG 60h / MEMOFST 00h
Reserved:
Write as read.
Socket Event Register - Byte 0
Default = 00h
Power cycle
complete:
CCD2#
CCD1#
Reserved:
status change: status change:
0 = No
0 = No
0 = No
1 = Yes
1 = Yes
1 = Yes
Write 1 to clear Write 1 to clear Write 1 to clear
PCICFG 61h / MEMOFST 01h
Socket Event Register - Byte 1
Default = 00h
Default = 00h
Default = 00h
Reserved: Write as read.
PCICFG 62h / MEMOFST 02h
PCICFG 63h / MEMOFST 03h
Socket Event Register - Byte 2
Reserved: Write as read.
Socket Event Register - Byte 3
Reserved. Write as read.
PCICFG 64h / MEMOFST 04h
Socket Mask Register - Byte 0
Default = 00h
Reserved:
Write as read.
Power cycle
status change
event:
CCD2#
status change
event:
CCD1#
status change
event:
Reserved
0 = Mask
0 = Mask
0 = Mask
1 = Enable
1 = Enable
1 = Enable
PCICFG 65h / MEMOFST 05h
Socket Mask Register - Byte 1
Default = 00h
Default = 00h
Default = 00h
Reserved: Write as read.
PCICFG 66h / MEMOFST 06h
PCICFG 67h / MEMOFST 07h
Socket Mask Register - Byte 2
Reserved: Write as read.
Socket Mask Register - Byte 3
Reserved: Write as read.
PCICFG 68h / MEMOFST 08h
Socket Present State Register (RO) - Byte 0
Default = 00h
Dock recog-
nized - updated
only on card
insertion:
PCIRQ# Status
0 = At least one
of PCIRQ0-3# 11 = Docking station
Device type - updated only on
card insertion:
Power cycle
status:
CCD2-1# state:
Reserved
00 = Dock attached
0 = Not suc-
cessful
01 = No dock attached
10 = No dock attached
11 = No dock attached
is low
All other combinations reserved
0 = Yes
1 = No
1 = PCIRQ0-3#
are all high
1 = Successful
PCICFG 69h / MEMOFST 09h
Socket Present State Register - Byte 1
Default = 00h
Reserved:
Reserved
3.3V dock
detected:
5.0V dock
detected:
Bad VCC
request(outside
CVS1-2,
Data lost (dock
detached
before transac-
tion completed):
Write as read.
0 = No
1 = Yes
0 = No
1 = Yes
CCD1-2#
range):
0 = No
0 = No
1 = Maybe
1 = Yes
PCICFG 6Ah / MEMOFST 0Ah
PCICFG 6Bh / MEMOFST 0Bh
Socket Present State Register - Byte 2
Default = 00h
Default = 30h
Reserved: Write as read.
Socket Present State Register - Byte 3 (bits are writeable)
OPTi
®
912-3000-047
Revision: 1.0
Page 35
January 08, 1998
82C814
Table 5-4
CardBus Register Group - PCICFG 60h-74h / MEMOFST 00h-7Fh
7
6
5
4
3
2
1
0
Socket can sup- Socket can sup-
Socket can
Socket can
Reserved:
ply Voltage Y:
ply Voltage X:
supply 3.3V:
supply 5.0V:
Write as read.
0 = No
0 = No
0 = No
0 = No
1 = Yes
1 = Yes
1 = Yes
1 = Yes
PCICFG 6Ch / MEMOFST 0Ch
Force Event Register - Byte 0
Default = 00h
Force dock rec-
ognized bit to 1:
Reserved:
Write as read. 11 = Docking station
All other combinations reserved
Force device type:
Force power
cycle event:
Force CCD2#
event:
Force CCD1#
event:
Reserved
0 = No
0 = No
0 = No
0 = No
1 = Yes
1 = Yes
1 = Yes
1 = Yes
PCICFG 6Dh / MEMOFST 0Dh
Force Event Register - Byte 1
Default = 00h
Reserved:
Force retest of
CVS1-2,
CCD1-2# pins
(or force bits):
Reserved
Force 3.3V
dock detected
bit to 1:
Force 5.0V
dock detected request bit to 1:
Force bad VCC Force data lost
bit to 1:
Write as read.
bit to 1:
0 = No
0 = No
0 = No
0 = No
1 = Yes
1 = Yes
0 = No
1 = Yes
1 = Yes
1 = Yes
PCICFG 6Eh / MEMOFST 0Eh
PCICFG 6Fh / MEMOFST 0Fh
Force Event Register - Byte 2
Default = 00h
Default = 00h
Reserved: Write as read.
Force Event Register - Byte 3
Reserved: Write as read.
PCICFG 70h / MEMOFST 10h
Control Register - Byte 0
Default = 00h
Reserved:
Dock VCC power request:
000 = Power off 100 = Voltage X
001 = Reserved
010 = 5.0V
011 = 3.3V
Reserved:
Dock VPP Power Request
Write as read.
Write as read.
Read/write bits; do not have any function. If
PCICFG 50h[0] = 1, these bits always return 0.
101 = Voltage Y
11x = Reserved
PCICFG 71h / MEMOFST 11h
PCICFG 72h / MEMOFST 12h
PCICFG 73h / MEMOFST 13h
Control Register - Byte 1
Default = 00h
Default = 00h
Default = 00h
Reserved: Write as read.
Control Register - Byte 2
Reserved: Write as read.
Control Register - Byte 3
Reserved: Write as read.
PCICFG 74h / MEMOFST 14h
Reserved
Default = 00h
The docking station access windows allow far more flexibility
in cycle selection, masking, etc. than do the CardBus window
registers.
5.5
Docking Station Window Selection
Group
One block of the 82C814 PCI-to-CardBus configuration regis-
ters is used to select the memory or I/O address ranges that
will be claimed by the bridge and passed onto the secondary
PCI bus for use with the OPTi PCI-to-ISA Bridge.
5.5.1 Docking Station Window Registers
The docking station registers are listed in Table 5-5. Table 5-
6 follows and includes the default settings for each register.
Windows 4-7, which were available in Rev 0.0 of the 82C814
chip and overlapped the CardBus windows, are no longer
available. Table 5-5 summarizes the features.
OPTi
®
Page 36
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-5
Docking Station Access Windows
Docking Station
Access Window #
Default Mask
Bits Decoded
Memory or I/O Selectable? Can Generate SMI#?
0
1
2
3
000FFFh
000FFFh
000003h
000003h
A[31:2]
A[31:2]
A[31:2]
A[31:2]
Yes - Defaults to Memory
Yes - Defaults to Memory
Yes - Defaults to I/O
Yes
Yes
Yes
Yes
Yes - Defaults to I/O
5.5.1.1
Cycle Decoding
5.5.1.3
ISA Window Selection
Each window can select either memory or I/O decoding, and
allows for a decode range anywhere from one dword to the
entire address space. Upper address bits from A31 on down
can be masked in the comparison, allowing any desired
degree of aliasing.
All docking station windows contain the ISA Window Selec-
tion bit. When set to 1, the window operation is modified as
follows.
• When a cycle initiated on the primary is claimed through
this window, the cycle will be immediately and automati-
cally retried.
5.5.1.2
Cycle Trapping
Instead of passing a claimed cycle onto the intended slave
PCI interface, the cycle controller can generate a STOP# or
CSTOP# on the master PCI interface (primary PCI interface
or slot interface) and cause the controlling device to back off.
At the same time, the cycle controller generates an IRQ
driveback cycle with SMI# active, therefore converting the
cycle into a System Management Interrupt trap.
• On the docking station side, the OPTi PCI-ISA Bridge will
claim the cycle and wait for positive decode on the ISA
bus.
- If positive decode is determined, the OPTi PCI-ISA
Bridge logic will terminate the cycle normally.
- If no positive decode can be achieved, the OPTi PCI-
ISA Bridge logic will terminate the cycle with a Target
Abort. Once this occurs, the 82C814 chip will simply
ignore the next retry attempt on its primary and allow
the cycle to pass to the local ISA bus of the host control-
ler.
At this point, the master will most likely retry the cycle, at
which time the 82C814 will allow it to proceed. It may or may
not be able to deliver valid data. The host chipset can then
run its SMM code. The SMM code can read the SMI Status
Register from the 82C814 to determine the window access
that caused the SMI. Once the value has been read, the host
must write a 1 back to each SMI indicator bit to re-enable
trapping and SMI generation on that window.
The retries occur up to the limit defined in PCICFG 5Eh[2:0]
before SERR# is generated.
Table 5-6
7
Docking Station Window Registers - PCICFG 80h-EFh
6
5
4
3
2
1
0
PCICFG 80h
Window 0 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window Start Address Bits:
RO:
Always
returns 0
If memory:
reads 0.
-
-
Register bits [31:0] indicate the start address for Window 0.
If I/O: Decoding
0 = 16-bit
The selection between memory or I/O, as well as other feature selections, are made through the
Window 0 Control Register.
AD[31:16] = 0
1 = 32-bit
PCICFG 81h
PCICFG 82h
PCICFG 83h
Window 0 Start Address Register - Byte 1: Address Bits [15:8]
Window 0 Start Address Register - Byte 2: Address Bits [23:16]
Window 0 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
Default = FFh
Default = FFh
PCICFG 84h
Window 0 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 0 Address Bits:
RO:
Always returns 0
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
OPTi
®
912-3000-047
Revision: 1.0
Page 37
January 08, 1998
82C814
Table 5-6
7
Docking Station Window Registers - PCICFG 80h-EFh (cont.)
6
5
4
3
2
1
0
PCICFG 85h
PCICFG 86h
PCICFG 87h
Window 0 Stop Address Register - Byte 1: Address Bits [15:8]
Window 0 Stop Address Register - Byte 2: Address Bits [23:16]
Window 0 Stop Address Register - Byte 3: Address Bits [31:24]
Default = 00h
Default = 00h
Default = 00h
PCICFG 88h
Window 0 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
Window 0 Mask Bits:
RO:
Always returns 1.
-
-
-
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space.
Setting any bit to a 1 masks out the comparison on this bit.
The register should be written to 0 to decode the entire address.
Bits [1:0] are always 11 (masked).
PCICFG 89h
PCICFG 8Ah
Window 0 Mask Register - Byte 1: Mask Bits [15:8]
Window 0 Mask Register - Byte 2: Mask Bits [23:16]
Default = 00h
Default = 00h
PCICFG 8Bh
Window 0 Control Register
Default = 48h
Window points
to ISA bus:
Reads are
prefetchable:
Writes can be
posted:
Reserved
Cycle qualifier:
0 = I/O
Window 0
Trap/SMI#:
Reserved
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = Disable
1 = Enable
1 = Memory
(Default)
Set to 0 for I/O Set to 0 for I/O
window window
PCICFG 8Ch-8Fh
Reserved
Window 1 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Default = 00h
PCICFG 90h
Window 1 Start Address Bits:
RO:
If memory:
reads 0.
-
-
Register bits [31:0] indicate the start address for Window 1.
Always
returns 0
If I/O: Decoding
0 = 16-bit
The selection between memory or I/O, as well as other feature selections, are made through the
Window 1 Control Register.
AD[31:16] = 0
1 = 32-bit
PCICFG 91h
PCICFG 92h
PCICFG 93h
Window 1 Start Address Register - Byte 1: Address Bits [15:8]
Window 1 Start Address Register - Byte 2: Address Bits [23:16]
Window 1 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
Default = FFh
Default = FFh
PCICFG 94h
Window 1 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 1 Stop Address Bits:
RO:
Always returns 0
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
PCICFG 95h
Window 1 Stop Address Register - Byte 1: Address Bits [15:8]
Window 1 Stop Address Register - Byte 2: Address Bits [23:16]
Window 1 Stop Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 96h
PCICFG 97h
Default = 00h
Default = 00h
PCICFG 98h
Window 1 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
OPTi
®
Page 38
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-6
Docking Station Window Registers - PCICFG 80h-EFh (cont.)
7
6
5
4
3
2
1
0
Window 1 Mask Bits:
RO:
Always returns 1.
-
-
-
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space.
Setting any bit to a 1 masks out the comparison on this bit.
The register should be written to 0 to decode the entire address.
Bits [1:0] are always 11 (masked).
PCICFG 99h
PCICFG 9Ah
Window 1 Mask Register - Byte 1: Mask Bits [15:8]
Window 1 Mask Register - Byte 2: Mask Bits [23:16]
Default = 00h
Default = 00h
PCICFG 9Bh
Window 1 Control Register
Default = 48h
Window points
to ISA bus:
Reads are
prefetchable:
Writes can be
posted:
Reserved
Cycle
qualifier:
Window 1
Trap/SMI#:
Reserved
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = I/O
0 = Disable
1 = Enable
1 = Memory
(Default)
Set to 0 for I/O Set to 0 for I/O
window window
PCICFG 9Ch-9Fh
Reserved
Window 2 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Default = 00h
PCICFG A0h
Window 2 Address Bits:
RO:
If memory:
reads 0.
-
-
Register bits [31:0] indicate the start address for Window 2.
Always returns
0
If I/O: Decoding
0 = 16-bit
The selection between memory or I/O, as well as other feature selections, are made through the
Window 2 Control Register.
AD[31:16] = 0
1 = 32-bit
PCICFG A1h
PCICFG A2h
PCICFG A3h
Window 2 Start Address Register - Byte 1: Address Bits [15:8]
Window 2 Start Address Register - Byte 2: Address Bits [23:16]
Window 2 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
Default = FFh
Default = FFh
PCICFG A4h
Window 2 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 2 Stop Address Bits:
RO:
Always returns 0
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
PCICFG A5h
Window 2 Stop Address Register - Byte 1: Address Bits [15:8]
Window 2 Stop Address Register - Byte 2: Address Bits [23:16]
Window 2 Stop Address Register - Byte 3: Address bits [31:24]
Default = 00h
PCICFG A6h
PCICFG A7h
Default = 00h
Default = 00h
PCICFG A8h
Window 2 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
Window 2 Mask Bits:
RO:
Always returns 1.
-
-
-
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space.
Setting any bit to a 1 masks out the comparison on this bit.
The register should be written to 0 to decode the entire address.
Bits [1:0] are always 11 (masked).
PCICFG A9h
PCICFG AAh
Window 2 Mask Register - Byte 1: Mask Bits [15:8]
Window 2 Mask Register - Byte 2: Mask Bits [23:16]
Default = 00h
Default = 00h
OPTi
®
912-3000-047
Revision: 1.0
Page 39
January 08, 1998
82C814
Table 5-6
7
Docking Station Window Registers - PCICFG 80h-EFh (cont.)
6
5
4
3
2
1
0
PCICFG ABh
Window 2 Control Register
Default = 00h
Window points
to ISA bus:
Reads are
prefetchable:
Writes can be
posted:
Reserved
Cycle
qualifier:
Window 2
Trap/SMI#:
Reserved
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = I/O (Default)
1 = Memory
0 = Disable
1 = Enable
Set to 0 for I/O Set to 0 for I/O
window window
PCICFG ACh-AFh
Reserved
Window 3 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Default = 00h
PCICFG B0h
Window 3 Address Bits:
RO:
If memory:
reads 0.
-
-
Register bits [31:0] indicate the start address for Window 3.
Always
returns 0
If I/O: Decoding
0 = 16-bit
The selection between memory or I/O, as well as other feature selections, are made through the
Window 3 Control Register.
AD[31:16] = 0
1 = 32-bit
PCICFG B1h
PCICFG B2h
PCICFG B3h
Window 3 Start Address Register - Byte 1: Address Bits [15:8]
Window 3 Start Address Register - Byte 2: Address Bits [23:16]
Window 3 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
Default = FFh
Default = FFh
PCICFG B4h
Window 3 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 3 Stop Address Bits:
RO:
Always returns 0
Default = 00h
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
PCICFG B5h
Window 3 Stop Address Register - Byte 1: Address Bits [15:8]
Window 3 Stop Address Register - Byte 2: Address Bits [23:16]
Window 3 Stop Address Register - Byte 3: Address Bits [31:24]
PCICFG B6h
PCICFG B7h
Default = 00h
Default = 00h
PCICFG B8h
Window 3 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
Window 3 Mask Bits:
RO:
Always returns 1.
-
-
-
-
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space.
Setting any bit to a 1 masks out the comparison on this bit.
The register should be written to 0 to decode the entire address.
Bits [1:0] are always 11 (masked).
Bit 23 is always 0
PCICFG B9h
PCICFG BAh
Window 3 Mask Register - Byte 1: Mask Bits [15:8]
Window 3 Mask Register - Byte 2: Mask Bits [23:16]
Bits [22:16]
Default = 00h
Default = 00h
Bit 23
Reserved
PCICFG BBh
Window 3 Control Register
Default = 00h
OPTi
®
Page 40
912-3000-047
Revision: 1.0
January 08, 1998
82C814
Table 5-6
Docking Station Window Registers - PCICFG 80h-EFh (cont.)
7
6
5
4
3
2
1
0
Window points
to ISA bus:
Reads are
prefetchable:
Writes can be
posted:
Reserved
Cycle
qualifier:
Window 3
Trap/SMI#:
Reserved
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = I/O (Default)
1 = Memory
0 = Disable
1 = Enable
Set to 0 for I/O Set to 0 for I/O
window window
PCICFG BCh-EFh
Reserved
Default = 00h
5.6
PCI Power Management Register Group
the following registers comprise the PCI Power Management Register Group.
Table 5-7
PCI Power Management Registers - PCICFG F0h-FFh
PCICFG F0h
Capabilities ID Register (RO)
Default = 01h
Default = 00h
Default = 01h
This register always returns 01h to identify the Linked List item as being the PCI Power Management Registers.
PCICFG F1h
Next Item Pointer Register (RO)
Value of 0 indicates no additional items in Capabilities List
PCICFG F2h
Reserved
Power Management Capabilities Register - Byte 0
Device Specific
Individualization
Reserved
Returns 001b to indicate Rev 1.0 of PCI Power
Management Specification
0 = No (always)
PCICFG F3h
Power Management Capabilities Register - Byte 1
Reserved Supports D2
Power Manage- Power Manage-
Default = 06h
Support D1
Reserved
ment State
ment State
1 = Yes
(always)
1 = Yes
(always)
PCICFG F4h
Power Management Control/Status Register - Byte 0
Default = 00h
Reserved
Power State
00 = State D0
01 = State D1
10 = State D2
11 = State D3hot
PCICFG F5h
Power Management Control/Status Register - Byte 1
Default = 00h
PME Status
0 = Inactive
1 = Active
Data Register (not Implemented)
PME# PCI
Function
0 = Disable
1 = Enabled
Write 1 to clear
OPTi
®
912-3000-047
Revision: 1.0
Page 41
January 08, 1998
82C814
Table 5-7
PCI Power Management Registers - PCICFG F0h-FFh (cont.)
PCICFG F6h
PCI-to-PCI Bridge Support Extensions Register (RO)
Default = C0h
Bus Power
Clock Control
B2/B3 Support
for D3hot
Reserved
1 = Enabled
(always)
1 =Enable
(always)*
*
Indicates that when Power State is programmed to D3hot, secondary PCI clocks will be stopped.
PCICFG F7h
Data Register (RO)
Default = 00h
Default = 00h
Data Register not implemented
PCICFG F8h-FFh
Reserved
OPTi
®
Page 42
912-3000-047
Revision: 1.0
January 08, 1998
82C814
6.0 Electrical Ratings
Stresses above those listed in the following tables may cause
permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tions of this specification are not implied.
6.1
Absolute Maximum Ratings
5.0 Volt
3.3 Volt
Symbol
VCC
Parameter
Min
Max
Min
Max
Unit
Supply Voltage
+6.5
VCC + 0.5
VCC + 0.5
+70
+4.0
V
V
VI
Input Voltage
–0.5
–0.5
0
–0.5
–0.5
0
VCC + 0.5
VCC + 0.5
+70
VO
Output Voltage
V
TOP
TSTG
Operating Temperature
Storage Temperature
°C
°C
–40
+125
–40
+125
6.2
DC Characteristics: VCC = 3.3V or 5.0V ±5%, TA = 0°C to +70°C
Symbol
Parameter
Min
Max
Unit
Condition
VIL
Input low Voltage
–0.5
+2.0
+0.8
VCC + 0.5
+0.4
V
V
VIH
VOL
VOH
IIL
Input high Voltage
Output low Voltage
Output high Voltage
Input Leakage Current
Tristate Leakage Current
Input Capacitance
V
IOL = 4.0mA
IOH = -1.6mA
VIN = VCC
+2.4
V
+10.0
+10.0
+10.0
+10.0
µA
µA
pF
pF
mA
IOZ
CIN
COUT
ICC
Output Capacitance
Power Supply Current
3.3V Core
Fully active
100
150
5.0V Core
OPTi
®
912-3000-047
Revision: 1.0
Page 43
January 08, 1998
82C814
6.3
AC Characteristics
Sym Parameter
Min
Max
Unit
Figure
Primary PCI Bus
t100
t101
t102
C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#,
PAR, SERR#, PERR# setup time to PCICLK rising
7
0
2
ns
ns
ns
6-1
6-2
6-3
C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#,
PAR, SERR#, PERR# hold time from PCICLK rising
C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#,
PAR, SERR#, PERR# valid delay from PCICLK rising
11
12
t103
t104
t105
REQ# setup time to PCICLK rising
REQ# hold time from PCICLK rising
GNT# valid delay from PCICLK rising
12
0
ns
ns
ns
6-1
6-2
6-3
2
Secondary PCI Bus
t200
t201
t202
CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#,
CBLOCK#, CPAR, CSERR#, CPERR# setup time to PCICLK rising
7
0
2
ns
ns
ns
6-1
6-2
6-3
CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#,
CBLOCK#, CPAR, CSERR#, CPERR# hold time from PCICLK rising
CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#,
CBLOCK#, CPAR, CSERR#, CPERR# valid delay from PCICLK rising
11
t203
t204
t205
t206
t207
t208
CREQ[3:0]# setup time to PCICLK rising
CREQ[3:0]# hold time from PCICLK rising
CGNT[3:0]# valid delay from PCICLK rising
PCIRQ[3:0]# setup time to PCICLK rising
PCIRQ[3:0]# hold time from PCICLK rising
PCIRQ[3:0]# valid delay from PCICLK rising
12
0
ns
ns
ns
ns
ns
ns
6-1
6-2
6-3
6-1
6-2
6-3
2
12
16
5
3
2
OPTi
®
Page 44
912-3000-047
Revision: 1.0
January 08, 1998
82C814
6.4
AC Timing Diagrams
Figure 6-1
Setup Timing Waveform
0ns
50ns
100ns
PCICLK
t100, t103, t200, t203, t206
SIGNAL
Figure 6-2
Hold Timing Waveform
0ns
50ns
100ns
PCICLK
SIGNAL
t101, t104, t201, t204, t207
Figure 6-3
Output Delay Timing Waveform
0ns
50ns
100ns
PCICLK
SIGNAL
t102, t105, t202, t203, t205, t208
OPTi
®
912-3000-047
Revision: 1.0
Page 45
January 08, 1998
82C814
OPTi
®
Page 46
912-3000-047
Revision: 1.0
January 08, 1998
82C814
7.0 Mechanical Package Outline
Figure 7-1
144-Pin LQFP, Low-Profile Quad Flat Pack
OPTi
®
912-3000-047
Revision: 1.0
Page 47
82C814
OPTi
®
Page 48
912-3000-047
Revision: 1.0
IRQ Driveback
Appendix A IRQ Driveback Protocol
The OPTi PCI IRQ Driveback cycle provides a clean and sim-
ple way to convey interrupt and DMA status information to the
host. The protocol is reliable and does not in any way com-
promise PCI compatibility.
cycle request is illustrated in the figure. A second data phase
is also possible.
A.1
Driveback Cycle Format
1. Whenever a PCI peripheral device must signal an IRQ or
SMI# to the system, it asserts its REQ# line to the host
for one PCI clock, deasserts it for one PCI clock, then
asserts it again and keeps it low until acknowledged.
The charts below illustrate the interrupt information indicated
IRQ bits indicate whether that IRQ line is being driven high or
low. The EN# bits indicate whether that IRQ is enabled to be
changed or not. When the EN# bit is low, the value on the
IRQ bit is valid. The device containing the central interrupt
controller claims this I/O write cycle, and can then change its
internal IRQ line state to match the value sent.
2. The host recognizes this sequence as a high-priority
request and immediately removes all other bus grants
(GNT# lines). Once the previous bus owner is off the
bus, the host acknowledges the high-priority request with
GNT# as usual.
When a PCI device needs to generate an interrupt to the sys-
tem, it runs a driveback cycle with the Enable bit low for each
IRQ line under its control. For example, a device on PCI
could run a driveback cycle with IRQ3 high and EN3# low to
generate IRQ3 to the system. When the interrupt has been
serviced and the device deasserts its interrupt, it starts
another driveback cycle with IRQ3 low and EN3# low.
3. The peripheral device logic runs an I/O write cycle to the
IRQ Driveback address specified in the PCI configura-
tion registers, and releases REQ#.
4. The host latches the information on AD[31:0] and sets
the IRQ lines appropriately.
During both of these instances, if the device controls inter-
rupts other than IRQ3, it must set its EN# bits low for all
channels it controls, not just for the interrupt whose state has
changed. The other IRQs must be driven with their previously
used values.
5. An optional second burst data cycle can take place to
convey additional interrupt information.
PCI-type devices on the secondary side of bridge chips can
use this same protocol to convey their interrupt requests
through the bridge to the host. The format of the driveback
Figure A-1 IRQ Driveback Cycle High-Priority Request
PCICLK
//
REQ#
//
//
GNT#
AD[31:0]
//
Table A-1
Information Provided on a Driveback Cycle
Low
AD15 AD14 AD13 AD12 AD11 AD10 AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Word
IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
High
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16
EN15# EN14# EN13# EN12# EN11# EN10# EN9# EN8# EN7# EN6# EN5# EN4# EN3# EN2# EN1# EN0#
Word
OPTi
®
912-3000-047
Revision: 1.0
Page 49
January 08, 1998
IRQ Driveback
There is a convention for assignment of otherwise unusable
IRQs:
nal from the ISA bus across the PCI bus. The sense of
IRQ13 is active high.
• IRQ2 generates an SMI#. Note that the sense of IRQ2 is
still active high. In this way, devices that use IRQ drive-
back can generate SMI# simply by routing their normal
interrupt to IRQ2 without needing to change the polarity of
the interrupt generation logic.
Table A-2 illustrates the format of the optional second data
phase of the IRQ driveback cycle. This phase is presently
reserved for returning the PCI interrupts and ACPI Events. If
the device needs to send back level-model interrupts, it
bursts the information on the PCI clock following data phase
one. The IRQ driveback address automatically increments to
(base +4) per PCI requirements. It is also allowable for
devices to drive back only phase 2, by directly accessing the
(base +4) address.
• IRQ13 generates an NMI. This feature allows PCI-to-ISA
bridges such as the 82C825 chip to return the CHCK# sig-
Table A-2
Information Provided on a Optional Data Phase 2 of IRQ Driveback Cycle
Low
Word
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
ACPI3 ACPI2 ACPI1 ACPI0 PCIRQ PCIRQ PCIRQ PCIRQ
3
2
1
0
High
Word
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
EN
EN
EN
EN
ENP3# ENP2# ENP1# ENP0#
ACPI3# ACPI2# ACPI1# ACPI0#
However, the INTA-D# lines can be shared by multiple
devices on the PCI bus. Thus, one device could perform an
IRQ driveback to set the INTx# line active for its purposes,
while another device could follow immediately by setting the
same INTx# line inactive. Therefore, the host is required to
implement a counter in this case, so that it considers the line
inactive only after it has received the same number of active-
going drivebacks as it has inactive-going drivebacks.
A.2
Edge vs Level Mode, IRQ Polarity
The IRQs driven back in data phase 1 are interpreted as
edge-mode interrupts, as expected for AT compatibility. The
AD[15:0] signals are interpreted as active when high (1); the
Enable (EN#) signals AD[31:16] are active when low (0).
In optional data phase 2, the PCIRQ0-3 bits are interpreted
as level-mode interrupts by the host hardware. As with data
phase 1, the controls indicated by AD[15:0] are interpreted as
active when high; the Enable (EN#) controls on AD[31:16]
are active when low. Note that PCI signals INTA-D# are
active low by definition.
A three-bit counter can be considered sufficient to handle the
situation, since this would allow up to seven devices to chain
to the same interrupt. It is unlikely that system requirements
would exceed this number given the latency penalty incurred.
A.3
Host Handling of IRQ Driveback
Information
The host chipset must handle the IRQ driveback information
differently depending on whether the selected interrupt is
sharable or not. Generally the ISA IRQ lines need no special
consideration.
OPTi
®
Page 50
912-3000-047
Revision: 1.0
January 08, 1998
OPTi
®
Sales Information
Michigan
Jay Marketing
44752 Helm Street., Ste. A
Plymouth, MI 48170
tel: 313-459-1200
fax: 313-459-1697
Wisconsin
Micro-Tex, Inc.
22660 Broadway, Ste. #4A
Waukesha, WI 53186
tel: 414-542-5352
fax: 414-542-7934
Singapore
HEADQUARTERS:
OPTi Inc.
888 Tasman Drive
Milpitas, CA 95035
tel: 408-486-8000
fax: 408-486-8011
Instep Microsolutions Pte Ltd.
18, Tannery Lane, #05-02
Lian Tong Building
Singapore 347780
tel: 65-741-7507
fax: 65-741-1478
New Jersey
International
Australia
South America
Uniao Digital
Rua Guido Caloi
Bloco B, Piso 3
Sao Paulo-SP, CEP 05802-140 Brazil
tel: 55-11-5514-3355
fax: 55-11-5514-1088
SALES OFFICES:
Japan
S-J Associates, Inc.
131-D Gaither Dr.
Mt. Laurel, NJ 08054
tel: 609-866-1234
fax: 609-866-8627
Braemac Pty. Ltd.
OPTi Japan KK
Unit 6, 111 Moore St., Leichhardt
Sydney, 2040 Australia
tel: 61-2-550-6600
Murata Building 6F, 2-22-7
Ohhashi Meguro-ku
Tokyo 153, Japan
tel: 81-3-5454-0178
fax: 81-3-5454-0168
New York
fax: 61-2-550-6377
S-J Associates, Inc.
265 Sunrise Highway
Rockville Centre, NY 11570
tel: 516-536-4242
Switzerland
China
Datacomp AG
Silbernstrasse 10
8953 Dietikon
Switzerland
tel: 41-1-740-5140
fax: 41-1-741-3423
Legend Electronic Components. Ltd.
Unit 413, Hong Kong Industrial
Technology Centre
72 Tat Chee Avenue
Kowloon Tong, Hong Kong
tel: 852-2776-7708
Taiwan
OPTi Inc.
9F, No 303, Sec 4, Hsin Yih Road
Taipei, Taiwan, ROC
tel: 886-2-325-8520
fax: 886-2-325-6520
fax: 516-536-9638
S-J Associates, Inc.
735 Victor-Pittsford
Victor, NY 14564
tel: 716-924-1720
fax: 852-2652-2301
United Kingdom
Spectrum
2 Grange Mews,
Station Road
Launton, Bicester
Oxfordshire,OX6 0DX
UK
United States
OPTi Inc.
20405 State Highway 249, Ste. #220
Houston, TX 77070
tel: 281-257-1856
fax: 281-257-1825
France
North & South Carolina
Tekelec Airtronic, France
5, Rue Carle Vernet
92315 Sevres Cedex
France
tel: 33-1-46-23-24-25
fax: 33-1-45-07-21-91
Concord Component Reps
10608 Dunhill Terrace
Raleigh, NC 27615
tel: 919-846-3441
fax: 919-846-3401
tel: 44-1869-325174
fax: 44-1869-325175
REPRESENTATIVES:
Ohio/W. Pennsylvania
Lyons Corp.
4812 Fredrick Rd., Ste. #101
Dayton, OH 45414
tel: 513-278-0714
fax: 513-278-3609
Germany
Kamaka
Rheinsrasse 22
76870 Kandel
Germany
tel: 49-7275-958211
fax: 49-7275-958220
MMD
3 Bennet Court,
Bennet Road
Reading
Berkshire, RG2 0QX
UK
tel: 44 1734 313232
fax: 44 1734 313255
United States
Alabama/Mississippi
Concord Component Reps
190 Line Quarry Rd., Ste. #102
Madison, AL 35758
Lyons Corp.
4615 W. Streetsboro
Richfield, OH 44286
tel: 216-659-9224
fax: 216-659-9227
tel: 205-772-8883
fax: 205-772-8262
India
Spectra Innovation
Unit S-822 Manipal Centre
47 Dickenson Road
Bangalore 560-042
Kamataka, India
tel: 91-80-558-8323/3977
fax: 91-80-558-6872
Florida
Engineered Solutions Ind., Inc.
1000 E. Atlantic Blvd., Ste. #202
Pompano Beach, FL 33060
tel: 305-784-0078
Lyons Corp.
248 N. State St.
Westerville, OH 43081
tel: 614-895-1447
fax: Same
fax: 305-781-7722
Israel
Georgia
Texas
Ralco Components (1994) Ltd.
11 Benyamini St.
67443 Tel Aviv
Israel
tel: 972-3-6954126
fax: 972-3-6951743
Concord Component Reps
6825 Jimmy Carter Blvd., Ste. #1303
Norcross, GA 30071
tel: 770-416-9597
fax: 770-441-0790
Axxis Technology Marketing, Inc.
701 Brazos, Suite 500
Austin, TX 78701
tel: 512-320-9130
fax: 512-320-5730
Illinois
Micro-Tex, Inc.
1870 North Roselle Rd., Ste. #107
Schaumburg, IL 60195-3100
tel: 708-885-8200
Korea
Axxis Technology Marketing, Inc.
6804 Ashmont Drive
Plano, TX 75023
tel: 214-491-3577
fax: 214-491-2508
Woo Young Tech Co., Ltd.
5th Floor Koami Bldg
13-31 Yoido-Dong
Youngduengpo-Ku
Seoul, Korea 150-010
tel: 02-369-7099
fax: 708-885-8210
Virginia
S-J Associates, Inc.
Massachusetts
fax: 02-369-7091
900 S. Washington St., Ste. #307
Falls Church, VA 22046
tel: 703-533-2233
S-J Associates, Inc.
267 Boston Road
Corporate Place, Ste. #3
N. Billerica, MA 01862
tel: 508-670-8899
fax: 508-670-8711
fax: 703-533-2236
The information contained within this document is subject to change without notice. OPTi Inc. reserves the right to make changes in this manual at any time as well
as in the products it describes, at any time without notice or obligation. OPTi Inc. assumes no responsibility for any errors contained within. In no event will OPTi Inc.
be liable for any damages, direct, indirect, incidental or consequential resulting from any error, defect, or omission in this specification.
Copyright © 1997 by OPTi Inc. All rights reserved. OPTi is a trademark of OPTi Incorporated. All other brand and product names are trademarks or copyrights of
their respective owners.
June 27, 1997
OPTi Inc. · 888 Tasman Drive · Milpitas, CA 95035 · (408) 486-8000
OPTi Inc.
888 Tasman Drive
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
www.opti.com
相关型号：
QT01180A-2120P
Board Stacking Connector, 180 Contact(s), 2 Row(s), Female, Straight, 0.02 inch Pitch, Surface Mount Terminal, Locking, Ivory Insulator, Receptacle,
FOXCONN
QT012206-1031-2H
Board Connector, 220 Contact(s), 2 Row(s), Female, Straight, 0.02 inch Pitch, Surface Mount Terminal, Locking, Black Insulator, Receptacle, HALOGEN FREE AND LEAD FREE
FOXCONN
QT012206-1041-3H
Board Connector, 220 Contact(s), 4 Row(s), Male, Straight, 0.02 inch Pitch, Surface Mount Terminal, Locking, Black Insulator, Plug, HALOGEN FREE AND LEAD FREE
FOXCONN
©2020 ICPDF网 联系我们和版权申明