RTL8169_技术文档

RTL8169

REALTEK GIGABIT

ETHERNET MEDIA ACCESS

CONTROLLER

WITH POWER MANAGEMENT

RTL8169

1. Features........................................................................ 2

2. General Description.................................................... 3

3. Block Diagram............................................................. 4

4. Pin Assignments .......................................................... 5

5. Pin Description............................................................ 6

5.1 Power Management/Isolation Interface ................. 6

5.2 PCI Interface .......................................................... 7

5.3 FLASH/BootPROM/EEPROM/MII Interface ....... 9

5.4 LED Interface....................................................... 10

5.5 GMII, TBI, PHY CP ............................................ 10

5.6 Clock and NC Pins............................................... 12

5.7 Power Pins ........................................................... 12

6. Register Descriptions................................................ 13

6.1 DTCCR: Dump Tally Counter Command............ 15

6.2 FLASH: Flash Memory Read/Write .................... 16

6.3 ERSR: Early Rx Status......................................... 16

6.4 Command............................................................. 17

6.5 TPPoll: Transmit Priority Polling......................... 17

6.6 Interrupt Mask...................................................... 18

6.7 Interrupt Status..................................................... 19

6.8 Transmit Configuration........................................ 20

6.9 Receive Configuration ......................................... 21

6.10 9346CR: 93C46 (93C56) Command.................. 23

6.11 CONFIG 0.......................................................... 23

6.12 CONFIG 1.......................................................... 24

6.13 CONFIG 2.......................................................... 25

6.14 CONFIG 3.......................................................... 25

6.15 CONFIG 4.......................................................... 26

6.16 CONFIG 5.......................................................... 27

6.17 Multiple Interrupt Select .................................... 28

6.18 PHYAR: PHY Access ........................................ 28

6.19 TBICSR: Ten Bit Interface Control and Status.. 28

6.20 TBI_ANAR: TBI Auto-Negotiation Advertisement .. 29

6.21 TBI_LPAR:TBIAuto-Negotiation Link PartnerAbility....... 29

6.22 PHYStatus: PHY(GMII or TBI) Status.............. 30

6.23 RMS: Receive (Rx) Packet Maximum Size....... 30

6.24 C+CR: C+ Command......................................... 31

6.25 RDSAR: Receive Descriptor Start Address....... 31

6.26 ETThR: Early Transmit Threshold..................... 31

6.27 Function Event................................................... 32

6.28 Function Event Mask ......................................... 32

6.29 Function Preset State.......................................... 33

6.30 Function Force Event......................................... 33

7. EEPROM (93C46 or 93C56) Contents ................... 34

7.1 EEPROM Registers.............................................. 35

7.2 EEPROM Power Management Registers............. 35

8. PCI Configuration Space Registers......................... 36

8.1 PCI Bus Interface................................................. 36

8.1.1 Byte Ordering............................................... 36

8.1.2 Interrupt Control........................................... 36

8.1.3 Latency Timer............................................... 36

8.1.4 64-Bit Data Operation .................................. 37

8.1.5 64-Bit Addressing......................................... 37

8.2 Bus Operation ...................................................... 37

8.2.1 Target Read................................................... 37

8.2.2 Target Write.................................................. 38

8.2.3 Master Read.................................................. 38

8.2.4 Master Write................................................. 39

8.2.5 Configuration Access ................................... 40

8.3 Packet Buffering .................................................. 40

8.3.1 Transmit Buffer Manager ............................. 40

8.3.2 Receive Buffer Manager............................... 40

8.3.3 Packet Recognition....................................... 40

8.4 PCI Configuration Space Table............................ 41

8.5 PCI Configuration Space Functions..................... 42

8.6 Default Value After Power-on (RSTB Asserted). 46

8.7 Power Management functions.............................. 47

8.8 Vital Product Data (VPD) .................................... 49

9. Functional Description ............................................. 50

9.1 Transmit & Receive Operations........................... 50

9.1.1 Transmit........................................................ 50

9.1.2 Receive......................................................... 55

9.2 Loopback Operation............................................. 58

9.3 Collision............................................................... 58

9.4 Flow Control........................................................ 58

9.4.1. Control Frame Transmission ....................... 58

9.4.2. Control Frame Reception ............................ 58

9.5 Memory Functions............................................... 59

9.5.1 Memory Read Line (MRL) .......................... 59

9.5.2 Memory Read Multiple (MRM)................... 59

9.5.3 Memory Write and Invalidate (MWI) .......... 60

9.5.4 Dual Address Cycle (DAC).......................... 60

9.6 LED Functions..................................................... 61

9.6.1 Link Monitor ................................................ 61

9.6.2 Rx LED ........................................................ 61

9.6.3 Tx LED......................................................... 62

9.6.4 Tx/Rx LED................................................... 62

9.6.5 LINK/ACT LED........................................... 63

9.7 Physical Layer Interfaces..................................... 64

9.7.1 Media Independent Interface (MII).............. 64

9.7.2 Gigabit Media Independent Interface (GMII) ...... 64

9.7.3 Ten Bit Interface (TBI)................................. 64

9.7.4 MII/GMII Management Interface................. 64

10. Application Diagrams............................................. 65

10.1 10/100/1000Base-T Application........................ 65

10.2 1000Base-X Application.................................... 65

11. Electrical Characteristics ....................................... 66

11.1 Temperature Limit Ratings................................. 66

11.2 DC Characteristics ............................................. 66

11.3 AC Characteristics ............................................. 67

11.3.1 FLASH/BOOT ROM Timing..................... 67

11.3.2 Serial EEPROM Interface Timing.............. 69

11.3.3 PCI Bus Operation Timing ......................... 70

11.3.4 MII Timing ................................................. 87

11.3.5 GMII Timing .............................................. 89

11.3.6 TBI Timing................................................. 90

12. Mechanical Dimensions.......................................... 91

2002/03/27

Rev.1.21

1

RTL8169

1. Features

ꢀ

208 pin QFP

ꢀ

Supports Wake-On-LAN function and remote wake-up

(Magic Packet*, LinkChg and Microsoft^®wake-up

frame)

Supports descriptor-based buffer management

Supports Microsoft* NDIS5 Checksum Offloads (IP,

TCP, UDP), and Largesend Offload

Supports IEEE 802.1Q VLAN tagging

Supports 4 Wake-On-LAN (WOL) signals (active high,

active low, positive pulse, and negative pulse)

ꢀ

Supports Transmit (Tx) Priority Queue for QoS, CoS ꢀ Supports auxiliary power-on internal reset, to be ready

applications

for remote wake-up when main power still remains off

Supports auxiliary power auto-detect, and sets the

related capability of power management registers in PCI

configuration space

ꢀ

Supports major Tally Counters

ꢀ

10Mbps, 100Mbps, and 1000Mbps operation at

MII/GMII, and 1000Mbps at TBI interfaces

ꢀ

Supports 10Mbps, 100Mbps, and 1000Mbps N-way ꢀ Advanced power saving mode when LAN function or

Auto-negotiation operation

wakeup function is not used

PCI local bus single-chip Fast Ethernet controller

ꢀ

3.3V and 1.8V power supplies needed

5V tolerant I/Os

ꢁ

Compliant to PCI Revision 2.2

Supports both Little-Endian and Big-Endian

Supports 16.75MHz-66MHz PCI clock

Supports both 32-bit and 64-bit PCI bus

Supports PCI target fast back-to-back transaction

Supports Memory Read Line, Memory Read

Includes a programmable, PCI burst size and early

Tx/Rx threshold

ꢀ

Supports a 32-bit general-purpose timer with the

external PCI clock as clock source, to generate

timer-interrupt

Multiple, Memory Write and Invalidate, and ꢀ Contains two large independent transmit (8KB) and

Dual Address Cycle

receive (48KB) FIFO devices

ꢁ

Provides PCI bus master data transfers and PCI ꢀ Uses 93C46 (64*16-bit EEPROM) or 93C56

memory space or I/O space mapped data

transfers of the RTL8169 operational registers

Supports PCI VPD (Vital Product Data)

Supports ACPI, PCI power management

(128*16-bit EEPROM) to store resource configuration,

ID parameter, and VPD data. The 93C56 can also be

used to store the CIS data structure for CardBus

applications

ꢁ

Supports optional PCI multi-function with ꢀ Supports LED pins for various network activity

additional slave mode only functions

indications

ꢀ

Supports CardBus. The CIS can be stored in 93C56 or ꢀ Supports both digital and external analog loopback

expansion ROM

ꢀ

Half/Full duplex capability (only Full duplex operation

at 1000Mbps)

Supports Boot ROM interface. Up to 128K bytes Boot

ROM interface for both EPROM and Flash memory ꢀ Supports Full Duplex Flow Control (IEEE 802.3x)

can be supported

* Third-party brands and names are the property of their

respective owners.

ꢀ

Supports 125MHz OSC as the internal clock source or

125MHz clock provided from external PHYceiver

Compliant to PC97, PC98, PC99 and PC2001 standards

These specifications are subject to change without notice.

2002/03/27

Rev.1.21

2

RTL8169

2. General Description

The Realtek RTL8169 is a highly integrated, high performance PCI Gigabit Ethernet Media Access Controller for use in network

adapters for servers and personal computers. The RTL8169 fully implements the 33/66MHz, 32/64-bit PCI v2.2 bus interface for

host communications with power management and is compliant with the IEEE 802.3 specification for 10/100Mbps Ethernet and

the IEEE 802.3z specification for 1000Mbps Ethernet. The RTL8169 supports the auxiliary power auto-detect function, and will

auto-configure related bits of the PCI power management registers in PCI configuration space.

It also supports the Advanced Configuration Power management Interface (ACPI), PCI power management for modern

operating systems that are capable of Operating System directed Power Management (OSPM) to achieve the most efficient

power management system possible.

In addition to the ACPI feature, the RTL8169 also supports remote wake-up (including AMD Magic Packet, LinkChg, and

Microsoft^®wake-up frame) in both ACPI and APM environments. The RTL8169 is capable of performing an internal reset

through the application of auxiliary power. When the auxiliary power is applied and the main power remains off, the RTL8169 is

ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides four different

output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8169 LWAKE pin

provides motherboards with Wake-On-LAN (WOL) functionality.

The PCI specification is inherently little-endian. The RTL8169 contains the ability to do little-endian to big-endian swaps. It is

also possible that the RTL8169 can be used as a basis for a RISC CPU platform which expect the data to be in a big-endian

format. This feature allows for maximum flexibility.

PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8169

LAN card). The information may consist of part number, serial number, and other detailed information.

The RTL8169 is fully compliant to Microsoft^®NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and

supports IEEE802.1Q Virtual bridged Local Area Network (VLAN). All the above RTL8169 features contribute to lowering

CPU utilization, which is a benefit in operation as a server network card. Also, the RTL8169 boosts its PCI performance by

supporting PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when

receiving. To be better qualified as a server card, the RTL8169 also supports the PCI Dual Address Cycle (DAC) command,

when the assigned buffers reside at a physical memory addresses higher than 4 Gigabytes. For QoS, CoS requirements, the

RTL8169 supports hardware high priority queues to reduce software implementation effort and significantly improve

performance.

The RTL8169 keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network

from 10/100Mbps to 1000Mbps. It also supports full-duplex operation, making possible 2000Mbps of bandwidth at no

additional cost. For special applications, the RTL8169 also supports a TBI interface, which can be used to provide a connection

to a Fiber channel, using a Fiber transceiver.

2002/03/27

Rev.1.21

3

RTL8169

3. Block Diagram

MAC

Boot ROM

Interface

EEPROM

Interface

LED Driver

Power Control Logic

Early Interrupt

Threshold

Interrupt

Register

Control

Logic

Early Interrupt

Control Logic

Transmit/

Receive

Logic

FIFO

Control

Logic

FIFO

Interface

2002/03/27

Rev.1.21

4

RTL8169

4. Pin Assignments

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

VDD33

RSTPHYB

TBILBK

GND

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

OEB

WEB

ROMCSB

MD0

TXD7

TXD6

TXD5

TXD4

TXD3

TXD2

TXD1

TXD0

TXEN

VDD33

GTXCLK

TX8

MD1

MD2

MD3

MD4

MD5

MD6

VDD18

MD7

LED0

GND

LED1

LED2

LED3

VDD33

MA16

MA15

MA14

MA13

NC

TXCLK

CRS

GND

COL

RXER

NC

RXCLK1

NC

MA12

NC

RXCLK

MA11

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

RXDV

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

VDD18

VDD33

CLOCK125

MDC

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

MA10

NC

MA9

MA8

MA7

MA6

GND

MA5

MA4

MA3

GND

EECS

MA2

MDIO

GND

MA1

MA0

ISOLATEB

M66EN

INTAB

RSTB

CLK

VDD33

LWAKE

PMEB

CLKRUNB

AD32

AD33

AD34

GND

GNTB

REQB

VDD33

AD31

AD35

AD36

AD37

AD38

VDD33

AD39

AD40

AD41

AD42

GND

AD30

AD29

AD28

GND

RTL8169

AD27

AD26

AD25

AD24

VDD33

CBE3B

IDSEL

AD23

GND

AD43

AD44

VDD18

AD45

AD46

VDD33

AD47

AD48

AD49

AD50

GND

AD22

AD21

GND

AD20

AD19

AD18

AD17

VDD33

AD16

CBE2B

FRAMEB

IRDYB

TRDYB

GND

AD51

AD52

AD53

AD54

VDD33

AD55

AD56

DEVSELB

STOPB

1

PERRB

NC

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

AD57

NC

2

3

SERRB

NC

AD58

NC

4

5

PAR

GND

6

NC

7

CBE1B

VDD33

AD15

AD14

AD13

AD12

GND

AD11

AD10

AD9

AD59

NC

8

9

AD60

AD61

AD62

VDD33

AD63

PAR64

CBE4B

CBE5B

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

AD8

VDD33

CBE0B

AD7

CBE6B

CBE7B

GND

AD6

REQ64B

ACK64B

VDD33

AD0

AD5

GND

AD4

AD3

AD1

AD2

VDD18

2002/03/27

Rev.1.21

5

RTL8169

5. Pin Description

In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are

separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.

5.1 Power Management/Isolation Interface

Symbol

PMEB

Type

Pin No

Description

O/D

87

Power Management Event: Open drain, active low. Used by the

RTL8169 to request a change in its current power management state

and/or to indicate that a power management event has occurred.

Isolate Pin: Active low. Used to isolate the RTL8169 from the PCI bus.

The RTL8169 does not drive its PCI outputs (excluding PME#) and

does not sample its PCI input (including RST# and PCICLK) as long as

the Isolate pin is asserted.

(PME#)

ISOLATEB

I

172

88

(ISOLATE#)

LWAKE/

O

LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3): This

signal is used to inform the motherboard to execute the wake-up

process. The motherboard must support Wake-On-LAN (WOL). There

are 4 choices of output, including active high, active low, positive pulse,

and negative pulse, that may be asserted from the LWAKE pin. Please

refer to LWACT bit in CONFIG1 register and LWPTN bit in CONFIG4

register for the setting of this output signal. The default output is an

active high signal. Once a PME event is received, the LWAKE and

PMEB assert at the same time when the LWPME (bit4, CONFIG4) is

set to 0. If the LWPME is set to 1, the LWAKE asserts only when the

PMEB asserts and the ISOLATEB is low.

CSTSCHG

CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal is

used in CardBus applications only and is used to inform the

motherboard to execute the wake-up process whenever a PME event

occurs. This is always an active high signal, and the setting of LWACT

(bit 4, Config1), LWPTN (bit2, Config4), and LWPME (bit4, Config4)

means nothing in this case.

This pin is a 3.3V signaling output pin.

2002/03/27

Rev.1.21

6

RTL8169

5.2 PCI Interface

Symbol

AD63-0

Type

Pin No

Description

T/S

40, 42-44, 46, 50,

52-54, 56-59, 61-64,

66-67, 69-70, 73-76,

78-81, 83-85, 180-183,

185-188, 192-194,

196-199, 201, 9-12,

14-17, 20-22, 24-26,

28-29

AD31-0: Low 32-bit PCI address and data multiplexed pins. The

address phase is the first clock cycle in which FRAMEB is asserted. During

the address phase, AD31-0 contains a physical address (32 bits). For I/O,

this is a byte address, and for configuration and memory, it is a double-word

address. The RTL8169 supports both big-endian and little-endian byte

ordering. Write data is stable and valid when IRDYB is asserted. Read data

is stable and valid when TRDYB is asserted. Data I is transferred during

those clocks where both IRDYB and TRDYB are asserted.

AD63-32: High 32-bit PCI address and data multiplexed pins.

During an address phase (when using the DAC command or when

REQ64B is asserted), the upper 32-bits of a 64-bit address are

transferred; otherwise, these bits are reserved, and are stable and

indeterminate. During a data phase, an additional 32-bits of data are

transferred when a 64-bit transaction has been negotiated by the

assertion of REQ64B and ACK64B.

PCI bus command and byte enables multiplexed pins. During the

address phase of a transaction, C/BE3-0 define the bus command.

During the data phase, C/BE3-0 are used as Byte Enables. The Byte

Enables are valid for the entire data phase and determine which byte

lanes carry meaningful data. C/BE0 applies to byte 0, and C/BE3

applies to byte 3.

C/BE7-0B

T/S

34-35, 37-38, 190, 202,

7, 19

During an address phase (when using DAC commands or when

REQ64B is asserted), the actual bus command is transferred on

C/BE7-4; otherwise, these bits are reserved and indeterminate. During a

data phase, C/BE7-4 are Byte Enables indicating which byte lanes carry

meaningful data when a 64-bit transaction has been negotiated by the

assertion of REQ64B and ACK64B. C/BE4 applies to byte 4 and

C/BE7 applies to byte 7.

PCI clock: This clock input provides timing for all PCI transactions and

is input to the PCI device. Supports up to a 66MHz PCI clock.

Clock Run: This signal is used by the RTL8169 to request starting (or

speeding up) the clock, CLK. CLKRUNB also indicates the clock

status. For the RTL8169, CLKRUNB is an open drain output as well as

an input. The RTL8169 requests the central resource to start, speed up,

or maintain the interface clock by the assertion of CLKRUNB. For the

host system, it is an S/T/S signal. The host system (central resource) is

responsible for maintaining CLKRUNB asserted, and for driving it high

to the negated (deasserted) state.

CLK

I

176

86

CLKRUNB

I/O

DEVSELB

FRAMEB

S/T/S

207

203

Device Select: As a bus master, the RTL8169 samples this signal to

insure that a PCI target recognizes the destination address for the data

transfer. As a target, the RTL8169 asserts this signal low when it

recognizes its target address after FRAMEB is asserted.

Cycle Frame: As a bus master, this pin indicates the beginning and

duration of an access. FRAMEB is asserted low to indicate the start of a

bus transaction. While FRAMEB is asserted, data transfer continues.

When FRAMEB is deasserted, the transaction is in the final data phase.

As a target, the device monitors this signal before decoding the address

to check if the current transaction is addressed to it.

cont...

2002/03/27

Rev.1.21

7

RTL8169

GNTB

I

177

31

Grant: This signal is asserted low to indicate to the RTL8169 that the

central arbiter has granted the ownership of the bus to the RTL8169.

This input is used when the RTL8169 is acting as a bus master.

Acknowledge 64-bit Transfer: This signal is asserted low by the

device that has positively decoded its address as the target of the current

access, indicates the target is willing to transfer data using 64 bits.

ACK64B has the same timing as DEVSELB.

ACK64B

S/T/S

REQB

T/S

178

32

Request: The RTL8169 will assert this signal low to request the

ownership of the bus from the central arbiter.

REQ64B

S/T/S

Request 64-bit Transfer: The RTL8169 asserts this signal low to

indicate that it wants to perform a 64-bit data transfer.

If the RTL8169 sees the REQ64B asserted on the rising edge of PCI

RSTB, the RTL8169 is on 64-bit slot and is capable of 64-bit

transaction. Otherwise, the RTL8169 is on 32-bit slot.

Initialization Device Select: This pin allows the RTL8169 to identify

when configuration read/write transactions are intended for it.

Interrupt A: Used to request an interrupt. It is asserted low when an

interrupt condition occurs, as defined by the Interrupt Status, Interrupt

Mask.

IDSEL

INTAB

I

191

174

O/D

IRDYB

S/T/S

204

Initiator Ready: This indicates the initiating agent’s ability to complete

the current data phase of the transaction.

As a bus master, this signal will be asserted low when the RTL8169 is

ready to complete the current data phase transaction. This signal is used

in conjunction with the TRDYB signal. Data transaction takes place at

the rising edge of CLK when both IRDYB and TRDYB are asserted

low. As a target, this signal indicates that the master has put data on the

bus.

TRDYB

S/T/S

205

Target Ready: This indicates the target agent’s ability to complete the

current phase of the transaction.

As a bus master, this signal indicates that the target is ready for the data

during write operations and with the data during read operations. As a

target, this signal will be asserted low when the (slave) device is ready

to complete the current data phase transaction. This signal is used in

conjunction with the IRDYB signal. Data transaction takes place at the

rising edge of CLK when both IRDYB and TRDYB are asserted low.

Parity: This signal indicates even parity across AD31-0 and C/BE3-0

including the PAR pin. PAR is stable and valid one clock after each

address phase. For data phase, PAR is stable and valid one clock after

either IRDYB is asserted on a write transaction or TRDYB is asserted

on a read transaction. Once PAR is valid, it remains valid until one clock

after the completion of the current data phase. As a bus master, PAR is

asserted during address and write data phases. As a target, PAR is

asserted during read data phases.

Parity Upper Double Word: This signal indicates even parity across

AD63-32 and C/BE7-4 including the PAR64 pin. PAR64 is valid one

clock after each address phase on any transaction in which REQ64B is

asserted. PAR64 is stable and valid for 64-bit data phase one clock after

either IRDYB is asserted on a write transaction or TRDYB is asserted

on a read transaction. As a bus master, PAR64 is asserted during address

and write data phases. As a target, the RTL8169 only supports 32-bit

transfers, so it will not assert PAR64.

PAR

T/S

5

PAR64

39

cont...

2002/03/27

Rev.1.21

8

RTL8169

M66EN

PERRB

SERRB

I

173

1

66MHZ_ENABLE: This pin indicates to the RTL8169 whether the bus

segment is operating at 66 or 33MHz. When this pin (active high) is

asserted, the current PCI bus segment that the RTL8169 resides on

operates in 66-MHz mode. If this pin is deasserted, the current PCI bus

segment operates in 33-MHz mode.

Parity Error: This pin is used to report data parity errors during all PCI

transactions except a Special Cycle. PERRB Is driven active (low) two

clocks after a data parity error is detected by the device receiving data,

and the minimum duration of PERRB is one clock for each data phase

with parity error detected.

System Error: If an address parity error is detected and Configuration

Space Status register bit 15 (detected parity error) is enabled, the

RTL8169 asserts the SERRB pin low and bit 14 of Status register in

Configuration Space.

Stop: Indicates that the current target is requesting the master to stop the

current transaction.

S/T/S

O/D

3

STOPB

RSTB

S/T/S

I

208

175

Reset: When RSTB is asserted low, the RTL8169 performs an internal

system hardware reset. RSTB must be held for a minimum of 120 ns

periods.

5.3 FLASH/BootPROM/EEPROM/MII Interface

Symbol

MA[16:9], MA7,

MA[5:3]

Type

O

Pin No

112-109, 107,

105-104, 102, 100,

97-95

Description

Boot PROM Address Bus: These pins are used to access up to a

128k-byte flash memory or EPROM.

MA16-3: Output pins to the Boot PROM address bus.

MA8: Input pin as Aux. Power detect pin to detect if Aux. Power exists

or not, when initial power-on. Besides connecting this pin to Boot

PROM, it should be pulled high to the Aux. Power via a resistor to

detect Aux. power. If this pin is not pulled high to Aux. Power, the

RTL8169 assumes that no Aux. power exists. To support wakeup from

ACPI D3cold or APM power-down, this pin must be pulled high to aux.

power via a resistor.

MA8

O, I

101

MA6/9356SEL: Input pin as 9356 select pin at initial power-up. When

this pin is pulled high with a 10KΩ resistor, the 93C56 EEPROM is

used to store the resource data and CIS for the RTL8169. The RTL8169

latches the status of this pin at power-up to determine what EEPROM

(93C46 or 93C56) is used, afterwards, this pin is used as MA6

MA6

O, I

O

99

92

MA2/EESK

MA2-0: The MA2-0 pins are switched to EESK, EEDI, EEDO in

93C46 (93C56) programming or auto-load mode.

MA1/EEDI

MA0/EEDO

EECS

O

O, I

O

91

90

93

EEPROM Chip Select: 93C46 (93C56) chip select

Boot PROM data bus during Boot PROM mode.

MD7-0

I/O

119, 121-127

ROMCSB

OEB

O

128

130

ROM Chip Select: This is the chip select signal of the Boot PROM.

Output Enable: This enables the output buffer of the Boot PROM or

Flash memory during a read operation.

Write Enable: This signal strobes data into the Flash memory during a

write cycle.

WEB

O

129

2002/03/27

Rev.1.21

9

RTL8169

5.4 LED Interface

Symbol

LED3-0

Type

Pin No

114-116, 118

Description

O

LED pins (Active low)

1000BaseT mode:

LEDS1-

0

00

01

10

11

Tx/Rx

LINK100

ACT(Tx/Rx)

Tx

LINK10/ACT

LINK100/ACT

LED0

LED1

LINK10/100/ LINK10/100/

1000

FULL

-

1000

Rx

FULL

LINK10

LINK1000

FULL

LINK1000/ACT

LED2

LED3

TBI mode:

LEDS1-

0

00

01

10

11

ACT

-

ACT

LINK

FULL

-

Tx

LINK

Rx

-

LED0

LED1

LED2

LED3

FULL

LINK

FULL

During power down mode, the LED signals are logic high.

5.5 GMII, TBI, PHY CP

Gigabit Media Independent Interface, Ten Bit Interface, PHY Control Pin

Symbol

GTxCLK

Type

O

Pin No

145

Description

Gigabit Tx clock: In GMII mode (1000Mbps Tx clock), GTxCLK is a

continuous clock used for operation at 1000Mbps. GTxCLK provides

the timing reference for the transfer of the TxEN, TxER, and TxD

signals. The values of TxEN, TxER, and TxDs are sampled by the PHY

on the rising edge of GTxCLK.

In GMII mode or TBI mode, the GTxCLK can be used as a 125MHz

reference clock, and it used as the 125MHz transmit clock to an external

PMD and is the reference for transmit TBI signaling.

Transmit Clock (MII mode only): TxCLK is a continuous clock that

provides a timing reference for the transfer of TxD[3:0], TxEN. In MII

mode, it uses the 25MHz or 2.5MHz supplied by the external PMD

device.

Transmit Enable: In GMII mode (or MII mode), the assertion of TxEN

indicates that the RTL8169 is presenting data on the GMII (or MII) for

transmission. TxEn is asserted synchronously with the first octet (or

nibble) of the preamble and remains asserted while all octets (or

nibbles) to be transmitted are presented to the GMII (or MII).

TxCLK

I

147

143

TxEN/

Tx[9]

O

This signal is synchronous to TxCLK and provides precise framing for

data carried on TXD3-0/TXD7-0 for the external PMD. It is asserted

when TXD3-0/TXD7-0 contains valid data to be transmitted.

Tx[9]: In TBI mode, Tx[9] is the MSB of the 10-bit vector representing

one transmission code-group. Tx[0] is the first bit to be transmitted, and

Tx[9] is the last bit to be transmitted.

Tx[8] (TBI mode only): In TBI mode, Tx[8] is one of the 10-bit vector

representing one transmission code-group.

Tx[8]

cont...

O

146

2002/03/27

Rev.1.21

10

RTL8169

TxD[7:0]/

Tx[7:0]

O

I

135-142

156

Transmit Data: In GMII mode, TxD[7:0] is a bundle of eight data

signals, representing a data byte on GMII for PHY to transmit. In MII

mode, only TxD[3:0] represent a data nibble on MII for PHY to

transmit. TxD[7:0] or TxD[3:0] transition synchronously with respect

to GTxCLK or TxCLK.

Tx[7:0]: In TBI mode, TxD[7:0] is part of the 10-bit vector (TxD[9:0])

representing one transmission code-group.

Receive Clock(0): RxCLK: In GMII mode or MII mode, the receive

clock is a continuous clock that provides the timing reference for the

transfer of the RxDV, RxER, and RxD from PHY device. RxDV, RxER,

and RxD are sampled on the rising edge of RxCLK.

RxCLK/

RxCLK0

RxCLK0: In TBI mode, the 62.5MHz receive clock is a continuous

clock and provides timing reference for the RTL8169 to latch

odd-numbered receive code-groups from PHY device.

RxCLK1

I

154

152

Receive Clock1: RxCLK1: In TBI mode, the 62.5MHz receive clock is

a continuous clock and provides timing reference for the RTL8169 to

latch even-numbered receive code-groups from PHY device.

Receive Coding Error: In GMII or MII mode, this pin is asserted

synchronously with respect to RxCLK, to indicate that the PHY device

detected a symbol that is not part of the valid data or delimiter set

somewhere in the frame being received. The RxER may be asserted for

one or more clock cycles.

RxER/

Rx[9]

Rx[9]: In TBI mode, Rx[9] is the MSB of the 10-bit vector representing

one receive code-group. Rx[0] is the first bit received, and Rx[9] is the

last bit received.

Receive Data Valid: In GMII or MII mode, this input pin is asserted

synchronously with respect to RxCLK, to indicate that the PHY is

presenting recovered, decoded, and valid data to the RTL8169. RxDV

remains asserted while valid data is being presented by the PHY.

Rx[8]: In TBI mode, Rx[8] is a bit of the 10-bit vector representing one

receive code-group. Rx[0] is the first bit received, and Rx[9] is the last

bit received.

Receive Data: In GMII mode, RxD[7:0] is a bundle of eight data

signals, representing a data byte transmitted from PHY to the RTL8169

on GMII. In MII mode, only RxD[3:0] represent a data nibble

transmitted from PHY to the RTL8169 on MII. RxD[7:0] or RxD[3:0]

transition synchronously with respect to RxCLK.

RxDV/

Rx[8]

I

157

165-158

151

RxD[7:0]/

Rx[7:0]

Rx[7:0]: In TBI mode, RxD[7:0] is part of the 10-bit vector (RxD[9:0])

representing one receive code-group.

COL

Collision Detected: In GMII or MII mode, this input pin is asserted

high by PHY to indicate the detection of a collision on the twisted pair

medium, and remains asserted while the collision condition persists. In

full duplex mode, this pin’s status is ignored by the RTL8169. The COL

transitions asynchronously with respect to RxCLK, GTxCLK, or

TxCLK.

In TBI mode, this pin’s status is ignored by the RTL8169.

cont...

2002/03/27

Rev.1.21

11

RTL8169

CRS

I

148

Carrier Sense: In GMII or MII mode, this pin is asserted high by the

GMII/MII PHY device whenever the transmit or receive medium is not

idle, and is deasserted when both transmit and receive media are idle.

The CRS remains asserted throughout the duration of a collision

condition. The CRS transitions asynchronously with respect to RxCLK,

GTxCLK, or TxCLK.

In TBI mode, this pin’s status is ignored by the RTL8169.

MDC

O

169

170

Management Data Clock: In GMII or MII mode, it is a synchronous

clock to the MDIO management data input/output serial interface (about

3.125MHz) which may be asynchronous to transmit and receive clocks.

In TBI mode, this pin is a reserved pin.

MDIO

I/O

Management Data Input/Output: Bi-directional signal used to

transfer or receive control and status information from the PHY device.

MDIO is driven and sampled synchronously with respect to MDC.

In TBI mode, this pin is a reserved pin.

TBILBK

O

133

132

TBI LoopBack: The RTL8169 asserts this pin high when the TBI is in

loopback mode.

RSTPHYB

PHY Reset pin: An active low signal used by the RTL8169 to force

hardware reset to external PHYceiver at initial power-on.

5.6 Clock and NC Pins

Symbol

Clock125

Type

Pin No

Description

125MHz clock input: The 125MHz reference clock for the RTL8169

comes from either external PHYceiver or 125MHz OSC.

Reserved

I

168

NC

-

2, 4, 6, 45, 47, 49, 51,

103, 106, 108, 153,

155,

5.7 Power Pins

Symbol

VDD33

Type

Pin No

Description

+3.3V

P

8, 18, 30, 41, 55, 65,

77, 89, 113, 131, 144,

167, 179, 189, 200

27, 120, 68, 166

VDD18

GND

P

+1.8V

Ground

13, 23, 36, 48, 60, 71,

82, 98, 117, 134, 150,

171, 184, 195, 206, 33,

94, 72, 149

2002/03/27

Rev.1.21

12

RTL8169

6. Register Descriptions

The RTL8169 provides the following set of operational registers mapped into PCI memory space or I/O space.

Offset

0000h

R/W

Tag

Description

R/W

IDR0

ID Register 0: The ID registers 0-5 are only permitted to write by

4-byte access. Read access can be byte, word, or double word access.

The initial value is autoloaded from EEPROM EthernetID field.

0001h

0002h

R/W

-

IDR1

IDR2

IDR3

IDR4

IDR5

-

ID Register 1

ID Register 2

0003h

ID Register 3

0004h

ID Register 4

0005h

ID Register 5

0006h-0007h

0008h

Reserved

R/W

MAR0

Multicast Register 0: The MAR registers 0-7 are only permitted to

write by 4-bye access. Read access can be byte, word, or double word

access. Driver is responsible for initializing these registers.

Multicast Register 1

0009h

000Ah

R/W

-

MAR1

MAR2

MAR3

MAR4

MAR5

MAR6

MAR7

DTCCR

-

Multicast Register 2

000Bh

Multicast Register 3

000Ch

Multicast Register 4

000Dh

Multicast Register 5

000Eh

Multicast Register 6

000Fh

Multicast Register 7

0010h-0017h

0018h-001Fh

0020h-0027h

Dump Tally Counter Command Register (64-byte alignment)

Reserved

Transmit Normal Priority Descriptors: Start address (64-bit).

R/W

TNPDS

(256-byte alignment)

0028h-002Fh

R/W

THPDS

Transmit High Priority Descriptors: Start address (64-bit).

(256-byte alignment)

0030h-0033h

0034h-0035h

0036h

R/W

R

FLASH

ERBCR

ERSR

CR

Flash memory read/write register

Early Receive (Rx) Byte Count Register

Early Rx Status Register

R

0037h

R/W

W

-

R/W

Command Register

0038h

TPPoll

-

Transmit Priority Polling register

Reserved

0039h-003Bh

003Ch-003Dh

003Eh-003Fh

0040h-0043h

0044h-0047h

0048h-004Bh

IMR

ISR

TCR

RCR

TCTR

Interrupt Mask Register

Interrupt Status Register

Transmit (Tx) Configuration Register

Receive (Rx) Configuration Register

Timer CounT Register: This register contains

a

32-bit

general-purpose timer. Writing any value to this 32-bit register will

reset the original timer and begin the count from zero.

004Ch-004Fh

R/W

MPC

Missed Packet Counter: This 24-bit counter indicates the number of

packets discarded due to Rx FIFO overflow. After a s/w reset, MPC is

cleared. Only the lower 3 bytes are valid.

When any value is written to MPC, it will be reset.

93C46 (93C56) Command Register

Configuration Register 0

0050h

0051h

0052h

0053h

0054h

R/W

9346CR

CONFIG0

CONFIG1

CONFIG2

CONFIG3

Configuration Register 1

Configuration Register 2

Configuration Register 3

cont...

2002/03/27

Rev.1.21

13

RTL8169

0055h

0056h

R/W

-

CONFIG4

CONFIG5

-

Configuration Register 4

Configuration Register 5

Reserved

0057h

R /W

0058h-005Bh

TimerInt

Timer Interrupt Register: Once having written a nonzero value to

this register, the Timeout bit of ISR register will be set whenever the

TCTR reaches to this value. The Timeout bit will never be set as long

as TimerInt register is zero.

005Ch-005Dh

005Eh-005Fh

0060h-0063h

0064h-0067h

0068h-0069h

006Ah-006Bh

006Ch

R/W

-

R/W

R

-

R/W

-

R/W

-

R/W

-

R/W

-

MULINT

-

Multiple Interrupt Select

Reserved

PHYAR

TBICSR0

TBI_ANAR

TBI_LPAR

PHYStatus

-

PHY Access Register

TBI Control and Status Register

TBI Auto-Negotiation Advertisement Register

TBI Auto-Negotiation Link Partner Ability Register

PHY(GMII, MII, or TBI) Status Register

Reserved

006Dh-0081h

0082-0083h

0084h–008Bh

008Ch–0093h

0094h–009Bh

009Ch–00A3h

00A4h–00ABh

00ACh–00B3h

00B4h–00BBh

00BCh–00C3h

00C4h-00C5h

00C6h-00C7h

00C8h-00C9h

00CAh-00CBh

00CCh-00CDh

00CEh-00D9h

00DAh-00DBh

00DCh-00DFh

00E0h-00E1h

00E2h-00E3h

00E4h-00EBh

00ECh

-

Reserved

Wakeup0

Wakeup1

Wakeup2LD

Wakeup2HD

Wakeup3LD

Wakeup3HD

Wakeup4LD

Wakeup4HD

CRC0

Power Management wakeup frame0 (64bit)

Power Management wakeup frame1 (64bit)

Power Management wakeup frame2 (128bit), low D-Word

Power Management wakeup frame2, high D-Word

Power Management wakeup frame3 (128bit), low D-Word

Power Management wakeup frame3, high D-Word

Power Management wakeup frame4 (128bit), low D-Word

Power Management wakeup frame4, high D-Word

16-bit CRC of wakeup frame 0

CRC1

16-bit CRC of wakeup frame 1

CRC2

16-bit CRC of wakeup frame 2

CRC3

16-bit CRC of wakeup frame 3

CRC4

16-bit CRC of wakeup frame 4

-

Reserved

RMS

Rx packet Maximum Size

-

Reserved

C+CR

C+ Command Register

-

Reserved

RDSAR

ETThR

-

Receive Descriptor Start Address Register (256-byte alignment)

Early Transmit Threshold Register

Reserved

00EDh-00EFh

00F0h-00F3h

00F4h-00F7h

00F8h-00FBh

00FCh-00FFh

R/W

R

FER

Function Event Register (Cardbus only)

Function Event Mask Register (CardBus only)

Function Present State Register (CardBus only)

Function Force Event Register (CardBus only)

FEMR

FPSR

W

FFER

2002/03/27

Rev.1.21

14

RTL8169

6.1 DTCCR: Dump Tally Counter Command

(Offset 0010h-0017h, R/W)

Bit

R/W

Symbol

Description

63:6

R/W

CntrAddr Starting address of the 12 Tally Counters being dumped to. (64-byte alignment

address, 64 bytes long)

Offset of

Counter

Description

starting

address

0

8

TxOk

RxOk

TxER

64-bit counter of Tx Ok packets.

64-bit counter of Rx Ok packets.

16

64-bit packet counter of Tx errors including Tx

abort, carrier lost, Tx underrun, and out of window

collision.

24

RxEr

32-bit packet counter of Rx errors including CRC

error packets (should be larger than 8 bytes) and

missed packets.

28

30

32

36

MissPkt 16-bit counter of missed packets (CRC Ok)

resulted from Rx FIFO full.

FAE

16-bit counter of Frame Alignment Error packets

(MII mode only)

Tx1Col 32-bit counter of those Tx Ok packets with only 1

collision happened before Tx Ok.

TxMCol 32-bit counter of those Tx Ok packets with more

than 1, and less than 16 collisions happened before

Tx Ok.

40

48

56

RxOkPh 64-bit counter of all Rx Ok packets with physical

y

address matched destination ID.

RxOkBrd 64-bit counter of all Rx Ok packets with broadcast

destination ID.

RxOkMu 32-bit counter of all Rx Ok packets with multicast

l

destination ID.

60

62

TxAbt

16-bit counter of Tx abort packets.

TxUndrn 16-bit counter of Tx underrun and discard packets

(only possible on jumbo frames).

5:4

3

-

Reserved

R/W

Cmd

Command: When set, the RTL8169 begins dumping 13 Tally counters to the address

specified above.

When this bit is reset by the RTL8169, the dumping has been completed.

Reserved

2:0

-

2002/03/27

Rev.1.21

15

RTL8169

6.2 FLASH: Flash Memory Read/Write

(Offset 0030h-0033h, R)

Bit

R/W

Symbol

Description

31:24

R/W

MD7-MD0

Flash Memory Data Bus: These bits set and reflect the state of the

MD7 - MD0 pins during the write and read process respectively.

Reserved

23:21

20

-

W

ROMCSB

OEB

Chip Select: This bit sets the state of the ROMCSB pin.

Output Enable: This bit sets the state of the OEB pin.

Write Enable: This bit sets the state of the WEB pin.

Enable software access to flash memory:

1: Enable read/write access to flash memory via software and

disable the EEPROM access during flash memory access via

software.

19

18

WEB

17

SWRWEn

0: Disable read/write access to flash memory via software.

Flash Memory Address Bus: These bits set the state of the MA16-0

pins.

16:0

W

MA16-MA0

6.3 ERSR: Early Rx Status

(Offset 0036h, R)

Bit

7:4

3

R/W

Symbol

-

Description

-

R

Reserved

ERGood

Early Rx Good packet: This bit is set whenever a packet is completely

received and the packet is good. Writing a ‘1’ will clear this bit.

Early Rx Bad packet: This bit is set whenever a packet is completely

received and the packet is bad. Writing a ‘1’ will clear this bit.

Early Rx OverWrite: This bit is set when the RTL8169's local address

pointer is equal to CAPR. In the early mode, this is different from buffer

overflow. It happens when the RTL8169 detects an Rx error and wants

to fill another packet data from the beginning address of that error

packet. Writing a ‘1’ will clear this bit.

Early Rx OK: The power-on value is 0. It is set when the Rx byte count

of the arriving packet exceeds the Rx threshold. After the whole packet

is received, the RTL8169 will set ROK or RER in ISR and clear this bit

simultaneously. Setting this bit will invoke a ROK interrupt.

2

1

R

ERBad

EROVW

0

R

EROK

2002/03/27

Rev.1.21

16

RTL8169

6.4 Command

(Offset 0037h, R/W)

Bit

7:5

4

R/W

-

Symbol

Description

-

Reserved

R/W

RST

Reset: Setting this bit to 1 forces the RTL8169 into a software reset

state which disables the transmitter and receiver, reinitializes the FIFOs,

and resets the system buffer pointer to the initial value (the start address

of each descriptor group set in TNPDS, THPDS and RDSAR registers).

The values of IDR0-5, MAR0-7 and PCI configuration space will have

no changes. This bit is 1 during the reset operation, and is cleared to 0

by the RTL8169 when the reset operation is complete.

Receiver Enable

3

2

1:0

R/W

-

RE

TE

-

Transmit Enable

Reserved

6.5 TPPoll: Transmit Priority Polling

(Offset 0038h, R/W)

Bit

R/W

Symbol

Description

7

W

HPQ

High Priority Queue polling: Writing a ‘1’ to this bit will notify the

RTL8169 that there is a high priority packet(s) waiting to be

transmitted. The RTL8169 will clear this bit automatically after all

high priority packets have been transmitted.

Writing a ‘0’ to this bit has no effect.

6

W

NPQ

Normal Priority Queue polling: Writing a ‘1’ to this bit will notify

the RTL8169 that there is a normal priority packet(s) waiting to be

transmitted. The RTL8169 will clear this bit automatically after all

normal priority packets have been transmitted.

Writing a ‘0’ to this bit has no effect.

5:1

0

-

W

-

Reserved

FSWInt

Forced Software Interrupt: Writing a ‘1’ to this bit will trigger an

interrupt, and the SWInt bit (bit8, ISR, offset3Eh-3Fh) will set.

The RTL8169 will clear this bit automatically after the SWInt bit (bit8,

ISR) is cleared.

Writing a ‘0’ to this bit has no effect.

2002/03/27

Rev.1.21

17

RTL8169

6.6 Interrupt Mask

(Offset 003Ch-003Dh, R/W)

Bit

R/W

Symbol

Description

15

R/W

SERR

System Error Interrupt:

1: Enable; 0: Disable.

Time Out Interrupt:

1: Enable; 0: Disable.

Reserved

14

R/W

TimeOut

13:10

9

8

-

Reserved

R/W

SWInt

Software Interrupt:

1: Enable; 0: Disable.

7

6

5

4

3

2

R/W

TDU

FOVW

PUN/LinkChg

RDU

Tx Descriptor Unavailable Interrupt:

1: Enable; 0: Disable.

Rx FIFO Overflow Interrupt:

1: Enable; 0: Disable.

Packet Underrun/Link Change Interrupt:

1: Enable; 0: Disable.

Rx Buffer Overflow/Rx Descriptor Unavailable Interrupt:

1: Enable; 0: Disable.

Tx Error Interrupt:

TER

1: Enable; 0: Disable.

Tx Ok:

TOK

Transmit (Tx) OK: Indicates that a packet transmission is completed

successfully.

1: Enable; 0: Disable.

Rx Error Interrupt:

1

0

R/W

RER

ROK

1: Enable; 0: Disable.

Rx OK Interrupt:

1: Enable; 0: Disable.

2002/03/27

Rev.1.21

18

RTL8169

6.7 Interrupt Status

(Offset 003Eh-003Fh, R/W)

Bit

R/W

Symbol

Description

15

R/W

SERR

System Error: This bit is set to 1 when the RTL8169 signals a system

error on the PCI bus.

14

R/W

TimeOut

Time Out: This bit is set to 1 when the TCTR register reaches the value

of the TimerInt register.

13:10

9

8

-

Reserved

R/W

SWInt

Software Interrupt: This bit is set to 1 whenever a ‘1’ is written by

software to FSWInt (bit0, offset D9h, TPPoll register).

Tx Descriptor Unavailable: When set, this bit indicates that the Tx

descriptor is unavailable.

Rx FIFO Overflow: This bit set to 1 is caused by RDU, poor PCI

performance, or overloaded PCI traffic.

Packet Underrun/Link Change: This bit is set to 1 when CAPR is

written but the Rx buffer is empty, or when link status is changed.

Rx Descriptor Unavailable: When set to 1, this bit indicates that the

Rx descriptor is unavailable.

7

6

5

4

R/W

TDU

FOVW

PUN/LinkChg

RDU

The MPC (Missed Packet Counter, offset 4Ch-4Fh) indicates the

number of packets discarded after Rx FIFO overflowed.

Transmit (Tx) Error: This bit set to 1 indicates that a packet

transmission was aborted, due to excessive collisions, according to the

TXRR's setting in the TCR register.

3

R/W

TER

2

1

R/W

TOK

RER

Transmit (Tx) OK: When set to 1, this bit indicates that a packet

transmission has been completed successfully.

Receive (Rx) Error: When set to 1, this bit indicates that a packet has

either a CRC error or a frame alignment error (FAE). A Rx error packet

of CRC error is determined according to the setting of RER8, AER, AR

bits in RCR register (offset 44h-47h).

Receive (Rx) OK: In normal mode, this bit set to 1 indicates the

successful completion of a packet reception. In early mode, this bit set

to 1 indicates that the Rx byte count of the arriving packet exceeds the

early Rx threshold.

0

R/W

ROK

ꢀ

Writing 1 to any bit in the ISR will reset that bit.

2002/03/27

Rev.1.21

19

RTL8169

6.8 Transmit Configuration

(Offset 0040h-0043h, R/W)

Bit

31

R/W

Symbol

-

Description

-

Reserved

Hardware Version ID0:

30:26

R

HWVERID0

Bit30 Bit29 Bit28 Bit27 Bit26 Bit23

RTL8139

RTL8139A

RTL8139A-G

RTL8139B

RTL8130

RTL8139C

RTL8139C+

RTL8100

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RTL8169

Reserved

All other combination

25:24

R/W

IFG1, 0

InterFrameGap Time: This field allows adjustment of the interframe

gap time to be longer than the standards of 9.6 µs for 10Mbps, 960 ns

for 100Mbps, and 96 ns for 1000Mbps. The time can be programmed

from 9.6 µs to 14.4 µs (10Mbps), 960ns to 1440ns (100Mbps), and 96ns

to 144ns (1000Mbps).

The setting of the inter frame gap is:

IFG[2:0] IFG@1000MHz IFG@100MHz IFG@10MHz

(ns)

96

96 + 8

96 + 16

96 + 24

96 + 48

(ns)

(µs)

0

1

0

1

0

1

0

1

0

960

9.6

960 + 8 * 10

960 + 16 * 10

960 + 24 * 10

960 + 48 * 10

9.6 + 8 * 0.1

9.6 + 16 * 0.1

9.6 + 24 * 0.1

9.6 + 48 * 0.1

-Other values are reserved.

Hardware Version ID1: Please see HWVERID0.

23

22:20

19

R

HWVERID1

-

Reserved

InterFrameGap2

R/W

IFG2

LBK1, LBK0

18:17

Loopback test: There will be no packets on the (G)MII or TBI interface

in Digital loopback mode, provided the external phyceiver is also set in

loopback mode. The digital loopback function is independent of the

current link status.

For analog loopback tests, software must force the external phyceiver

into loopback mode while the RTL8169 operates normally.

00 : Normal operation

01 : Digital loopback mode

10 : Reserved

11 : Reserved

16

R/W

-

CRC

-

Append CRC: Setting this bit to 1 means that there is no CRC

appended at the end of a packet. Setting to 0 means that there is a CRC

appended at the end of a packet.

15:11

Reserved

cont...

2002/03/27

Rev.1.21

20

RTL8169

10:8

R/W

MXDMA2, 1, 0

Max DMA Burst Size per Tx DMA Burst: This field sets the maximum

size of transmit DMA data bursts according to the following table:

000 = 16 bytes

001 = 32 bytes

010 = 64 bytes

011 = 128 bytes

100 = 256 bytes

101 = 512 bytes

110 = 1024 bytes

111 = Unlimited

Reserved

7:0

-

ꢂ

The TCR register can only be changed after having set TE (bit2, Command register, offset 0037h).

6.9 Receive Configuration

(Offset 0044h-0047h, R/W)

Bit

31:25

24

R/W

-

Symbol

-

Description

Reserved

R/W

MulERINT

Multiple Early Interrupt Select: When this bit is set to 1, any received

packets invoke an early interrupt according to the

MULINT<MISR[11:0]> setting in early mode.

23:17

16

-

Reserved

R/W

RER8

When this bit is set to 1, the RTL8169 will calculate the CRC of any

received packed with a length larger than 8 bytes.

When this bit is cleared, the RTL8169 only calculates the CRC of any

received packet with a length larger than 64-bytes. The power-on

default is zero.

If AER or AR is set, the RTL8169 always calculates the CRC of any

incoming packet with a packet length larger than 8 bytes. The RER8 is

in a “Don’t care” state in this situation.

Rx FIFO Threshold: Specifies the Rx FIFO Threshold level. When the

number of the received data bytes from a packet, which is being

received into the Rx FIFO of the RTL8169, has reached this level (or the

FIFO contains a complete packet), the receive PCI bus master function

will begin to transfer the data from the FIFO to the host memory. This

field sets the threshold level according to the following table:

15:13

R/W

RXFTH2, 1, 0

000 = Reserved

001 = Reserved

010 = 64 bytes

011 = 128 bytes

100 = 256 bytes

101 = 512 bytes

110 = 1024 bytes

111 = no Rx threshold. The RTL8169 begins the transfer of data after

having received a whole packet in the FIFO.

Reserved

12:11

cont...

-

2002/03/27

Rev.1.21

21

RTL8169

10:8

R/W

MXDMA2, 1, 0

Max DMA Burst Size per Rx DMA Burst: This field sets the

maximum size of the receive DMA data bursts according to the

following table:

000 = Reserved

001 = Reserved

010 = 64 bytes

011 = 128 bytes

100 = 256 bytes

101 = 512 bytes

110 = 1024 bytes

111 = Unlimited

7

6

-

Reserved

R

9356SEL

This bit reflects what type of EEPROM is used.

1: The EEPROM used is 9356.

0: The EEPROM used is 9346.

Accept Error Packet:

5

R/W

AER

AR

When set to 1, all packets with CRC error, alignment error, and/or

collided fragments will be accepted.

When set to 0, all packets with CRC error, alignment error, and/or

collided fragments will be rejected.

4

R/W

Accept Runt: This bit set to 1 allows the receiver to accept packets that

are smaller than 64 bytes. The packet must be at least 8 bytes long to be

accepted as a runt.

3

2

1

0

R/W

AB

AM

APM

AAP

Accept Broadcast Packets: 1: Accept, 0: Reject

Accept Multicast Packets: 1: Accept, 0: Reject

Accept Physical Match Packets: 1: Accept, 0: Reject

Accept All Packets with Destination Address: 1: Accept, 0: Reject

2002/03/27

Rev.1.21

22

RTL8169

6.10 9346CR: 93C46 (93C56) Command

(Offset 0050h, R/W)

Bit

R/W

Symbol

Description

7:6

R/W

EEM1-0

Operating Mode: These 2 bits select the RTL8169 operating mode.

EEM1

EEM0

Operating Mode

0

1

Normal (RTL8169 network/host communication mode)

Auto-load: Entering this mode will make the RTL8169

load the contents of the 93C46 (93C56) as when the

RSTB signal is asserted. This auto-load operation will

take about 2 ms. Upon completion, the RTL8169

automatically returns to normal mode (EEM1 = EEM0 =

0) and all of the other registers are reset to default values.

93C46 (93C56) programming: In this mode, both network

and host bus master operations are disabled. The 93C46

(93C56) can be directly accessed via bit3-0 which now

reflect the states of EECS, EESK, EEDI, & EEDO pins

respectively.

1

0

1

Config register write enable: Before writing to CONFIGx

registers, the RTL8169 must be placed in this mode. This

will prevent RTL8169 configurations from accidental

change.

5:4

3

-

Reserved

R/W

R

EECS

EESK

EEDI

EEDO

These bits reflect the state of the EECS, EESK, EEDI & EEDO pins in

auto-load or 93C46 (93C56) programming mode and are valid only

when the Flash bit is cleared.

2

1

0

Note: EESK, EEDI and EEDO is valid after boot ROM complete.

6.11 CONFIG 0

(Offset 0051h, R/W)

Bit

7:3

2-0

R/W

Symbol

Description

Reserved

Select Boot ROM Size

-

R

BS2, BS1, BS0

BS2

0

BS1

0

BS0

0

Description

No Boot ROM

0

1

0

1

0

1

0

1

0

1

0

8K Boot ROM

16K Boot ROM

32K Boot ROM

64K Boot ROM

128K Boot ROM

unused

1

unused

2002/03/27

Rev.1.21

23

RTL8169

6.12 CONFIG 1

(Offset 0052h, R/W)

Bit

R/W

Symbol

Description

Refer to the LED PIN definition. These bits initial value com from

93C46/93C56.

7:6

R/W

LEDS1-0

5

4

R/W

DVRLOAD

LWACT

Driver Load: Software maybe use this bit to make sure that the driver has been

loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN,

MEMEN, BMEN of PCI configuration space are written, the RTL8169 will clear

this bit automatically.

LWAKE Active Mode: The LWACT bit and LWPTN bit in CONFIG4 register

are used to program the LWAKE pin’s output signal. According to the

combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,

active high, active low, positive (high) pulse, and negative (low) pulse. The

output pulse width is about 150 ms. In CardBus application, the LWACT and

LWPTN have no meaning.

The default value of each of these two bits is 0, i.e., the default output signal of

LWAKE pin is an active high signal.

LWAKE output

LWACT

0

1

0

1

Active high*

Active low

LWPTN

Positive pulse

Negative pulse

* Default value.

3

2

1

R

MEMMAP

IOMAP

VPD

Memory Mapping: The operational registers are mapped into PCI memory space.

I/O Mapping: The operational registers are mapped into PCI I/O space.

Vital Product Data: Set to enable Vital Product Data. The VPD data is stored in

93C46 or 93C56 from within offset 40h-7Fh.

R/W

0

R/W

PMEn

Power Management Enable:

Writable only when 93C46CR register EEM1=EEM0=1

Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI

Configuration space offset 06h.

Let B denote the Cap_Ptr register in the PCI Configuration space offset 34h.

Let C denote the Cap_ID (power management) register in the PCI

Configuration space offset 0DCh.

Let D denote the power management registers in the PCI Configuration space

offset from 0DDh to 0E1h.

Let E denote the Next_Ptr (power management) register in the PCI

Configuration space offset 0DDh.

PMEn setting:

0: A=B=C=E=0, D is invalid

1: A=1, B=0DCh, C=01h, D is valid, E is valid and depends on whether VPD

is enabled or not.

2002/03/27

Rev.1.21

24

RTL8169

6.13 CONFIG 2

(Offset 0053h, R)

Bit

7:5

4

R/W

Symbol

-

Description

-

R

Reserved

Aux_Status

Auxiliary Power Present Status:

1: The Aux. Power is present.

0: The Aux. Power is absent.

The value of this bit is fixed after each PCI reset.

PCI Bus Width:

3

R

PCIBusWidth

PCICLKF2-0

1: 64-bit slot

0: 32-bit slot

2:0

PCI clock frequency:

PCICLKF2-0

000

MHz

33

001

66

Other values

Reserved

6.14 CONFIG 3

(Offset 0054h, R/W)

Bit

R/W

Symbol

Description

7

R

GNTSel

Grant Select: Select the Frame’s asserted time after the Grant signal

has been asserted. The Frame and Grant are the PCI signals.

1: delay one clock from GNT assertion.

0: No delay

Reserved

6

5

-

R/W

Magic

Magic Packet: This bit is valid when the PWEn bit of CONFIG1

register is set. The RTL8169 will assert the PMEB signal to wakeup the

operating system when the Magic Packet is received.

Once the RTL8169 has been enabled for Magic Packet wakeup and has

been put into an adequate state, it scans all incoming packets addressed to

the node for a specific data sequence, which indicates to the controller that

this is a Magic Packet frame. A Magic Packet frame must also meet the

basic requirements: Destination address + Source address + data + CRC

The destination address may be the node ID of the receiving station or a

multicast address, which includes the broadcast address.

The specific sequence consists of 16 duplications of 6 byte ID registers,

with no breaks or interrupts. This sequence can be located anywhere within

the packet, but must be preceded by a synchronization stream, 6 bytes of

FFh. The device will also accept a multicast address, as long as the 16

duplications of the IEEE address match the address of the ID registers.

If the Node ID is 11h 22h 33h 44h 55h 66h, then the format of the Magic

frame looks like the following:

Destination address + source address + MISC + FF FF FF FF FF FF +

MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11

22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44

55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11

22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44

55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC

cont...

2002/03/27

Rev.1.21

25

RTL8169

4

R/W

LinkUp

Link Up: This bit is valid when the PWEn bit of the CONFIG1 register

is set. The RTL8169, in an adequate power state, will assert the PMEB

signal to wakeup the operating system when the cable connection is

reestablished.

3

2

1

R

CardB_En

CLKRUN_En

FuncRegEn

Card Bus Enable:

1: Enable CardBus related registers and functions.

0: Disable CardBus related registers and functions.

CLKRUN Enable:

1: Enable CLKRUN.

0: Disable CLKRUN.

Functions Registers Enable (CardBus only):

1: Enable the 4 Function Registers (Function Event Register,

Function Event Mask Register, Function Present State Register, and

Function Force Event Register) for CardBus application.

0: Disable the 4 Function Registers for CardBus application.

Fast Back to Back Enable: 1: Enable; 0: Disable.

0

R

FBtBEn

6.15 CONFIG 4

(Offset 0055h, R/W)

Bit

7:5

4

R/W

-

Symbol

-

Description

Reserved

R/W

LWPME

LANWAKE vs PMEB:

1: The LWAKE can only be asserted when the PMEB is asserted and

the ISOLATEB is low.

0: The LWAKE and PMEB are asserted at the same time.

In CardBus applications, this bit has no meaning.

3

2

1:0

-

R/W

-

Reserved

LWPTN

-

LWAKE Pattern: Please refer to the LWACT bit in CONFIG1 register.

Reserved

2002/03/27

Rev.1.21

26

RTL8169

6.16 CONFIG 5

(Offset 0056h, R/W)

This register, unlike other Config registers, is not protected by 93C46 Command register. I.e. there is no need to enable the

Config register write prior to writing to Config5.

Bit

7

6

R/W

-

R/W

Symbol

-

BWF

Description

Reserved

Broadcast Wakeup Frame:

1: Enable Broadcast Wakeup Frame with mask bytes of only DID

field = FF FF FF FF FF FF.

0: Default value. Disable Broadcast Wakeup Frame with mask bytes

of only DID field = FF FF FF FF FF FF.

The power-on default value of this bit is 0.

Multicast Wakeup Frame:

5

4

R/W

MWF

UWF

1: Enable Multicast Wakeup Frame with mask bytes of only DID

field, which is a multicast address.

0: Default value. Disable Multicast Wakeup Frame with mask bytes

of only DID field, which is a multicast address.

The power-on default value of this bit is 0.

Unicast Wakeup Frame:

1: Enable Unicast Wakeup Frame with mask bytes of only DID

field, which is its own physical address.

0: Default value. Disable Unicast Wakeup Frame with mask bytes

of only DID field, which is its own physical address.

The power-on default value of this bit is 0.

Reserved

3:2

1

-

R/W

LANWake

LANWake Signal Enable/Disable:

1: Enable LANWake signal.

0: Disable LANWake signal.

0

R/W

PME_STS

PME_Status bit: Always sticky/can be reset by PCI RST# and

software.

1: The PME_Status bit can be reset by PCI reset or by software.

0: The PME_Status bit can only be reset by software.

ꢃ

Bit1 and bit0 are auto-loaded from the EEPROM Config5 byte to the RTL8169 Config5 register.

2002/03/27

Rev.1.21

27

RTL8169

6.17 Multiple Interrupt Select

(Offset 005Ch-005Dh, R/W)

Bit

15:12

11:0

R/W

-

Symbol

-

Description

Reserved

R/W

MISR11-0

Multiple Interrupt Select: Indicates that the RTL8169 will make a

receive interrupt after the RTL8169 has transferred the data bytes

specified in this register into the system memory. If the value of this

register is zero, there will be no early receive interrupts before the whole

received packet is transferred to system memory. Bit1, 0 must be zero.

ꢃ

When MulERINT=1, any received packet invokes an early interrupt according to the MISR[11:0] setting in early mode.

6.18 PHYAR: PHY Access

(Offset 0060h-0063h, R/W)

PHY address is fixed at 00001.

Bit

R/W

Symbol

Flag

Description

31

R/W

Flag bit, used as PCI VPD access method:

1: Write data to MII register, and turn to 0 automatically whenever

the RTL8169 has completed writing to the specified MII register.

0: Read data from MII register, and turn to 1 automatically whenever

the RTL8169 has completed retrieving data from the specified MII

register.

30:21

20:16

15:0

-

Reserved

R/W

RegAddr4-0

Data15-0

5-bit GMII/MII register address.

16-bit GMII/MII register data.

6.19 TBICSR: Ten Bit Interface Control and Status

(Offset 0064h-0067h, R/W)

Bit

R/W

Symbol

Description

31

R/W

ResetTBI

Reset TBI: This bit, when set, indicates to the TBI to reset the

interfacing PHY device. This bit is cleared when the reset process is

completed.

30

29

28

R/W

TBILoopBack

TBINWEn

TBI Loopback Enable: This bit, when set, indicates to the TBI that

the interfacing PHY device is in loopback mode.

TBI Auto-negotiation Enable: This bit, when set, enables the

auto-negotiation function for the TBI interface.

TBI Restart Auto-negotiation: This bit, when set, restarts the

auto-negotiation. This bit is cleared when the auto-negotiation

completes.

TBIReNW

27:26

25

-

R

-

Reserved

TBILinkOk

TBI Link Ok: This bit, when set, indicates that the channel

connecting to the link partner is established.

TBI Nway Complete: This bit, when set, indicates that the

auto-negotiation process has completed in TBI mode.

Reserved: For Realtek internal testing.

24

R

TBINWComplete

23:20

19

TXOSETST3-0

-

Reserved

18:16

15:13

12:8

7:4

ANST2-0

-

Reserved: For Realtek internal testing.

Reserved

RXST4-0

SYNCST3-0

TXCGST3-0

Reserved: For Realtek internal testing.

3:0

Reserved: For Realtek internal testing.

2002/03/27

Rev.1.21

28

RTL8169

6.20 TBI_ANAR: TBI Auto-Negotiation Advertisement

(Offset 0068h-0069h, R/W)

Bit

15:14

13:12

R/W

-

R/W

Symbol

-

RF2, RF1

Description

Reserved. Always 0.

Remote Fault Bits: These 2 bits indicate that a fault or error condition

has occurred. The default value is 00.

RF1

RF2

Description

No error, link Ok (default)

Offline

Link_Failure

Auto-Negotiation Error

0

1

0

1

0

1

11:9

8:7

-

Reserved. Always 0.

R/W

PS2(ASM_DIR),

PS1(PAUSE)

Asymmetric Pause: When this bit is set, the value of bit7 (Pause)

indicates the direction PAUSE frames are supported.

PS1

0

PS2

0

1

Capability

No Pause.

Asymmetric PAUSE toward link

partner.

1

0

1

Symmetric PAUSE.

Both symmetric PAUSE and

asymmetric PAUSE toward local

device.

6

5

-

Reserved.

R

FullDup

Full Duplex: This bit is always set. Full duplex capability is

advertised toward the link partner in NWay mode.

Reserved

4:0

-

6.21 TBI_LPAR:TBIAuto-NegotiationLinkPartnerAbility

(Offset 006Ah-006Bh, R)

Bit

R/W

Symbol

Description

15

R

link partner has a next page to transmit.

14

R

Ack

Acknowledge: When set, this bit indicates that the link partner has

successfully received at least 3 consecutive and matching pages

(ignoring the Ack bit in the received pages).

13:12

RF2, RF1

Remote Fault bits: These 2 bits indicate that a fault or error condition

has occurred. The default value is 00.

RF1

RF2

Description

No error, link Ok (default)

Offline

Link_Failure

Auto-Negotiation Error

0

1

0

1

0

1

11:9

-

Reserved

cont...

2002/03/27

Rev.1.21

29

RTL8169

8:7

R

PS2(ASM_DIR),

PS1(PAUSE)

Asymmetric Pause: When this bit is set, the value of bit7 (Pause)

indicates the direction that PAUSE frames are supported by the link partner.

PS1

0

PS2

0

Capability

No Pause.

0

1

Asymmetric PAUSE toward link

partner.

1

0

1

Symmetric PAUSE.

Both symmetric PAUSE and

asymmetric PAUSE toward local

device.

6

5

4:0

R

-

HalfDup

FullDup

-

Half Duplex: When set, the link partner supports half duplex.

Full Duplex: When set, the link partner supports full duplex.

Reserved

6.22 PHYStatus: PHY(GMII or TBI) Status

(Offset 006Ch, R)

Bit

R/W

Symbol

Description

7

R

EnTBI

TBI Enable: This bit is autoloaded from the EEPROM.

1: TBI mode, 0: GMII(MII) mode.

6

5

4

3

2

1

0

R

TxFlow

RxFlow

1000MF

100M

Transmit Flow Control: 1: Enabled, 0: Disabled.

Receive Flow Control: 1: Enabled, 0: Disabled.

Link speed is 1000Mbps and in full-duplex. (GMII mode only)

Link speed is 100Mbps. (GMII or MII mode only)

Link speed is 10Mbps. (GMII or MII mode only)

Link Status. 1: Link Ok, 0: No Link.

10M

LinkSts

FullDup

Full-Duplex Status: 1: Full-duplex mode, 0: Half-duplex mode.

-

MII registers polling cycle: 320ns * (32 MDC clock + 32 MDC clock) * 6 registers

6.23 RMS: Receive (Rx) Packet Maximum Size

(Offset 00DAh-00DBh, R)

Bit

15:14

13:0

R/W

-

R/W

Symbol

-

RMS

Description

Reserved

Rx packet Maximum Size:

i. This register should be always set to a value other than 0, in

order to receive packets.

ii. The maximum size supported is 2¹⁴-1, i.e., 16K-1 bytes.

2002/03/27

Rev.1.21

30

RTL8169

6.24 C+CR: C+ Command

(Offset 00E0h-00E1h, R/W)

Bit

15:10

9

R/W

-

Symbol

-

Description

Reserved

R/W

ENDIAN

Endian Mode:

1: Big-endian mode.

0: Little-endian mode.

8

7

6

5

4

-

Reserved (Home LAN Enable, always 0)

-

Reserved

R/W

RxVLAN

RxChkSum

DAC

Receive VLAN De-tagging Enable: 1: Enable; 0: Disable.

Receive Checksum Offload Enable: 1: Enable; 0: Disable.

PCI Dual Address Cycle Enable: When set, the RTL8169 will

perform Tx/Rx DMA using PCI Dual Address Cycle only when the

High 32-bit buffer address is not equal to 0.

1: Enable; 0: Disable (initial value at power-up).

PCI Multiple Read/Write Enable: If this bit is enabled, the setting of

Max Tx/Rx DMA burst size is no longer valid.

1: Enable; 0: Disable.

3

R/W

-

MulRW

-

2:0

Reserved

ꢀ

This register is the key before configuring other registers and descriptors.

This register is word access only, byte access to this register has no effect.

6.25 RDSAR: Receive Descriptor Start Address

(Offset 00E4h-00EBh, R/W)

Bit

63:0

R/W

Symbol

RDSA

Description

Receive Descriptor Start Address: 64-bit address, 256-byte

alignment address.

Bit[31:0]: Offset E7h-E4h, low 32-bit address.

Bit[63:32]: Offset EBh-E8h, high 32-bit address.

6.26 ETThR: Early Transmit Threshold

(Offset 00ECh, R/W)

Bit

7:6

5:0

R/W

-

Symbol

-

Description

Reserved

R/W

ETTh

Early Tx Threshold: Specifies the threshold level in the Tx FIFO to

begin the transmission. When the byte count of the data in the Tx

FIFO reaches this level, (or the FIFO contains at least one complete

packet) the RTL8169 will transmit the packet.

-

These fields count from 000001 to 111111 in units of 32 bytes.

This threshold must be avoided from exceeding 2K bytes.

000000 is reserved. Do not set to this value.

2002/03/27

Rev.1.21

31

RTL8169

6.27 Function Event

(Offset 00F0h-00F3h, R/W)

Bit

31:16

15

R/W

-

Symbol

-

Description

Reserved

R/W

INTR

Interrupt: This bit is set to 1 when the INTR field in the Function Force

Event Register is set. Writing a 1 may clear this bit. Writing a 0 has no

effect. This bit is not affected by the RST# pin and software reset.

Reserved

General Wakeup: This bit is set to 1 when the GWAKE field in the

Function Present State Register changes its state from 0 to 1. This bit

can also be set when the GWAKE bit of the Function Force Register is

set. Writing a 1 may clear this bit. Writing a 0 has no effect. This bit is

not affected by the RST# pin.

14:5

4

-

R/W

GWAKE

3:0

-

Reserved

ꢃ

This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).

The Function Event (Offset F0h), Function Event Mask (Offset F4h), Function Present State (Offset F8h), and Function

Force Event (Offset FCh) registers have some corresponding fields with the same names. The GWAKE and INTR bits

of these registers reflect the wake-up event signaled on the SCTCSCHG pin. The operation of CSTCSCHG pin is

similar to PME# pin except that the CSTCSCHG pin is asserted high.

6.28 Function Event Mask

(Offset 00F4h-00F7h, R/W)

Bit

31:16

15

R/W

-

Symbol

-

Description

Reserved

R/W

INTR

Interrupt mask: When cleared (0), setting of the INTR bit in either

the Function Present State Register or the Function Event Register will

neither cause assertion of the INT# signal while the CardBus PC Card

interface is powered up, nor the system Wakeup (CSTSCHG) while

the interface is powered off.

Setting this bit to 1, enables the INTR bit in both the Function Present

State Register and the Function Event Register to generate the INT#

signal (and the system Wakeup if the corresponding WKUP field in

this Function Event Mask Register is also set).

This bit is not affected by RST#.

14

R/W

WKUP

Wakeup mask: When cleared (0), the Wakeup function is disabled,

i.e., the setting of this bit in the Function Event Register will not assert

the CSTSCHG signal.

Setting this bit to 1, enables the fields in the Function Event Register to

assert the CSTSCHG signal.

This bit is not affected by RST#.

13:5

4

-

Reserved

R/W

GWAKE

General Wakeup mask: When cleared (0), setting this bit in the

Function Event Register will not cause CSTSCHG pin asserted.

Setting this bit to 1, enables the GWAKE field in the Function Event

Register to assert CSTSCHG pin if bit14 of this register is also set.

This bit is not affected by the RST# pin.

3:0

-

Reserved

ꢃ

This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).

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RTL8169

6.29 Function Preset State

(Offset 00F8h-00FBh, R)

Bit

31:16

15

R/W

Symbol

-

Description

-

Reserved

R

INTR

Interrupt: This bit is set when one of the ISR register bits has been set

to 1. This bit remains set (1), until all of the ISR register bits have been

cleared.

This bit is not affected by the RST# pin.

14:5

4

-

R

-

Reserved

GWAKE

General Wakeup: This bit reflects the current state of the Wakeup

event(s), and is just like the PME_Status bit of the PMCSR register.

This bit remains set (1), until the PME_Status bit of the PMCSR

register is cleared.

It is not affected by the RST# pin.

Reserved

3:0

-

ꢃ

This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).

This read-only register reflects the current state of the function.

6.30 Function Force Event

(Offset 00FCh-00FFh, W)

Bit

31:16

15

R/W

-

Symbol

-

Description

Reserved

W

INTR

Interrupt: Writing a 1 sets the INTR bit in the Function Event

Register. However, the INTR bit in the Function Present State Register

is not affected and continues to reflect the current state of the ISR

register.

Writing a 0 to this bit has no effect.

14:5

4

-

W

-

Reserved

GWAKE

General Wakeup: Setting this bit to 1, sets the GWAKE bit in the

Function Event Register. However, the GWAKE bit in the Function

Present State Register is not affected and continues to reflect the

current state of the Wakeup request.

Writing a 0 to this bit has no effect.

Reserved

3:0

-

ꢃ

This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).

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33

RTL8169

7. EEPROM (93C46 or 93C56) Contents

The RTL8169 supports the attachment of an external EEPROM. The 93C46 is a 1K-bit EEPROM, and the 93C56 is a 2K-bit

EEPROM. The EEPROM interface provides the ability for the RTL8169 to read from and write data to an external serial

EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be

overridden following internal power on reset or software EEPROM autoload command. The RTL8169 will autoload values from

the EEPROM to these fields in configuration space and I/O space. If the EEPROM is not present, the RTL8169 initialization

uses default values for the appropriate Configuration and Operational Registers. Software can read and write to the EEPROM

using “bit-bang” accesses via the 9346CR Register.

Although it is actually addressed by words, its contents are listed below by bytes for convenience. After the initial power on or

autoload command in 9346CR, the RTL8169 performs a series of EEPROM read operations from the 93C46 (93C56) address

00h to 31h.

ꢄ

It is suggested to obtain Realtek approval before changing the default settings of the EEPROM.

Bytes

00h

Contents

29h

Description

These 2 bytes contain ID code words for the RTL8169. The RTL8169 will load the

contents of the EEPROM into the corresponding location if the ID word (8129h) is

correct. Otherwise, the Vendor ID and Device ID of the PCI configuration space are

"10ECh" and "8169h".

01h

81h

02h-03h

04h-05h

06h-07h

08h-09h

0Ah

VID

DID

SVID

SMID

MNGNT

MXLAT

PCI Vendor ID: PCI configuration space offset 00h-01h.

PCI Device ID: PCI configuration space offset 02h-03h.

PCI Subsystem Vendor ID: PCI configuration space offset 2Ch-2Dh.

PCI Subsystem ID: PCI configuration space offset 2Eh-2Fh.

PCI Minimum Grant Timer: PCI configuration space offset 3Eh.

PCI Maximum Latency Timer: PCI configuration space offset 3Fh. Set by software to

the number of PCI clocks that the RTL8169 may hold the PCI bus.

Bit3: EnTBI. When set, TBI mode is enabled. Otherwise, the RTL8169 operates in

GMII/MII mode.

0Bh

0Ch

CONFIGx

Bit

7

6

5

4

3

2

1

0

-

EnTBI (bit7,

PHYStatus)

-

0Dh

CONFIG3

RTL8169 Configuration register 3: Operational register offset 59h.

0Eh-13h

Ethernet ID

Ethernet ID: After auto-load command or hardware reset, the RTL8169 loads Ethernet

ID to IDR0-IDR5 of the RTL8169's I/O registers.

RTL8169 Configuration register 0: Operational registers offset 51h.

RTL8169 Configuration register 1: Operational registers offset 52h.

Reserved: Do not change this field without Realtek approval.

Power Management Capabilities. PCI configuration space address 52h and 53h.

Reserved

14h

15h

16h-17h

CONFIG0

CONFIG1

PMC

18h

19h

-

CONFIG4

Reserved: Do not change this field without Realtek approval.

RTL8169 Configuration register 4, operational registers offset 5Ah.

Reserved

1Ah-1Eh

1Fh

-

CONFIG_5

Do not change this field without Realtek approval.

Bit7-2: Reserved.

Bit1: LANWake signal Enable/Disable

Set to 1: Enable LANWake signal.

Set to 0: Disable LANWake signal.

Bit0: PME_Status bit property

Set to 1: The PME_Status bit can be reset by PCI reset or by software if

D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a

sticky bit.

Set to 0: The PME_Status bit is always a sticky bit and can only be reset by software.

cont...

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34

RTL8169

20h-2Fh

30h-31h

-

Reserved

CISPointer

Reserved: Do not change this field without Realtek approval.

CIS Pointer.

32h-33h

CheckSum

Reserved: Do not change this field without Realtek approval.

Checksum of the EEPROM content.

Reserved: Do not change this field without Realtek approval.

PXE ROM code parameter.

VPD data field: Offset 40h is the start address of the VPD data.

CIS data field: Offset 80h is the start address of the CIS data. (93C56 only).

34h-3Eh

3Fh

-

PXE_Para

40h-7Fh

80h-FFh

VPD_Data

CIS_Data

7.1 EEPROM Registers

Offset

Name

Type

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00h-05h IDR0 – IDR5 R/W*

51h

52h

54h

CONFIG0

CONFIG1

CONFIG3

R

W

R

-

BS2

-

BS1

-

VPD

BS0

-

PMEN

*

-

LEDS1

GNTDel

LEDS0 DVRLOAD LWACT MEMMAP IOMAP

LEDS0 DVRLOAD LWACT

*

-

W

R

-

Magic

LinkUp CardB_En CLKRU FuncReg FBtBEn

N_En

-

LWPTN

En

-

*

-

Magic

-

LinkUp

LWPME

-

W

55h

56h

CONFIG4

CONFIG5

*

RxFIFOAuto

R/W

Clr

-

*

-

LANWakePME_STS

R/W

R

6Ch

E1h

PHYStatus

C+CR

EnTBI

-

R/W

Endian

*'

The registers marked with type = 'W can be written only if bits EEM1=EEM0=1.

*

7.2 EEPROM Power Management Registers

Configuration Name Type

Space offset

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DEh

DFh

PMC

R

Aux_I_b1 Aux_I_b0

DSI

Reserved PMECLK

Version

D1

PME_D3_coldPME_D3_hotPME_D2 PME_D1 PME_D0

D2

Aux_I_b2

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35

RTL8169

8. PCI Configuration Space Registers

8.1 PCI Bus Interface

The RTL8169 implements the PCI bus interface as defined in the PCI Local Bus Specifications Rev. 2.2. When internal registers

are being accessed, the RTL8169 acts as a PCI target (slave mode). When accessing host memory for descriptor or packet data

transfer, the RTL8169 acts as a PCI bus master.

All of the required pins and functions are implemented in the RTL8169 as well as the optional pin, INTAB for support of interrupt

requests is implemented as well. The bus interface also supports 64-bit and 66Mhz operation in addition to the more common 32-bit

and 33-Mhz capabilities. For more information, refer to the PCI Local Bus Specifications Rev. 2.2, December 18, 1998.

8.1.1 Byte Ordering

The RTL8169 can be configured to order the bytes of data on the PCI AD bus to conform to little-endian or big-endian ordering

through the use of the ENDIAN bit of the C+ Command Register. When the RTL8169 is configured in big-endian mode, all the

data in the data phase of either memory or I/O transaction to or from RTL8169 is in big-endian mode. All data in the data phase

of any PCI configuration transaction to the RTL8169 should be in little-endian mode, regardless if the RTL8169 is set to

big-endian or little-endian mode.

When configured for little-endian mode (ENDIAN bit=0), the byte orientation for receive and transmit data and descriptors in

system memory is as follows:

31

24

23

16 15

8

7

0

Byte 3

Byte 2

Byte 1

Byte 0

C/BE[3]

(MSB)

C/BE[2]

C/BE[1]

C/BE[0]

(LSB)

Little-Endian Byte Ordering

When configured for big-endian mode (ENDIAN bit=1), the byte orientation for receive and transmit data and descriptors in

system memory is as follows:

31

24 23

16 15

8

7

0

Byte 0

Byte 1

Byte 2

Byte 3

C/BE[3]

(LSB)

C/BE[2]

C/BE[1]

C/BE[0]

(MSB)

Big-Endian Byte Ordering

8.1.2 Interrupt Control

Interrupts are performed by asynchronously asserting the INTAB pin. This pin is an open drain output. The source of the

interrupt can be determined by reading the Interrupt Status Register (ISR). One or more bits in the ISR will be set, denoting all

currently pending interrupts. Writing 1 to any bit in the ISR register clears that bit. Masking of specific interrupts can be

accomplished by using the Interrupt Mask Register (IMR). Assertion of INTAB can be prevented by clearing the Interrupt

Enable bit in the Interrupt Mask Register. This allows the system to defer interrupt processing as needed.

8.1.3 Latency Timer

The PCI Latency Timer described in LTR defines the maximum number of bus clocks that the device will hold the bus. Once the

device gains control of the bus and issues FRAMEB, the Latency Timer will begin counting down. The LTR register specifies,

in units of PCI bus clocks, the value of the latency timer of the RTL8169. When the RTL8169 asserts FRAMEB, it enables its

latency timer to count. If the RTL8169 deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored.

Otherwise, after the count expires, the RTL8169 initiates transaction termination as soon as its GNTB is deasserted. Software is

able to read or write to LTR, and the default value is 00H.

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36

RTL8169

8.1.4 64-Bit Data Operation

The RTL8169 samples the REQ64B pin at PCI RSTB deasserted to determine if the bus is 64-bit capable.

8.1.5 64-Bit Addressing

The RTL8169 supports 64-bit addressing (Dual Address Cycle, DAC) as a bus master for transferring descriptor and packet data

information. The DAC mode can be enabled or disabled through software. The RTL8169 only supports 32-bit addressing as a

target.

8.2 Bus Operation

8.2.1 Target Read

A Target Read operation starts with the system generating FRAMEB, Address, and either an IO read (0010b) or Memory Read

(0110b) command. If the 32-bit address on the address bus matches the IO address range specified in IOAR (for I/O reads) or the

memory address range specified in MEM (for memory reads), the RTL8169 will generate DEVSELB 2 clock cycles later

(medium speed). The system must tri-state the Address bus, and convert the C/BE bus to byte enables, after the address cycle. On

the 2nd cycle after the assertion of DEVSELB, all 32-bits of data and TRDYB will become valid. If IRDYB is asserted at that

time, TRDYB will be forced HIGH on the next clock for 1 cycle, and then tri-stated.

If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8169 will still make data available as described above, but will

also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until FRAMEB is

detected as deasserted.

Target Read Operation

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37

RTL8169

8.2.2 Target Write

A Target Write operation starts with the system generating FRAMEN, Address, and Command (0011b or 0111b). If the upper 24

bits on the address bus match IOAR (for I/O reads) or MEM (for memory reads), the RTL8169 will generate DEVSELB 2 clock

cycles later. On the 2nd cycle after the assertion of DEVSELB, the device will monitor the IRDYB signal. If IRDYB is asserted

at that time, the RTL8169 will assert TRDYB. On the next clock the 32-bit double word will be latched in, and TRDYB will be

forced HIGH for 1 cycle and then tri-stated. Target write operations must be 32-bits wide.

If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8169 will still latch the first double word as described above,

but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until

FRAMEB is detected as deasserted.

Target Write Operation

8.2.3 Master Read

A Master Read operation starts with the RTL8169 asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB,

Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3

cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB.

The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within 8 clocks, the device will

issue a master abort by asserting FRAMEB HIGH for 1 cycle, and IRDYB will be forced HIGH on the following cycle. Both

signals will become tri-state on the cycle following their deassertion.

On the clock edge after the generation of Address and Command, the address bus will become tri-state, and the C/BE bus will contain

valid byte enables. On the clock edge after FRAMEB was asserted, IRDYB will be asserted (and FRAMEB will be deasserted if this

is to be a single read operation). On the clock where both TRDYB and DEVSELB are detected as asserted, data will be latched in (and

the byte enables will change if necessary). This will continue until the cycle following the deassertion of FRAMEB.

On the clock where the second to last read cycle occurs, FRAMEB will be forced HIGH (it will be tri-stated 1 cycle later). On the

next clock edge that the device detects TRDYB asserted, it will force IRDYB HIGH. It, too, will be tri-stated 1 cycle later. This

will conclude the read operation. The RTL8169 will never force a wait state during a read operation.

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38

RTL8169

Master Read Operation

8.2.4 Master Write

A Master Write operation starts with the RTL8169 asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB,

Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3

cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB.

The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within 8 clocks, the device will

issue a Master Abort by asserting FRAMEB HIGH for 1 cycle. IRDYB will be forced HIGH on the following cycle. Both signals

will become tri-state on the cycle following their deassertion.

On the clock edge after the generation of Address and Command, the data bus will become valid, and the C/BE bus will contain

valid byte enables. On the clock edge after FRAMEB was asserted, IRDYB will be asserted (and FRAMEB will be deasserted if

this is to be a single read operation). On the clock where both TRDYB and DEVSELB are detected as asserted, valid data for the

next cycle will become available (and the byte enables will change if necessary). This will continue until the cycle following the

deassertion of FRAMEB.

On the clock where the second to last write cycle occurs, FRAMEB will be forced HIGH (it will be tri-stated 1 cycle later). On

the next clock edge that the device detects TRDYB asserted, it will force IRDYB HIGH. It, too, will be tri-stated 1 cycle later.

This will conclude the write operation. The RTL8169 will never force a wait state during a write operation.

Master Write Operation

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39

RTL8169

8.2.5 Configuration Access

Configuration register accesses are similar to target reads and writes in that they are single data word transfers and are initiated

by the system. For the system to initiate a Configuration access, it must also generate IDSEL as well as the correct Command

(1010b or 1011b) during the Address phase. The RTL8169 will respond as it does during Target operations. Configuration reads

must be 32-bits wide, but writes may access individual bytes.

8.3 Packet Buffering

The RTL8169 incorporates two independent FIFOs for transferring data to/from the system interface and from/to the network.

The FIFOs, providing temporary storage of data freeing the host system from the real-time demands of the network.

The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the Transmit Configuration and

Receive Configuration registers. These values determine how full or empty the FIFOs must be before the device requests the

bus. Additionally, there is a threshold value that determines how full the transmit FIFO must be before beginning transmission.

Once the RTL8169 requests the bus, it will attempt to empty or fill the FIFOs as allowed by the respective MXDMA settings in

the Transmit Configuration and Receive Configuration registers.

8.3.1 Transmit Buffer Manager

The buffer management scheme used on the RTL8169 allows quick, simple and efficient use of the frame buffer memory. The

buffer management scheme uses separate buffers and descriptors for packet information. This allows effective transfers of data

to the transmit buffer manager by simply transferring the descriptor information to the transmit queue.

The Tx Buffer Manager DMAs packet data from system memory and places it in the 8KB transmit FIFO, and pulls data from the

FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO, allowing packets to be transmitted with minimum

interframe gap. The way in which the FIFO is emptied and filled is controlled by the ETTH (Early Transmit Threshold) and

RXFTH (Rx FIFO Threshold) values. Additionally, once the RTL8169 requests the bus, it will attempt to fill the FIFO as

allowed by the MXDMA setting.

The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by drawing from two separate

descriptor lists to fill the internal FIFO. If packets are available in the high priority queues, they will be loaded into the FIFO

before those of low priority.

8.3.2 Receive Buffer Manager

The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer Manager retrieves

packet data from the Rx MAC and places it in the 32KB receive data FIFO, and pulls data from the FIFO for DMA to system

memory. Similar to the transmit FIFO, the receive FIFO is controlled by the FIFO threshold value in RXFTH. This value

determines the number of long words written into the FIFO from the MAC unit before a DMA request for system memory

occurs. Once the RTL8169 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less

than one long word, or has reached the end of the packet, or the max DMA burst size is reached , as set in MXDMA.

8.3.3 Packet Recognition

The Rx packet filter and recognition logic allows software to control which packets are accepted, based on destination address

and packet type. Address recognition logic includes support for broadcast, multicast hash, and unicast addresses. The packet

recognition logic includes support for WOL, Pause, and programmable pattern recognition.

2002/03/27

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40

RTL8169

8.4 PCI Configuration Space Table

No.

00h

01h

02h

03h

Name

Type

R

Bit7

Bit6

Bit5

Bit4

VID4

VID12

DID4

DID12

MWIEN

0

Bit3

Bit2

VID2

VID10

DID2

DID10

Bit1

VID1

VID9

DID1

DID9

Bit0

VID0

VID8

DID0

DID8

VID

VID7

VID6

VID5

VID3

R

VID15

VID14

VID13

VID11

DID

R

DID7

DID6

DID5

DID3

R

DID15

DID14

DID13

DID11

04h Command

05h

R

0

PERRSP

0

-

0

BMEN MEMEN

IOEN

W

-

PERRSP

-

R

0

-

0

FBTBEN SERREN

W

-

0

SERREN

06h

07h

Status

R

FBBC

0

NewCap

0

R

DPERR

SSERR

RMABT RTABT

STABT

DST1

DST0

DPD

W

DPERR

SSERR

STABT

-

DPD

08h Revision ID

R

0

09h

0Ah

0Bh

0Ch

0Dh

PIFR

SCR

BCR

CLS

LTR

R

0

R

0

R

0

1

0

R/W

R

0

LTR7

LTR6

LTR5

LTR4

LTR3

LTP2

LTR1

LTR0

0

W

LTR7

LTR6

LTR5

LTR4

LTR3

LTP2

LTR1

0Eh

0Fh

10h

HTR

BIST

IOAR

R

0

-

0

-

0

-

0

-

0

R

0

R

0

-

IOIN

-

W

-

11h

12h

13h

R/W

R

IOAR15

IOAR23

IOAR31

0

IOAR14

IOAR22

IOAR30

0

IOAR13 IOAR12 IOAR11 IOAR10

IOAR9

IOAR8

IOAR21 IOAR20 IOAR19 IOAR18 IOAR17 IOAR16

IOAR29 IOAR28 IOAR27 IOAR26 IOAR25 IOAR24

14h MEMAR

0

-

0

-

0

-

0

-

0

-

MEMIN

-

MEM8

W

-

15h

16h

17h

18h-2

7h

28h-2

Bh

2Ch

2Dh

2Eh

2Fh

30h

R/W

MEM15

MEM23

MEM31

MEM14

MEM22

MEM30

MEM13 MEM12 MEM11 MEM10

MEM9

MEM21 MEM20 MEM19 MEM18 MEM17 MEM16

MEM29 MEM28 MEM27 MEM26 MEM25 MEM24

RESERVED

CISPtr

SVID

Cardbus CIS Pointer

R

SVID7

SVID15

SMID7

SMID15

0

SVID6

SVID14

SMID6

SMID14

0

SVID5

SVID13 SVID12 SVID11 SVID10

SMID5 SMID4 SMID3 SMID2

SVID4

SVID3

SVID2

SVID1

SVID0

SVID8

SMID0

SMID8

BROMEN

0

SVID9

SMID

BMAR

R

SMID1

R

SMID13 SMID12 SMID11 SMID10

SMID9

R

0

-

0

-

0

-

0

-

0

-

0

-

0

-

W

R

-

31h

BMAR15 BMAR14 BMAR13 BMAR12 BMAR11

W

-

32h

33h

34h

35h-3

Bh

3Ch

R/W BMAR23 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16

R/W BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24

Cap_Ptr

R

1

0

1

0

RESERVED

ILR

IPR

R/W

R

IRL7

0

ILR6

0

ILR5 ILR4

ILR3

0

ILR2

0

ILR1

0

ILR0

1

3Dh

cont...

0

2002/03/27

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41

RTL8169

3Eh MNGNT

R

0

1

0

3Fh

40h–

5Fh

60h

MXLAT

RESERVED

VPDID

NextPtr

R

0

1

0

1

0

61h

62h Flag VPD R/W VPDADDR VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD

Address

7

Flag

6

R5

R4

R3

R2

R1

R0

63h

R/W

VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD

14

R13

Data5

Data13

Data21

Data29

R12

Data4

Data12

Data20

Data28

R11

Data3

Data11

Data19

Data27

R10

Data2

Data10

Data18

Data26

R9

R8

64h VPD Data R/W

Data7

Data15

Data23

Data31

Data6

Data14

Data22

Data30

Data1

Data9

Data17

Data25

Data0

Data8

Data16

Data24

65h

66h

67h

R/W

68h-

DBh

DCh

DDh

DEh

DFh

E0h

RESERVED

PMID

NextPtr

PMC

R

0

1

0

1

DSI

0

1

0

R

Aux_I_b1 Aux_I_b0

Reserved PMECLK

Version

D1

R

PME_D3_coldPME_D3_hotPME_D2 PME_D1 PME_D0

D2

0

-

Aux_I_b2

PMCSR

R

0

-

0

-

0

-

0

-

0

-

Power State

-

W

R

E1h

PME_Status

PME_En

W

E2h-

FFh

RESERVED

ꢂ

The above table is based on both VPD and Power Management are enabled.

8.5 PCI Configuration Space Functions

The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The

functions of the RTL8169's configuration space are described below.

VID: Vendor ID. This field will be set to a value corresponding to PCI Vendor ID in the external EEPROM. If there is no

EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID.

DID: Device ID. This field will be set to a value corresponding to PCI Device ID in the external EEPROM. If there is no

EEPROM, this field will default to a value of 8129h.

Command: The command register is a 16-bit register used to provide coarse control over a device's ability to generate and

respond to PCI cycles.

Bit

15:10

9

Symbol

-

Description

Reserved

FBTBEN

Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The

RTL8169 will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This read/write bit

controls whether or not a master can do fast back-to-back transactions to different devices.

Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means

the master is allowed to generate fast back-to-back transaction to different agents. A value of 0 means

fast back-to-back transactions are only allowed to the same agent. This bit’s state after RST# is 0.

System Error Enable: When set to 1, the RTL8169 asserts the SERRB pin when it detects a parity

error on the address phase (AD<31:0> and CBEB<3:0> ).

8

7

SERREN

ADSTEP

Address/Data Stepping: Read as 0, and write operations have no effect. The RTL8169 never

performs address/data stepping.

cont...

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6

PERRSP

Parity Error Response: When set to 1, the RTL8169 will assert the PERRB pin on the detection of a

data parity error when acting as the target, and will sample the PERRB pin as the master. When set to

0, any detected parity error is ignored and the RTL8169 continues normal operation.

Parity checking is disabled after hardware reset (RSTB).

5

4

VGASNOOP

MWIEN

VGA palette SNOOP: Read as 0, write operations have no effect.

Memory Write and Invalidate cycle Enable: This is an enable bit for using the Memory Write and

Invalidate command. When this bit is 1, the RTL8169 as a master may generate the command. When

this bit is 0, the RTL8169 may generate Memory Write command instead. State after PCI RSTB is 0.

Special Cycle Enable: Read as 0, write operations have no effect. The RTL8169 ignores all special

cycle operations.

Bus Master Enable: When set to 1, the RTL8169 is capable of acting as a PCI bus master. When set

to 0, it is prohibited from acting as a bus master.

3

2

SCYCEN

BMEN

For normal operations, this bit must be set by the system BIOS.

1

0

MEMEN

IOEN

Memory Space Access: When set to 1, the RTL8169 responds to memory space accesses. When set to

0, the RTL8169 ignores memory space accesses.

I/O Space Access: When set to 1, the RTL8169 responds to IO space accesses. When set to 0, the

RTL8169 ignores I/O space accesses.

Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register

behave normally. Writes are slightly different in that bits can be reset, but not set.

Bit

Symbol

Description

15

DPERR

Detected Parity Error: This bit, when set, indicates that the RTL8169 has detected a parity error, even if

parity error handling is disabled in command register PERRSP bit.

Signaled System Error: This bit, when set, indicates that the RTL8169 has asserted the system error pin,

SERRB. Writing a 1 clears this bit to 0.

14

13

SSERR

RMABT

RTABT

STABT

DST1-0

DPD

Received Master Abort: This bit, when set, indicates that the RTL8169 has terminated a master

transaction with master abort. Writing a 1 clears this bit to 0.

12

Received Target Abort: This bit, when set, indicates that an RTL8169 master transaction was

terminated due to a target abort. Writing a 1 clears this bit to 0.

11

Signaled Target Abort: This bit is set to 1 whenever the RTL8169 terminates a transaction with a target

abort. Writing a 1 clears this bit to 0.

10:9

8

Device Select Timing: These bits encode the timing of DEVSELB. They are set to 01b (medium),

indicating the RTL8169 will assert DEVSELB two clocks after FRAMEB is asserted.

Data Parity error Detected: This bit is set when the following conditions are met:

* The RTL8169 asserts parity error (PERRB pin) or it senses the assertion of PERRB pin by another device.

* The RTL8169 operates as a bus master for the operation that caused the error.

* The Command register PERRSP bit is set.

Writing a 1 clears this bit to 0.

7

6

FBBC

UDF

Fast Back-To-Back Capable: Config3<FbtBEn>=0, Read as 0, write operations have no effect.

Config3<FbtBEn>=1, Read as 1.

User Definable Features Supported: Read as 0, and write operations have no effect. The RTL8169

does not support UDF.

66MHz Capable: Read as 1, and write operations have no effect. The RTL8169 supports 66MHz PCI clock.

New Capability: Config3<PMEn>=0, Read as 0, and write operations have no effect.

Config3<PMEn>=1, Read as 1.

5

4

66MHz

NewCap

0:3

-

Reserved

RID: Revision ID Register

The Revision ID register is an 8-bit register that specifies the RTL8169 controller revision number.

PIFR: Programming Interface Register

The programming interface register is an 8-bit register that identifies the programming interface of the RTL8169

controller. The PCI specification reversion 2.1 doesn't define any other specific value for network devices. So PIFR = 00h.

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RTL8169

SCR: Sub-Class Register

The Sub-class register is an 8-bit register that identifies the function of the RTL8169. SCR = 00h indicates that the

RTL8169 is an Ethernet controller.

BCR: Base-Class Register

The Base-class register is an 8-bit register that broadly classifies the function of the RTL8169. BCR = 02h indicates that

the RTL8169 is a network controller.

CLS: Cache Line Size

Specifies, in units of 32-bit words (double-words), the system cache line size. The RTL8169 supports cache line size of

8, and 16 longwords (DWORDs). The RTL8169 uses Cache Line Size for PCI commands that are cache oriented, such as

memory-read-line, memory-read-multiple, and memory-write-and-invalidate.

LTR: Latency Timer Register

Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8169.

When the RTL8169 asserts FRAMEB, it enables its latency timer to count. If the RTL8169 deasserts FRAMEB prior to

count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the RTL8169 initiates

transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is 00h.

HTR: Header Type Register

Reads will return a 0, writes are ignored.

BIST: Built-in Self Test

Reads will return a 0, writes are ignored.

IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also

specifies the number of bytes required as well as an indication that it can be mapped into IO space. Britain

Bit

31:8

7:2

Symbol

IOAR31-8

IOSIZE

Description

BASE IO Address: This is set by software to the Base IO address for the operational register map.

Size Indication: Read back as 0. This allows the PCI bridge to determine that the RTL8169 requires

256 bytes of IO space.

Reserved

1

0

-

IOIN

IO Space Indicator: Read only. Set to 1 by the RTL8169 to indicate that it is capable of being mapped

into IO space.

MEMAR: This register specifies the base memory address for memory accesses to the RTL8169 operational registers. This

register must be initialized prior to accessing any RTL8169's register with memory access.

Bit

31:8

7:4

3

Symbol

MEM31-8

MEMSIZE

MEMPF

Description

Base Memory Address: This is set by software to the base address for the operational register map.

Memory Size: These bits return 0, which indicates that the RTL8169 requires 256 bytes of Memory Space.

Memory Prefetchable: Read only. Set to 0 by the RTL8169.

2:1

MEMLOC

Memory Location Select: Read only. Set to 0 by the RTL8169. This indicates that the base register is

32-bits wide and can be placed anywhere in the 32-bit memory space.

Memory Space Indicator: Read only. Set to 0 by the RTL8169 to indicate that it is capable of being

mapped into memory space.

0

MEMIN

CISPtr: CardBus CIS Pointer. This field is valid only when CardB_En (bit3, Config3) = 1. The value of this register is

auto-loaded from 93C46 or 93C56 (from offset 30h-31h).

-

Bit 2-0: Address Space Indicator

Bit2:0

7

Meaning

The CIS begins in the Expansion ROM space.

6:1

The CIS begins in the memory address governed by one of the six Base

Address Registers. Ex., if the value is 2, then the CIS begins in the memory

address space governed by Base Address Register 2.

Not supported. (CIS begins in device-dependent configuration space.)

Bit27-3: Address Space Offset

0

-

Bit31-28: ROM Image number

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RTL8169

Bit2-0

0

Space Type

Address Space Offset Values

Configuration space

Memory space

Not supported.

X; 1≤X≤6

0h≤value≤FFFF FFF8h. This is the offset into the memory address space

governed by Base Address Register X. Adding this value to the value in the

Base Address Register gives the location of the start of the CIS. For the

RTL8169, the value is 100h.

0≤image number≤Fh, 0h≤value≤0FFF FFF8h. This is the offset into the

expansion ROM address space governed by the Expansion ROM Base

Register. The image number is in the uppermost nibble of the CISPtr

register. The value consists of the remaining bytes. For the RTL8169, the

image number is 0h.

7

Expansion ROM

This read-only register points to where the CIS begins, in one of the following spaces:

i. Memory Space – The CIS may be in any of the memory spaces from offset 100h and up after being auto-loaded from

93C56. The CIS is stored in 93C56 EEPROM physically from offset 80h-FFh.

ii. Expansion ROM space – The CIS is stored in expansion ROM physically within the 128KB max.

SVID: Subsystem Vendor ID. This field will be set to a value corresponding to PCI Subsystem Vendor ID in the external

EEPROM. If there is no EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI

Subsystem Vendor ID.

SMID: Subsystem ID. This field will be set to value corresponding to PCI Subsystem ID in the external EEPROM. If there is no

EEPROM, this field will default to a value of 8129h.

BMAR: This register specifies the base memory address for memory accesses to the RTL8169 operational registers. This

register must be initialized prior to accessing any of the RTL8169's register with memory access.

Bit

Symbol

Description

31:18 BMAR31-18

Boot ROM Base Address

17:11

ROMSIZE

Boot ROM Size: These bits indicate how many Boot ROM spaces to be supported. The Relationship

between Config 0 <BS2:0> and BMAR17-11 is as follows:

BS2 BS1 BS0 Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Boot ROM, BROMEN=0 (R)

8K Boot ROM, BROMEN (R/W), BMAR12-11 = 0 (R), BMAR17-13 (R/W)

16K Boot ROM, BROMEN (R/W), BMAR13-11 = 0 (R), BMAR17-14 (R/W)

32K Boot ROM, BROMEN (R/W), BMAR14-11 = 0 (R), BMAR17-15 (R/W)

64K Boot ROM, BROMEN (R/W), BMAR15-11 = 0 (R), BMAR17-16 (R/W)

128K Boot ROM, BROMEN(R/W), BMAR16-11=0 (R), BMAR17 (R/W)

unused

10:1

0

-

Reserved (read back 0)

BROMEN

Boot ROM Enable: This is used by the PCI BIOS to enable accesses to Boot ROM.

ILR: Interrupt Line Register

The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt. It is written by the

POST software to set interrupt line for the RTL8169.

IPR: Interrupt Pin Register

The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8169. The RTL8169 uses INTA

interrupt pin. Read only. IPR = 01h.

MNGNT: Minimum Grant Timer: Read only

Specifies how long a burst period the RTL8169 needs at 33MHz clock rate in units of 1/4 microsecond. This field will be

set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.

MXLAT: Maximum Latency Timer: Read only

Specifies how often the RTL8169 needs to gain access to the PCI bus in unit of 1/4 microsecond. This field will be set to

a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.

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RTL8169

8.6 Default Value After Power-on (RSTB Asserted)

PCI Configuration Space Table

No.

00h

01h

02h

03h

04h

Name

Type

R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

VID

1

0

1

0

-

0

-

0

1

0

1

0

R

0

1

0

DID

R

0

1

R

1

0

Command

R

0

W

-

PERRSP

MWIEN

-

BMEN MEMEN IOEN

05h

R

0

-

0

W

-

NewCap

0

-

0

-

SERREN

06h

07h

Status

R

0

R

0

1

W

DPERR

SSERR RMABT RTABT

STABT

-

DPD

08h

09h

0Ah

0Bh

0Ch

0Dh

Revision ID

PIFR

R

0

1

0

R

0

SCR

R

0

BCR

R

0

1

0

CLS

R/W

R

0

LTR

0

W

LTR7

LTR6

LTR5

LTR4

LTR3

LTP2

0

LTR1

LTR0

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

|

HTR

BIST

IOAR

R

0

1

0

R

0

R

0

R/W

R

0

MEMAR

0

R/W

0

RESERVED(ALL 0)

-

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

R

0

1

0

1

0

-

0

1

0

-

0

1

0

1

0

-

0

1

0

-

0

1

0

1

0

-

0

CISPtr

0

R

0

R

0

SVID

SMID

BMAR

R

1

0

R

0

R

0

1

R

0

1

R

0

W

R

-

BROMEN

31h

0

-

W

R/W

R

BMAR15 BMAR14 BMAR13 BMAR12 BMAR11

-

32h

33h

34h

0

Ptr7

0

Ptr6

0

Ptr5

0

Ptr4

0

Ptr3

0

Cap-Ptr

Ptr2

Ptr1

Ptr0

cont...

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RTL8169

35h

|

RESERVED(ALL 0)

-

3Bh

3Ch

3Dh

3Eh

3Fh

40h

|

ILR

IPR

R/W

R

0

1

0

1

0

MNGNT

MXLAT

R

0

R

RESERVED(ALL 0)

-

FFh

8.7 Power Management functions

The RTL8169 is compliant to ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class Power

Management Reference Specification (V1.0a), such as to support OS Directed Power Management (OSPM) environment. To

support this, the RTL8169 provides the following capabilities:

ꢃ

The RTL8169 can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via

PME# when such a packet or event occurs. Then, the whole system can be restore to a working state to process the

incoming jobs.

When the RTL8169 is in power down mode (D1 ~ D3):

♦

The Rx state machine is stopped, and the RTL8169 keeps monitoring the network for wakeup events such as Magic

Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8169

will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO.

♦

The FIFO status and the packets which are already received into Rx FIFO before entering into power down mode, are

kept by the RTL8169 during power down mode

♦

Transmission is stopped. The action of the PCI bus master mode is stopped, too. The Tx FIFO is kept.

After restoration to a D0 state, the PCI bus master mode continues to transfer the data, which is not yet moved into the

Tx FIFO from the last break. The packet that was not transmitted completely last time is transmitted again.

D3cold_support_PME bit(bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI configuration space.

If EEPROM D3cold_support_PME bit(bit15, PMC) = 1, the above 4 bits depend on the existence of Aux power.

If EEPROM D3cold_support_PME bit(bit15, PMC) = 0, the above 4 bits are all 0's.

Ex.:

1. If EEPROM D3c_support_PME = 1,

ꢃ

If Aux. power exists, then PMC in PCI config space is the same as EEPROM PMC, i.e. if EEPROM

PMC = C2 F7, then PCI PMC = C2 F7.

ꢃ

If Aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above

4 bits are all 0’s. I.e. if EEPROM PMC = C2 F7, the PCI PMC = 02 76.

ꢄ

In this case, if wakeup support is desired when the main power is off, it is suggested that the

EEPROM PMC be set to: C2 F7 (RT EEPROM default value).

2. If EEPROM D3c_support_PME = 0,

ꢃ

If Aux. power exists, then PMC in PCI config space is the same as EEPROM PMC. I.e. if EEPROM

PMC = C2 77, then PCI PMC = C2 77.

ꢃ

If Aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above

4 bits are all 0’s. I.e. if EEPROM PMC = C2 77, the PCI PMC = 02 76.

ꢄ

In this case, if wakeup support is not desired when the main power is off, it is suggested that the

EEPROM PMC be set to be 02 76.

Link Wakeup occurs only when the following conditions are met:

♦

The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in

current power state.

♦

The Link status is re-established.

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RTL8169

Magic Packet Wakeup occurs only when the following conditions are met:

♦

The destination address of the received Magic Packet is acceptable to the RTL8169, such as broadcast, multicast, or

unicast address to the current RTL8169 adapter.

♦

The received Magic Packet does not contain a CRC error.

The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in current

power state.

♦

The Magic Packet pattern matches, i.e. 6 * FFh + MISC(can be none)+ 16 * DID(Destination ID) in any part of a valid

(Fast) Ethernet packet.

Wakeup Frame event occurs only when the following conditions are met:

♦

The destination address of the received Wakeup Frame is acceptable to the RTL8169, such as broadcast, multicast, or

unicast address to the current RTL8169 adapter.

♦

ꢅ

The received Wakeup Frame does not contain a CRC error.

The PMEn bit (CONFIG1#0) is set to 1.

The 16-bit CRC* (or 16-bit CRC) of the received Wakeup Frame matches with the 16-bit CRC* of the sample

Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8169 is configured to allow direct packet wakeup,

such as broadcast, multicast, or unicast network packet.

ꢀ

16-bit CRC:

The RTL8169 supports 5 wakeup frames that includes 2 normal wakeup frames (covering 64 mask bytes from offset

0 to 63 of any incoming network packet) and 3 long wakeup frames (covering 128 mask bytes from offset 0 to 127 of

any incoming network packet).

The PME# signal is asserted only when the following conditions are met:

ꢅ

The PMEn bit (bit0, CONFIG1) is set to 1.

The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.

The RTL8169 may assert PME# in current power state, or the RTL8169 is in isolation state, referring to

PME_Support(bit15-11) of the PMC register in PCI Configuration Space.

ꢅ

Magic Packet, LinkUp, or Wakeup Frame has occurred.

* Writing a 1 to the PME_Status (bit15) of PMCSR register in the PCI Configuration Space will clear this bit and cause

the RTL8169 to stop asserting a PME# (if enabled).

When the RTL8169 is in power down mode, ex. D1-D3, the IO, MEM, and Boot ROM spaces are all disabled, after a RST#

assertion, the RTL8169’s power state is restored to D0 automatically, if the original power state is D3_cold. There is no hardware

delay at the RTL8169’s power state transition. When in ACPI mode, the RTL8169 does not support PME from D0 (This is

Realtek default setting of PMC register autoloaded from EEPROM. The setting may be changed from the EEPROM, if

required.).

The RTL8169 also supports the legacy LAN WAKE-UP function. The LWAKE pin is used to notify legacy motherboards to

execute the wake-up process whenever the RTL8169 receives a wakeup event, such as Magic Packet.

The LWAKE signal is asserted according the following setting.

ꢅ

LWPME bit (bit4, CONFIG4):

1: The LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low.

0: The LWAKE is asserted whenever there is wakeup event occurs.

Bit1 of DELAY byte(offset 1Fh, EEPROM):

1: LWAKE signal is enabled

ꢅ

0: LWAKE signal is disabled.

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RTL8169

8.8 Vital Product Data (VPD)

Bit 31 of the VPD is used to issue VPD read/write command and is also a flag used to indicate whether the transfer of data

between the VPD data register and the 93C46/93C56 is completed or not.

1. Write VPD register: (write data to 93C46/93C56)

Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When the flag bit is reset

to 0 by the RTL8169, the VPD data (4 bytes per VPD access) has been transferred from the VPD data register to

EEPROM.

2. Read VPD register: (read data from 93C46/93C56)

Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM. When the flag bit

is set to 1 by the RTL8169, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data

register.

-

Please refer to PCI Configuration Space Table in Section 8.1 and PCI 2.2 Specifications for further information.

The VPD address does not have to be a DWORD-aligned address as defined in the PCI 2.2 Specifications, but the

VPD data is always consecutive 4-byte data starting from the VPD address specified.

Realtek reserves offset 40h to 7Fh in EEPROM mainly for VPD data to be stored.

The VPD function of the RTL8169 is designed to be able to access the full range of the EEPROM (either 93C46 or

93C56).

-

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RTL8169

9. Functional Description

9.1 Transmit & Receive Operations

The RTL8169 supports a new descriptor-based buffer management that will significantly reduce host CPU utilization and is

more suitable for a server application. The new buffer management algorithm provides capabilities of Microsoft Large-Send

offload, IP checksum offload, TCP checksum offload, UDP checksum offload, and IEEE802.1P, 802.1Q VLAN tagging. The

RTL8169 supports up to 1024 consecutive descriptors in memory for transmit and receive separately, which means there might

be 3 descriptor rings, one is a high priority transmit descriptor ring, another is a normal priority transmit descriptor ring, and the

other is a receive descriptor ring, each descriptor ring may consist of up to 1024 4-double-word consecutive descriptors. Each

descriptor consists of 4 consecutive double words. The start address of each descriptor group should be 256-byte alignment.

Software must pre-allocate enough buffers and configure all descriptor rings before transmitting and/or receiving packets.

Descriptors can be chained to form a packet in both Tx and Rx. Please refer to the Realtek RTL8169 programming guide for

detailed information. Any Tx buffers pointed to by one of Tx descriptors should be at least 4 bytes.

Padding: The RTL8169 will automatically pad any packets less than 64 bytes (including 4 bytes CRC) to 64-byte long (including

4-byte CRC) before transmitting that packet onto network medium.

If a packet consists of 2 or more descriptors, then the descriptors in command mode should have the same configuration, except

EOR, FS, LS bits.

9.1.1 Transmit

This portion implements the transmit portion of 802.3 Media Access Control. The Tx MAC retrieves packet data from the Tx

Buffer Manager and sends it out through the transmit physical layer interface. Additionally, the Tx MAC provides MIB control

information for transmit packets. The Tx MAC supports 4-bit MII, 8-bit GMII, and 10-bit TBI interfaces to physical layer

devices.

The Tx MAC has the capability to insert a 4-byte VLAN tag in the transmit packet. If Tx VLAN Tag insertion is enabled, the

MAC will insert the 4 bytes, as specified in the VTAG register, following the source and destination addresses of the packet. The

VLAN tag insertion can be enabled on a global or per-packet basis.

When operating in 1G mode, the RTL8169 operates in full duplex mode only.

The Tx MAC supports task offloading of IP, TCP, and UDP checksum generation. It can generate the checksums and insert them

into the packet. The checksum generation can be enabled on a global or per-packet basis.

The following information describes what the Tx descriptor may look like, depending on different states in each Tx descriptor.

The minimum Tx buffer should be at least 4 bytes.

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RTL8169

Large-Send Task Offload Tx Descriptor Format (before transmitting, OWN=1, LGSEN=1, Tx command mode 0)

bit 31 30 29 28 27 26

16 15

8

7

6

5

4

3

2

1

0

O E F L L Large-Send MSS value

W O S S G (11 bits)

Offset 0

Frame_Length

N R

=

S

E

N

=

1

T R

VLAN_TAG

Offset 4

Offset 8

RSVD

A S

G V

C D

VIDL

PRIO C VIDH

FI

TX_BUFFER_ADDRESS_LOW

TX_BUFFER_ADDRESS_HIGH

Offset 12

Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: This bit, when set, indicates that the descriptor is owned

by THE NIC, and the data relative to this descriptor is ready to be

transmitted. When cleared, it indicates that the descriptor is owned by

host system. The NIC clears this bit when the relative buffer data is

transmitted. In this case, OWN=1.

End of Descriptor Ring: This bit, when set, indicates that this is the

last descriptor in descriptor ring. When the NIC’s internal transmit

pointer reaches here, the pointer will return to the first descriptor of the

descriptor ring after transmitting the data relative to this descriptor.

First Segment Descriptor: This bit, when set, indicates that this is the

first descriptor of a Tx packet, and that this descriptor is pointing to the

first segment of the packet.

Last Segment Descriptor: This bit, when set, indicates that this is the

last descriptor of a Tx packet, and that this descriptor is pointing to the

last segment of the packet.

Large Send: A command bit; TCP/IP Large send operation enable. The

driver sets this bit to ask the NIC to offload the Large send operation. In

this case, LGSEN=1.

0

30

EOR

0

29

28

27

FS

LS

LGSEN

0

4

26:16

15:0

MSS

Frame_Length

RSVD

Maximum Segmentation Size: An 11-bit long command field, the

driver passes large send MSS to the NIC through this field.

Transmit Drame Length: This field indicates the length in TX buffer,

in byte, to be transmitted

31:18

Reserved

cont...

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4

17

TAGC

VLAN tag control bit: 1: Enable; 0: Disable.

1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating

that this is a IEEE 802.1Q VLAN packet) is inserted after source

address, and 2 bytes are inserted after tag protocol ID from

VLAN_TAG field in transmit descriptor.

0: Packet remains unchanged when transmitting. I.e., the packet

transmitted is the same as it was passed down by upper layer.

Reserved

4

16

15:0

RSVD

VLAN_TAG

The 2-byte VLAN_TAG contains information, from the upper layer, of

user priority, canonical format indication, and VLAN ID. Please refer to

IEEE 802.1Q for more VLAN tag information.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

Low 32-bit address of transmit buffer

High 32-bit address of transmit buffer

8

12

31:0

TxBuffL

TxBuffH

Normal (including IP, TCP, UDP Checksum Task Offloads) Tx Descriptor Format (before transmitting, OWN=1,

LGSEN=0, Tx command mode 1)

bit 31 30 29 28 27 26

16 15

8

7

6

5

4

3

2

1

0

O E F L L R R R R R R R R I U T

W O S S G S S S S S S S S P D C

Offset 0

Frame_Length

N R

=

S V V V V V V V V C P P

E D D D D D D D D S C C

1

N

=

0

S S

T R

A S

G V

C D

VLAN_TAG

Offset 4

Offset 8

Offset 12

RSVD

VIDL

PRIO C

FI

VIDH

TX_BUFFER_ADDRESS_LOW

TX_BUFFER_ADDRESS_HIGH

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Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: This bit, when set, indicates that the descriptor is owned

by the NIC, and that the data relative to this descriptor is ready to be

transmitted. When cleared, it indicates that the descriptor is owned by

the host system. The NIC clears this bit when the relative buffer data is

transmitted. In this case, OWN=1.

0

30

EOR

End of descriptor Ring: This bit, when set, indicates that this is the last

descriptor in the descriptor ring. When the NIC’s internal transmit

pointer reaches here, the pointer will return to the first descriptor of the

descriptor ring after transmitting the data relative to this descriptor.

First segment descriptor: This bit, when set, indicates that this is the

first descriptor of a Tx packet, and that this descriptor is pointing to the

first segment of the packet.

0

29

28

27

FS

LS

Last segment descriptor: This bit, when set, indicates that this is the

last descriptor of a Tx packet, and that this descriptor is pointing to the

last segment of the packet.

LGSEN

Large Send: A command bit; TCP/IP Large send operation enable.

Driver sets this bit to ask NIC to offload Large send operation. In this

case, LGSEN=0.

0

26:19

18

RSVD

IPCS

Reserved

IP checksum offload: A command bit. The driver sets this bit to ask the

NIC to offload the IP checksum.

UDP checksum offload: A command bit. The driver sets this bit to ask

the NIC to offload the UDP checksum.

0

17

16

UDPCS

TCPCS

TCP checksum offload enable: A command bit; The driver sets this

bit to ask the NIC to offload the TCP checksum.

Transmit frame length: This field indicates the length of the TX

buffer, in bytes, to be transmitted

15:0

Frame_Length

4

31:18

17

RSVD

TAGC

Reserved

VLAN tag control bit: 1: Enable; 0: Disable.

1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating

that this is an IEEE 802.1Q VLAN packet) is inserted after the

source address, and 2 bytes are inserted after tag protocol ID from

the VLAN_TAG field in transmit descriptor.

0: Packet remains unchanged when transmitting. I.e., the packet

transmitted is the same as it was passed down by upper layer.

Reserved

4

16

15:0

RSVD

VLAN_TAG

VLAN Tag: The 2-byte VLAN_TAG contains information, from upper

layer, of user priority, canonical format indicator, and VLAN ID. Please

refer to IEEE 802.1Q for more VLAN tag information.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

Low 32-bit address of transmit buffer

High 32-bit address of transmit buffer

8

12

31:0

TxBuffL

TxBuffH

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Offset 0

Tx Status Descriptor (after transmitting, OWN=0, Tx status mode)

After having transmitted, the Tx descriptor turns into a Tx status descriptor.

bit 31 30 29 28 27 26

16 15

8

7

6

5

4

3

2

1

0

O E F L R R R R R R R R RSVD

W O S S S S S S S S S S

RSVD

N R

=

V V V V V V V V

D D D D D D D D

0

T R

VLAN_TAG

Offset 4

RSVD

A S

G V

C D

VIDL

PRIO C

FI

VIDH

Offset 8

TX_BUFFER_ADDRESS_LOW

TX_BUFFER_ADDRESS_HIGH

Offset 12

Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: This bit, when set, indicates that the descriptor is owned

by the NIC. When cleared, it indicates that the descriptor is owned by

the host system. NIC clears this bit when the relative buffer data is

already transmitted. In this case, OWN=0.

End of Descriptor Ring: When set, indicates that this is the last

descriptor in descriptor ring. When NIC’s internal transmit pointer

reaches here, the pointer will return to the first descriptor of the

descriptor ring after transmitting the data relative to this descriptor.

First Segment Descriptor: This bit, when set, indicates that this is the

first descriptor of a Tx packet, and that this descriptor is pointing to the

first segment of the packet.

Last Segment Descriptor: This bit, when set, indicates that this is the

last descriptor of a Tx packet, and that this descriptor is pointing to the

last segment of the packet.

Reserved

0

30

EOR

0

29

28

FS

LS

0

4

27:0

31:18

17

RSVD

TAGC

VLAN Tag Control Bit: 1: Enable; 0: Disable.

1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating

that this is an IEEE 802.1Q VLAN packet) is inserted after source

address, and 2 bytes are inserted after tag protocol ID from

VLAN_TAG field in transmit descriptor.

0: Packet remains unchanged when transmitting. I.e., the packet

transmitted is the same as it was passed down by the upper layer.

Reserved

4

16

RSVD

cont...

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4

15:0

VLAN_TAG

VLAN Tag: The 2-byte VLAN_TAG contains information, from the

upper layer, of user priority, canonical format indicator, and VLAN ID.

Please refer to IEEE 802.1Q for more VLAN tag information.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

Low 32-bit address of transmit buffer

High 32-bit address of transmit buffer

8

12

31:0

TxBuffL

TxBuffH

9.1.2 Receive

The receive portion implements the receive portion of 802.3 Media Access Control. The Rx MAC retrieves packet data from the

receive portion and sends it to the Rx Buffer Manager. Additionally, the Rx MAC provides MIB control information and packet

address data for the Rx Filter. The Rx MAC supports 4-bit MII, 8-bit GMII, and 10-bit TBI interfaces to physical layer devices.

The Rx MAC can detect packets containing a 4-byte VLAN tag, and remove the VLAN tag from the received packet. If Rx

VLAN Tag Removal is enabled, then the 4 bytes following the source and destination addresses will be stripped out. The VLAN

status can be returned in the VLAN Tag field.

The Rx MAC supports IP checksum verification. It can validate IP checksums as well as TCP and UDP checksums. Packets can

be discarded based on detecting checksum errors.

The following information describes what the Rx descriptor may look like, depending on different states in each Rx descriptor.

Any Rx buffers pointed to by one of the Rx descriptors should be to at least 8 bytes in length and to 8-byte alignment in memory.

Rx Command Descriptor (OWN=1)

The driver should pre-allocate Rx buffers and configure Rx descriptors before packet reception. The following describes what

Rx descriptors may look like before packet reception.

bit 31 30 29 28

O E

19 18 17 16 15

13 12

8

7

6

5

4

3

2

1

0

Offset 0

Offset 4

Offset 8

Offset 12

W O

N R

=

RSVD

Buffer_Size

1

T

VLAN_TAG

PRIO

RSVD

A

V

A

VIDL

C

VIDH

FI

RX_BUFFER_ADDRESS_LOW

RX_BUFFER_ADDRESS_HIGH

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Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: This bit, when set, indicates that the descriptor is owned

by the NIC, and is ready to receive a packet. The OWN bit is set by the

driver after having pre-allocated the buffer at initialization, or the host

has released the buffer to the driver. In this case, OWN=1.

End of Rx descriptor Ring: This bit, set to 1 indicates that this

descriptor is the last descriptor of the Rx descriptor ring. Once the

NIC’s internal receive descriptor pointer reaches here, it will return to

the first descriptor of the Rx descriptor ring after this descriptor is used

by packet reception.

0

30

EOR

0

4

29:14

13:0

31:17

16

RSVD

Buffer_Size

RSVD

Reserved

Buffer Size: This field indicate the receive buffer size in bytes.

Reserved

TAVA

Tag Available: This bit, when set, indicates that the received packet is

an IEEE802.1Q VLAN TAG (0x8100) available packet.

VLAN Tag: If the TAG of the packet is 0x8100, The RTL8169 MAC

extracts four bytes from after source ID, sets the TAVA bit to 1, and

moves the TAG value of this field in Rx descriptor.

VIDH: The high 4 bits of a 12-bit VLAN ID.

4

15:0

VLAN_TAG

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

8

12

31:0

RxBuffL

RxBuffH

Low 32-bit Address of Receive Buffer

High 32-bit Address of Receive Buffer

Rx Status Descriptor (OWN=0)

When packet is received, the Rx command descriptor turns to be a Rx status descriptor.

bit 31 30 29 28 27 26

16 15 14 13 12

8

7

6

5

4

3 2 1 0

O E F L M PA B B F R R R C PI PI

U T

Frame_Length

Offset 0

Offset 4

W O S S A M A O O W E U R D D IP D C

N R

=

R

R V V T S N C 1 0 F P P

F F

T

F F

0

T

VLAN_TAG

PRIO

RSVD

A

V

A

VIDL

C

VIDH

FI

Offset 8

RX_BUFFER_ADDRESS_LOW

RX_BUFFER_ADDRESS_HIGH

Offset 12

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Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: This bit, when set, indicates that the descriptor is owned by

the NIC. When cleared, it indicates that the descriptor is owned by the

host system. The NIC clears this bit when the NIC has filled up this Rx

buffer with a packet or part of a packet. In this case, OWN=0.

End of Rx Descriptor Ring: This bit, set to 1, indicates that this

descriptor is the last descriptor of the Rx descriptor ring. Once the

NIC’s internal receive descriptor pointer reaches here, it will return to

the first descriptor of the Rx descriptor ring after this descriptor is used

by packet reception.

0

30

EOR

0

29

28

FS

LS

First Segment descriptor: This bit, when set, indicates that this is the

first descriptor of a received packet, and this descriptor is pointing to the

first segment of the packet.

Last Segment Descriptor: This bit, when set, indicates that this is the last

descriptor of a received packet, and this descriptor is pointing to the last

segment of the packet.

0

27

26

MAR

PAM

Multicast Address Packet Received: This bit, when set, indicates that

a multicast packet has been received.

Physical Address Matched: This bit, when set, indicates that the

destination address of this Rx packet matches the value in the

RTL8169’s ID registers.

0

25

BAR

Broadcast Address Received: This bit, when set, indicates that a

broadcast packet has been received. BAR and MAR will not be set

simultaneously.

0

24

23

22

21

BOVF

FOVF

RWT

RES

Buffer Overflow: This bit, when set, indicates that the receive buffer

has been exhausted before this packet was received.

FIFO Overflow: This bit, when set, indicates that a FIFO overflow has

occurred before this packet was received.

Receive Watchdog Timer Expired: This bit, when set, indicates that

the received packet length exceeded 4096 bytes.

Receive Error Summary: This bit, when set, indicates that at least one

of the following errors has occurred: CRC, RUNT, RWT, FAE. This bit

is valid only when LS (Last segment bit) is set

0

20

19

RUNT

CRC

Runt Packet: This bit, when set, indicates that the received packet

length is smaller than 64 bytes. RUNT packets are able to be received

only when RCR_AR is set.

CRC Error: This bit, when set, indicates that a CRC error has occurred

on the received packet. A CRC packet is able to be received only when

RCR_AER is set.

18:17

PID1, PID0

Protocol ID1, Protocol ID0: These 2 bits indicate the protocol type of

the packet received.

PID1

PID0

0

1

0

1

0

1

Non-IP

TCP/IP

UDP/IP

IP

0

16

15

14

IPF

UDPF

TCPF

IP Checksum Failure: 1: Failure, 0: No failure.

UDP Checksum Failure: 1: Failure, 0: No failure.

TCP Checksum Failure: 1: Failure, 0: No failure.

13:0

Frame_Length

When OWN=0 and LS =1, these bits indicate the received packet length

including CRC, in bytes.

4

31:17

RSVD

Reserved

cont...

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4

16

TAVA

Tag Available: When set, the received packet is an IEEE802.1Q VLAN

TAG (0x8100) available packet.

15:0

VLAN_TAG

VLAN Tag: If the TAG of the packet is 0x8100, The RTL8169 MAC

extracts four bytes from the after source ID, sets TAVA bit to 1, and

moves the TAG value to this field in the Rx descriptor.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

8

12

31:0

RxBuffL

RxBuffH

Low 32-bit Address of Receive Buffer

High 32-bit Address of Receive Buffer

9.2 Loopback Operation

Loopback mode is normally used to verify that the logic operations up to the Ethernet cable/fiber channel function correctly. The

RTL8169 supports both internal and external loopback capabilities. The RTL8169 internal loopback is actually a digital

loopback inside the RTL8169. To test an external loopback, the RTL8169 must operate in normal mode and the external

PHYceiver should be configured in loopback mode.

9.3 Collision

If the RTL8169 is not in full-duplex mode, a collision event occurs when the receive input is not idle while the RTL8169

transmits. If the collision was detected during the preamble transmission, a jam pattern is transmitted after completing the

preamble (including the JK symbol pair when network speed is 100Mbps). The RTL8169 does not support half-duplex mode in

1000Mbps mode. Therefore, there is no collision when the RTL8169 operates in 1000Mbps mode.

9.4 Flow Control

The RTL8169 supports IEEE802.3X flow control to improve performance in full-duplex mode. It detects and sends PAUSE

packets to achieve the flow control task. Results from the N-Way process with the link partner determine if flow control is

supported for the current connection.

9.4.1. Control Frame Transmission

When the RTL8169 is running out of receive descriptors in full duplex mode, it sends a PAUSE packet (with

pause_time=FFFFh) to inform the source station to stop transmission for the specified period of time. Once the receive

descriptors are available again, the RTL8169 sends another PAUSE packet (with pause_time=0000h) to wake up the source

station to restart transmission.

9.4.2. Control Frame Reception

The RTL8169 enters backoff state for the specified period of time when it receives a valid PAUSE packet (with pause_time=n)

in full duplex mode. If the PAUSE packet is received while the RTL8169 is transmitting, the RTL8169 starts to backoff after the

current transmission is completed. The RTL8169 is free to transmit packets when it receives a valid PAUSE packet (with

pause_time=0000h) or the backoff timer(=n*512 bit time) elapses.

The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. a PAUSE packet). The N-way flow

control capability can be disabled. Please refer to Section 7, EEPROM (93C46 or 93C56) Contents for further information.

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9.5 Memory Functions

9.5.1 Memory Read Line (MRL)

The Memory Read Line command reads more than a longword (DWORD) up to the cache line boundary in a prefetchable

address space. The Memory Read Line command is semantically identical to the Memory Read command except that it

additionally indicates that the master intends to fetch a complete cache line. This command is intended to be used with bulk

sequential data transfers where the memory system and the requesting master might gain some performance advantages by

reading up to a cache line boundary in response to the request rather than a single memory cycle. As with the Memory Read

command, pre-fetched buffers must be invalidated before any synchronization events are passed through this access path.

The RTL8169 performs MRL according to the following rules:

i. Read accesses that reach the cache line boundary use the Memory Read Line command (MRL) instead of the Memory

Read command.

ii. Read accesses that do not reach the cache line boundary use the Memory Read (MR) command.

iii. The Memory Read Line (MRL) command operates in conjunction with the Memory Read Multiple command (MRM).

iv. The RTL8169 will terminate the read transaction on the cache line boundary when it is out of resources on the transmit

DMA. For example, when the transmit FIFO is almost full.

9.5.2 Memory Read Multiple (MRM)

The Memory Read Multiple command is semantically identical to the Memory Read command except that it additionally

indicates that the master may intend to fetch more than one cache line before disconnecting. The memory controller should

continue pipelining memory requests as long as FRAMEB is asserted. This command is intended to be used with bulk sequential

data transfers where the memory system and the requesting master might gain some performance advantage by sequentially

reading ahead one or more additional cache line(s) when a software transparent buffer is available for temporary storage.

The RTL8169 performs MRM according to the following rules,

i. When the RTL8169 reads full cache lines, it will use the Memory Read Multiple command.

ii. If the memory buffer is not cache-aligned, the RTL8169 will use the Memory Read Line command to reach the cache line

boundary first.

Example:

Assume the packet length = 1514 byte, cache line size = 16 longwords (DWORDs), and Tx buffer start address =

64m+4 (m > 0).

;Step1: Memory Read Line (MRL)

;Data: (0-3) => (4-7) => (8-11) =>………... => (56-59)

;From Address: <64m+4>, <64m+8>, ………., <64m+60>

;Step2. Memory Read Multiple (MRM)

(byte offset of the Tx packet)

(reach cache line boundary)

;Data: (60-63) => (64-67) => (68-71) => ……………………….….. => (1454-1467)

;From Address: <64m+64>, <64m+68>, ……………….…., <64m+64+(16*4)*21+(16-1)*4>

;Step3. Memory Read(MR)

;Data: (1468-1471) => (1472-1475) => ……………………………, => (1510-1513)

;From Address:<64m+64+(16*4)*22>,<64m+64+(16*4)*22+4>,..,<64m+64+(16*4)*22+42>

Step1: Memory Read Multiple (MRM)

Data: (0-3) => (4-7) => (8-11) =>………….. => (1454-1467)

From Address: <64m+4>, <64m+8>, ………., <64m+64+(16*4)*21+(16-1)*4>

Step2. Memory Read(MRL)

Data: (1468-1471) => (1472-1475) => ……………………………, => (1510-1513)

From Address:<64m+64+(16*4)*22>,<64m+64+(16*4)*22+4>,..,<64m+64+(16*4)*22+42>

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9.5.3 Memory Write and Invalidate (MWI)

The Memory Write and Invalidate command is semantically identical to the Memory Write command except that it additionally

guarantees a minimum transfer of one complete cache line; i.e., the master intends to write all bytes within the addressed cache

line in a single PCI transaction unless interrupted by the target. Note: All byte enables must be asserted during each data phase

for this command. The master may allow the transaction to cross a cache line boundary only if it intends to transfer the entire

next line also. This command requires implementation of a configuration register in the master indicating the cache line size and

may only be used with Linear Burst Ordering. It allows a memory performance optimization by invalidating a "dirty" line in a

write-back cache without requiring the actual write-back cycle, thus shortening access time. The RTL8169 uses the MWI

command while writing full cache lines, and the Memory Write command while writing partial cache lines.

The RTL8169 issues MWI command, instead of MW command on Rx DMA when the following requirements are met:

i. The Cache Line Size written in offset 0Ch of the PCI configuration space is 8 or 16 longwords (DWORDs).

ii. The accessed address is cache line aligned.

iii. The RTL8169 has at least 8/16 longwords (DWORDs) of data in its Rx FIFO.

iv. The MWI (bit 4) in the PCI Configuration Command register should be set to 1.

The RTL8169 uses the Memory Write (MW) command instead of the MWI whenever there any one of the above listed

requirements has failed. The RTL8169 terminates the WMI cycle at the end of the cache line when a WMI cycle has started and

at least one of the requirements are no longer held.

Example:

Assume Rx packet length = 1514 byte, cache line size = 16 DWORDs (longwords), and Rx buffer start address =

64m+4 (m > 0).

Step1: Memory Write (MW)

Data: (0-3) => (4-7) => (8-11) => ………... => (56-59)

To Address: <64m+4>, <64m+8>, …………., <64m+60>

Step2. Memory Write and Invalidate (MWI)

(byte offset of the Rx packet)

(reach cache line boundary)

Data: (60-63) => (64-67) => (68-71) => ……………………..….... => (1454-1457)

To Address: <64m+64>, <64m+68>, ………………..….., <64m+64+(16*4)*21+(16-1)*4>

Step3. Memory Write(MW)

Data: (1458-1461) => (1462-1465) => ……………………..……... => (1512-1513)

To Address: <64m+64+(16*4)*22>, <64m+64+(16*4)*22+4>, , <64m+64+(16*4)*22+42>

9.5.4 Dual Address Cycle (DAC)

The Dual Address Cycle (DAC) command is used to transfer a 64-bit address to devices that support 64-bit addressing when the

address is not in the low 4 GB address space. The RTL8169 is capable of performing DAC, such that it is very competent as a

network server card in a heavy-duty server with the possibility of allocating a memory buffer above a 4GB memory address space.

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9.6 LED Functions

The RTL8169 supports 4 LED signals in 4 different configurable operation modes. The following sections describe the different

LED actions.

9.6.1 Link Monitor

The Link Monitor senses the link integrity or if a station is down, such as LINK10, LINK100, LINK1000, LINK10/100/1000,

LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link LED pin is driven low.

Once a cable is disconnected, the link LED pin is driven high indicating that no network connection exists.

9.6.2 Rx LED

In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring.

Power On

LED = High

No

Receiving

Packet?

Yes

LED = High for (100 +- 10) ms

LED = Low for (12 +- 2) ms

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9.6.3 Tx LED

In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring.

Power On

LED = High

No

Transmitting

Packet?

Yes

LED = High for (100 +- 10) ms

LED = Low for (12 +- 2) ms

9.6.4 Tx/Rx LED

In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring.

Power On

LED = High

No

Tx/Rx Packet?

Yes

LED = High for (100 +- 10) ms

LED = Low for (12 +- 2) ms

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RTL8169

9.6.5 LINK/ACT LED

In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8169 is linked and operating properly. This

LED high for extended periods, indicates that a link problem exists.

Power On

LED = High

No

Link?

Yes

LED = Low

No

Tx/Rx packet?

Yes

LED = High for (100 +- 10) ms

LED = Low for (12 +- 2) ms

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RTL8169

9.7 Physical Layer Interfaces

The RTL8169 supports standard media independent MII and GMII for 10Mbps, 100Mbps, and 1000Mbps applications. The

RTL8169 also supports TBI (Ten-Bit Interface) for 1000Base-X applications by connecting to industry standard external

SERDES devices for fiber applications. The RTL8169 only operates in full-duplex mode in 1000Mbps for both GMII and TBI

applications. In addition, a management interface is defined for MII and GMII.

9.7.1 Media Independent Interface (MII)

The RTL81689 supports 10Mbps and 100Mbps physical layer devices through the MII as defined in the IEEE 802.3 (clause 22)

specifications. The MII consists of a transmit data interface (TxEN, TxER, TXD[3:0], and TxCLK), a receive data interface

(RxDV, RxER, RXD[3:0], and RxCLK), 2 status signals (CRS and COL) and a management interface (MDC and MDIO). In

this mode of operation, both Transmit and Receive clocks are supplied by the PHY.

9.7.2 Gigabit Media Independent Interface (GMII)

The RTL81689 can support 1000Mbps physical layer devices through the GMII as defined in the IEEE 802.3 (clause 35)

specifications. The GMII extends from the MII to use 8-bit data interfaces and to operate at a higher frequency. The GMII

consists of a transmit data interface (TxEN, TxER, TXD[7:0], and GTxCLK), a receive data interface (RxDV, RxER, RXD[7:0],

and RxCLK), 2 status signals (CRS and COL) and a management interface (MDC and MDIO). Many of the signals are shared

with the MII interface. One significant difference is the Transmit clock (GTxCLK) is supplied by the RTL81689 instead of the

PHY. The management interface (described later) is the same in both MII and GMII modes

9.7.3 Ten Bit Interface (TBI)

The TBI provides a port for transmit and receive data for interfacing to devices that support the 1000Base-X portion of the 802.3

specifications. This includes 1000Base-FX fiber devices. The port consists of data paths that are 10 bits wide in each direction as

well as control signals. This interface shares pins with the MII and GMII interfaces.

9.7.4 MII/GMII Management Interface

The MII/GMII management interface utilizes a communication protocol similar to a serial EEPROM. Signaling occurs on two

signals: clock (MDC) and data (MDIO). This protocol provides capability for addressing up to 32 individual Physical Media

Dependent (PMD) devices which share the same serial interface, and for addressing up to 32 16-bit read/write registers within

each PMD. The MII management protocol utilizes the following frame format: start bits (SB), opcode (OP), PMD address (PA),

register address (RA), line turnaround (LT) and data, as shown below.

SB

OP

PA

RA

LT

2

Data

2 bits 2 bits

5 bits

16 bits

bits

MII Management Frame Format

i. Start bits are defined as <01>.

ii. Opcode bits are defined as <01> for a Write access and <10> for a Read access.

iii. PMD address is the device address.

iv. Register address is address of the register within that device.

v. Line turnaround bits will be <10> for Write accesses and will be <xx> for Read accesses. This allows time for the MII

lines to “turn around”.

vi. Data is the 16 bits of data that will be written to or read from the PMD device.

A reset frame, defined as 32 consecutive 1s (FFFF FFFFh), is also provided. After power up, all MII PMD devices must wait for

a reset frame to be received prior to participating in MII management communication. Additionally, a reset frame may be issued

at any time to allow all connected PMDs to re-synchronize to the data traffic.

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RTL8169

10. Application Diagrams

10.1 10/100/1000Base-T Application

Main/Aux. Power

Regulators

Power 3.3V, 2.5V, 1.8V

Power

3.3V, 1.8V

LED

Power 3.3V

Power 3.3V,

2.5V, 1.8V

BootROM /

FLASH

GMII

Power 3.3V

RTL8169

External PHY -

Marvell 88E1000

EEPROM

125MHz

clock

25MHz clock

32-/64-bit 33/66MHz PCI

Interface

10.2 1000Base-X Application

Main/Aux. Power

Regulators

Power 3.3V, 1.8V

Power

125MHz

Clock

3.3V, 1.8V

LED

Power 3.3V

Power 3.3V, ...

BootROM /

FLASH

TBI

Power 3.3V

RTL8169

Optical

External 1.25Gb

SERDES

Transceiver

EEPROM

32-/64-bit 33/66MHz PCI

Interface

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65

RTL8169

11. Electrical Characteristics

11.1 Temperature Limit Ratings

Parameter

Minimum

Maximum

+125

Units

°C

Storage temperature

-55

0

Operating temperature

70

11.2 DC Characteristics

Below is a description of the general DC specifications for the RTL8169.

Symbol

VDD33

VDD18

Parameter

3.3V Supply Voltage

1.8V Supply Voltage

Minimum High Level Output Voltage

Maximum Low Level Output Voltage

Minimum High Level Input Voltage

Maximum Low Level Input Voltage

Input Current

Conditions

Minimum Typical Maximum Units

3.0

1.71

3.3

1.8

3.6

1.89

V

ih

V

I

0.9 * Vcc

Vcc

V

oh

ol

oh = -8mA

ol = 8mA

0.1 * Vcc

Vcc+0.5

0.3 * Vcc

1.0

V

uA

0.5 * Vcc

-0.5

il

I

V

-1.0

-10

in

in = cc or GND

I

V

Tri-State Output Leakage Current

10

oz

out = cc or GND

Average Operating Supply Current from

Icc33

100

70

mA

3.3V

Average Operating Supply Current from

1.8V

I

cc18

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RTL8169

11.3 AC Characteristics

11.3.1 FLASH/BOOT ROM Timing

FLASH/BOOT ROM - Read

MA16-0

TRC

ROMCSB

TWRBR

OEB

TOES

TCE

WEB

TOHZ

TOOLZ

TOH

TCOLZ

MD7-0

TACC

Symbol

Description

Minimum

Typical

Maximum

Units

ns

TRC

TCE

Read Cycle

135

-

200

60

-

40

0

Chip Enable Access Time

Address Access Time

Output Enable Access Time

Chip Enable to Output in Low Z

-

ns

TACC

TOES

TCOLZ

TOOLZ

TOHZ

TOH

ns

0

-

ns

Output Enable to Output in Low Z

Output Disable to Output in High Z

Output Hold from Address, ROMCSB, or

OEB

ns

0

ns

TWRBR

Write Recovery time Before Read

6

-

us

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RTL8169

FLASH MEMORY - Write

SETUPMPROGRAM

COMMAND

PROGRAM COMMAND

STANDBY/VCC

PROGRAM

VERIFY

VCC POWER-UP

& STANDBY

LATCH ADDRESS

& DATA

POWER-DOWN

PROGRAMMING

VERIFICATION

COMMAND

MA16-0

ROMCSB

OEB

tWC

tAS

tRC

tAH

tCH

tAH

tCS

tCH

tCS

tWHWH1

tWHGL

tWPH

tGHWL

tDF

tWP

tDS

tWP

tDS

tOH

tOE

WEB

tDS

tDH

tOOLZ

VALID

DATAOUT

=40H

DATAOUT

=C0H

DATAO

UT

DATA

IN

MD7-0

tCOLZ

tCE

Symbol

TWC

Description

Write Cycle Time

Address Set-up Time

Address Hold Time

Data Set-up Time

Data Hold Time

Minimum

Typical

Maximum

Units

ns

135

0

-

TAS

ns

TAH

60

50

10

6

0

20

ns

TDS

ns

TDH

ns

TWHGL

TGHWL

TCS

Write Recovery Time before Read

Read Recovery Time before Write

Chip Enable Set-up Time before

Write

us

ns

TCH

TWP

Chip Enable Hold Time

Write Pulse Width

0

-

us

ns

us

50

20

10

TWPH

Write Pulse Width High

TWHWH1

Duration of Programming Operation

25

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68

RTL8169

11.3.2 Serial EEPROM Interface Timing

(93C46(64*16)/93C56(128*16))

EESK

tcs

EECS

(Read)

1

0

1

An

A2 A1 A0

EEDI

(Read)

0

Dn

D1 D0

EEDO

High Impedance

EESK

EECS

EEDI

tcs

...

(Write)

1

A0 Dn

D0

(Write)

BUSY

tcsh

READY

EEDO

High Impedance

twp

tsk

EESK

tskh

tskl

tcss

tdis

EECS

EEDI

tdih

tdos

tdoh

(Read)

EEDO

tsv

STATUS VALID

(Program)

Symbol

tcs

Parameter

Min.

9346/9356 1000/250

9346/9356

Typical

Max.

Unit

Minimum CS Low Time

Write Cycle Time

SK Clock Cycle Time

SK High Time

ns

ms

us

ns

twp

tsk

10/10

9346/9356

4/1

tskh

tskl

tcss

tcsh

tdis

tdih

tdos

tdoh

tsv

9346/9356 1000/500

9346/9356 1000/250

9346/9356 200/50

SK Low Time

CS Setup Time

CS Hold Time

9346/9356

0/0

DI Setup Time

9346/9356 400/50

9346/9356 400/100

9346/9356 2000/500

9346/9356

DI Hold Time

DO Setup Time

DO Hold Time

2000/500

1000/500

CS to Status Valid

9346/9356

EEPROM Access Timing Parameters

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69

RTL8169

11.3.3 PCI Bus Operation Timing

PCI Bus Timing Parameters

66MHz

33MHz

Symbol

T val

Parameter

Min

Max

Min

Max

Units

CLK to Signal Valid Delay-bused signals

2

6

2

11

12

ns

CLK to Signal Valid Delay-point to point

Float to Active Delay

Active to Float Delay

T val(ptp)

T on

ns

14

28

ns

T off

T su

Input Setup Time to CLK-bused signals

Input Setup Time to CLK-point to point

Input Hold Time from CLK

Reset active time after power stable

Reset active time after CLK STABLE

Reset Active to Output Float delay

REQB to REQ64B Setup Time

RSTB to REQ64B Hold Time

3

5

0

1

7

10

0

1

100

ns

T su(ptp)

T h

ns

ms

us

T rst

100

T rst-clk

T rst-off

Trrsu

40

50

40

50

ns

10*Tcyc

ns

0

2^25

5

0

2^25

5

ns

Trrh

RSTB High to First configuration Access

RSTB High to First FRAMEB assertion

clocks

T rhfa

T rhff

PCI Interface Timing Parameters

V_th

V_tl

V_test

CLK

T_val

OUTPUT

DELAY

V_trise, V_tfall

Tri-State

OUTPUT

V_test

T_on

V_test

T_off

Output Timing Measurement Condition

V_th

V_test

CLK

V_tl

T_su

inputs valid

T_h

V_th

V_tl

V_test

V_max

INPUT

Input Timing Measurement Conditions

Symbol

Vth

Level

0.6Vcc

Units

V

0.2Vcc

0.4Vcc

V

Vtf

V

Vtest

0.285Vcc

0.615Vcc

0.4Vcc

V

Vtrise

V

Vtfall

V

Vmax

1

V/ns

Input Signal

Edge Rate

Measurement Condition Parameters

2002/03/27

Rev.1.21

70

RTL8169

PCI Clock Specification

T_high

0.6Vcc

T_low

0.5Vcc

0.4Vcc

0.4Vcc, peak-to-peak

(minimum)

0.3Vcc

0.2Vcc

T_cyc

3.3V Clock Waveform

V_ih

V_test

CLK (@ Device #1)

V_il

T_skew

V_ih

T_skew

V_test

CLK (@ Device #2)

V_il

Clock Skew Diagram

66MHz

33MHz

Symbol

Tcyc

Parameter

CLK Cycle Time

Min

15

Max

30

Min

30

Max

∞

Units

ns

Thigh

Tlow

--

6

11

1

ns

V/ns

mV/ns

ns

CLK High Time

CLK Low Time

CLK Slew Rate

RST# Slew Rate

CLK Skew

1.5

50

4

-

1

4

--

50

-

Tskew

2

Clock and Reset Specifications

2002/03/27

Rev.1.21

71

RTL8169

PCI Transactions

CLK

1

2

3

4

5

6

7

8

9

10

FRAMEB

AD31-0

ADDRESS

BUS CMD

DATA

BE3-0B

C/BE3-0B

IRDYB

TRDYB

DEVSELB

I/O Read

CLK

FRAMEB

AD31-0

1

2

3

4

5

6

7

8

9

10

ADDRESS

BUS CMD

DATA

BE3-0B

C/BE3-0B

IRDYB

TRDYB

DEVSELB

Fig. 11.3.3.3.2 I/O Write

2002/03/27

Rev.1.21

72

RTL8169

CLK

FRAMEB

IDSEL

1

2

3

4

5

6

7

8

9

10

ADDRESS

BUS CMD

DATA

AD31-0

BE3-0B

C/BE3-0B

IRDYB

TRDYB

DEVSELB

Configuration Read

CLK

FRAMEB

IDSEL

1

2

3

4

5

6

7

8

9

10

ADDRESS

BUS CMD

DATA

AD31-0

BE3-0B

C/BE3-0B

IRDYB

TRDYB

DEVSELB

Configuration Write

2002/03/27

Rev.1.21

73

RTL8169

CLK

REQB-A

REQB-B

GNTB-A

GNTB-B

FRAMEB

AD

1

2

3

4

5

6

7

8

9

10

ADDRESS

DATA

ADDRESS

DATA

BUS Arbitration

CLK

FRAMEB

AD31-0

1

2

3

4

5

6

7

8

9

DATA-1

DATA-2

DATA-3

ADDRESS

BUS CMD

BE3-0B

C/BE3-0B

IRDYB

TRDYB

DEVSELB

Memory Read below 4GB (32-bit address, 32-bit data; 32-bit slot)

2002/03/27

Rev.1.21

74

RTL8169

CLK

FRAMEB

AD31-0

1

2

3

4

5

6

7

8

9

ADDRESS

DATA-1

DATA-2

DATA-3

BUS CMD BE3-0B-1 BE3-0B-2

BE3-0B-3

C/BE3-0B

IRDYB

TRDYB

DEVSELB

Memory Write below 4GB (32-bit address, 32-bit data; 32-bit slot)

2002/03/27

Rev.1.21

75

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

DATA-1

DATA-2

DATA-3

ADDRESS

BUS CMD

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

BE3-0B

BE7-4B

TRDYB

DEVSELB

ACK64B

Memory Read below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot)

2002/03/27

Rev.1.21

76

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

ADDRESS

DATA-1

DATA-2

DATA-3

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

BUS CMD BE3-0B-1 BE3-0B-2

BE7-4B-1

BE3-0B-3

TRDYB

DEVSELB

ACK64B

Memory Write below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot)

2002/03/27

Rev.1.21

77

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

DATA-1

DATA-2

DATA-3

DATA-4

DATA-5

DATA-6

ADDRESS

BUS CMD

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

BE3-0B

BE7-4B

TRDYB

DEVSELB

ACK64B

Memory Read below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot)

2002/03/27

Rev.1.21

78

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

ADDRESS

DATA-1

DATA-2

DATA-3

DATA-4

DATA-5

DATA-6

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

BUS CMD BE3-0B-1 BE3-0B-2

BE7-4B-1 BE7-4B-2

BE3-0B-3

BE7-4B-3

TRDYB

DEVSELB

ACK64B

Memory Write below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot)

2002/03/27

Rev.1.21

79

RTL8169

CLK

FRAMEB

AD31-0

1

2

3

4

5

6

7

8

9

10

HI-ADDR

LO-ADDR

DAC CMD

DATA-1

DATA-2

DATA-3

BUS CMD

BE3-0B

C/BE3-0B

IRDYB

TRDYB

DEVSELB

Memory Read above 4GB (DAC, 64-bit address, 32-bit data; 32-bit slot)

CLK

FRAMEB

AD31-0

1

2

3

4

5

6

7

8

9

10

LO-ADDR HI-ADDR

DATA-1

DATA-2

DATA-3

BUS CMD

DAC CMD

BE3-0B-1 BE3-0B-2

BE3-0B-3

C/BE3-0B

IRDYB

TRDYB

DEVSELB

Memory Write above 4GB (DAC, 64-bit address, 32-bit data; 32-bit slot)

2002/03/27

Rev.1.21

80

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

10

HI-ADDR

LO-ADDR

DATA-1

DATA-2

DATA-3

HI-ADDR

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

DAC CMD

BUS CMD

BE3-0B

BUS CMD

BE7-4B

TRDYB

DEVSELB

ACK64B

Memory Read above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot)

2002/03/27

Rev.1.21

81

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

10

LO-ADDR HI-ADDR

HI-ADDR

DATA-1

DATA-2

DATA-3

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

BUS CMD

DAC CMD

BE3-0B-1 BE3-0B-2

BE7-4B-1

BE3-0B-3

BUS CMD

TRDYB

DEVSELB

ACK64B

Memory Write above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot)

2002/03/27

Rev.1.21

82

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

10

LO-ADDR HI-ADDR

HI-ADDR

DATA-1

DATA-2

DATA-3

DATA-4

DATA-5

DATA-6

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

DAC CMD BUS CMD

BUS CMD

BE3-0B

BE7-4B

TRDYB

DEVSELB

ACK64B

Memory Read above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot)

2002/03/27

Rev.1.21

83

RTL8169

CLK

FRAMEB

REQ64B

AD31-0

1

2

3

4

5

6

7

8

9

10

HI-ADDR

LO-ADDR

DATA-1

DATA-2

DATA-3

DATA-4

DATA-5

DATA-6

HI-ADDR

AD63-32

C/BE3-0B

C/BE7-4B

IRDYB

DAC CMD

BUS CMD BE3-0B-1 BE3-0B-2

BE3-0B-3

BE7-4B-3

BUS CMD

BE7-4B-1 BE7-4B-2

TRDYB

DEVSELB

ACK64B

Memory Write above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot)

CLK

1

2

3

4

5

6

7

8

9

FRAMEB

AD31-0

IRDYB

ADDRESS

DATA-1

DATA-2

TRDYB

STOPB

DEVSELB

Target Initiated Termination - Retry

2002/03/27

Rev.1.21

84

RTL8169

CLK

FRAMEB

IRDYB

1

2

3

4

5

6

7

8

9

TRDYB

STOPB

DEVSELB

Target Initiated Termination - Disconnect

CLK

FRAMEB

IRDYB

1

2

3

4

5

6

7

8

9

TRDYB

STOPB

DEVSELB

Target Initiated Termination - Abort

2002/03/27

Rev.1.21

85

RTL8169

CLK

FRAMEB

IRDYB

1

2

3

4

5

6

7

8

9

TRDYB

NO RESPONSE

ACKNOWLEDGE

DEVSELB

FAST

MED

SLOW

SUB

Master Initiated Termination - Abort

CLK

FRAMEB

AD

1

2

3

4

5

6

7

8

9

10

ADDRESS

BUS CMD

DATA

BE#

ADDRESS

BUS CMD

DATA

BE#

C/BE#

PAR/PAR64

SERR#

PERR#

Parity Operation - One Example

2002/03/27

Rev.1.21

86

RTL8169

11.3.4 MII Timing

MII Timing – MII PORT - Transmit

tTxCC

tTxCH

Vih(min)

Vil(max)

TxCLK

tTxCL

tTxRV

tTxHT

Vih(min)

Vil(max)

TxD[3:0], TxEN

MII Transmit Timing

10MHz

100MHz

Symbol

tTxCC

tTxCH

tTxCL

tTxRV

tTxHD

Description

Min

Max Min

Max Units

Typical

Tx Clock Cycle

400

40

ns

Tx Clock High Time

Tx Clock Low Time

Tx Clock rise to TxD, TxEN valid

TxD, TxEN Hold Time

140

260

20

14

26

20

5

MII Transmit Timing Parameters

MII Timing – MII PORT - Receive

tRxCC

tRxCH

Vih(min)

Vil(max)

RxCLK

tRxCL

tRxSU

tRxHT

Vih(min)

Vil(max)

RxD[3:0], RxDV,

RxER

MII Transmit Timing

10MHz

100MHz

Typical

40

Symbol

tRxCC

tRxCH

tRxCL

tRxSU

tRxHD

Description

Min

Max Min

Max Units

Typical

Rx Clock Cycle

400

ns

Rx Clock High Time

Rx Clock Low Time

RxD, RxDV, RxER Setup Time

RxD, RxDV, RxER Hold Time

140

10

260

20

14

26

20

ns

14

10

5

MII Transmit Timing Parameters

2002/03/27

Rev.1.21

87

RTL8169

MII Timing – MII Management Port

tMCC

tMCH

Vih(min)

Vil(max)

MDC

tMCL

tMSU

tMRV

tMHT

Vih(min)

Vil(max)

MDIO

MII Management Timing

Symbol

tMCC

tMCH

tMCL

tMSU

tMHT

tMRV

Description

Min

Max

Units

ns

Typical

MDC Cycle Time

50

25

10

5

MDC High Time

ns

MDC Low Time

ns

MDIO Setup Time

MDIO Hold Time

ns

MDC Clock rise to MDIO valid

40

ns

MII Management Timing Parameters

2002/03/27

Rev.1.21

88

RTL8169

11.3.5 GMII Timing

tGCC

tGCH

tF

Vih_ac(min)

Vil_ac(max)

RxCLK, GTxCLK

tGCL

tGSUT

tGSUR

tGHTT

tGHTR

Vih_ac(min)

Vil_ac(max)

RxD[7:0], RxDV,

RxER, TxD[7:0],

TxEN

tR

GMII Timing

Symbol

Description

Min

Typical

Max

Units

V

Vil_ac

Vih_ac

Input Low Voltage ac

0.7

Input High Voltage ac

1.9

V

fGTxCLK, fRxCLK GTxCLK, RxCLK frequency

125 - 100ppm

125

8

125 + 100ppm MHz

tGCC

tGCH

tGCL

tR

GTxCLK, RxCLK Cycle Time

GTxCLK, RxCLK High Time

GTxCLK, RxCLK Low Time

GTxCLK, RxCLK Rise Time

GTxCLK, RxCLK Fall Time

7.5

2.5

8.5

ns

1

ns

tF

ns

RSR

GTxCLK, RxCLK Rising Slew Rate

GTxCLK, RxCLK Falling Slew Rate

TxD, TxEN Setup to ↑ of GTxCLK

TxD, TxEN Hold from ↑ of GTxCLK

RxD, RxDV, RxER Setup to ↑ of RxCLK

RxD, RxDV, RxER Hold from ↑ of RxCLK

0.6

2.5

0.5

2

V/ns

ns

FSR

tGSUT

tGHTT

tGSUR

tGHTR

ns

0

ns

GMII Timing Parameters

2002/03/27

Rev.1.21

89

RTL8169

11.3.6 TBI Timing

tTxCC

tRC

tFC

2.0V

1.4V

0.8V

GTxCLK

tRD

tTxSU

tTxHT

2.0V

0.8V

Tx[9:0]

Valid Data

tFD

TBI Tx Timing

tA-B

1.4V

RxCLK0

Rx[9:0]

tRxSU

2.0V

0.8V

tRxHT

1.4V

RxCLK1

TBI Rx Timing

Symbol

Description

Tx Clock Cycle

Min

Typical

8

125

Max

Units

tTxCC

ns

MHz

ns

fGTxCLK GTxCLK frequency

125 – 100ppm

0.7

125 + 100ppm

2.4

tRC

Clock Rise Time of GTxCLK,

RxCLK0, RxCLK1

tFC

Clock Fall Time of GTxCLK,

RxCLK0, RxCLK1

0.7

40

2.4

60

ns

%

tDUTY

Clock Duty Cycle of GTxCLK,

RxCLK0, RxCLK1

tTxSU

tTxHT

tRD

2.0

1.0

0.7

ns

Data Setup to ↑ of GTxCLK

Data Hold from ↑ of GTxCLK

Data Rise Time of Tx[9:0],

Rx[9:0]

rFD

Data Fall Time of Tx[9:0],

Rx[9:0]

0.7

ns

fRxCLKx RxCLK0, RxCLK1 frequency

62.5

MHz

us/MHz

ns

tDRIFT

tRxSU

tRxHT

tA-B

RxCLK0/1 Drift Rate

0.2

2.5

1.5

7.5

Data Setup to ↑ of RxCLK0/1

Data Hold after ↑ of RxCLK0/1

TBI RxCLK Skew

ns

8.5

TBI Timing Parameters

2002/03/27

Rev.1.21

90

RTL8169

12. Mechanical Dimensions

Note:

1.Dimensions D & E do not include interlead flash.

Symbol

Dimension in inch

Min Typical Max

Dimension in mm

Min Typical Max

2.Dimension b does not include dambar protrusion/intrusion.

3.Controlling dimension: Millimeter

A

A₁

A₂

B

C

D

0.136 0.144 0.152 3.45 3.65 3.85

0.004 0.010 0.036 0.10 0.25 0.91

0.119 0.128 0.136 3.02 3.24 3.46

0.004 0.008 0.012 0.10 0.20 0.30

0.002 0.006 0.010 0.04 0.15 0.26

1.093 1.102 1.112 27.75 28.00 28.25

0.012 0.020 0.031 0.30 0.50 0.80

1.169 1.205 1.240 29.70 30.60 31.50

0.010 0.020 0.030 0.25 0.50 0.75

0.041 0.051 0.061 1.05 1.30 1.55

4.General appearance spec. should be based on final visual

Inspection spec.

TITLE : 208L QFP ( 28x28 mm**2 ) FOOTPRINT 2.6mm

PACKAGE OUTLINE DRAWING

E

e

LEADFRAME MATERIAL:

APPROVE

CHECK

DOC. NO.

VERSION

PAGE

DWG NO.

DATE

530-ASS-P004

1

22 OF 22

Q208 - 1

H_D

H_E

L

L₁

Y

APR. 11.1997

-

0.004

12°

-

0°

-

0.10

12°

Θ

0

°

REALTEK SEMICONDUCTOR CO., LTD

2002/03/27

Rev.1.21

91

RTL8169

Realtek Semiconductor Corp.

Headquarters

1F, No. 2, Industry East Road IX, Science-based

Industrial Park, Hsinchu, 300, Taiwan, R.O.C.

Tel : 886-3-5780211 Fax : 886-3-5776047

WWW: www.realtek.com.tw

2002/03/27

Rev.1.21

92


型号：	RTL8169
厂家：	ETC
描述：	RTL8169 Specification RTL8169规格\n
文件：	总92页 (文件大小：1346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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