RTL8169S-32 [REALTEK]
LAN Controller, PQFP128;
| 型号： | RTL8169S-32 |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | LAN Controller, PQFP128 局域网 外围集成电路 |
| 文件： | 总55页 (文件大小：985K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8169S-32/RTL8169S-64
INTEGRATED GIGABIT ETHERNET CONTROLLER (NIC)
DATASHEET
Rev. 1.7
12 August 2004
Track ID: JATR-1076-21
RTL8169S-32/RTL8169S-64
Datasheet
COPYRIGHT
©2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
USING THIS DOCUMENT
This document is intended for use by the software engineer when programming for Realtek RTL8169S-32
& RTL8169S-64 controller chips. Information pertaining to the hardware design of products using these
chips is contained in a separate document.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
Release Date
2003/03/20
2003/04/12
2003/06/24
Summary
First release.
1.1
1.2
Revised pin name and pin assignments.
Minor 233-pin TFBGA pin number corrections.
IEEE 802.3z changed to IEEE 802.3ab in General Description.
Add the voltage variation to DC characteristics.
Remove “JTAG support” from the Features section. The RTL8169S does not
support JTAG.
1.3
1.4
2003/09/23
2003/09/24
1.5
1.6
1.7
2004/01/16
2004/02/26
2004/08/12
EEDI/AUX and EEDO description changed in Table 3, page 9.
VDD18 parameters changed in Table 12, page 23, and Table 15, page 24.
Revised Pin 126 (VDD18A) description (see Table 8, page 11, Table 11, page 23,
Table 12, page 23, and Table 15, page 24).
Integrated Gigabit Ethernet Controller (NIC)
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Track ID: JATR-1076-21 Rev. 1.7
RTL8169S-32/RTL8169S-64
Datasheet
Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................2
3. SYSTEM APPLICATIONS.................................................................................................................................................2
4. PIN ASSIGNMENTS ...........................................................................................................................................................3
4.1.
4.2.
128-PIN QFP PIN ASSIGNMENTS..................................................................................................................................3
233-PIN TFBGA PIN ASSIGNMENTS ............................................................................................................................4
5. PIN DESCRIPTIONS ..........................................................................................................................................................5
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
POWER MANAGEMENT/ISOLATION...............................................................................................................................5
PCI INTERFACE............................................................................................................................................................6
EEPROM ....................................................................................................................................................................9
TRANSCEIVER INTERFACE............................................................................................................................................9
CLOCK .......................................................................................................................................................................10
REGULATOR & REFERENCE........................................................................................................................................10
LEDS .........................................................................................................................................................................10
POWER & GROUND ....................................................................................................................................................11
NC (NOT CONNECTED)..............................................................................................................................................11
6. FUNCTIONAL DESCRIPTION.......................................................................................................................................12
6.1.
6.1.1.
6.1.2.
6.2.
TRANSCEIVER ............................................................................................................................................................12
Transmitter ...........................................................................................................................................................12
Receiver................................................................................................................................................................12
MAC..........................................................................................................................................................................13
NEXT PAGE ................................................................................................................................................................13
MII/GMII INTERFACE................................................................................................................................................14
MII........................................................................................................................................................................14
GMII.....................................................................................................................................................................14
LEDS .........................................................................................................................................................................14
Link Monitor.........................................................................................................................................................14
RX LED ................................................................................................................................................................15
TX LED.................................................................................................................................................................16
TX/RX LED...........................................................................................................................................................17
6.3.
6.4.
6.4.1.
6.4.2.
6.5.
6.5.1.
6.5.2.
6.5.3.
6.5.4.
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6.5.5.
6.6.
6.7.
LINK/ACT LED ....................................................................................................................................................18
FLASH/EEPROM INTERFACE ....................................................................................................................................19
POWER MANAGEMENT...............................................................................................................................................20
7. CHARACTERISTICS.......................................................................................................................................................23
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
ABSOLUTE MAXIMUM RATINGS .................................................................................................................................23
RECOMMENDED OPERATING CONDITIONS .................................................................................................................23
CRYSTAL REQUIREMENTS ..........................................................................................................................................23
THERMAL CHARACTERISTICS.....................................................................................................................................24
DC CHARACTERISTICS...............................................................................................................................................24
AC CHARACTERISTICS...............................................................................................................................................25
Serial EEPROM Interface Timing ........................................................................................................................25
PCI BUS OPERATION TIMING .....................................................................................................................................26
PCI Bus Timing Parameters.................................................................................................................................26
PCI Clock Specification .......................................................................................................................................28
PCI Transactions..................................................................................................................................................29
7.6.1.
7.7.
7.7.1.
7.7.2.
7.7.3.
8. MECHANICAL DIMENSIONS .......................................................................................................................................45
8.1.
8.2.
8.3.
8.4.
128-PIN QFP MECHANICAL DIMENSIONS ..................................................................................................................45
NOTES FOR 128-PIN QFP DIMENSIONS ......................................................................................................................46
233-PIN TFBGA MECHANICAL DIMENSIONS............................................................................................................47
NOTES FOR 233-PIN TFBGA DIMENSIONS.................................................................................................................48
9. ORDERING INFORMATION..........................................................................................................................................49
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Datasheet
List of Tables
TABLE 1. POWER MANAGEMENT/ISOLATION ..............................................................................................................................5
TABLE 2. PCI INTERFACE ...........................................................................................................................................................6
TABLE 3. EEPROM ....................................................................................................................................................................9
TABLE 4. TRANSCEIVER INTERFACE............................................................................................................................................9
TABLE 5. CLOCK .......................................................................................................................................................................10
TABLE 6. REGULATOR & REFERENCE .......................................................................................................................................10
TABLE 7. LEDS.........................................................................................................................................................................10
TABLE 8. POWER & GROUND....................................................................................................................................................11
TABLE 9. NC (NOT CONNECTED)..............................................................................................................................................11
TABLE 10. FLASH/EEPROM INTERFACE....................................................................................................................................19
TABLE 11. ABSOLUTE MAXIMUM RATINGS................................................................................................................................23
TABLE 12. RECOMMENDED OPERATING CONDITIONS.................................................................................................................23
TABLE 13. CRYSTAL REQUIREMENTS .........................................................................................................................................23
TABLE 14. THERMAL CHARACTERISTICS....................................................................................................................................24
TABLE 15. DC CHARACTERISTICS ..............................................................................................................................................24
TABLE 16. EEPROM ACCESS TIMING PARAMETERS .................................................................................................................25
TABLE 17. PCI BUS TIMING PARAMETERS .................................................................................................................................26
TABLE 18. MEASUREMENT CONDITION PARAMETERS................................................................................................................27
TABLE 19. CLOCK AND RESET SPECIFICATIONS..........................................................................................................................28
TABLE 20. ORDERING INFORMATION..........................................................................................................................................49
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Datasheet
List of Figures
FIGURE 1. 128-PIN QFP PIN ASSIGNMENTS ................................................................................................................................3
FIGURE 2. 233-PIN TFBGA PIN ASSIGNMENTS ..........................................................................................................................4
FIGURE 3. RX LED...................................................................................................................................................................15
FIGURE 4. TX LED ...................................................................................................................................................................16
FIGURE 5. TX/RX LED.............................................................................................................................................................17
FIGURE 6. LINK/ACT LED......................................................................................................................................................18
FIGURE 7. SERIAL EEPROM INTERFACE TIMING .....................................................................................................................25
FIGURE 8. OUTPUT TIMING MEASUREMENT CONDITIONS .........................................................................................................27
FIGURE 9. INPUT TIMING MEASUREMENT CONDITIONS ............................................................................................................27
FIGURE 10. 3.3V CLOCK WAVEFORM.........................................................................................................................................28
FIGURE 11. CLOCK SKEW DIAGRAM...........................................................................................................................................28
FIGURE 12. I/O READ .................................................................................................................................................................29
FIGURE 13. I/O WRITE................................................................................................................................................................29
FIGURE 14. CONFIGURATION READ ............................................................................................................................................30
FIGURE 15. CONFIGURATION WRITE...........................................................................................................................................31
FIGURE 16. BUS ARBITRATION ...................................................................................................................................................31
FIGURE 17. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT)...........................................................32
FIGURE 18. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT) .........................................................33
FIGURE 19. TARGET INITIATED TERMINATION - DISCONNECT....................................................................................................33
FIGURE 20. TARGET INITIATED TERMINATION - ABORT .............................................................................................................34
FIGURE 21. MASTER INITIATED TERMINATION - ABORT.............................................................................................................34
FIGURE 22. PARITY OPERATION – ONE EXAMPLE ......................................................................................................................35
FIGURE 23. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) .........................36
FIGURE 24. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ........................37
FIGURE 25. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)..........................38
FIGURE 26. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ........................39
FIGURE 27. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT).................................................40
FIGURE 28. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT) ...............................................40
FIGURE 29. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)................41
FIGURE 30. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ..............42
FIGURE 31. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)................43
FIGURE 32. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ..............44
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RTL8169S-32/RTL8169S-64
Datasheet
1. General Description
The Realtek RTL8169S-32 and RTL8169S-64 combine a triple-speed IEEE 802.3 compliant media access
controller (MAC) with a triple-speed Ethernet transceiver, 32(64*)-bit PCI bus controller, and embedded
memory. With state-of-the-art DSP technology and mixed-mode signal technology, they offer high-speed
transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover
Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo
cancellation, timing recovery, and error correction are implemented to provide robust transmission and
reception capability at high speeds.
The devices support the PCI v2.2 bus interface for host communications with power management and are
compliant with the IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification
for 1000Mbps Ethernet. They support an auxiliary power auto-detect function, and will auto-configure
related bits of the PCI power management registers in PCI configuration space.
They support the Advanced Configuration and Power Interface (ACPI)--power management for modern
operating systems that are capable of Operating System directed Power Management (OSPM)--to achieve
the most efficient power management possible.
In addition to the ACPI feature, the RTL8169S-32 and RTL8169S-64 support remote wake-up (including
AMD Magic Packet, Re-LinkOk, and Microsoft® Wake-up frame) in both ACPI and APM (Advanced
Power Management) environments. The LWAKE pin provides four different output signals including
active high, active low, positive pulse, and negative pulse. The versatility of the LWAKE pin provides
motherboards with Wake-On-LAN (WOL) functionality. To support WOL from a deep power down state
(e.g. D3cold, i.e. main power is off and only auxiliary exists), the auxiliary power source must be able to
provide the needed power for the RTL8169S-32 and RTL8169S-64.
The RTL8169S is fully compliant with Microsoft® NDIS5 (IP, TCP, UDP) Checksum and Segmentation
Task-offload features, and supports IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The
above features contribute to lowering CPU utilization, especially benefiting performance when in
operation as a server network card. The devices also boost their PCI performance by supporting PCI
Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when
receiving. To better qualify as a server card, the RTL8169S-32 and RTL8169S-64 support the PCI Dual
Address Cycle (DAC) command when the assigned buffers reside at a physical memory address higher
than 4 Gigabytes.
* 233-PIN TFBGA package only.
Integrated Gigabit Ethernet Controller (NIC)
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Track ID: JATR-1076-21 Rev. 1.7
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Datasheet
2. Features
ꢀ Integrated 10/100/1000 transceiver
ꢀ Fully compliant with IEEE 802.3,
IEEE 802.3u, IEEE 802.3ab
ꢀ Auto-Negotiation with Next page
capability
ꢀ Supports IEEE 802.1Q VLAN tagging
ꢀ Serial EEPROM and/or Flash support
ꢀ 3.3V signaling, 5V PCI I/O tolerant
ꢀ Supports PCI 2.2, 32-bit/64-bit
(RTL8169S-64 only), 33/66MHz
ꢀ Supports pair swap/polarity/skew
ꢀ Transmit/Receive FIFO (8K/64K)
correction
support
ꢀ Crossover Detection &
ꢀ Supports power down/link down power
Auto-Correction
saving
ꢀ Wake-on-LAN and remote wake-up
ꢀ 128-pin QFP/233-pin TFBGA package
support
ꢀ Microsoft® NDIS5 Checksum Offload
(IP, TCP, UDP) and largesend offload
support
ꢀ Supports Full Duplex flow control
(IEEE 802.3x)
3. System Applications
ꢀ Gigabit Ethernet Network Interface Cards/Workstation Cards
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Datasheet
4. Pin Assignments
4.1. 128-Pin QFP Pin Assignments
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AVDDL
VSSPST
GND
ISOLATEB
VDD18
INTAB
VDD33
PCIRSTB
PCICLK
GNTB
REQB
PMEB
VDD18
PCIAD31
PCIAD30
GND
PCIAD29
PCIAD28
VSSPST
19
MDI3-
MDI3+
VSS
AVDDL
MDI2-
MDI2+
VSS
NC
NC
AVDDH
VSS
CTRL25
AVDDL
MDI1-
MDI1+
VSS
AVDDL
MDI0-
MDI0+
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VSS
RSET
VDD18A
CTRL18
VSS
VSS
XTAL2
XTAL1
AVDDH
VSSPST
GND
LED0
VDD18
LED1
LED2
LED3
GND
EESK
VDD18
EEDI
EEDO
VDD33
EECS
LANWAKE
PCIAD0
PCIAD27
PCIAD26
VDD33
PCIAD25
PCIAD24
CBEB3
VDD18
IDSEL
PCIAD23
GND
PCIAD22
PCIAD21
VSSPST
GND
PCIAD20
VDD18
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RTL8169S-32
PCIAD19
VDD33
PCIAD18
PCIAD17
PCIAD16
CBEB2
FRAMEB
GND
IRDYB
VDD18
PCIAD1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
NC
VSSPST
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
PCIAD2
VSSPST
GND
TRDYB
DEVSELB
STOPB
PERRB
VDD33
NC
VDD18
PCIAD3
PCIAD4
PCIAD5
PCIAD6
GND
NC
VDD33
PCIAD7
CBEB0
VSSPST
PCIAD8
PCIAD9
SERRB
PAR
CBEB1
VDD18
PCIAD15
GND
VSSPST
PCIAD14
PCIAD13
M66EN
80
81
82
83
PCIAD10
PCIAD11
PCIAD12
VDD33
Figure 1. 128-Pin QFP Pin Assignments
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RTL8169S-32/RTL8169S-64
Datasheet
4.2. 233-Pin TFBGA Pin Assignments
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
A
B
C
D
E
F
RTL8169S-64
G
H
J
K
L
M
N
P
R
T
V
Figure 2. 233-Pin TFBGA Pin Assignments
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Datasheet
5. Pin Descriptions
The following signal type codes are used in the tables:
I: Input.
O: Output
T/S: Tri-State bi-directional input/output pin.
S/T/S: Sustained Tri-State.
O/D: Open Drain.
5.1. Power Management/Isolation
Table 1. Power Management/Isolation
Pin No Description
(128QFP) (233BGA)
Symbol
Type Pin No
PMEB
(PME#)
O/D
I
31
P3
Power Management Event. Open drain, active low.
Used to request a change in the current power management state
and/or to indicate that a power management event has occurred.
ISOLATEB
23
J1
Isolate Pin. Active low.
(ISOLATE#)
Used to isolate the RTL8169S from the PCI bus. The RTL8169S
will not drive its PCI outputs (excluding PME#) and will not sample
its PCI input (including PCIRSTB and PCICLK) as long as the
Isolate pin is asserted.
LANWAKE
O
105
A13
LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3).
This signal is used to inform the motherboard to execute the
wake-up process. The motherboard must support Wake-On-LAN
(WOL). There are 4 choices of output that may be asserted from the
LANWAKE pin (active high, active low, positive pulse, and
negative pulse). We can configure the LANWAKE output via two
CONFIG bits: LWACT (Config1.4) and LWPTN (Config4.2).
LWAKE Output
LWACT
0
1
LWPTN
0
1
Active high
Positive pulse
Active low
Negative pulse
The default output is an active high signal. Once a PME event is
received, the LANWAKE and PMEB assert at the same time if the
LWPME (bit4, CONFIG4) is set to 0. If the LWPME is set to 1, the
LANWAKE asserts only when PMEB asserts and ISOLATEB is
low.
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
5.2. PCI Interface
Table 2. PCI Interface
Symbol
Type
Pin No.
Description
Pin No.
(233BGA)
(128QFP)
PCIADPIN63-32
T/S
T3, R4, U4,
T5, T6, U7,
U8, U9, U11,
U12, U13,
U15, T14,
R12, R15,
U16, U17,
R17, P16,
N16, M17,
M15, K17,
J16, H17,
G17, G15,
F16, E16,
D17, C17,
B17
AD63-32: High 32-bit PCI address and data multiplexed
pins.
Address and Data are multiplexed on the same pins and
provide 32 additional bits. During an address phase (when
using the DAC command and when REQ64B is asserted),
the upper 32-bits of a 64-bit address are transferred;
otherwise, these bits are reserved but are stable and
undetermined. During a data phase, an additional 32-bits of
data are transferred when a 64-bit transaction has been
negotiated by the assertion of REQ64B and ACK64B.
PCIADPIN31-0
T/S
33, 34, 36, T1, T2, U2, AD31-0: Low 32-bit PCI address and data multiplexed pins.
37, 39, 40, R3, T4, U3,
42, 43, 47, R5, U5, T7,
49, 50, 53, T8, T9, T10,
The address phase is the first clock cycle in which
FRAMEB is asserted. During the address phase, AD31-0
contains a physical address (32 bits). For I/O, this is a byte
address, and for configuration and memory, it is a
double-word address. The RTL8169S supports both
big-endian and little-endian byte ordering. Write data is
stable and valid when IRDYB is asserted. Read data is
stable and valid when TRDYB is asserted. Data I is
transferred during those clocks where both IRDYB and
TRDYB are asserted.
55, 57, 58,
T11, R9,
59, 79, 82, T12, U14,
83, 85, 86, L16, K16,
87, 89, 90,
J17, J15,
93, 95, 96, H16, G16,
97, 98, 102, E17, E15,
103, 104
C16, A17,
B16, D15,
A15, C14,
B13, C12
AD16-0: Boot PROM Address Bus. These pins are used to
access up to a 128k-byte flash memory or EPROM.
AD31-24: Boot PROM data bus during Boot PROM mode.
CBEBPIN7-4
CBEBPIN3-0
T/S
T/S
M2, M3, N1, PCI bus command and byte enables multiplexed pins.
R1
During the address phase of a transaction, CBEBPIN7-4
define the bus command. During the data phase,
CBEBPIN7-4 are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which byte
lanes carry meaningful data. CBEBPIN4 applies to byte 4,
and CBEBPIN7 applies to byte 7.
44, 60, 77,
92
R6, T13,
PCI bus command and byte enables multiplexed pins.
L17, D16 During the address phase of a transaction, CBEBPIN3-0
define the bus command. During the data phase,
CBEBPIN3-0 are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which byte
lanes carry meaningful data. CBEBPIN0 applies to byte 0,
and CBEBPIN3 applies to byte 3.
Integrated Gigabit Ethernet Controller (NIC)
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RTL8169S-32/RTL8169S-64
Datasheet
Symbol
Type
Pin No.
(233BGA)
Description
Pin No.
(128QFP)
28
PCICLK
I
M1
PCI Clock. This clock input provides timing for all PCI
transactions and is input for the PCI device. Supports up to a
66MHz PCI clock.
DEVSELB
FRAMEB
S/T/S
S/T/S
68
61
T16
Device Select. As a bus master, the RTL8169S samples this
signal to insure that a PCI target recognizes the destination
address for the data transfer. As a target, the RTL8169S
asserts this signal low when it recognizes its target address
after FRAMEB is asserted.
Cycle Frame. As a bus master, this pin indicates the
beginning and duration of an access. FRAMEB is asserted
low to indicate the start of a bus transaction. While
FRAMEB is asserted, data transfer continues. When
FRAMEB is de-asserted, the transaction is in the final data
phase.
R13
As a target, the device monitors this signal before decoding
the address to check if the current transaction is addressed to
it.
GNTB
I
29
N2
Grant. This signal is asserted low to indicate to the
RTL8169S that the central arbiter has granted the ownership
of the bus to the RTL8169S. This input is used when the
device is acting as a bus master.
REQB
IDSEL
T/S
I
30
46
P2
Request. The RTL8169S will assert this signal low to
request the ownership of the bus from the central arbiter.
Initialization Device Select. This pin allows the device to
identify when configuration read/write transactions are
intended for it.
U6
INTAB
IRDYB
O/D
25
63
K3
Interrupt A. Used to request an interrupt. It is asserted low
when an interrupt condition occurs, as defined by the
Interrupt Status, Interrupt Mask.
S/T/S
R14
Initiator Ready. This indicates the initiating agent’s ability
to complete the current data phase of the transaction.
As a bus master, this signal will be asserted low when the
device is ready to complete the current data phase
transaction. This signal is used in conjunction with the
TRDYB signal. Data transaction takes place at the rising
edge of CLK when both IRDYB and TRDYB are asserted
low. As a target, this signal indicates that the master has put
data on the bus.
TRDYB
S/T/S
67
R16
Target Ready. This indicates the target agent’s ability to
complete the current phase of the transaction.
As a bus master, this signal indicates that the target is ready
for the data during write operations, or is ready to provide
the data during read operations. As a target, this signal will
be asserted low when the (slave) device is ready to complete
the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes
place at the rising edge of CLK when both IRDYB and
TRDYB are asserted low.
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Datasheet
Symbol
Type
Pin No.
(233BGA)
Description
Pin No.
(128QFP)
76
PAR
T/S
M16
Parity. This signal indicates even parity across
PCIADPIN31-0 and CBEB3-0 including the PAR pin. PAR
is stable and valid one clock after each address phase. For
data phase, PAR is stable and valid one clock after either
IRDYB is asserted on a write transaction or TRDYB is
asserted on a read transaction. Once PAR is valid, it remains
valid until one clock after the completion of the current data
phase. As a bus master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read
data phases.
M66EN
PERRB
SERRB
I
88
70
75
F17
P17
N15
66MHZ_ENABLE. This pin indicates to the device whether
the bus segment is operating at 66 or 33MHz. When this pin
(active high) is asserted, the current PCI bus segment that
the device resides on operates in 66MHz mode. If this pin is
de-asserted, the current PCI bus segment operates in
33MHz mode.
Parity Error. This pin is used to report data parity errors
during all PCI transactions except a Special Cycle. PERRB
is driven active (low) two clocks after a data parity error is
detected by the device receiving data, and the minimum
duration of PERRB is one clock for each data phase with
parity error detected.
S/T/S
O/D
System Error. If an address parity error is detected and
Configuration Space Status register bit 15 (detected parity
error) is enabled, the device asserts the SERRB pin low and
bit 14 of the Status register in Configuration Space.
STOPB
S/T/S
I
69
27
T17
L3
Stop. Indicates that the current target is requesting the
master to stop the current transaction.
Reset. When PCIRSTB is asserted low, the device performs
an internal system hardware reset. PCIRSTB must be held
for a minimum period of 120 ns.
PCIRSTB
ACK64B
S/T/S
K2
Acknowledge 64-bit Transfer. When actively driven by a
device that has positively decoded its address as the target
of the current access, indicates the target is willing to
transfer data using 64 bits. ACK64B has the same timing as
DEVSELB.
REQ64B
PAR64
S/T/S
T/S
L2
R2
Request 64-bit Transfer. When asserted by the current bus
master, indicates it desires to transfer data using 64 bits.
REQ64B also has the same timing as FRAMEB.
Parity Upper DWORD. An even parity bit that protects
AD[64:32] and C/BE[7:4]. PAR64 must be valid one clock
after each address phase on any transaction in which
REQ64B is asserted.
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Datasheet
5.3. EEPROM
Table 3. EEPROM
Symbol
Type
Pin No
Pin No
Description
(128QFP) (233BGA)
EESK
O
111
109
A11
B11
Serial data clock.
EEDI/AUX
O/I
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial
power-on.
This pin should be connected to EEPROM. To support wakeup
from ACPI D3cold or APM power-down, this pin must be pulled
high to aux. power via a resistor. If this pin is not pulled high to
Aux. Power, the RTL8169S assumes that no Aux. Power exists.
EEDO
I
108
106
A12
B12
Input from serial data output pin of EEPROM.
EECS/BROM
CSB
O
EECS: EEPROM chip select
BROMCSB: This is the chip select signal of the Boot PROM.
5.4. Transceiver Interface
Table 4. Transceiver Interface
Symbol
Type
Pin No
Pin No
Description
(128QFP) (233BGA)
MDI[0]+
I/O
I/O
1
2
C2
D1
In MDI mode, this is the first pair in 1000Base-T, i.e. the
BI_DA+/- pair, and is the transmit pair in 10Base-T and
100Base-TX.
MDI[0]−
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and
is the receive pair in 10Base-T and 100Base-TX.
MDI[1]+
I/O
I/O
5
6
D2
E1
In MDI mode, this is the second pair in 1000Base-T, i.e. the
BI_DB+/- pair, and is the transmit pair in 10Base-T and
100Base-TX.
MDI[1]−
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and
is the transmit pair in 10Base-T and 100Base-TX.
MDI[2]+
I/O
I/O
14
15
F1
In MDI mode, this is the third pair in 1000Base-T, i.e. the
BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
MDI[2]−
G2
MDI[3]+
I/O
I/O
18
19
G1
H2
In MDI mode, this is the fourth pair in 1000Base-T, i.e. the
BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
MDI[3]−
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Datasheet
5.5. Clock
Table 5. Clock
Symbol
Type
Pin No
Pin No
Description
(128QFP) (233BGA)
Xtal1
Xtal2
I
121
122
A5
A6
Input of 25MHz clock reference.
output of 25MHz clock reference.
O
5.6. Regulator & Reference
Table 6. Regulator & Reference
Symbol
Type
Pin No
Pin No
Description
(128QFP) (233BGA)
CTRL25
CTRL18
RSET
O
O
I
8
E4
B3
D4
Regulator Control. Voltage control to external 2.5V regulator.
Regulator Control. Voltage control to external 1.8V regulator.
Reference. External Resistor Reference.
125
127
5.7. LEDs
Table 7. LEDs
Symbol
Type Pin No
Pin No Description
(128QFP) (233BGA)
LED0/
BROMO
EB
O
117
C10
LEDS1-0
LED0
00
01
10
11
Tx/Rx
ACT(Tx/Rx)
Tx
LINK10/
ACT
LED1
LED2
LED3
O
O
O
115
114
113
D10
C11
D9
LED1
LED2
LED3
LINK1
00
LINK10/100/1
000
LINK10/100/1
000
LINK100/
ACT
LINK1
0
FULL
Rx
FULL
LINK1
000
-
FULL
LINK1000/A
CT
BROMOEB: This enables the output buffer of the Boot PROM or Flash
memory during a read operation.
Note 1: During power down mode, the LED signals are logic high.
Note 2: LEDS1-0’s initial value comes from 93C46/93C56.
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Datasheet
5.8. Power & Ground
Table 8. Power & Ground
Symbol
Type
Pin No
(128QFP)
126
Pin No
(233BGA)
P12
Description
VDD18A
VDD18
Power
Power
Analog 1.8V power supply.
Digital 1.8V power supply.
24, 32, 45, 54,
64, 78, 99, 110,
116
C5, C7, D8, F14,
H4, K14, L4, P6, P9
VDD33
Power
Power
26, 41, 56, 71, B10, C8, C9, F15, H1, Digital 3.3V power supply.
84, 94, 107
H15, J2, J3, K15,
L15, R7, R8, R10,
R11
GND/VSSPST
21, 22, 35, 38, D11, D12, D13, D14, Digital Ground
48, 51, 52, 62, E14, G7, G8, G9,
66, 73, 80, 81, G10, G11, G14, H7,
91, 100, 101,
112, 118, 119
H8, H9, H10, H11,
H14, J4, J7, J8, J9,
J10, J11, J14, K4, K7,
K8, K9, K10, K11,
L7, L8, L9, L10, L11,
L14, M4, M14, N4,
N14, P4, P5, P7, P8,
P10, P11, P13, P14
AVDDL
AVDDH
VSS
Power
Power
3, 7, 16, 20
10, 120
C3, D3, G3, H3
Analog 2.5V power supply.
Analog 3.3V power supply.
E2, C6
Power 4, 9, 13, 17, 123, F4, G4, C4, D5, D6, Analog Ground
124, 128 D7, E3
5.9. NC (Not Connected)
Table 9. NC (Not Connected)
Symbol
Type
Pin No
Pin No
Description
(128QFP)
(233BGA)
NC
11, 12, 65, 72,
74
A1, A2, A3, A4, A7, Not Connected.
A8, A9, A10, A14, A16,
B1, B2, B4, B5, B6, B7,
B8, B9, B14, B15, C1,
C13, C15, F2, F3, K1,
L1, N3, N17, P1, P15,
T15, U1, U10
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Datasheet
6. Functional Description
6.1. Transceiver
6.1.1.
Transmitter
In 10M mode, the Tx MAC retrieves packet data from the Tx Buffer Manager and sends it out through the
transmitting physical layer interface. The transmit 4-bit nibbles (TXD[3:0]) clocked at 2.5Mhz (TXC), are
serialized into 10Mbps serial data. Then, the 10Mbps serial data is converted into a Manchester-encoded
data stream and is transmitted onto the media by the DAC converter.
In 100M mode, the transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25Mhz (TXC), are
converted into 5B symbol code via 4B/5B coding technology, scrambling, and serializing before being
converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signal is passed to the MLT3 encoder,
then to the DAC converter for transmission onto the media.
In 1000M mode, the RTL8169S’s PCS layer receives data bytes from the MAC through the GMII interface
and performs the generation of continuous code-groups through 4D-PAM5 coding technology. Then, those
code groups are passed through waveform shaping filter to minimize EMI effect, and are transmitted onto
the 4-pair CAT5 cable at 125MBaud/s through DAC converter.
6.1.2.
Receiver
In MII (10Mbps) mode, the received differential signal is converted into a Manchester-encoded data
stream. The stream is processed with a Manchester decoder, and is de-serialized into 4-bit wide nibbles.
The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz. In 100Mbps mode, the
MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery,
MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and then is presented to the MII interface in 4-bit
wide nibbles at a clock speed of 25MHz.
In GMII mode, the input signal from the media first passes through the on-chip sophisticated hybrid circuit
to subtract the transmitted signal from the input signal for effective reduction of near-end echo.
Afterwards, the received signal is processed with adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. Then, the 8-bit wide data is recovered and is sent to the GMII interface at a clock speed of
125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the
Rx Buffer Manager.
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Datasheet
6.2. MAC
The RTL8169S supports new descriptor-based buffer management that significantly reduces host CPU
utilization and is particularly effective in server applications. The new buffer management algorithm
provides Microsoft Large-Send offload, IP checksum offload, TCP checksum offload, UDP checksum
offload, and IEEE 802.1P, 802.1Q VLAN tagging capabilities. The device supports up to 1024
consecutive descriptors in memory for transmit and receive separately, which means there might be 3
descriptor rings, one a high priority transmit descriptor ring, another a normal priority transmit descriptor
ring, and the other a receive descriptor ring. Each descriptor ring may consist of up to 1024 consecutive
descriptors. Each descriptor consists of 4 consecutive double words. The start address of each descriptor
ring should be 256-byte aligned. Software must pre-allocate enough buffers and configure all descriptor
rings before transmitting and/or receiving packets. Descriptors can be chained to form a packet in both Tx
and Rx. Refer to the Realtek RTL8169S Programming Guide for detailed information. Any Tx buffers
pointed to by the Tx descriptors should be at least 4 bytes.
The RTL8169S will automatically pad any packets less than 64 bytes to 64-bytes long (including a 4-byte
CRC) before transmitting that packet onto the network medium. If a packet consists of two or more
descriptors, then the descriptors in command mode should have the same configuration, except EOR, FS,
LS bits.
6.3. Next Page
If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the
two link partners. Users can set Reg4.15 to 1 to exchange extra Next Pages via Reg7 and Reg8 as defined
in IEEE 802.3ab.
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Datasheet
6.4. MII/GMII Interface
6.4.1.
MII
The RTL8169S supports 10Mbps and 100Mbps link operation. During the operation, the PHY
communicates with the MAC through the MII as defined in the IEEE 802.3 (clause 22) specifications. The
MII consists of a transmit data interface (TxEN, TxER, TXD[3:0], and TxCLK), a receive data interface
(RxDV, RxER, RXD[3:0], and RxCLK), two status signals (CRS and COL) and a management interface
(MDC and MDIO). In this mode of operation, both Transmit and Receive clocks are supplied by the PHY.
6.4.2.
GMII
In 1000Base-T mode, the GMII interface is selected, the 125MHz transmit clock is expected on GTXCLK,
TXCLK sources 25MHz, 2.5MHz, or 0MHz clock depending on the operation mode, and RXCLK sources
the 125MHz receive clock.
6.5. LEDs
The RTL8169S supports four LED signals in four different configurable operation modes. The modes are
shown in Pin Descriptions, page 5.
6.5.1.
Link Monitor
The Link Monitor senses a link, such as LINK10, LINK100, LINK1000, LINK10/100/1000. Whenever a
link is established, the specific link LED pin is driven low. Once disconnected, the link LED pin is driven
high indicating that no network connection exists.
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Datasheet
6.5.2.
RX LED
In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring.
Power On
LED = High
No
Receiving
Packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 3. RX LED
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Datasheet
6.5.3.
TX LED
In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring.
Power On
LED = High
No
Transmitting
Packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 4. TX LED
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Datasheet
6.5.4.
TX/RX LED
In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is
occurring.
Power On
LED = High
No
Tx/Rx Packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 5. TX/RX LED
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Datasheet
6.5.5.
LINK/ACT LED
In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8169S is linked and
operating properly. When this LED is high for extended periods, it indicates that a link problem exists.
Power On
LED = High
No
Link?
Yes
LED = Low
No
Tx/Rx packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 6. LINK/ACT LED
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Datasheet
6.6. Flash/EEPROM Interface
The Flash interface consists of address bus MA(16:0) and data bus MD(7:0) which share the pin with PCI
interface AD(16:0) and AD(32:24), respectively. It also consists of several control signals: WEB,
OEB(LED0), CSB(EECS). The RTL8169S supports the attachment of an external EEPROM. The 93C46
is a 1K-bit EEPROM (the 93C56 is a 2K-bit EEPROM).
The EEPROM interface provides the ability for the RTL8169S to read from and write data to an external
serial EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space
and I/O space to be overridden following a reboot or software EEPROM auto load command. The
RTL8169S will auto load values from the EEPROM. If the EEPROM is not present, the RTL8169S
initialization uses default values for the appropriate Configuration and Operational Registers. Software can
read and write to the EEPROM using “bit-bang” accesses via the 9346CR Register. The interface consists
of EESK, EECS, EEDO, and EEDI.
Table 10. Flash/EEPROM Interface
Flash
Description
MA[16:0]
(PCIAD16:0)
Boot PROM Address Bus. These pins are used to access up to a 128k-byte flash
memory or EEPROM.
MD7-0(PCIAD31:24)
CSB(EECS/BROMCSB)
Boot PROM data bus when in Boot PROM mode.
The chip select signal of the Boot PROM.
OEB(LED0/BROMOEB) Enables the output buffer of the Boot PROM or Flash memory during a read operation.
EEPROM
EECS
EESK
Description
93C46 (93C56) chip select
EEPROM serial data clock
EEDI/Aux
Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on.
This pin should be connected to Boot PROM. To support wakeup from ACPI D3cold
or APM power-down, this pin must be pulled high to aux. power via a resistor. If this
pin is not pulled high to Aux. Power, the RTL8169S assumes that no Aux. Power
exists.
EEDO
Output data bus
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Datasheet
6.7. Power Management
The RTL8169S is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and
Network Device Class Power Management Reference Specification (V1.0a), such as to support an
OS-directed Power Management (OSPM) environment.
The RTL8169S can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify
the system via PME# when such a packet or event occurs. Then, the whole system can be restored to a
normal state to process incoming jobs.
When the RTL8169S is in power down mode (D1 ~ D3):
•
The Rx state machine is stopped, and the RTL8169S monitors the network for wakeup events such as a
Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power
down mode, the RTL8169S will not reflect the status of any incoming packets in the ISR register and
will not receive any packets into the Rx FIFO buffer.
•
The FIFO status and packets that have already been received into the Rx FIFO before entering power
down mode are held by the RTL8169S.
•
•
Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
After restoration to a D0 state, the RTL8169S transfers data that was not moved into the Tx FIFO buffer
during power down mode. Packets that were not transmitted completely last time are re-transmitted.
The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI
configuration space depend on the existence of Aux power (bit15, PMC) = 1.
If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0's.
Example:
If EEPROM D3c_support_PME = 1:
•
•
If Aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C2 F7, then PCI PMC = C2 F7).
If Aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the
above 4 bits are all 0’s (if EEPROM PMC = C2 F7, the PCI PMC = 02 76).
In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM
PMC be set to C2 F7 (Realtek EEPROM default value).
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If EEPROM D3c_support_PME = 0:
•
•
If Aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C2 77, then PCI PMC = C2 77).
If Aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the
above 4 bits are all 0’s (if EEPROM PMC = C2 77, then PCI PMC = 02 76).
In the above case, if wakeup support is not desired when main power is off, it is suggested that the
EEPROM PMC be set to 02 76.
Link Wakeup occurs only when the following conditions are met:
•
The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be
asserted in the current power state.
•
The Link status is re-established.
Magic Packet Wakeup occurs only when the following conditions are met:
•
The destination address of the received Magic Packet is acceptable to the RTL8169S, e.g. a broadcast,
multicast, or unicast packet addressed to the current RTL8169S adapter.
The received Magic Packet does not contain a CRC error.
•
•
The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be
asserted in the current power state.
•
The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in
any part of a valid (Fast) Ethernet packet.
A Wakeup Frame event occurs only when the following conditions are met:
•
The destination address of the received Wakeup Frame is acceptable to the RTL8110S, e.g. a broadcast,
multicast, or unicast address to the current RTL8110S adapter.
•
•
•
The received Wakeup Frame does not contain a CRC error.
The PMEn bit (CONFIG1#0) is set to 1.
The 16-bit CRC* of the received Wakeup Frame matches with the 16-bit CRC* of the sample Wakeup
Frame pattern given by the local machine’s OS. Or, the RTL8169S is configured to allow direct packet
wakeup, e.g. a broadcast, multicast, or unicast network packet.
*16-bit CRC: The RTL8169S supports two normal wakeup frames (covering 64 mask bytes from offset 0
to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from
offset 0 to 127 of any incoming network packet).
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Datasheet
The PME# signal is asserted only when the following conditions are met:
1. The PMEn bit (bit0, CONFIG1) is set to 1.
2. The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
3. The RTL8169S may assert PME# in the current power state or in isolation state, depending on the
PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
4. A Magic Packet, LinkUp, or Wakeup Frame has been received.
5. Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears
this bit and causes the RTL8169S to stop asserting a PME# (if enabled).
When the device is in power down mode, e.g. D1-D3, the IO, MEM, and Boot ROM spaces are all
disabled. After a RST# assertion, the device’s power state is restored to D0 automatically if the original
power state was D3cold. There is no hardware delay at the device’s power state transition. When in ACPI
mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default
setting of the PMC register auto loaded from EEPROM). The setting may be changed from the EEPROM,
if required). The RTL8169S also supports the legacy LAN WAKE-UP function. The LWAKE pin is used
to notify legacy motherboards to execute the wake-up process whenever the device receives a wakeup
event, such as Magic Packet.
The LWAKE signal is asserted according to the following settings:
1. LWPME bit (bit4, CONFIG4):
•
•
LWAKE can only be asserted when PMEB is asserted and ISOLATEB is low.
LWAKE is asserted whenever a wakeup event occurs.
2. Bit1 of DELAY byte (offset 1Fh, EEPROM):
•
•
LWAKE signal is enabled.
LWAKE signal is disabled.
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Datasheet
7. Characteristics
7.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the
device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise
specified.
Table 11. Absolute Maximum Ratings
Description/Symbol
Minimum
-0.5
Maximum
Unit
V
V
V
V
Supply Voltage (VDD33, AVDDH)
Supply Voltage (VDD25)
Supply Voltage (VDD18, VDD18A)
Input Voltage (DCinput)
Output Voltage (DCoutput)
Storage Temperature
4
3
2
-0.5
-0.5
-0.5
-0.5
VDD33 + 0.5
VDD33 + 0.5
+125
V
°C
-55
7.2. Recommended Operating Conditions
Table 12. Recommended Operating Conditions
Description
Pins
Minimum
Typical
Maximum
Unit
Supply Voltage VDD
VDD33,
AVDDH
3.0
3.3
3.6
V
VDD25
VDD18,
VDD18A
2.25
1.6
0
2.5
1.8
2.75
2.0
V
V
Ambient Temperature TA
Maximum Junction
Temperature
70
125
°C
°C
7.3. Crystal Requirements
Table 13. Crystal Requirements
Description/Condition
Minimum
Typical
Maximum Unit
Symbol
Fref
Parallel resonant crystal reference frequency,
fundamental mode, AT-cut type.
25
MHz
Fref
Stability
Fref Tolerance
Parallel resonant crystal frequency stability,
fundamental mode, AT-cut type. Ta=25°C.
Parallel resonant crystal frequency tolerance,
fundamental mode, AT-cut type.
Ta=-20°C ~+70°C.
-50
-30
+50
+30
ppm
ppm
Fref
Reference clock input duty cycle.
40
60
%
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
Description/Condition
Load Capacitance.
Equivalent Series Resistance.
Drive Level.
Minimum
Typical
Maximum Unit
Symbol
Duty Cycle
CL
ESR
DL
27
10
pF
Ω
0.5
mW
7.4. Thermal Characteristics
Table 14. Thermal Characteristics
Parameter
Minimum
Maximum
Units
Storage temperature
Operating temperature
-55
0
+125
70
°C
°C
7.5. DC Characteristics
Table 15. DC Characteristics
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VDD33
3.3V Supply Voltage
3.0
3.3
3.6
V
VDD18,
1.8V Supply Voltage
1.6
2.25
1.8
2.5
2.0
V
VDD18A
2.75
VDD25
2.5V Supply Voltage
V
V
Minimum High Level
Output Voltage
V
I
0.9 * Vcc
Vcc
oh
oh = -8mA
Maximum Low Level
Output Voltage
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
V
ol
I
0.1 * Vcc
Vcc+0.5
0.3 * Vcc
V
V
V
ol = 8mA
V
ih
0.5 * Vcc
-0.5
V
il
V
V
in = cc or
I
Input Current
-1.0
-10
1.0
10
uA
uA
in
GND
V
V
out = cc or
Tri-State Output
Leakage Current
I
oz
GND
At 1Gbps with
heavy network
traffic
Average Operating
Supply Current from
3.3V
Icc33
170
660
mA
mA
At 1Gbps with
heavy network
traffic
Average Operating
Supply Current from
1.8V
I
cc18
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
7.6. AC Characteristics
7.6.1.
Serial EEPROM Interface Timing
93C46(64*16)/93C56(128*16)
EESK
tcs
EECS
EEDI
(Read)
(Read)
1
1
0
An
A2 A1 A0
0
Dn
D1 D0
EEDO
High Impedance
EESK
EECS
EEDI
tcs
...
...
(Write)
1
0
1
An
A0 Dn
D0
(Write)
BUSY
READY
EEDO
High Impedance
twp
tsk
EESK
tskh
tskl
tcsh
tcss
EECS
EEDI
tdis
tdih
tdos
tdoh
(Read)
EEDO
EEDO
tsv
STATUS VALID
(Program)
Figure 7. Serial EEPROM Interface Timing
Table 16. EEPROM Access Timing Parameters
Symbol
Parameter
EEPROM Type
Min.
Max.
Unit
tcs
Minimum CS Low Time
9346/9356
1000/250
ns
twp
tsk
tskh
tskl
tcss
Write Cycle Time
SK Clock Cycle Time
SK High Time
SK Low Time
CS Setup Time
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
10/10
ms
µs
ns
ns
ns
4/1
1000/500
1000/250
200/50
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Datasheet
Symbol
tcsh
Parameter
CS Hold Time
DI Setup Time
DI Hold Time
DO Setup Time
DO Hold Time
CS to Status Valid
EEPROM Type
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
Min.
0/0
400/50
400/100
2000/500
Max.
Unit
ns
ns
ns
ns
tdis
tdih
tdos
tdoh
tsv
2000/500
1000/500
ns
ns
7.7. PCI Bus Operation Timing
7.7.1.
PCI Bus Timing Parameters
Table 17. PCI Bus Timing Parameters
66MHz
33MHz
Symbol
Parameter
Min
Max
Min
Symbol
Parameter
T val
CLK to Signal Valid
Delay-bused signals
2
6
2
11
ns
T val
(ptp)
T on
T off
T su
CLK to Signal Valid
Delay-point to point
Float to Active Delay
Active to Float Delay
Input Setup Time to
CLK-bused signals
2
2
6
2
2
12
28
ns
ns
ns
ns
14
3
7
T su (ptp)
T h
Input Setup Time to
CLK-point to point
Input Hold Time from
CLK
5
10
0
ns
ns
0
T rst
Reset active time after
power stable
1
1
ms
T rst-clk
T rst-off
T rrsu
T rrh
Reset active time after
CLK STABLE
Reset Active to Output
Float delay
REQB to REQ64B
Setup Time
RSTB to REQ64B Hold
Time
RSTB High to First
configuration Access
RSTB High to First
FRAMEB assertion
100
100
µs
40
50
40
50
ns
10*Tcyc
10*Tcyc
ns
0
2^25
5
0
2^25
5
ns
T rhfa
T rhff
clocks
clocks
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Datasheet
V_th
V_tl
V_test
T_val
CLK
OUTPUT
DELAY
V_trise, V_tfall
Tri-State
OUTPUT
V_test
V_test
T_on
T_off
Figure 8. Output Timing Measurement Conditions
V_th
V_tl
V_test
CLK
T_su
inputs valid
T_h
V_th
V_tl
V_test
V_test
V_max
INPUT
Figure 9. Input Timing Measurement Conditions
Table 18. Measurement Condition Parameters
Symbol
Level
0.6Vcc
0.2Vcc
0.4Vcc
0.285Vcc
0.615Vcc
0.4Vcc
1
Units
V
Vth
Vtf
V
Vtest
Vtrise
V
V
Vtfall
V
Vmax
V
Input Signal Edge Rate
V/ns
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Datasheet
7.7.2.
PCI Clock Specification
T_high
T_low
0.6Vcc
0.5Vcc
0.4Vcc, peak-to-peak
(minimum)
0.4Vcc
0.3Vcc
0.2Vcc
T_cyc
Figure 10. 3.3V Clock Waveform
V_ih
V_test
CLK (@ Device #1)
CLK (@ Device #2)
T_skew
V_il
T_skew
V_ih
T_skew
V_test
V_il
Figure 11. Clock Skew Diagram
Table 19. Clock and Reset Specifications
66MHz 33MHz
Symbol
Parameter
Min
15
6
6
1.5
50
Max
30
Min
30
11
11
1
Symbol
Parameter
Tcyc
Thigh
Tlow
--
--
Tskew
CLK Cycle Time
CLK High Time
CLK Low Time
CLK Slew Rate
RST# Slew Rate
CLK Skew
∞
ns
ns
ns
V/ns
mV/ns
ns
4
-
1
4
-
2
50
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Datasheet
7.7.3.
PCI Transactions
CLK
1
2
3
4
5
6
7
8
9
10
FRAMEB
AD31-0
ADDRESS
BUS CMD
DATA
BE3-0B
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 12. I/O Read
CLK
FRAMEB
AD31-0
1
2
3
4
5
6
7
8
9
10
ADDRESS
BUS CMD
DATA
BE3-0B
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 13. I/O Write
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Datasheet
CLK
FRAMEB
IDSEL
1
2
3
4
5
6
7
8
9
10
ADDRESS
BUS CMD
DATA
AD31-0
BE3-0B
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 14. Configuration Read
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Datasheet
CLK
FRAMEB
IDSEL
1
2
3
4
5
6
7
8
9
10
ADDRESS
BUS CMD
DATA
AD31-0
BE3-0B
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 15. Configuration Write
CLK
REQB-A
REQB-B
GNTB-A
GNTB-B
FRAMEB
AD
1
2
3
4
5
6
7
8
9
10
ADDRESS
DATA
ADDRESS
DATA
Figure 16. Bus Arbitration
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
AD31-0
1
2
3
4
5
6
7
8
9
DATA-1
DATA-2
DATA-3
ADDRESS
BUS CMD
BE3-0B
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 17. Memory Read below 4GB (32-bit address, 32-bit data; 32-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
AD31-0
1
2
3
4
5
6
7
8
9
ADDRESS
DATA-1
DATA-2
DATA-3
BUS CMD BE3-0B-1 BE3-0B-2
BE3-0B-3
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 18. Memory Write below 4GB (32-bit address, 32-bit data; 32-bit slot)
CLK
FRAMEB
IRDYB
1
2
3
4
5
6
7
8
9
TRDYB
STOPB
DEVSELB
Figure 19. Target Initiated Termination - Disconnect
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Datasheet
CLK
FRAMEB
IRDYB
1
2
3
4
5
6
7
8
9
TRDYB
STOPB
DEVSELB
Figure 20. Target Initiated Termination - Abort
CLK
FRAMEB
IRDYB
1
2
3
4
5
6
7
8
9
TRDYB
NO RESPONSE
ACKNOWLEDGE
DEVSELB
FAST
MED
SLOW
SUB
Figure 21. Master Initiated Termination - Abort
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Datasheet
CLK
FRAMEB
AD
1
2
3
4
5
6
7
8
9
10
ADDRESS
BUS CMD
DATA
BE#
ADDRESS DATA
BUS CMD
BE#
C/BE#
PAR/PAR64
SERR#
PERR#
Figure 22. Parity Operation – One Example
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Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
DATA-1
DATA-2
DATA-3
ADDRESS
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
BE3-0B
BUS CMD
BE7-4B
TRDYB
DEVSELB
ACK64B
Figure 23. Memory Read Below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
ADDRESS
DATA-1
DATA-2
DATA-2
DATA-3
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
BUS CMD BE3-0B-1 BE3-0B-2
BE7-4B-1
BE3-0B-3
TRDYB
DEVSELB
ACK64B
Figure 24. Memory Write below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
DATA-1
DATA-2
DATA-3
DATA-4
DATA-5
DATA-6
ADDRESS
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
BE3-0B
BUS CMD
BE7-4B
TRDYB
DEVSELB
ACK64B
Figure 25. Memory Read below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
ADDRESS
DATA-1
DATA-2
DATA-3
DATA-4
DATA-5
DATA-6
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
BUS CMD BE3-0B-1 BE3-0B-2
BE7-4B-1 BE7-4B-2
BE3-0B-3
BE7-4B-3
TRDYB
DEVSELB
ACK64B
Figure 26. Memory Write below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
AD31-0
1
2
3
4
5
6
7
8
9
10
HI-ADDR
LO-ADDR
DAC CMD
DATA-1
DATA-2
DATA-3
BUS CMD
BE3-0B
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 27. Memory Read above 4GB (DAC, 64-bit address, 32-bit data; 32-bit slot)
CLK
1
2
3
4
5
6
7
8
9
10
FRAMEB
AD31-0
LO-ADDR HI-ADDR
DATA-1
DATA-2
DATA-3
BUS CMD
DAC CMD
BE3-0B-1 BE3-0B-2
BE3-0B-3
C/BE3-0B
IRDYB
TRDYB
DEVSELB
Figure 28. Memory Write above 4GB (DAC, 64-bit address, 32-bit data; 32-bit slot)
Integrated Gigabit Ethernet Controller (NIC) 40 Track ID: JATR-1076-21 Rev. 1.7
RTL8169S-32/RTL8169S-64
Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
10
HI-ADDR
LO-ADDR
DATA-1
DATA-2
DATA-3
HI-ADDR
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
DAC CMD
BUS CMD
BE3-0B
BUS CMD
BE7-4B
TRDYB
DEVSELB
ACK64B
Figure 29. Memory Read above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
10
LO-ADDR HI-ADDR
HI-ADDR
DATA-1
DATA-2
DATA-2
DATA-3
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
BUS CMD
DAC CMD
BE3-0B-1 BE3-0B-2
BE7-4B-1
BE3-0B-3
BUS CMD
TRDYB
DEVSELB
ACK64B
Figure 30. Memory Write above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
10
LO-ADDR HI-ADDR
HI-ADDR
DATA-1
DATA-2
DATA-3
DATA-4
DATA-5
DATA-6
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
DAC CMD BUS CMD
BUS CMD
BE3-0B
BE7-4B
TRDYB
DEVSELB
ACK64B
Figure 31. Memory Read above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Track ID: JATR-1076-21 Rev. 1.7
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Datasheet
CLK
FRAMEB
REQ64B
AD31-0
1
2
3
4
5
6
7
8
9
10
HI-ADDR
LO-ADDR
DATA-1
DATA-2
DATA-3
DATA-4
DATA-5
DATA-6
HI-ADDR
AD63-32
C/BE3-0B
C/BE7-4B
IRDYB
DAC CMD
BUS CMD BE3-0B-1 BE3-0B-2
BE3-0B-3
BE7-4B-3
BUS CMD
BE7-4B-1 BE7-4B-2
TRDYB
DEVSELB
ACK64B
Figure 32. Memory Write above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot)
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
8. Mechanical Dimensions
8.1. 128-Pin QFP Mechanical Dimensions
See the Mechanical Dimensions notes on the next page.
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Datasheet
8.2. Notes for 128-Pin QFP Dimensions
Notes:
Symbol Dimensions in inches
Min Typical Max
Dimensions in mm
Min Typical Max
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar rotrusion/intrusion.
3. Controlling dimension: Millimeter
-
-
0.134
-
-
3.40
0.91
3.10
A
0.004 0.010 0.036
0.102 0.112 0.122
0.10
2.60
0.25
2.85
A1
A2
4. General appearance spec. Should be based on final
visual inspection.
b
c
0.005 0.009 0.013
0.002 0.006 0.010
0.12
0.05
0.22
0.15
0.32
0.25
0.541 0.551 0.561 13.75 14.00 14.25
0.778 0.787 0.797 19.75 20.00 20.25
TITLE: 128 QFP (14x20 mm ) PACKAGE OUTLINE
-CU L/F, FOOTPRINT 3.2 mm
D
E
0.010 0.020 0.030
0.25
0.5
0.75
LEADFRAME MATERIAL
e
0.665 0.677 0.689 16.90 17.20 17.50
0.902 0.913 0.925 22.90 23.20 23.50
APPROVE
CHECK
DOC. NO.
VERSION
PAGE
HD
HE
L
0.027 0.035 0.043
0.053 0.063 0.073
0.68
1.35
-
0.88
1.08
1.85
0.10
12°
1.60
DWG NO.
DATE
Q128 - 1
L1
y
-
-
-
0.004
12°
-
-
0°
0°
θ
REALTEK SEMICONDUCTOR CORP.
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
8.3. 233-PIN TFBGA Mechanical Dimensions
See the Mechanical Dimensions notes on the next page.
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
8.4. Notes for 233-Pin TFBGA Dimensions
Integrated Gigabit Ethernet Controller (NIC)
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Datasheet
9. Ordering Information
Table 20. Ordering Information
Part number
RTL8169S-32
RTL8169S-64
Package
128-pin QFP
233-pin TFBGA
Status
Realtek Semiconductor Corp.
Headquarters
No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
Integrated Gigabit Ethernet Controller (NIC)
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Track ID: JATR-1076-21 Rev. 1.7
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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