S1D15606D02B [ETC]
Single-chip dot matrix liquid crystal display drivers; 单芯片点阵液晶显示器的驱动
| 型号： | S1D15606D02B |
| 厂家： | 
ETC |
| 描述： | Single-chip dot matrix liquid crystal display drivers |
| 文件： | 总87页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8. S1D15605 Series
Rev. 2.4a
Contents
1. DESCRIPTION ................................................................................................................................................8-1
2. FEATURES......................................................................................................................................................8-1
3. BLOCK DIAGRAM........................................................................................................................................... 8-3
4. PAD .................................................................................................................................................................8-4
5. PIN DESCRIPTIONS .....................................................................................................................................8-20
6. DESCRIPTION OF FUNCTIONS ..................................................................................................................8-24
7. COMMANDS .................................................................................................................................................8-49
8. COMMAND DESCRIPTION ..........................................................................................................................8-58
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................8-64
10. DC CHARACTERISTICS...............................................................................................................................8-65
11. TIMING CHARACTERISTICS .......................................................................................................................8-73
12. THE MPU INTERFACE (REFERENCE EXAMPLES) ...................................................................................8-81
13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE).....................................................8-82
14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) ..................................................8-83
15. A SAMPLE TCP PIN ASSIGNMENT .............................................................................................................8-84
16. EXTERNAL VIEW OF TCP PINS ..................................................................................................................8-85
– i –
Rev. 2.4a
S1D15605 Series
• High-speed 8-bit MPU interface (The chip can be
connected directly to the both the 80x86 series MPUs
and the 68000 series MPUs)
/Serial interfaces are supported.
• Abundant command functions
1. DESCRIPTION
The S1D15605 Series is a series of single-chip dot matrix
liquid crystal display drivers that can be connected
directly to a microprocessor bus. 8-bit parallel or serial
display data sent from the microprocessor is stored in
the internal display data RAM and the chip generates a
liquid crystal drive signal independent of the micro-
Display data Read/Write, display ON/OFF, Normal/
Reverse display mode, page address set, display start
line set, column address set, status read, display all
points ON/OFF, LCD bias set, electronic volume,
read/modify/write, segment driver direction select,
power saver, static indicator, common output status
select, V5 voltage regulation internal resistor ratio
set.
processor. Because the chips in the S1D15605*****
contain 65 × 132 bits of display data RAM and there is
a 1-to-1 correspondence between the liquid crystal
panel pixels and the internal RAM bits, these chips
enable displays with a high degree of freedom.
The S1D15606***** chips contain 49 common output
• Static drive circuit equipped internally for indicators.
(1 system, with variable flashing speed.)
• Low-power liquid crystal display power supply circuit
equipped internally.
circuits and 132 segment output circuits, so that a single
chip can drive a 49 × 132 dot display (capable of
displaying 8 columns × 4 rows of a 16 × 16 dot kanji
font). The S1D15607***** chips contain 33 common
Booster circuit (with Boost ratios of Double/Triple/
Quad, where the step-up voltage reference power
supply can be input externally)
High-accuracy voltage adjustment circuit (Thermal
gradient –0.05%/°C or –0.2%/°C or external input)
V5 voltage regulator resistors equipped internally,
V1 to V4 voltage divider resistors equipped internally,
electronic volume function equipped internally,
voltage follower.
output circuits and 132 segment output circuits, so that
a single chip can drive 33 × 132 dot display (capable of
displaying 8 columns × 2 rows of 16 × 16 dot kanji
fonts). Thanks to the built-in 55 common output circuits
and 132 segment output circuits, the S1D15608*****
is capable of displaying 55 × 132 dots (11 columns × 4
lines using 11 × 12 dots Kanji font) with a single chip.
The S1D15609***** chips contain 53 common output
circuits and 132 segment output circuits, so that a single
• CR oscillator circuit equipped internally (external
clock can also be input)
• Extremely low power consumption
chip can drive 53 × 132 dot display (capable of displaying
11 columns × 4 rows of 11 × 12 dot kanji fonts).
Moreover, the capacity of the display can be extended
through the use of master/slave structures between
chips.
The chips are able to minimize power consumption
because no external operating clock is necessary for the
display data RAM read/write operation. Furthermore,
because each chip is equipped internally with a low-
power liquid crystal driver power supply, resistors for
liquid crystal driver power voltage adjustment and a
display clock CR oscillator circuit, the S1D15605 Series
chips can be used to create the lowest power display
system with the fewest components for high-
performance portable devices.
Operating power when the built-in power supply is
used (an example)
S1D15605D00B 81 µA (VDD – VSS = VDD – VSS2=
*
/S1D15605D11B 3.0 V, Quad voltage, V5 – VDD =
*
–11.0 V)
S1D15606D00B 43 µA (VDD – VSS = VDD – VSS2
=
*
/S1D15606D11B 3.0 V, Triple voltage, V5 – VDD =
*
–8.0 V)
S1D15607D00B 29 µA (VDD – VSS = VDD – VSS2
=
*
/S1D15607D11B 3.0 V, Triple voltage, V5 – VDD =
*
–8.0 V)
S1D15608D00B /S1D15608D11B
*
*
/S1D15609D00B /S1D15609D11B
*
*
46µA (VDD – VSS = VDD – VSS2 =
3.0 V, Triple voltage, V5 – VDD =
– 8.0 V)
2. FEATURES
• Direct display of RAM data through the display data
RAM.
Conditions: When all displays are in white and the
normal mode is selected (see page 60 *12 for details
of the conditions).
RAM bit data: “1” Display on
“0” Display off
(during normal display)
• RAM capacity
65 × 132 = 8580 bits
• Display driver circuits
• Power supply
Operable on the low 1.8 voltage
Logic power supply VDD – VSS = 1.8 V to 5.5 V
Boost reference voltage: VDD – VSS2 = 1.8 V to
6.0 V
Liquid crystal drive power supply: V5 – VDD = –4.5
V to –16.0 V
S1D15605*****:65 common output and 132
segment outputs
S1D15606*****:49 common output and 132
segment outputs
• Wide range of operating temperatures: –40 to 85°C
• CMOS process
• Shipping forms include bare chip and TCP.
• These chips not designed for resistance to light or
resistance to radiation.
S1D15607*****:33 common outputs and 132
segment outputs
S1D15608*****:55 common outputs and 132
segment outputs
S1D15609*****:53 common outputs and 132
segment outputs
Rev. 2.4a
EPSON
8–1
S1D15605 Series
Series Specifications
Bare chip
Product Name
Duty
Bias
SEG Dr
COM Dr
VREG Temperature
Gradient
Chip
Thickness
S1D15605D00B
1/65
1/65
1/65
1/65
1/65
1/49
1/49
1/49
1/49
1/33
1/33
1/33
1/33
1/55
1/53
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/9, 1/7
1/8, 1/6
1/8, 1/6
1/8, 1/6
1/8, 1/6
1/6, 1/5
1/6, 1/5
1/6, 1/5
1/6, 1/5
1/8, 1/6
1/8, 1/6
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
65
65
65
65
65
49
49
49
49
33
33
33
33
55
53
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.2%/°C
625 µm
625 µm
300 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
625 µm
*
S1D15605D11B
S1D15605D11E
S1D15605D01B
S1D15605D02B
S1D15606D00B
S1D15606D01B
S1D15606D02B
S1D15606D11B
S1D15607D00B
S1D15607D01B
S1D15607D02B
S1D15607D11B
S1D15608D00B
S1D15609D00B
*
*
*
*
*
*
*
*
*
*
*
*
*
*
External Input
–0.05%/°C
–0.2%/°C
External Input
–0.05%/°C
–0.05%/°C
–0.2%/°C
External Input
–0.05%/°C
–0.05%/°C
–0.05%/°C
TCP
Product Name
Duty
1/65
1/49
1/33
Bias
SEG Dr
132
COM Dr
65
VREG Temperature Gradient
–0.05%/°C
1/9, 1/7
1/8, 1/6
1/6, 1/5
S1D15605T00**
S1D15606T00**
S1D15607T00**
132
49
–0.05%/°C
132
33
–0.05%/°C
Product name of custom TCP can be coped with specially.
8–2
EPSON
Rev. 2.4a
S1D15605 Series
3. BLOCK DIAGRAM
Example: S1D15605
*****
• • • • • • • • • • • • • • • • • • • • • • • • •
• • • • • • • • • •
VSS
VDD
V1
V2
SEG Drivers
COM Drivers
Shift register
V3
V4
V5
CAP1+
CAP1–
CAP2+
CAP2–
CAP3+
VOUT
Display data latch circuit
FRS
FR
CL
Power
supply
circuit
Display data RAM
132 x 65
DOF
M/S
VSS2
VR
VRS
IRS
HPM
Column address circuit
CLS
Bus holder
Command decoder
MPU interface
Status
Rev. 2.4a
EPSON
8–3
S1D15605 Series
4. PAD
Pad Layout
99
1
100
309
275
S1D15605 Series
(0, 0)
Die No.
134
135
274
Chip Size
10.82 mm × 2.81 mm
0.625 mm
Chip Thickness
Bump Pitch
Bump Size
71 µm (Min.)
PAD No. 1~24
PAD No. 25~82
PAD No. 83~99
PAD No. 100
85 µm × 85 µm
64 µm × 85 µm
85 µm × 85 µm
85 µm × 73 µm
85 µm × 47 µm
85 µm × 73 µm
73 µm × 85 µm
47 µm × 85 µm
73 µm × 85 µm
86 µm × 73 µm
85 µm × 47 µm
85 µm × 73 µm
PAD No. 101~133
PAD No. 134
PAD No. 135
PAD No. 136~273
PAD No. 274
PAD No. 275
PAD No. 276~308
PAD No. 309
Bump Height
17 µm (Typ.)
8–4
EPSON
Rev. 2.4a
S1D15605 Series
S1D15605
Pad Center Coordinates
*****
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
(NC)
FRS
FR
CL
DOF
4973
4853
4734
4614
4494
1246
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CAP3–
(NC)
695
605
516
427
338
249
160
71
1246
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101 COM31
102 COM30
103 COM29
104 COM28
105 COM27
106 COM26
107 COM25
108 COM24
109 COM23
110 COM22
111 COM21
112 COM20
113 COM19
114 COM18
115 COM17
116 COM16
117 COM15
118 COM14
119 COM13
120 COM12
TEST4 –2867 1246
(NC)
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
TEST0 4375
VSS
CS1
CS2
VDD
RES
A0
4255
4136
4016
3896
3777
3657
3538
–18
CAP2+ –107
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
–196
–285
–374
–463
–552
–641
–730
–819
–908
IRS
VDD
VSS
14 WR, R/W 3418
TEST5 –4375
TEST6 –4494
TEST7 –4614
TEST8 –4734
TEST9 –4853
15
16
17
18
19
20
21
22
RD, E
VDD
D0
D1
D2
D3
D4
D5
3298
3179
3059
2940
2820
2700
2581
2461
(NC)
(NC)
–4973
–5252 1248
1163
1090
1017
945
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
23 D6, SCL 2342
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D7, SI
(NC)
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
–145
–218
TEST1 –2155
TEST1 –2244
TEST2 –2333
TEST2 –2422
(NC)
–2511
TEST3 –2600
TEST3 –2689
TEST4 –2778
873
784
Rev. 2.4a
EPSON
8–5
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
121 COM11 –5252 –291
161 SEG22 –3127 –1246
162 SEG23 –3055
163 SEG24 –2983
164 SEG25 –2912
165 SEG26 –2840
166 SEG27 –2768
167 SEG28 –2696
168 SEG29 –2624
169 SEG30 –2552
170 SEG31 –2480
171 SEG32 –2408
172 SEG33 –2336
173 SEG34 –2265
174 SEG35 –2193
175 SEG36 –2121
176 SEG37 –2049
177 SEG38 –1977
178 SEG39 –1905
179 SEG40 –1833
180 SEG41 –1761
181 SEG42 –1689
182 SEG43 –1618
183 SEG44 –1546
184 SEG45 –1474
185 SEG46 –1402
186 SEG47 –1330
187 SEG48 –1258
188 SEG49 –1186
189 SEG50 –1114
190 SEG51 –1042
191 SEG52 –971
192 SEG53 –899
193 SEG54 –827
194 SEG55 –755
195 SEG56 –683
196 SEG57 –611
197 SEG58 –539
198 SEG59 –467
199 SEG60 –395
200 SEG61 –324
201 SEG62 –252 –1246
202 SEG63 –180
203 SEG64 –108
122 COM10
–363
–436
–509
–581
–654
–727
–800
–872
–945
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
(NC)
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
–1018
–1090
–1163
–1248
–5009 –1246
–4924
–4853
–4781
(NC)
(NC)
(NC)
(NC)
SEG0 –4709
SEG1 –4637
SEG2 –4565
SEG3 –4493
SEG4 –4421
SEG5 –4349
SEG6 –4277
SEG7 –4206
SEG8 –4134
SEG9 –4062
219 SEG80 1042
220 SEG81 1114
221 SEG82 1186
222 SEG83 1258
223 SEG84 1330
224 SEG85 1402
225 SEG86 1474
226 SEG87 1546
227 SEG88 1618
228 SEG89 1689
229 SEG90 1761
230 SEG91 1833
231 SEG92 1905
232 SEG93 1977
233 SEG94 2049
234 SEG95 2121
235 SEG96 2193
236 SEG97 2265
237 SEG98 2336
238 SEG99 2408
239 SEG100 2480
240 SEG101 2552
149 SEG10 –3990
150 SEG11 –3918
151 SEG12 –3846
152 SEG13 –3774
153 SEG14 –3702
154 SEG15 –3630
155 SEG16 –3559
156 SEG17 –3487
157 SEG18 –3415
158 SEG19 –3343
159 SEG20 –3271
160 SEG21 –3199
8–6
EPSON
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
241 SEG102 2624 –1246
242 SEG103 2696
243 SEG104 2768
244 SEG105 2840
245 SEG106 2912
246 SEG107 2983
247 SEG108 3055
248 SEG109 3127
249 SEG110 3199
250 SEG111 3271
251 SEG112 3343
252 SEG113 3415
253 SEG114 3487
254 SEG115 3558
255 SEG116 3630
256 SEG117 3702
257 SEG118 3774
258 SEG119 3846
259 SEG120 3918
260 SEG121 3990
261 SEG122 4062
262 SEG123 4134
263 SEG124 4206
264 SEG125 4277
265 SEG126 4349
266 SEG127 4421
267 SEG128 4493
268 SEG129 4565
269 SEG130 4637
270 SEG131 4709
281 COM37 5252
282 COM38
283 COM39
284 COM40
285 COM41
286 COM42
287 COM43
288 COM44
289 COM45
290 COM46
291 COM47
292 COM48
293 COM49
294 COM50
295 COM51
296 COM52
297 COM53
298 COM54
299 COM55
300 COM56
301 COM57
302 COM58
303 COM59
304 COM60
305 COM61
306 COM62
307 COM63
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
308
309
COMS
(NC)
271
272
273
274
275
276 COM32
277 COM33
278 COM34
279 COM35
280 COM36
(NC)
(NC)
(NC)
(NC)
(NC)
4781
4853
4924
5009
5252 –1248
–1163
–1090
–1018
–945
–872
Rev. 2.4a
EPSON
8–7
S1D15605 Series
S1D15606 Pad Center Coordinates
*****
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
(NC)
FRS
FR
CL
DOF
4973
4853
4734
4614
4494
1246
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CAP3–
(NC)
695
605
516
427
338
249
160
71
1246
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
TEST4 –2867 1246
(NC)
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
TEST0 4375
VSS
CS1
CS2
VDD
RES
A0
4255
4136
4016
3896
3777
3657
3538
–18
CAP2+ –107
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
–196
–285
–374
–463
–552
–641
–730
–819
–908
VSS
14 WR, R/W 3418
TEST5 –4375
TEST6 –4494
TEST7 –4614
TEST8 –4734
TEST9 –4853
15
16
17
18
19
20
21
22
RD, E
VDD
D0
D1
D2
D3
D4
D5
3298
3179
3059
2940
2820
2700
2581
2461
(NC)
(NC)
(NC)
(NC)
–4973
–5252 1248
1163
1090
1017
945
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
23 D6, SCL 2342
103 COM23
104 (NC)
105 COM22
106 (NC)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D7, SI
(NC)
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
107 COM21
108 COM20
109 COM19
110 COM18
111 COM17
112 COM16
113 COM15
114 COM14
115 COM13
116 COM12
117 COM11
118 COM10
TEST1 –2155
TEST1 –2244
TEST2 –2333
TEST2 –2422
(NC)
–2511
TEST3 –2600
TEST3 –2689
TEST4 –2778
873
784
119
120
COM9
COM8
–145
–218
8–8
EPSON
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
COM7 –5252 –291
161 SEG22 –3127 –1246
162 SEG23 –3055
163 SEG24 –2983
164 SEG25 –2912
165 SEG26 –2840
166 SEG27 –2768
167 SEG28 –2696
168 SEG29 –2624
169 SEG30 –2552
170 SEG31 –2480
171 SEG32 –2408
172 SEG33 –2336
173 SEG34 –2265
174 SEG35 –2193
175 SEG36 –2121
176 SEG37 –2049
177 SEG38 –1977
178 SEG39 –1905
179 SEG40 –1833
180 SEG41 –1761
181 SEG42 –1689
182 SEG43 –1618
183 SEG44 –1546
184 SEG45 –1474
185 SEG46 –1402
186 SEG47 –1330
187 SEG48 –1258
188 SEG49 –1186
189 SEG50 –1114
190 SEG51 –1042
191 SEG52 –971
192 SEG53 –899
193 SEG54 –827
194 SEG55 –755
195 SEG56 –683
196 SEG57 –611
197 SEG58 –539
198 SEG59 –467
199 SEG60 –395
200 SEG61 –324
201 SEG62 –252 –1246
202 SEG63 –180
203 SEG64 –108
COM6
COM5
COM4
COM3
COM2
COM1
(NC)
–363
–436
–509
–581
–654
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
–727
–800
COM0
(NC)
–872
–945
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
–1018
–1090
–1163
–1248
–5009 –1246
–4924
–4853
–4781
SEG0 –4709
SEG1 –4637
SEG2 –4565
SEG3 –4493
SEG4 –4421
SEG5 –4349
SEG6 –4277
SEG7 –4206
SEG8 –4134
SEG9 –4062
219 SEG80 1042
220 SEG81 1114
221 SEG82 1186
222 SEG83 1258
223 SEG84 1330
224 SEG85 1402
225 SEG86 1474
226 SEG87 1546
227 SEG88 1618
228 SEG89 1689
229 SEG90 1761
230 SEG91 1833
231 SEG92 1905
232 SEG93 1977
233 SEG94 2049
234 SEG95 2121
235 SEG96 2193
236 SEG97 2265
237 SEG98 2336
238 SEG99 2408
239 SEG100 2480
240 SEG101 2552
149 SEG10 –3990
150 SEG11 –3918
151 SEG12 –3846
152 SEG13 –3774
153 SEG14 –3702
154 SEG15 –3630
155 SEG16 –3559
156 SEG17 –3487
157 SEG18 –3415
158 SEG19 –3343
159 SEG20 –3271
160 SEG21 –3199
Rev. 2.4a
EPSON
8–9
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
241 SEG102 2624 –1246
242 SEG103 2696
243 SEG104 2768
244 SEG105 2840
245 SEG106 2912
246 SEG107 2983
247 SEG108 3055
248 SEG109 3127
249 SEG110 3199
250 SEG111 3271
251 SEG112 3343
252 SEG113 3415
253 SEG114 3487
254 SEG115 3558
255 SEG116 3630
256 SEG117 3702
257 SEG118 3774
258 SEG119 3846
259 SEG120 3918
260 SEG121 3990
261 SEG122 4062
262 SEG123 4134
263 SEG124 4206
264 SEG125 4277
265 SEG126 4349
266 SEG127 4421
267 SEG128 4493
268 SEG129 4565
269 SEG130 4637
270 SEG131 4709
281
(NC)
5252
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
282 COM26
283 COM27
284 COM28
285 COM29
286 COM30
287 COM31
288 COM32
289 COM33
290 COM34
291 COM35
292 COM36
293 COM37
294 COM38
295 COM39
296 COM40
297 COM41
298 COM42
299 COM43
300 COM44
301 COM45
302 COM46
303
304 COM47
(NC)
305
306
307
308
309
(NC)
COMS
(NC)
(NC)
(NC)
271
272
273
274
275
276
277
278 COM24
279 (NC)
280 COM25
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
4781
4853
4924
5009
5252 –1248
–1163
–1090
–1018
–945
–872
8–10
EPSON
Rev. 2.4a
S1D15605 Series
S1D15607
Pad Center Coordinates
*****
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
(NC)
FRS
FR
CL
DOF
4973
4853
4734
4614
4494
1246
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CAP3–
(NC)
695
605
516
427
338
249
160
71
1246
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101 COM15
102 COM15
103 COM14
104 COM14
105 COM13
106 COM13
107 COM12
108 COM12
109 COM11
110 COM11
111 COM10
112 COM10
TEST4 –2867 1246
(NC)
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
TEST0 4375
VSS
CS1
CS2
VDD
RES
A0
4255
4136
4016
3896
3777
3657
3538
–18
CAP2+ –107
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
–196
–285
–374
–463
–552
–641
–730
–819
–908
VSS
14 WR, R/W 3418
TEST5 –4375
TEST6 –4494
TEST7 –4614
TEST8 –4734
TEST9 –4853
15
16
17
18
19
20
21
22
RD, E
VDD
D0
D1
D2
D3
D4
D5
3298
3179
3059
2940
2820
2700
2581
2461
(NC)
(NC)
–4973
–5252 1248
1163
1090
1017
945
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
23 D6, SCL 2342
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D7, SI
(NC)
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
872
799
727
654
581
509
436
363
TEST1 –2155
TEST1 –2244
TEST2 –2333
TEST2 –2422
113
114
115
116
117
118
119
120
COM9
COM9
COM8
COM8
COM7
COM7
COM6
COM6
291
218
145
73
0
–73
–145
–218
(NC)
–2511
TEST3 –2600
TEST3 –2689
TEST4 –2778
873
784
Rev. 2.4a
EPSON
8–11
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
COM5 –5252 –291
161 SEG22 –3127 –1246
162 SEG23 –3055
163 SEG24 –2983
164 SEG25 –2912
165 SEG26 –2840
166 SEG27 –2768
167 SEG28 –2696
168 SEG29 –2624
169 SEG30 –2552
170 SEG31 –2480
171 SEG32 –2408
172 SEG33 –2336
173 SEG34 –2265
174 SEG35 –2193
175 SEG36 –2121
176 SEG37 –2049
177 SEG38 –1977
178 SEG39 –1905
179 SEG40 –1833
180 SEG41 –1761
181 SEG42 –1689
182 SEG43 –1618
183 SEG44 –1546
184 SEG45 –1474
185 SEG46 –1402
186 SEG47 –1330
187 SEG48 –1258
188 SEG49 –1186
189 SEG50 –1114
190 SEG51 –1042
191 SEG52 –971
192 SEG53 –899
193 SEG54 –827
194 SEG55 –755
195 SEG56 –683
196 SEG57 –611
197 SEG58 –539
198 SEG59 –467
199 SEG60 –395
200 SEG61 –324
201 SEG62 –252 –1246
202 SEG63 –180
203 SEG64 –108
COM5
COM4
COM4
COM3
COM3
COM2
COM2
COM1
COM1
COM0
COM0
COMS
(NC)
–363
–436
–509
–581
–654
–727
–800
–872
–945
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
–1018
–1090
–1163
–1248
–5009 –1246
–4924
–4853
–4781
(NC)
(NC)
(NC)
(NC)
SEG0 –4709
SEG1 –4637
SEG2 –4565
SEG3 –4493
SEG4 –4421
SEG5 –4349
SEG6 –4277
SEG7 –4206
SEG8 –4134
SEG9 –4062
219 SEG80 1042
220 SEG81 1114
221 SEG82 1186
222 SEG83 1258
223 SEG84 1330
224 SEG85 1402
225 SEG86 1474
226 SEG87 1546
227 SEG88 1618
228 SEG89 1689
229 SEG90 1761
230 SEG91 1833
231 SEG92 1905
232 SEG93 1977
233 SEG94 2049
234 SEG95 2121
235 SEG96 2193
236 SEG97 2265
237 SEG98 2336
238 SEG99 2408
239 SEG100 2480
240 SEG101 2552
149 SEG10 –3990
150 SEG11 –3918
151 SEG12 –3846
152 SEG13 –3774
153 SEG14 –3702
154 SEG15 –3630
155 SEG16 –3559
156 SEG17 –3487
157 SEG18 –3415
158 SEG19 –3343
159 SEG20 –3271
160 SEG21 –3199
8–12
EPSON
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
241 SEG102 2624 –1246
242 SEG103 2696
243 SEG104 2768
244 SEG105 2840
245 SEG106 2912
246 SEG107 2983
247 SEG108 3055
248 SEG109 3127
249 SEG110 3199
250 SEG111 3271
251 SEG112 3343
252 SEG113 3415
253 SEG114 3487
254 SEG115 3558
255 SEG116 3630
256 SEG117 3702
257 SEG118 3774
258 SEG119 3846
259 SEG120 3918
260 SEG121 3990
261 SEG122 4062
262 SEG123 4134
263 SEG124 4206
264 SEG125 4277
265 SEG126 4349
266 SEG127 4421
267 SEG128 4493
268 SEG129 4565
269 SEG130 4637
270 SEG131 4709
281 COM18 5252
282 COM19
283 COM19
284 COM20
285 COM20
286 COM21
287 COM21
288 COM22
289 COM22
290 COM23
291 COM23
292 COM24
293 COM24
294 COM25
295 COM25
296 COM26
297 COM26
298 COM27
299 COM27
300 COM28
301 COM28
302 COM29
303 COM29
304 COM30
305 COM30
306 COM31
307 COM31
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
308
309
COMS
(NC)
271
272
273
274
275
276 COM16
277 COM16
278 COM17
279 COM17
280 COM18
(NC)
(NC)
(NC)
(NC)
(NC)
4781
4853
4924
5009
5252 –1248
–1163
–1090
–1018
–945
–872
Rev. 2.4a
EPSON
8–13
S1D15605 Series
S1D15608 Pad Center Coordinates
*****
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CAP3–
(NC)
695
605
516
427
338
249
160
71
1246
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
TEST4 –2867 1246
1
2
3
4
5
6
7
8
9
10
11
12
13
(NC)
FRS
FR
CL
DOF
4973
4853
4734
4614
4494
1246
(NC)
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
TEST0 4375
VSS
CS1
CS2
VDD
RES
A0
4255
4136
4016
3896
3777
3657
3538
–18
CAP2+ –107
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
–196
–285
–374
–463
–552
–641
–730
–819
–908
VSS
TEST5 –4375
TEST6 –4494
TEST7 –4614
TEST8 –4734
TEST9 –4853
14 WR, R/W 3418
15
16
17
18
19
20
21
22
RD, E
VDD
D0
D1
D2
D3
D4
D5
3298
3179
3059
2940
2820
2700
2581
2461
(NC)
(NC)
(NC)
–4973
–5252 1248
1163
1090
1017
945
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
102 COM26
103 (NC)
23 D6, SCL 2342
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D7, SI
(NC)
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
104 COM25
105 COM25
106 COM23
107 COM22
108 COM21
109 COM20
110 COM19
111 COM18
112 COM17
113 COM16
114 COM15
115 COM14
116 COM13
117 COM12
118 COM11
119 COM10
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
TEST1 –2155
TEST1 –2244
TEST2 –2333
TEST2 –2422
(NC)
–2511
TEST3 –2600
TEST3 –2689
TEST4 –2778
–145
–218
873
784
120
COM9
8–14
EPSON
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
COM8 –5252 –291
161 SEG22 –3127 –1246
162 SEG23 –3055
163 SEG24 –2983
164 SEG25 –2912
165 SEG26 –2840
166 SEG27 –2768
167 SEG28 –2696
168 SEG29 –2624
169 SEG30 –2552
170 SEG31 –2480
171 SEG32 –2408
172 SEG33 –2336
173 SEG34 –2265
174 SEG35 –2193
175 SEG36 –2121
176 SEG37 –2049
177 SEG38 –1977
178 SEG39 –1905
179 SEG40 –1833
180 SEG41 –1761
181 SEG42 –1689
182 SEG43 –1618
183 SEG44 –1546
184 SEG45 –1474
185 SEG46 –1402
186 SEG47 –1330
187 SEG48 –1258
188 SEG49 –1186
189 SEG50 –1114
190 SEG51 –1042
191 SEG52 –971
192 SEG53 –899
193 SEG54 –827
194 SEG55 –755
195 SEG56 –683
196 SEG57 –611
197 SEG58 –539
198 SEG59 –467
199 SEG60 –395
200 SEG61 –324
201 SEG62 –252 –1246
202 SEG63 –180
203 SEG64 –108
COM7
COM6
COM5
COM4
COM3
COM2
COM1
(NC)
–363
–436
–509
–581
–654
–727
–800
–872
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
COM0
(NC)
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
–945
–1018
–1090
–1163
–1248
–5009 –1246
–4924
–4853
–4781
SEG0 –4709
SEG1 –4637
SEG2 –4565
SEG3 –4493
SEG4 –4421
SEG5 –4349
SEG6 –4277
SEG7 –4206
SEG8 –4134
SEG9 –4062
219 SEG80 1042
220 SEG81 1114
221 SEG82 1186
222 SEG83 1258
223 SEG84 1330
224 SEG85 1402
225 SEG86 1474
226 SEG87 1546
227 SEG88 1618
228 SEG89 1689
229 SEG90 1761
230 SEG91 1833
231 SEG92 1905
232 SEG93 1977
233 SEG94 2049
234 SEG95 2121
235 SEG96 2193
236 SEG97 2265
237 SEG98 2336
238 SEG99 2408
239 SEG100 2480
240 SEG101 2552
149 SEG10 –3990
150 SEG11 –3918
151 SEG12 –3846
152 SEG13 –3774
153 SEG14 –3702
154 SEG15 –3630
155 SEG16 –3559
156 SEG17 –3487
157 SEG18 –3415
158 SEG19 –3343
159 SEG20 –3271
160 SEG21 –3199
Rev. 2.4a
EPSON
8–15
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
241 SEG102 2624 –1246
242 SEG103 2696
243 SEG104 2768
244 SEG105 2840
245 SEG106 2912
246 SEG107 2983
247 SEG108 3055
248 SEG109 3127
249 SEG110 3199
250 SEG111 3271
251 SEG112 3343
252 SEG113 3415
253 SEG114 3487
254 SEG115 3558
255 SEG116 3630
256 SEG117 3702
257 SEG118 3774
258 SEG119 3846
259 SEG120 3918
260 SEG121 3990
261 SEG122 4062
262 SEG123 4134
263 SEG124 4206
264 SEG125 4277
265 SEG126 4349
266 SEG127 4421
267 SEG128 4493
268 SEG129 4565
269 SEG130 4637
270 SEG131 4709
281 COM29 5252
282 COM30
283 COM31
284 COM32
285 COM33
286 COM34
287 COM35
288 COM36
289 COM37
290 COM38
291 COM39
292 COM40
293 COM41
294 COM42
295 COM43
296 COM44
297 COM45
298 COM46
299 COM47
300 COM48
301 COM48
302 COM50
303 COM51
304 COM52
305 COM53
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
306
307
308
309
(NC)
COMS
(NC)
(NC)
271
272
273
274
275
276
277 COM27
278 (NC)
279 COM28
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
4781
4853
4924
5009
5252 –1248
–1163
–1090
–1018
–945
280
(NC)
–872
8–16
EPSON
Rev. 2.4a
S1D15605 Series
S1D15609
Pad Center Coordinates
*****
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
(NC)
FRS
FR
CL
DOF
4973
4853
4734
4614
4494
1246
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CAP3–
(NC)
695
605
516
427
338
249
160
71
1246
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
TEST4 –2867 1246
(NC)
VDD
M/S
CLS
VSS
C86
P/S
VDD
HPM
VSS
IRS
VDD
–2957
–3059
–3179
–3298
–3418
–3538
–3657
–3777
–3896
–4016
–4136
–4255
CAP1+
CAP1+
CAP1–
CAP1–
CAP2–
CAP2–
CAP2+
TEST0 4375
VSS
CS1
CS2
VDD
RES
A0
4255
4136
4016
3896
3777
3657
3538
–18
CAP2+ –107
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
VR
VDD
VDD
–196
–285
–374
–463
–552
–641
–730
–819
–908
VSS
14 WR, R/W 3418
TEST5 –4375
TEST6 –4494
TEST7 –4614
TEST8 –4734
TEST9 –4853
15
16
17
18
19
20
21
22
RD, E
VDD
D0
D1
D2
D3
D4
D5
3298
3179
3059
2940
2820
2700
2581
2461
(NC)
(NC)
(NC)
–4973
–5252 1248
1163
1090
1017
945
–997
–1086
–1176
–1265
–1354
–1443
–1532
–1621
–1710
–1799
–1888
–1977
–2066
102 COM25
103 (NC)
104 COM24
105 (NC)
23 D6, SCL 2342
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D7, SI
(NC)
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
2222
2119
2030
1941
1852
1763
1674
1585
1496
1407
1318
1229
1140
1051
962
872
799
727
654
581
509
436
363
291
218
145
73
0
–73
106 COM23
107 COM22
108 COM21
109 COM20
110 COM19
111 COM18
112 COM17
113 COM16
114 COM15
115 COM14
116 COM13
117 COM12
118 COM11
119 COM10
TEST1 –2155
TEST1 –2244
TEST2 –2333
TEST2 –2422
(NC)
–2511
TEST3 –2600
TEST3 –2689
TEST4 –2778
873
784
–145
–218
120
COM9
Rev. 2.4a
EPSON
8–17
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
COM8 –5252 –291
161 SEG22 –3127 –1246
162 SEG23 –3055
163 SEG24 –2983
164 SEG25 –2912
165 SEG26 –2840
166 SEG27 –2768
167 SEG28 –2696
168 SEG29 –2624
169 SEG30 –2552
170 SEG31 –2480
171 SEG32 –2408
172 SEG33 –2336
173 SEG34 –2265
174 SEG35 –2193
175 SEG36 –2121
176 SEG37 –2049
177 SEG38 –1977
178 SEG39 –1905
179 SEG40 –1833
180 SEG41 –1761
181 SEG42 –1689
182 SEG43 –1618
183 SEG44 –1546
184 SEG45 –1474
185 SEG46 –1402
186 SEG47 –1330
187 SEG48 –1258
188 SEG49 –1186
189 SEG50 –1114
190 SEG51 –1042
191 SEG52 –971
192 SEG53 –899
193 SEG54 –827
194 SEG55 –755
195 SEG56 –683
196 SEG57 –611
197 SEG58 –539
198 SEG59 –467
199 SEG60 –395
200 SEG61 –324
201 SEG62 –252 –1246
202 SEG63 –180
203 SEG64 –108
COM7
COM6
COM5
COM4
COM3
COM2
COM1
(NC)
–363
–436
–509
–581
–654
–727
–800
–872
204 SEG65
205 SEG66
206 SEG67
207 SEG68
208 SEG69
209 SEG70
210 SEG71
211 SEG72
212 SEG73
213 SEG74
214 SEG75
215 SEG76
216 SEG77
217 SEG78
218 SEG79
–36
36
108
180
252
324
395
467
539
611
683
755
827
899
971
COM0
(NC)
COMS
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
–945
–1018
–1090
–1163
–1248
–5009 –1246
–4924
–4853
–4781
SEG0 –4709
SEG1 –4637
SEG2 –4565
SEG3 –4493
SEG4 –4421
SEG5 –4349
SEG6 –4277
SEG7 –4206
SEG8 –4134
SEG9 –4062
219 SEG80 1042
220 SEG81 1114
221 SEG82 1186
222 SEG83 1258
223 SEG84 1330
224 SEG85 1402
225 SEG86 1474
226 SEG87 1546
227 SEG88 1618
228 SEG89 1689
229 SEG90 1761
230 SEG91 1833
231 SEG92 1905
232 SEG93 1977
233 SEG94 2049
234 SEG95 2121
235 SEG96 2193
236 SEG97 2265
237 SEG98 2336
238 SEG99 2408
239 SEG100 2480
240 SEG101 2552
149 SEG10 –3990
150 SEG11 –3918
151 SEG12 –3846
152 SEG13 –3774
153 SEG14 –3702
154 SEG15 –3630
155 SEG16 –3559
156 SEG17 –3487
157 SEG18 –3415
158 SEG19 –3343
159 SEG20 –3271
160 SEG21 –3199
8–18
EPSON
Rev. 2.4a
S1D15605 Series
Units: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
241 SEG102 2624 –1246
242 SEG103 2696
243 SEG104 2768
244 SEG105 2840
245 SEG106 2912
246 SEG107 2983
247 SEG108 3055
248 SEG109 3127
249 SEG110 3199
250 SEG111 3271
251 SEG112 3343
252 SEG113 3415
253 SEG114 3487
254 SEG115 3558
255 SEG116 3630
256 SEG117 3702
257 SEG118 3774
258 SEG119 3846
259 SEG120 3918
260 SEG121 3990
261 SEG122 4062
262 SEG123 4134
263 SEG124 4206
264 SEG125 4277
265 SEG126 4349
266 SEG127 4421
267 SEG128 4493
268 SEG129 4565
269 SEG130 4637
270 SEG131 4709
281 COM28 5252
282 COM29
283 COM30
284 COM31
285 COM32
286 COM33
287 COM34
288 COM35
289 COM36
290 COM37
291 COM38
292 COM39
293 COM40
294 COM41
295 COM42
296 COM43
297 COM44
298 COM45
299 COM46
300 COM47
301 COM48
302 COM49
303 COM50
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
304
(NC)
305 COM51
306
307
308
309
(NC)
COMS
(NC)
(NC)
271
272
273
274
275
276
277 COM26
278 (NC)
279 COM27
280 (NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
4781
4853
4924
5009
5252 –1248
–1163
–1090
–1018
–945
–872
Rev. 2.4a
EPSON
8–19
S1D15605 Series
5. PIN DESCRIPTIONS
Power Supply Pins
No. of
Pins
Pin Name
I/O
Function
VDD
Power Shared with the MPU power supply terminal VCC.
Supply
13
VSS
VSS2
VRS
Power This is a 0V terminal connected to the system GND.
Supply
9
Power This is the reference power supply for the step-up voltage circuit for the
Supply liquid crystal drive.
4
Power This is the externally-input VREG power supply for the LCD power supply
Supply voltage regulator.
2
These are only enabled for the models with the VREG external input option.
V1, V2,
V3, V4,
V5
Power This is a multi-level power supply for the liquid crystal drive. The voltage
Supply applied is determined by the liquid crystal cell, and is changed through the
use of a resistive voltage divided or through changing the impedance using
an op. amp. Voltage levels are determined based on VDD, and must
maintain the relative magnitudes shown below.
10
VDD (= V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master operation: When the power supply turns ON, the internal power
supply circuits produce the V1 to V4 voltages shown below. The voltage
settings are selected using the LCD bias set command.
S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609*****
V1 1/9•V5 1/7•V5 1/8•V5 1/6•V5 1/6•V5 1/5•V5 1/8•V5 1/6•V5 1/8•V5 1/6•V5
V2 2/9•V5 2/7•V5 2/8•V5 2/6•V5 2/6•V5 2/5•V5 2/8•V5 2/6•V5 2/8•V5 2/6•V5
V3 7/9•V5 5/7•V5 6/8•V5 4/6•V5 4/6•V5 3/5•V5 6/8•V5 4/6•V5 6/8•V5 4/6•V5
V4 8/9•V5 6/7•V5 7/8•V5 5/6•V5 5/6•V5 4/5•V5 7/8•V5 5/6•V5 7/6•V5 5/6•V5
LCD Power Supply Circuit Terminals
No. of
Pins
Pin Name
I/O
Function
CAP1+
O
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP1- terminal.
2
2
2
2
2
2
2
CAP1–
CAP2+
CAP2–
CAP3–
VOUT
O
O
O
O
I/O
I
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP1+ terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP2- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP2+ terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
the CAP1+ terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and
VSS2.
VR
Output voltage regulator terminal. Provides the voltage between VDD and
V5 through a resistive voltage divider.
These are only enabled when the V5 voltage regulator internal resistors are
not used (IRS = LOW).
These cannot be used when the V5 voltage regulator internal resistors are
used (IRS = HIGH).
8–20
EPSON
Rev. 2.4a
S1D15605 Series
System Bus Connection Terminals
No. of
Pins
Pin Name
I/O
Function
D7 to D0
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus.
8
(SI)
(SCL)
When the serial interface is selected (P/S = LOW), then D7 serves as the
serial data input terminal (SI) and D6 serves as the serial clock input
terminal (SCL). At this time, D0 to D5 are set to high impedance.
When the chip select is inactive, D0 to D7 are set to high impedance.
A0
I
This is connect to the least significant bit of the normal MPU address bus,
and it determines whether the data bits are data or a command.
A0 = HIGH: Indicates that D0 to D7 are display data.
1
A0 = LOW: Indicates that D0 to D7 are display control data.
RES
I
I
I
When RES is set to LOW, the settings are initialized.
The reset operation is performed by the RES signal level.
1
2
1
CS1
CS2
This is the chip select signal. When CS1 = LOW and CS2 = HIGH, then the
chip select becomes active, and data/command I/O is enabled.
RD
(E)
• When connected to an 8080 MPU, this is active LOW.
This pin is connected to the RD signal of the 8080 MPU, and the
S1D15605 series data bus is in an output status when this signal is LOW.
• When connected to a 6800 Series MPU, this is active HIGH.
This is the 6800 Series MPU enable clock input terminal.
WR
(R/W)
I
• When connected to an 8080 MPU, this is active LOW.
This terminal connects to the 8080 MPU WR signal. The signals on
the data bus are latched at the rising edge of the WR signal.
• When connected to a 6800 Series MPU:
1
This is the read/write control signal input terminal.
When R/W = HIGH: Read.
When R/W = LOW: Write.
C86
P/S
I
I
This is the MPU interface switch terminal.
C86 = HIGH: 6800 Series MPU interface.
C86 = LOW: 8080 MPU interface.
1
1
This is the parallel data input/serial data input switch terminal.
P/S = HIGH: Parallel data input.
P/S = LOW: Serial data input.
The following applies depending on the P/S status:
P/S Data/Command
Data
Read/Write Serial Clock
HIGH
LOW
A0
A0
D0 to D7
SI (D7)
RD, WR
Write only
SCL (D6)
When P/S = LOW, D0 to D5 are HZ. D0 to D5 may be HIGH, LOW or Open.
RD (E) and WR (P/W) are fixed to either HGIH or LOW.
With serial data input, RAM display data reading is not supported.
CLS
I
Terminal to select whether or enable or disable the display clock internal
oscillator circuit.
1
CLS = HIGH: Internal oscillator circuit is enabled
CLS = LOW: Internal oscillator circuit is disabled (requires external input)
When CLS = LOW, input the display clock through the CL terminal.
When using the S1D15605 Series as a master or slave, set respective
CLS pins at the same level.
Display clock
Built-in oscillator circuit used
External input
Master
HIGH
LOW
Slave
HIGH
LOW
Rev. 2.4a
EPSON
8–21
S1D15605 Series
No. of
Pins
Pin Name
I/O
Function
M/S
I
This terminal selects the master/slave operation for the S1D15605 Series
chips. Master operation outputs the timing signals that are required for the
LCD display, while slave operation inputs the timing signals required for the
liquid crystal display, synchronizing the liquid crystal display system.
M/S = HIGH: Master operation
1
M/S = LOW: Slave operation
The following is true depending on the M/S and CLS status:
Power
Supply
Circuit
Oscillator
Circuit
M/S CLS
CL
FR
FRS
DOF
HIGH HIGH Enabled
LOW Disabled
Enabled
Enabled
Output Output Output Output
Input Output Output Output
LOW HIGH Disabled
LOW Disabled
Disabled
Disabled
Input
Input
Input Output Input
Input Output Input
CL
I/O
This is the display clock input terminal
The following is true depending on the M/S and CLS status.
1
M/S CLS CL
HIGH HIGH Output
LOW
Input
LOW HIGH
LOW
Input
Input
When the S1D15605 Series chips are used in master/slave mode, the
various CL terminals must be connected.
FR
I/O
I/O
This is the liquid crystal alternating current signal I/O terminal.
M/S = HIGH: Output
M/S = LOW: Input
When the S1D15605 Series chip is used in master/slave mode, the various
FR terminals must be connected.
1
1
DOF
This is the liquid crystal display blanking control terminal.
M/S = HIGH: Output
M/S = LOW: Input
When the S1D15605 Series chip is used in master/slave mode, the various
DOF terminals must be connected.
FRS
IRS
O
I
This is the output terminal for the static drive.
This terminal is only enabled when the static indicator display is ON when
in master operation mode, and is used in conjunction with the FR terminal.
1
1
This terminal selects the resistors for the V5 voltage level adjustment.
IRS = HIGH: Use the internal resistors
IRS = LOW: Do not use the internal resistors. The V5 voltage level is
regulated by an external resistive voltage divider attached to the VR
terminal.
This pin is enabled only when the master operation mode is selected.
It is fixed to either HIGH or LOW when the slave operation mode is selected.
HPM
I
This is the power control terminal for the power supply circuit for liquid
crystal drive.
1
HPM = HIGH: Normal mode
HPM = LOW: High power mode
This pin is enabled only when the master operation mode is selected.
It is fixed to either HIGH or LOW when the slave operation mode is selected.
8–22
EPSON
Rev. 2.4a
S1D15605 Series
Liquid Crystal Drive Terminals
No. of
Pins
Pin Name
I/O
Function
SEG0
to
SEG131
O
These are the liquid crystal segment drive outputs. Through a combination 132
of the contents of the display RAM and with the FR signal, a single level is
selected from VDD, V2, V3, and V5.
RAM DATA
FR
Output Voltage
Normal Display Reverse Display
HIGH
HIGH
HIGH
LOW
HIGH
LOW
—
VDD
V5
V2
V3
LOW
V2
VDD
V5
LOW
V3
Power save
VDD
COM0
to
O
These are the liquid crystal common drive outputs.
Part No.
COM
Part No.
No. of pins
COMn
COM 0 ~ COM 63
COM 0 ~ COM 47
COM 0 ~ COM 31
COM 0 ~ COM 53
COM 0 ~ COM 51
64
48
32
54
52
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****
S1D15609*****
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****
S1D15609*****
Through a combination of the contents of the scan data and with the
FR signal, a single level is selected from VDD, V1, V4, and V5.
Scan Data
HIGH
FR
HIGH
LOW
HIGH
LOW
—
Output Voltage
V5
VDD
V1
HIGH
LOW
LOW
V4
Power Save
VDD
COMS
O
These are the COM output terminals for the indicator. Both terminals
output the same signal.
2
Leave these open if they are not used.
When in master/slave mode, the same signal is output by both master and
slave.
Test Terminals
No. of
Pins
Pin Name
I/O
Function
TEST0 to 9
I/O
These are terminals for IC chip testing.
TEST0 to 4 and 7 to 9 should be open, TEST 5 and 6 should be fixed to
HIGH.
14
.
.
.
.
.
Total: 288 pins for the S1D15605*****
272 pins for the S1D15606*****
256 pins for the S1D15607*****
278 pins for the S1D15608*****
276 pins for the S1D15609*****
Rev. 2.4a
EPSON
8–23
S1D15605 Series
through a serial data input (SI). Through selecting the P/
S terminal polarity to the HIGH or LOW it is possible to
select either parallel data input or serial data input as
shown in Table 1.
6. DESCRIPTION OF FUNCTIONS
The MPU Interface
Selecting the Interface Type
With the S1D15605 Series chips, data transfers are done
through an 8-bit bi-directional data bus (D7 to D0) or
Table 1
P/S
HIGH: Parallel Input CS1 CS2
LOW: Serial Input CS1 CS2
CS1 CS2
A0
A0
A0
RD
RD
—
WR C86
D7
D7
SI
D6
D6
D5~D0
D5~D0
(HZ)
WR C86
—
—
SCL
“—” indicates fixed to either HIGH or to LOW. HZ is in the state of High Impedance.
8080-system MPU or a 6800 Series MPU (as shown in
Table 2) by selecting the C86 terminal to either HIGH
or to LOW.
The Parallel Interface
When the parallel interface has been selected (P/S =
HIGH), then it is possible to connect directly to either an
Table 2
CS1 CS2
HIGH: 6800 Series MPU Bus CS1 CS2
LOW: 8080 MPU Bus CS1 CS2
P/S
A0
A0
A0
RD
E
WR
D7~D0
R/W D7~D0
RD
WR
D7~D0
Moreover, data bus signals are recognized by a
combination of A0, RD (E), WR (R/W) signals, as
shown in Table 3.
Table 3
8080 Series
Shared 6800 Series
Function
A0
1
R/W
RD
0
WR
1
1
0
1
0
Reads the display data
Writes the display data
Status read
1
1
0
0
0
1
0
1
0
Write control data (command)
8–24
EPSON
Rev. 2.4a
S1D15605 Series
of the eighth serial clock for the processing.
The Serial Interface
The A0 input is used to determine whether or the serial
data input is display data or command data; when A0 =
HIGH, the data is display data, and when A0 = LOW
then the data is command data. The A0 input is read and
used for detection every 8th rising edge of the serial
clock after the chip becomes active.
When the serial interface has been selected (P/S =
LOW) then when the chip is in active state (CS1 = LOW
and CS2 = HIGH) the serial data input (SI) and the serial
clock input (SCL) can be received. The serial data is
read from the serial data input pin in the rising edge of
the serial clocks D7, D6 through D0, in this order. This
data is converted to 8 bits parallel data in the rising edge
Figure 1 is a serial interface signal chart.
CS1
CS2
SI
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0 D7
D6
10
D5
D4
D3
13
D2
14
SCL
8
9
11
12
A0
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their initial states.
* Reading is not possible while in serial interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that
operation be rechecked on the actual equipment.
LSIs is performed through the bus holder attached to the
internal data bus.
The Chip Select
The S1D15605 Series chips have two chip select
terminals: CS1 and CS2. The MPU interface or the
serial interface is enabled only when CS1 = LOW and
CS2 = HIGH.
When the chip select is inactive, D0 to D7 enter a high
impedance state, and the A0, RD, and WR inputs are
inactive. When the serial interface is selected, the shift
register and the counter are reset.
For example, when the MPU writes data to the display
data RAM, once the data is stored in the bus holder, then
it is written to the display data RAM before the next data
write cycle. Moreover, when the MPU reads the display
data RAM, the first data read cycle (dummy) stores the
read data in the bus holder, and then the data is read from
the bus holder to the system bus at the next data read
cycle.
There is a certain restriction in the read sequence of the
display data RAM. Please be advised that data of the
specified address is not generated by the read instruction
issued immediately after the address setup. This data is
generated in data read of the second time. Thus, a
dummy read is required whenever the address setup or
write cycle operation is conducted.
Accessing the Display Data RAM and the
Internal Registers
Data transfer at a higher speed is ensured since the MPU
is required to satisfy the cycle time (tCYC) requirement
alone in accessing the S1D15605 Series. Wait time may
not be considered.
And, in the S1D15605 Series chips, each time data is
sent from the MPU, a type of pipeline process between
This relationship is shown in Figure 2.
Rev. 2.4a
EPSON
8–25
S1D15605 Series
The Busy Flag
read instruction. If the cycle time (tCYC) is maintained,
it is not necessary to check for this flag before each
command. This makes vast improvements in MPU
processing capabilities possible.
When the busy flag is “1” it indicates that the S1D15605
Series chip is running internal processes, and at this
time no command aside from a status read will be
received. The busy flag is outputted to D7 pin with the
Writing
WR
DATA
N
N+1
N+2
N+3
Latch
N
N+1
N+2
N+3
BUS Holder
Write Signal
Reading
WR
RD
DATA
N
N
n
n+1
Address Preset
Read Signal
Column Address
Bus Holder
Preset N
Increment N+1
n
N+2
N
n+1
n+2
Address Set
#n
Dummy
Read
Data Read
#n
Data Read
#n+1
Figure 2
8–26
EPSON
Rev. 2.4a
S1D15605 Series
the time of display data transfer when multiple S1D15605
series chips are used, thus and display structures can be
created easily and with a high degree of freedom.
Moreover, reading from and writing to the display
RAM from the MPU side is performed through the I/O
buffer, which is an independent operation from signal
reading for the liquid crystal driver. Consequently, even
if the display data RAM is accessed asynchronously
during liquid crystal display, it will not cause adverse
effects on the display (such as flickering).
Display Data RAM
Display Data RAM
The display data RAM is a RAM that stores the dot data
for the display. It has a 65 (8 page × 8 bit +1) × 132 bit
structure. It is possible to access the desired bit by
specifying the page address and the column address.
Because, as is shown in Figure 3, the D7 to D0 display
data from the MPU corresponds to the liquid crystal
display common direction, there are few constraints at
D0 0 1 1 1
D1 1 0 0 0
D2 0 0 0 0
D3 0 1 1 1
D4 1 0 0 0
—
0
0
0
0
0
COM0
COM1
COM2
COM3
COM4
—
Display data RAM
Liquid crystal display
Figure 3
Table 4
The Page Address Circuit
SEG
Output
As shown in Figure 6-4, page address of the display data
RAM is specified through the Page Address Set
Command. The page address must be specified again
when changing pages to perform access.
SEG0
SEG 131
ADC “0” 0 (H) → Column Address → 83 (H)
(D0) “1” 83 (H) ← Column Address ← 0 (H)
Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page
for the RAM region used only by the indicators, and
only display data D0 is used.
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies
the line address relating to the COM output when the
contents of the display data RAM are displayed. Using
the display start line address set command, what is
normally the top line of the display can be specified (this
is the COM0 output when the common output mode is
normal, and the COM63 output for S1D15605 Series,
COM47 output for S1D15606 Series, COM31 output for
The Column Addresses
As is shown in Figure 4, the display data RAM column
address is specified by the Column Address Set
command. The specified column address is incremented
(+1) with each display data read/write command. This
allows the MPU display data to be accessed continuously.
Moreover, the incrementation of column addresses stops
with 83H. Because the column address is independent
of the page address, when moving, for example, from
page 0 column 83H to page 1 column 00H, it is necessary
to respecify both the page address and the column
address.
the S1D15607 Series, COM53 output for S1D15608*****
andCOM51outputforS1D15609*****)whenthecommon
output mode is reversed. The display area is a 65 line area
for the S1D15605 Series, a 49 line are for the S1D15606,
a 33 line area for the S1D15607 Series , 55 line area for
Furthermore, as is shown in Table 4, the ADC command
(segment driver direction select command) can be used
to reverse the relationship between the display data
RAM column address and the segment output. Because
of this, the constraints on the IC layout when the LCD
module is assembled can be minimized.
the S1D15608*****
and 53 line area for the
S1D15609***** from the display start line address.
If the line addresses are changed dynamically using the
display start line address set command, screen scrolling,
page swapping, etc. can be performed.
Rev. 2.4a
EPSON
8–27
S1D15605 Series
When the
common output
mode is normal
Page Address
Line
COM
Data
Address
Output
D3
0
D2
D1
D0
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
11H
12H
13H
14H
15H
16H
17H
18H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM0
COM1
COM2
COM3
0
0
Page 0
Page 1
Page 2
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
Page 3
Page 4
Start
0
0
1
1
0
1
1
0
Page 5
Page 6
0
1
1
0
1
0
1
0
Page 7
Page 8
Regardless of the display
start line address, the
S1D15605 Series
accesses 65th line, the
S1D15606 Series
accesses 49th line and
the S1D15607 Series
accesses 33th line and
the S1D15608 Series
accesses 55th line, the
S1D15609 Series
accesses 53 lines.
Figure 4
8–28
EPSON
Rev. 2.4a
S1D15605 Series
Display Timing Generator Circuit
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily
stores the display data that is output to the liquid crystal
driver circuit from the display data RAM.
Because the display normal/reverse status, display ON/
OFF status, and display all points ON/OFF commands
control only the data within the latch, they do not change
the data within the display data RAM itself.
The display timing generator circuit generates the timing
signal to the line address circuit and the display data
latch circuit using the display clock. The display data is
latched into the display data latch circuit synchronized
with the display clock, and is output to the data driver
output terminal. Reading to the display data liquid
crystal driver circuits is completely independent of
accesses to the display data RAM by the MPU.
Consequently, even if the display data RAM is accessed
asynchronously during liquid crystal display, there is
absolutely no adverse effect (such as flickering) on the
display.
Moreover, the display timing generator circuit generates
the common timing and the liquid crystal alternating
current signal (FR) from the display clock. It generates
a drive wave form using a 2 frame alternating current
drive method, as is shown in Figure 5, for the liquid
crystal drive circuit.
The Oscillator Circuit
This is a CR-type oscillator that produces the display
clock. The oscillator circuit is only enabled when M/S
= HIGH and CLS = HIGH.
When CLS = LOW the oscillation stops, and the display
clock is input through the CL terminal.
Two-frame alternating current drive wave form (S1D15605*****)
64 65
1
2
3
4
5
6
60 61 62 63 64 65
1
2
3
4
5
6
CL
FR
V
V
DD
1
COM0
COM1
V
V
4
5
V
V
DD
1
V
V
4
5
RAM
DATA
V
V
V
V
DD
2
SEGn
3
5
Figure 5
Rev. 2.4a
EPSON
8–29
S1D15605 Series
When multiple S1D15605 Series chips are used, the
slave chips must be supplied the display timing signals
(FR, CL, DOF) from the master chip[s].
Table 5 shows the status of the FR, CL, and DOF
signals.
Table 5
Operating Mode
FR
CL
DOF
Master (M/S = HIGH) The internal oscillator circuit is enabled (CLS = HIGH) Output Output Output
The internal oscillator circuit is disabled (CLS = LOW) Output Input
Output
Slave (M/S = LOW) Set the CLS pin to the same level as with the master. Input
Input
Input
Input
Input
Input
The Common Output Status Select
Circuit
In the S1D15605 Series chips, the COM output scan
direction can be selected by the common output status
select command. (See Table 6.) Consequently, the
constraints in IC layout at the time of LCD module
assembly can be minimized.
Table 6
Status
COM Scan Direction
S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609*****
Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51
Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0
The Liquid Crystal Driver Circuits
These are a 197-channel (S1D15605 Series), a 181-
channel (S1D15606 Series) multiplexers 165-channel
(S1D15607 Series), 187-channel (S1D15608 Series)
and a 185-channel (S1D15609 Series) that generate
four voltage levels for driving the liquid crystal. The
combination of the display data, the COM scan signal,
and the FR signal produces the liquid crystal drive
voltage output.
Figure 6 shows examples of the SEG and COM output
wave form.
8–30
EPSON
Rev. 2.4a
S1D15605 Series
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
V
V
DD
SS
FR
V
V
V
DD
1
2
COM0
COM1
COM2
V3
V4
V5
V
V
V
DD
1
2
COM8
V3
V4
V5
COM9
COM10
COM11
COM12
COM13
COM14
COM15
V
V
V
DD
1
2
V3
V4
V5
V
V
V
DD
1
2
SEG0
SEG1
SEG2
V
V
V
3
4
5
V
V
V
DD
1
2
V3
V4
V5
V
V
V
DD
1
2
V3
V4
V5
V5
V4
V3
V
V
V
2
1
∞
COM0–SEG0
–V
1
2
–V
–V3
–V4
–V5
V5
V4
V3
V
V
V
2
1
COM0–SEG1
∞
–V
1
2
–V
–V3
–V4
–V5
Figure 6
Rev. 2.4a
EPSON
8–31
S1D15605 Series
operation.
The power supply circuits can turn the Booster circuits,
the voltage regulator circuits, and the voltage follower
circuits ON of OFF independently through the use of the
Power Control Set command. Consequently, it is possible
to make an external power supply and the internal
power supply function somewhat in parallel. Table 7
shows the Power Control Set Command 3-bit data
control function, and Table 8 shows reference
combinations.
The Power Supply Circuits
The power supply circuits are low-power consumption
power supply circuits that generate the voltage levels
required for the liquid crystal drivers. They comprise
Booster circuits, voltage regulator circuits, and voltage
follower circuits. They are only enabled in master
Table 7 The Control Details of Each Bit of the Power Control Set Command
Status
Item
“1”
“0”
D2 Booster circuit control bit
D1 Voltage regulator circuit (V regulator circuit) control bit
D0 Voltage follower circuit (V/F circuit) control bit
ON
ON
ON
OFF
OFF
OFF
Table 8 Reference Combinations
Step-up
voltage
system
terminal
V
External
voltage
input
Step-up
circuit
V/F
circuit
Use Settings
D2 D1 D0
regulator
circuit
1
2
Only the internal power supply is
used
Only the V regulator circuit and
the V/F circuit are used
Only the V/F circuit is used
Only the external power supply is
used
1
0
1
1
1
1
O
X
O
O
O
O
VSS2
Used
VOUT, VSS2 Open
3
4
0
0
0
0
1
0
X
X
X
X
O
X
V5, VSS2
V1 to V5
Open
Open
* The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–.
* While other combinations, not shown above, are also possible, these combinations are not recommended
because they have no practical use.
difference between VDD and VSS2.
Double step-up:
Connect capacitor C1 between
The Step-up Voltage Circuits
CAP1+ and CAP1–, and between VSS2 and
VOUT, leave CAP2+ open, and short
between CAP2–, CAP3– and VOUT to
produce a voltage in the negative direction
at the VOUT terminal that is twice the voltage
between VDD and VSS2.
Using the step-up voltage circuits equipped within the
S1D15605 Series chips it is possible to product a Quad
step-up, a Triple step-up, and a Double step-up of the
VDD – VSS2 voltage levels.
Quad step-up: Connect capacitor C1 between CAP1+
and CAP1–, between CAP2+ and CAP2–,
between CAP1+ and CAP3–, and between
VSS2 and VOUT, to produce a voltage level
in the negative direction at the VOUT
terminal that is 4 times the voltage level
between VDD and VSS2.
The step-up voltage relationships are shown in Figure 7.
Triple step-up: Connect capacitor C1 between CAP1+
and CAP1–, between CAP2+ and CAP2–
and between VSS2 and VOUT, and short
between CAP3– and VOUT to produce a
voltage level in the negative direction at the
VOUT terminal that is 3 times the voltage
8–32
EPSON
Rev. 2.4a
S1D15605 Series
V
SS2
V
V
SS2
V
SS2
+
+
+
+
C1
C1
C1
C1
VOUT
OUT
VOUT
CAP3–
CAP1+
CAP3–
CAP1+
CAP3–
CAP1+
C1
C1
+
+
+
+
C1
C1
CAP1–
CAP2–
CAP1–
CAP2–
CAP1–
CAP2–
C1
CAP2+
CAP2+
OPEN CAP2+
4 x step-up voltage circuit
3 x step-up voltage circuit
2 x step-up voltage circuit
V
DD = 0V
V
V
DD = 0V
V
V
DD = 0V
SS2 = –5V
V
SS2 = –3V
SS2 = –3V
V
OUT = 3 x VSS2 = –9V
V
OUT = 2 x VSS2 = –10V
V
OUT = 4 x VSS2 = –12V
4x step-up voltage relationships
3x step-up voltage relationships
2x step-up voltage relationships
Figure 7
* The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated
value.
The Voltage Regulator Circuit
(A) When the V5 Voltage Regulator Internal
Resistors Are Used
The step-up voltage generated at VOUT outputs the
liquid crystal driver voltage V5 through the voltage
regulator circuit.
Because the S1D15605 Series chips have an internal
high-accuracy fixed voltage power supply with a 64-
level electronic volume function and internal resistors
for the V5 voltage regulator, systems can be constructed
without having to include high-accuracy voltage
regulator circuit components.
Through the use of the V5 voltage regulator internal
resistors and the electronic volume function the liquid
crystal power supply voltage V5 can be controlled by
commands alone (without adding any external resistors),
making it possible to adjust the liquid crystal display
brightness. The V5 voltage can be calculated using
equation A-1 over the range where | V5 | < | VOUT |.
Moreover, in the S1D15605 Series, three types of thermal
gradients have been prepared as VREG options: (1)
approximately -0.05%/°C (2) approximately -0.2%/°C,
and (3) external input (supplied to the VRS terminal).
Rev. 2.4a
EPSON
8–33
S1D15605 Series
Rb
Ra
V5 = 1+
VEV
Rb
Ra
α
= 1+
1–
VREG
162
α
VEV = 1−
VREG
(
)
(Equation A-1)
[
]
162
V
DD
VEV (constant voltage supply + electronic volume)
Internal Ra
Internal Rb
+
V5
–
Figure 8
VREG is the IC-internal fixed voltage supply, and its
voltage at Ta = 25°C is as shown in Table 9.
Table 9
Equipment Type
Thermal Gradient
Units
VREG
Units
(1) Internal Power Supply
(2) Internal Power Supply
(3) External Input
–0.05
–0.2
—
[%/°C ]
[%/°C ]
—
–2.1
–4.9
VRS
[V]
[V]
[V]
α is set to 1 level of 64 possible levels by the electronic
volume function depending on the data set in the 6-bit
electronic volume register. Table 10 shows the value for
α depending on the electronic volume register settings.
Table 10
Rb/Ra is the V5 voltage regulator internal resistor ratio,
and can be set to 8 different levels through the V5
voltage regulator internal resistor ratio set command.
The (1 + Rb/Ra) ratio assumes the values shown in
Table 11 depending on the 3-bit data settings in the V5
voltage regulator internal resistor ratio register.
D5 D4 D3 D2 D1 D0
α
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
63
62
61
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
2
1
0
8–34
EPSON
Rev. 2.4a
S1D15605 Series
V5 voltage regulator internal resistance ratio register
value and (1 + Rb/Ra) ratio (Reference value)
Table 11
S1D15605*****
S1D15606*****
Register
Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ]
D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input (1) –0.05 (2) –0.2 (3) VREG External Input
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.4
1.3
1.5
1.8
2.0
2.3
2.5
2.8
3.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
3.0
3.5
4.0
4.5
5.0
5.4
5.9
6.4
1.3
1.5
1.8
2.0
2.3
2.5
2.8
3.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
S1D15607*****
S1D15608*****/S1D15609*****
Register
Equipment Type by Thermal Gradient [Units: %/
°
C ] Equipment Type by Thermal Gradient [Units: %/°C ]
D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input
–0.05
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.0
3.5
4.0
4.5
5.0
5.4
5.9
6.4
1.3
1.5
1.8
2.0
2.3
2.5
2.8
3.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
3
3.5
4
4.5
5
5.4
5.9
6.4
For the internal resistance ratio, a manufacturing
dispersion of up to ±7% should be taken into account.
When not within the tolerance, adjust the V5 voltage by
externally mounting Ra and Rb.
Figs. 9, 10, 11 (for S1D15605 Series), 12, 13, 14 (for
S1D15606 Series), 15, 16, 17 (for S1D15607 Series), 18
(for S1D15608D00B ) and Figs. 19 (for
*
S1D15609D00B ) show V5 voltage measured by values
*
of the internal resistance ratio resistor for V5 voltage
adjustment and electric volume resister for each
temperature grade model, when Ta = 25 °C.
Rev. 2.4a
EPSON
8–35
S1D15605 Series
S1D15605D00B /S1D15605D11B
*
*
–16
–15
–14
–13
–12
–11
–10
–9
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
–8
–7
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
–3
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 9: S1D15605D00B /S1D15605D11B (1) For Models Where the Thermal Gradient = -0.05%/°C
*
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15605D01B
*
–16
1 1 1
–15
–14
–13
–12
–11
–10
–9
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
–8
–7
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
–3
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 10: S1D15605D01B (2) For Models Where the Thermal Gradient = -0.2%/°C
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
8–36
EPSON
Rev. 2.4a
S1D15605 Series
S1D15605D02B
–16
–15
–14
–13
–12
–11
–10
–9
*
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
–8
–7
0 0 1
0 0 0
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
–3
–2
–1
(D2, D1, D0)
0
Electric Volume
Resister
Figure 11: S1D15605D02B (3) For models with External Input
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15606D00B /S1D15606D11B
*
*
–16
–15
–14
–13
–12
–11
–10
–9
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
–8
–7
–6
–5
The V5 voltage
–4
regulator internal
resistance ratio
registers
–3
(D2, D1, D0)
–2
–1
0
Electric Volume
Resister
Figure 12: S1D15606D00B /S1D15606D11B (1) For Models Where the Thermal Gradient = -0.05%/°C
*
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
Rev. 2.4a
EPSON
8–37
S1D15605 Series
S1D15606D01B
–16
–15
–14
–13
–12
–11
–10
–9
*
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
–8
–7
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
–3
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 13: S1D15606D01B (2) For Models Where the Thermal Gradient = -0.2%/°C
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15606D02B
–16
–15
–14
–13
–12
–11
–10
–9
*
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
–8
–7
0 0 1
0 0 0
–6
–5
–4
The V5 voltage
–3
regulator internal
resistance ratio
registers
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 14: S1D15606D02B (3) For models with External Input
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
8–38
EPSON
Rev. 2.4a
S1D15605 Series
S1D15607D00B /S1D15607D11B
–16
–15
–14
–13
–12
–11
–10
–9
*
*
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
–8
–7
0 0 0
–6
–5
The V5 voltage
–4
regulator internal
resistance ratio
registers
–3
(D2, D1, D0)
–2
–1
0
Electric Volume
Resister
Figure 15: S1D15607D00B /S1D15607D11B (1) For Models Where the Thermal Gradient = -0.05%/°C
*
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15607D01B
–16
–15
–14
–13
–12
–11
–10
–9
*
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
–8
–7
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
–3
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 16: S1D15607D01B (2) For Models Where the Thermal Gradient = -0.2%/°C
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
Rev. 2.4a
EPSON
8–39
S1D15605 Series
S1D15607D02B
–16
–15
–14
–13
–12
–11
–10
–9
*
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
–8
0 1 0
0 0 1
0 0 0
–7
–6
–5
–4
The V5 voltage
–3
regulator internal
resistance ratio
registers
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 17: S1D15607D02B (3) For models with External Input
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
S1D15608D00B
–16
–15
–14
–13
–12
–11
–10
–9
*
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
–8
0 1 0
0 0 1
0 0 0
–7
–6
–5
–4
The V5 voltage
–3
regulator internal
resistance ratio
registers
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 18: S1D15608D00B (1) For Models Where the Thermal Gradient = –0.05%/°C
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
8–40
EPSON
Rev. 2.4a
S1D15605 Series
S1D15609D00B
*
–16
–15
–14
–13
–12
–11
–10
–9
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
–8
0 1 0
0 0 1
0 0 0
–7
–6
–5
–4
The V5 voltage
regulator internal
resistance ratio
registers
–3
–2
(D2, D1, D0)
–1
0
Electric Volume
Resister
Figure 19: S1D15609D00B Temperature Gradient = –0.05%/°C Model
*
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic
volume register.
Setup example: When selecting Ta = 25°C and V5 = 7
V for an S1D15607 model on which Temperature
gradient = –0.05%/°C.
At this time, the variable range and the notch width of
the V5 voltage is, as shown Table 13, as dependent on
the electronic volume.
Using Figure 15 and the equation A-1, the following
setup is enabled.
Table 12
Register
Contents
D5 D4 D3 D2 D1 D0
For V5 voltage
regulator
Electronic Volume
—
1
—
0
—
0
0
1
1
0
0
1
Table 13
Typ.
V5
Min.
Max.
Units
Variable Range
Notch width
–8.4 (63 levels)
–6.8 (central value) –5.1 (0 level)
51
[V]
[mV]
Rev. 2.4a
EPSON
8–41
S1D15605 Series
respectively. When this is done, the use of the electronic
volume function makes it possible to adjust the brightness
of the liquid crystal display by controlling the liquid
crystal power supply voltage V5 through commands.
In the range where | V5 | < | VOUT |, the V5 voltage can
be calculated using equation B-1 based on the external
resistances Ra’ and Rb’.
(B) When an External Resistance is Used
(i.e., The V5 Voltage Regulator Internal
Resistors Are Not Used) (1)
The liquid crystal power supply voltage V5 can also be
set without using the V5 voltage regulator internal
resistors (IRS terminal = LOW) by adding resistors Ra’
and Rb’ between VDD and VR, and between VR and V5,
Rb'
V5 = 1+
= 1+
VEV
Ra'
Rb'
Ra'
α
1–
VREG
162
α
VEV = 1−
VREG
(
)
( Equation B-1)
[
]
162
V
DD
V
EV (fixed voltage power supply + electronic volume)
External
resistor Ra'
+
V
5
–
External
resistor Rb'
Figure 20
Setup example: When selecting Ta = 25°C and V5 = –
7 V for an S1D15607 Series model where the temperature
gradient = –0.05%/°C.
When the central value of the electron volume register
is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α
= 31 and VREG = –2.1 V so, according to equation B-1,
Consequently, by equations B-2 and B-3,
Rb'
= 3.12
Ra'
Ra' = 340kΩ
Rb' = 1060kΩ
Rb'
Ra'
α
V5 = 1+
1−
1−
VREG
−2.1
At this time, the V5 voltage variable range and notch
width, based on the electron volume function, is as
given in Table 14.
162
Rb'
Ra'
31
−11V = 1+
(
)
(Equation B-2)
162
Moreover, when the value of the current running through
Ra’ and Rb’ is set to 5 µA,
(Equation B-3)
Table 14
Typ.
Ra' +Rb' = 1.4MΩ
V5
Min.
Max.
Units
Variable Range
Notch width
–8.6 (63 levels)
–7.0 (central value) –5.3 (0 level)
52
[V]
[mV]
8–42
EPSON
Rev. 2.4a
S1D15605 Series
the electronic volume function makes it possible to
control the liquid crystal power supply voltage V5 by
commands to adjust the liquid crystal display brightness.
In the range where | V5 | < | VOUT | the V5 voltage can
be calculated by equation C-1 below based on the R1
and R2 (variable resistor) and R3 settings, where R2 can
be subjected to fine adjustments (∆ R2).
(C) When External Resistors are Used
(i.e. The V5 Voltage Regulator Internal
Resistors Are Not Used). (2)
When the external resistor described above are used,
adding a variable resistor as well makes it possible to
perform fine adjustments on Ra’ and Rb’, to set the
liquid crystal drive voltage V5. In this case, the use of
R3 + R2 − ∆R2
V5 = 1+
= 1+
VEV
R1 + ∆R2
R3 + R2 − ∆R2
R1 + ∆R2
α
1–
VREG
162
α
VEV = 1−
VREG
(Equation C-1)
(
)
[
]
162
V
DD
V
EV (fixed voltage supply + electronic volume)
External
resistor R
Ra'
1
+
V5
∆R2
External
resistor R
–
2
VR
External
resistor R
Rb'
3
Figure 21
When ∆ R2 = R2, in order to make V = –5 V,
Setup example: When selecting Ta = 25°C and V5 = –
5 to –9 V (using R2) for an S1D15607 model where the
temperature gradient = –0.05%/°C.
R3
31
−5V = 1 +
1 −
−2.1
(
)
R + R2
162
1
When the central value for the electronic volume register
is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0),
(Equation C-3)
Moreover, when the current flowing VDD and V5 is set
α
= 31
to 5 µA,
VREG = −2.1V
R + R2 + R3 = 1.4MΩ
(Equation C-4)
1
so, according to equation C-1, when ∆ R2 = 0 Ω, in order
to make V5 = –9 V,
With this, according to equation C-2, C-3 and C-4,
R
= 264kΩ
1
R3 + R2
31
−9V = 1 +
1 −
−2.1
(
)
R2 = 211kΩ
R3 = 925kΩ
R
162
1
(Equation C-2)
At this time, the V5 voltage variable range and notch
width based on the electron volume function is as shown
in Table 15.
Table 15
Typ.
V5
Min.
Max.
Units
Variable Range
Notch width
–8.7 (63 levels)
–7.0 (central value) –5.3 (0 level)
53
[V]
[mV]
Rev. 2.4a
EPSON
8–43
S1D15605 Series
* When the V5 voltage regulator internal resistors or
the electronic volume function is used, it is necessary
to at least set the voltage regulator circuit and the
voltage follower circuit to an operating mode using
the power control set commands. Moreover, it is
necessary to provide a voltage from VOUT when the
Booster circuit is OFF.
* The VR terminal is enabled only when the V5 voltage
regulator internal resistors are not uesd (i.e. the IRS
terminal = LOW). When the V5 voltage regulator
internal resistors are uesd (i.e. when the IRS terminal
= HIGH), then the VR terminal is left open.
High Power Mode
The power supply circuit equipped in the S1D15605
Series chips has very low power consumption (normal
mode: HPM = HIGH). However, for LCDs or panels
with large loads, this low-power power supply may
cause display quality to degrade. When this occurs,
setting the HPM terminal to LOW (high power mode)
can improve the quality of the display. We recommend
that the display be checked on actual equipment to
determine whether or not to use this mode.
Moreover, if the improvement to the display is inadequate
even after high power mode has been set, then it is
necessary to add a liquid crystal drive power supply
externally.
* Because the input impedance of the VR terminal is
high, it is necessary to take into consideration short
leads, shield cables, etc. to handle noise.
The Internal Power Supply Shutdown
Command Sequence
The Liquid Crystal Voltage Generator Circuit
The V5 voltage is produced by a resistive voltage
divider within the IC, and can be produced at the V1, V2,
V3, and V4 voltage levels required for liquid crystal
driving. Moreover, when the voltage follower changes
the impedance, it provides V1, V2, V3 and V4 to the
liquid crystal drive circuit. 1/9 bias or 1/7 bias for
S1D15605 Series, 1/8 bias or 1/6 bias for S1D15606
Series, 1/6 bias or 1/5 bias for the S1D15607 Series, 1/
8 bias or 1/6 bias for S1D15608 Series and 1/8 bias or
1/6 bias for S1D15609 Series can be selected.
The sequence shown in Figure 22 is recommended for
shutting down the internal power supply, first placing
the power supply in power saver mode and then turning
the power supply OFF.
Sequence
Details
(Command, status)
Command address
D7 D6 D5 D4 D3 D2 D1 D0
Power saver
commands
(compound)
Step1
Step2
End
Display OFF
1
1
0
0
1
1
0
0
1
0
1
1
1
0
0
1
Display all points ON
Internal power supply OFF
Figure 22
8–44
EPSON
Rev. 2.4a
S1D15605 Series
Reference Circuit Examples
Figure 22 shows reference circuit examples.
➀ When used all of the step-up circuit, voltage regulating circuit and V/F circuit
(1) When the voltage regulator internal resistor
is used.
(2) When the voltage regulator internal resistor
is not used.
(Example where VSS2 = VSS, with 4x step-up)
(Example where VSS2 = VSS, with 4x step-up)
V
V
DD
VDD
IRS M/S
IRS M/S
V
V
SS2
V
V
SS2
C
1
C
1
OUT
OUT
SS
V
V
SS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
C
C
1
1
C
C
1
1
C1
C1
R
R
R
3
2
1
V
5
V
V
5
V
R
R
V
DD
DD
V
V
V
V
V
V
DD
V
V
V
V
V
V
DD
1
C2
C2
C2
C2
C2
C
C
C
C
C
2
2
2
2
2
1
2
2
3
3
4
4
5
5
➁ When the voltage regulator circuit and V/F
circuit alone are used
(2) When the V
is used.
5
voltage regulator internal resistor
(1) When the V
5
voltage regulator internal resistor
is not used.
V
DD
VDD
IRS M/S
IRS M/S
VSS2
V
SS2
V
OUT
V
OUT
V
V
SS
V
SS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
External
power
supply
External
power
supply
R3
R2
R1
V5
V5
VR
VR
DD
VDD
V
V
V
V
V
V
DD
V
V
V
V
V
V
DD
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
1
1
2
2
3
3
4
4
5
5
Rev. 2.4a
EPSON
8–45
S1D15605 Series
➂ When the V/F circuit alone is used
➃ When the built-in power is not used
VDD
VSS
V
DD
IRS M/S
IRS M/S
V
V
SS2
V
V
SS2
OUT
OUT
VSS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
External
power
supply
V
V
5
V
V
5
R
R
V
DD
VDD
V
V
V
V
V
V
DD
1
V
V
V
V
V
V
DD
1
C2
C2
C2
C2
C2
2
2
External
power
supply
3
3
4
4
5
5
5 When the built-in power circuit is used to drive a
liquid crystal panel heavily loaded with AC or DC, it
is recommended to connect an external resistor to
stabilize potentials of V1, V2, V3 and V4 which are
output from the built-in voltage follower.
Examples of shared reference settings
When V5 can vary between –8 and 12 V
Item
Set value
Units
C1
C2
1.0 to 4.7
0.01 to 1.0
µF
µF
V
DD, V0
R4
R4
C2
V
V
V
V
1
2
3
4
Reference set value R4: 100kΩ ~ 1MΩ
It is recommended to set an optimum
resistance value R4 taking the liquid crystal
display and the drive waveform.
R4
R4
V
5
Figure 23
* 1 Because the VR terminal input impedance is high, use short leads and shielded lines.
* 2 C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal
drive voltage.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that
stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance
value.
• Next turn all the power supplies ON and determine C1.
8–46
EPSON
Rev. 2.4a
S1D15605 Series
* Precautions when installing the COG
the resistance of ITO wiring is being inserted in
series with the switching transistor, thus dominating
the boosting ability.
Consequently, the boosting ability will be hindered
as a result and pay sufficient attention to the wiring
to respective boosting capacitors.
When installing the COG, it is necessary to duly consider
the fact that there exists a resistance of the ITO wiring
occurring between the driver chip and the externally
connected parts (such as capacitors and resistors). By the
influence of this resistance, non-conformity may occur
with the indications on the liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the driver
chip pin to the externally connected parts as much as
possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
2. Connection of the smoothing capacitors for the
liquid crystal drive
The smoothing capacitors for the liquid crystal
driving potentials (V1. V2, V3 and V4) are
indispensable for liquid crystal drives not only for
the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs
pursuant to installation of the COG is supplemented
to these smoothing capacitors, the liquid crystal
driving potentials become unstable to cause non-
conformity with the indications of the liquid crystal
display. Therefore, when using the COG module,
we definitely recommend to connect reinforcing
resistors externally.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
Also, as for this driver IC, pay sufficient attention to the
following points when connecting to external parts for
the characteristics of the circuit.
1. Connection to the boosting capacitors The boosting
capacitors (the capacitors connecting to respective
CAP pins and capacitor being inserted between
VOUT and VSS2) of this IC are being switched over
by use of the transistor with very low ON-resistance
of about 10Ω. However, when installing the COG,
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these
reinforcing resistors, current consumption will
increase.
Indicated below is an exemplary connection diagram of
external resistors.
Please make sufficient evaluation work for the display
statuses with any connection tests.
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
VDD
V
DD
V
DD
R4
R4
V
V
V
1
2
3
V
V
V
1
2
3
C2
C2
C2
C2
C2
C2
R4
R4
V
V
4
5
V
V
4
5
C
2
2
C
2
2
R4
R4
C
C
Rev. 2.4a
EPSON
8–47
S1D15605 Series
The Reset Circuit
When the RES input comes to the LOW level, these
LSIs return to the default state. Their default states are
as follows:
On the other hand, when the reset command is used, the
above default settings from 11 to 19 are only executed.
When the power is turned on, the IC internal state
becomes unstable, and it is necessary to initialize it
using the RES terminal. After the initialization, each
input terminal should be controlled normally.
Moreover, when the control signal from the MPU is in
the high impedance, an overcurrent may flow to the IC.
After applying a current, it is necessary to take proper
measures to prevent the input terminal from getting into
the high impedance state.
1. Display OFF
2. Normal display
3. ADC select: Normal (ADC command D0 = LOW)
4. Power control register: (D2, D1, D0) = (0, 0, 0)
5. Serial interface internal register data clear
6.
LCD power supply b.i.a.s..r.a.t.e..:.............. 1/9 bias
S1D15605*****
S1D15606*****, 15608*****, 15609*****
If the internal liquid crystal power supply circuit is not
used on S1D15605D11B , S1D15606D11B ,
................................................................................ 11//68 bbiiaass
*
*
S1D15607*********
S1D15607D11B , S1D15608D11B
and
*
*
7. All-indicator lamps-on OFF (All-indicator lamps
ON/OFF command D0 = LOW)
S1D15609D11B , it is necessary that RES is HIGH
*
when the external liquid crystal power supply is turned
on. This IC has the function to discharge V5 when RES
is LOW, and the external power supply short-circuits to
VDD when RES is LOW.
8. Power saving clear
9. V5 voltage regulator internal resistors Ra and Rb
separation
(In case of S1D15605D11B , S1D15606D11B ,
S1D15607D11B , S1D15608D11B and
*
*
While RES is LOW, the oscillator and the display
timing generator stop, and the CL, FR, FRS and DOF
terminals are fixed to HIGH. The terminals D0 to D7
are not affected. The VDD level is output from the SEG
and COM output terminals. This means that an internal
resistor is connected between VDD and V5.
When the internal liquid crystal power supply circuit is
not used on other models of S1D15605 series, it is
necessary that RE is LOWwhen the external liquid
crystal power supply is turned on.
*
*
S1D15609D11B , internal resistors are connected
*
while RES is LOW.)
10. Output conditions of SEG and COM terminals
SEG : V2/V3, COM : V1/V4
(In case of S1D15605D11B , S1D15606D11B ,
S1D15607D11B , S1D15608D11B and
*
*
*
*
S1D15609D11B , both the SEG terminal and the
*
COM terminal output the VDA level while RES is
LOW. In case of other models, the SEG terminal
outputs V2 and the COM terminal outputs V1 while
RES is LOW.)
While RES is LOW, the oscillator works but the display
timing generator stops, and the CL, FR, FRS and DOF
terminals are fixed to HIGH. The terminals D0 to D7
are not affected.
11. Read modify write OFF
12. Static indicator OFF
Static indicator register : (D1, D2) = (0, 0)
13. Display start line set to first line
14. Column address set to Address 0
15. Page address set to Page 0
16. Common output status normal
17. V5 voltage regulator internal resistor ratio set mode
clear
18. Electronic volume register set mode clear
Electronic volume register : (D5, D4, D3, D2, D1,
D0) = (1, 0. 0, 0, 0, 0)
19. Test mode clear
8–48
EPSON
Rev. 2.4a
S1D15605 Series
7. COMMANDS
The S1D15605 Series chips identify the data bus signals by a combination of A0, RD (E), WR (R/W) signals. Command
interpretation and execution does not depend on the external clock, but rather is performed through internal timing only,
and thus the processing is fast enough that normally a busy check is not required.
In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and
inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read
mode when an HIGH signal is input to the R/W terminal and placed in a write mode when a LOW signal is input to the
R/W terminal and then the command is launched by inputting a high pulse to the E terminal. (See “10. Timing
Characteristics” regarding the timing.) Consequently, the 6800 Series MPU interface is different than the 80x86 Series
MPU interface in that in the explanation of commands and the display commands the status read and display data read
RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface
as the example.
When the serial interface is selected, the data is input in sequence starting with D7.
<Explanation of Commands>
(1) Display ON/OFF
This command turns the display ON and OFF.
E
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
0
1
0
1
0
1
0
1
1
1
1
0
Display ON
Display OFF
When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See
the section on the power saver for details.
(2) Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further
details see the explanation of this function in “The Line Address Circuit”.
E
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Line address
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
↓
↓
1
1
1
1
1
1
1
1
1
1
0
1
62
63
(3) Page Address Set
This command specifies the page address corresponding to the low address when the MPU accesses the display data
RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data
RAM. Changing the page address does not accompany a change in the status display. See the page address circuit in
the Function Description (page 1–20) for the detail.
E
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Page address
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
↓
↓
0
1
1
0
1
0
1
0
7
8
Rev. 2.4a
EPSON
8–49
S1D15605 Series
(4) Column Address Set
This command specifies the column address of the display data RAM shown in Figure 4. The column address is split
into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the
display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to
continuously read from/write to the display data. The column address increment is topped at 83H. This does not change
the page address continuously. See the function explanation in “The Column Address Circuit,” for details.
E
R/W
Column
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 address
HIGH bits →
LOW bits →
0
1
0
0
0
0
1 A7 A6 A5 A4 0
0 A3 A2 A1 A0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
↓
↓
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
130
131
(5) Status Read
R/W
E
A0 RD WR
D7
BUSY
D6
D5
D4
D3 D2 D1 D0
0
0
1
ADC ON/OFF RESET
0
0
0
0
BUSY
When BUSY = 1, it indicates that either processing is occurring internally or a reset condition
is in process. While the chip does not accept commands until BUSY = 0, if the cycle time can
be satisfied, there is no need to check for BUSY conditions.
ADC
This shows the relationship between the column address and the segment driver.
0: Reverse (column address 131-n ↔ SEG n)
1: Normal (column address n ↔ SEG n)
(The ADC command switches the polarity.)
ON/OFF ON/OFF: indicates the display ON/OFF state.
0: Display ON
1: Display OFF
(This display ON/OFF command switches the polarity.)
RESET
This indicates that the chip is in the process of initialization either because of a RES signal or
because of a reset command.
0: Operating state
1: Reset in progress
(6) Display Data Write
This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically
incremented by “1” after the write, the MPU can write the display data.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
Write data
(7) Display Data Read
This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically
incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required
immediately after the column address has been set. See the function explanation in “Display Data RAM” for the
explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes
unavailable.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
Read Data
8–50
EPSON
Rev. 2.4a
S1D15605 Series
(8) ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence between the display RAM data column address and the segment driver
output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address
circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the
display data is done according to the column address indicated in Figure 4.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
0
1
0
1
0
1
0
0
0
0
0
1
Normal
Reverse
(9) Display Normal/Reverse
This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When
this is done the display data RAM contents are maintained.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
0
1
0
1
0
1
0
0
1
1
0
RAM Data HIGH
LCD ON voltage (normal)
RAM Data LOW
1
LCD ON voltage (reverse)
(10) Display All Points ON/OFF
This command makes it possible to force all display points ON regardless of the content of the display data RAM. The
contents of the display data RAM are maintained when this is done. This command takes priority over the display
normal/reverse command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
0
1
0
1
0
1
0
0
1
0
0
1
Normal display mode
Display all points ON
When the display is in an OFF mode, executing the display all points ON command will place the display in power save
mode. For details, see the (20) Power Save section.
(11) LCD Bias Set
This command selects the voltage bias ratio required for the liquid crystal display. This command can be valid while
the V/F circuit of Power Supply circuit is in operation.
E R/W
Select Status
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609*****
0
1
0
1
0
1
0
0
0
1
0
1
1/9 bias
1/7 bias
1/8 bias
1/6 bias
1/6 bias
1/5 bias
1/8 bias
1/6 bias
1/8 bias
1/6 bias
(12) Read/Modify/Write
This command is used paired with the “END” command. Once this command has been input, the display data read
command does not change the column address, but only the display data write command increments (+1) the column
address. This mode is maintained until the END command is input. When the END command is input, the column
address returns to the address it was at when the read/modify/write command was entered. This function makes it
possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when
there is a blanking cursor.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
0
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
However, the column address set command cannot be used.
Rev. 2.4a
EPSON
8–51
S1D15605 Series
• The sequence for cursor display
Page address set
Column address set
Read/modify/write
Dummy read
Data read
Data process
Data write
No
Change complete?
Yes
End
Figure 24
(13) End
This command releases the read/modify/write mode, and returns the column address to the address it was at when the
mode was entered.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
• • •
N+m
N
Read/modify/write mode set
End
Figure 25
(14) Reset
This command initializes the display start line, the column address, the page address, the common output mode, the V5
voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/
write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in
“Reset” for details.
The reset operation is performed after the reset command is entered.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
0
The initialization when the power supply is applied must be done through applying a reset signal to the RES terminal.
The reset command must not be used instead.
8–52
EPSON
Rev. 2.4a
S1D15605 Series
(15) Common Output Mode Select
This command can select the scan direction of the COM output terminal. For details, see the function explanation in
“Common Output Mode Select Circuit.”
E
R/W
Selected Mode
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609*****
Normal COM0→COM63COM0→COM47 COM0→COM31 COM0→COM53COM0→COM51
Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0
0
1
0
1
1
0
0
0
1
*
*
*
* Disabled bit
(16) Power Controller Set
This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,”
for details
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Selected Mode
0
1
0
0
0
1
0
1
0
1
Booster circuit: OFF
Booster circuit: ON
0
1
Voltage regulator circuit: OFF
Voltage regulator circuit: ON
0
1
Voltage follower circuit: OFF
Voltage follower circuit: ON
[Translator’s Note: the abbreviations explained within these parentheses for V
and V/F have been written out in the English translation and are therefore no
longer necessary.]
(17) V5 Voltage Regulator Internal Resistor Ratio Set
This command sets the V5 voltage regulator internal resistor ratio. For details, see the function explanation is “The
Power Supply Circuits.”
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Rb/Ra Ratio
0
1
0
0
0
1
0
0
0
0
0
0
0
1
↓
0
1
0
Small
↓
1
1
1
1
0
1
Large
(18) The Electronic Volume (Double Byte Command)
This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal
drive voltage V5 through the output from the voltage regulator circuits of the internal liquid crystal power supply.
This command is a two byte command used as a pair with the electronic volume mode set command and the electronic
volume register set command, and both commands must be issued one after the other.
• The Electronic Volume Mode Set
When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume
mode has been set, no other command except for the electronic volume register command can be used. Once the
electronic volume register set command has been used to set data into the register, then the electronic volume mode is
released.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0
0
0
0
0
1
Rev. 2.4a
EPSON
8–53
S1D15605 Series
• Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes
one of the 64 voltage levels.
When this command is input, the electronic volume mode is released after the electronic volume register has been set.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
| V5 |
0
0
0
1
1
1
0
0
0
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Small
↓
↓
0
0
1
1
0
0
*
*
*
*
1
1
1
1
1
1
1
1
1
1
0
1
Large
* Inactive bit
When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)
• The Electronic Volume Register Set Sequence
Electronic volume mode set
Electronic volume register set
Electronic volume mode clear
No
Changes complete?
Yes
Figure 26
(19) Static Indicator (Double Byte Command)
This command controls the static drive system indicator display. The static indicator display is controlled by this
command only, and is independent of other display control commands.
This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other
is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the
dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the
electrodes.
The static indicator ON command is a double byte command paired with the static indicator register set command, and
thus one must execute one after the other. (The static indicator OFF command is a single byte command.)
• Static Indicator ON/OFF
When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static
indicator ON command has been entered, no other command aside from the static indicator register set command can
be used. This mode is cleared when data is set in the register by the static indicator register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Static Indicator
0
1
0
1
0
1
0
1
1
0
0
1
OFF
ON
8–54
EPSON
Rev. 2.4a
S1D15605 Series
• Static Indicator Register Set
This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking
mode.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Indicator Display State
0
1
0
*
*
*
*
*
*
0
0
1
1
0
1
0
1
OFF
ON (blinking at approximately one second intervals)
ON (blinking at approximately 0.5 second intervals)
ON (constantly on)
* Disabled bit
• Static Indicator Register Set Sequence
Static indicator mode set
Static indicator register set
Static indicator
mode clear
No
Changes complete?
Yes
Figure 27
(20) Power Save (Compound Command)
When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered,
thus greatly reducing power consumption.
The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF,
it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered.
In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before
the power saver mode was initiated, and the MPU is still able to access the display data RAM.
Refer to figure 28 for power save off sequence.
Static indicator OFF
Static indicator ON
Power saver (compound command)
Sleep mode
Standby mode
Power save OFF (compound command)
Display all points OFF command
Static indicator ON
Power save OFF
(Display all points OFF command)
(2 bytes command)
Sleep mode cancel
Standby mode cancel
Figure 28
Rev. 2.4a
EPSON
8–55
S1D15605 Series
• Sleep Mode
This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption
current is reduced to a value near the static current. The internal modes during sleep mode are as follows:
1 The oscillator circuit and the LCD power supply circuit are halted.
2 All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level.
• Standby Mode
The duty LCD display system operations are halted and only the static drive system for the indicator continues to
operate, providing the minimum required consumption current for the static drive. The internal modes are in the
following states during standby mode.
1 The LCD power supply circuits are halted. The oscillator circuit continues to operate.
2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output
a VDD level. The static drive system does not operate.
When a reset command is performed while in standby mode, the system enters sleep mode.
* When an external power supply is used, it is recommended that the functions of the external power supply circuit
be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage
are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the
electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The
S1D15605 series chips have a liquid crystal display blanking control terminal DOF. This terminal enters an LOW
state when the power saver mode is launched. Using the output of DOF, it is possible to stop the function of an external
power supply circuit.
* When the master is turned on, the oscillator circuit is operable immediately after the powering on.
(21) NOP
Non-OPeration Command
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
1
(22) Test
This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared
by applying a LOW signal to the RES input by the reset command or by using an NOP.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
1
*
*
*
*
* Inactive bit
Note: The S1D15605 Series chips maintain their operating modes until something happens to change them.
Consequently, excessive external noise, etc., can change the internal modes of the S1D15605 Series chip. Thus
in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise
from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to
prevent the effects of unanticipated noise.
8–56
EPSON
Rev. 2.4a
S1D15605 Series
Table 16 Table of S1D15605 Series Commands
Command Code
Command
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
(1) Display ON/OFF
0
1
0
1
0
1
0
1
1
1
0
1
LCD display ON/OFF
0: OFF, 1: ON
(2) Display start line set
(3) Page address set
0
1
0
0
1
Display start address
Sets the display RAM display
start line address
0
0
1
1
0
0
1
0
0
0
1
0
1
1
Page address
Sets the display RAM page
address
Sets the most significant 4 bits
of the display RAM column
address.
(4) Column address
set upper bit
Most significant
column address
Column address
set lower bit
0
1
0
0
0
0
0
Least significant
column address
Sets the least significant 4 bits of
the display RAM column address.
(5) Status read
0
1
1
0
0
1
0
1
1
0
1
0
Status
0
0
0
0
Reads the status data
(6) Display data write
(7) Display data read
(8) ADC select
Write data
Read data
Writes to the display RAM
Reads from the display RAM
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
Sets the display RAM address
SEG output correspondence
0: normal, 1: reverse
(9) Display normal/
reverse
0
0
0
1
1
1
0
0
0
0
1
Sets the LCD display normal/
reverse
0: normal, 1: reverse
(10) Display all points
ON/OFF
0
1
Display all points
0: normal display
1: all points ON
(11) LCD bias set
0
1
Sets the LCD drive voltage
bias ratio
S1D15605*****.. 0: 1/9, 1: 1/7
S1D15606*****
/S1D15608*****. 0: 1/8, 1: 1/6
/S1D15609*****
S1D15607*****.. 0: 1/6, 1: 1/5
Column address increment
At write: +1
(12) Read/modify/write
0
1
0
1
1
1
0
0
0
0
0
At read: 0
(13) End
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
*
1
1
*
0
0
*
Clear read/modify/write
Internal reset
(14) Reset
(15) Common output
mode select
0
1
Select COM output scan
direction
0: normal direction,
1: reverse direction
(16) Power control set
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
Operating
mode
Select internal power
supply operating mode
(17) V5 voltage
regulator internal
resistor ratio set
Resistor ratio
Select internal resistor ratio
(Rb/Ra) mode
(18) Electronic volume
mode set
0
0
1
1
0
0
1
*
0
*
0
0
0
0
0
1
Electronic volume
register set
Electronic volume value
Set the V5 output voltage
electronic volume register
(19) Static indicator
ON/OFF
0
0
1
1
0
0
1
*
0
*
1
*
0
*
1
*
1
*
0
0
1
0: OFF, 1: ON
Static indicator
register set
Mode
Set the flashing mode
(20) Power saver
Display OFF and display all
points ON compound command
(21) NOP
(22) Test
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
*
0
*
1
*
1
*
Command for non-operation
Command for IC test. Do not
use this command
(Note) *: disabled data
Rev. 2.4a
EPSON
8–57
S1D15605 Series
8. COMMAND DESCRIPTION
Instruction Setup: Reference (reference)
(1) Initialization
Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1
and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is
remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the
VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To
avoid occurrence of such a failure, we recommend the following flow when turning on the power.
1
When the built-in power is being used immediately after turning on the power:
Turn ON the VDD-VSS power keeping the
RES pin = LOW.
When the power is stabilized
Release the reset state. (RES pin = HIGH)
Initialized state (Default) *1
(In case of S1D15605D11B ,
*
Function setup by command input (User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
S1D15606D11B , S1D15607D11B ,
*
*
S1D15608D11B and S1D15609D11B )
*
*
Arrange to execute all the procedures
from releasing the reset state through
setting the power control within 5ms.
(In case of other models) execute the
procedures from turning on the power
to setting the power control in 5ms.
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Function setup by command input (User setup)
(16) Power control setting *7
This concludes the initialization
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.
*1: 6. Description of functions; “Resetting circuit” (If takes not more than 2 ms from Power Supply ON to
the stability of internal oscillating circuit.)
*2: 7. Command description; “(11) LCD bias setting”
*3: 7. Command description; “(8) ADC selection”
*4: 7. Command description; “(15) Common output state selection”
*5: 6. Description of functions; “Power circuit” & Command description; “(17) Setting the built-in
resistance radio for regulation of the V5 voltage”
*6: 6. Description of functions; “Power circuit” & Command description; “(18) Electronic volume control”
*7: 6. Description of functions; “Power circuit” & Command description; “(16) Power control setting”
8–58
EPSON
Rev. 2.4a
S1D15605 Series
2
When the built-in power is not being used immediately after turning on the power:
Turn ON the VDD-VSS power keeping the
RES pin = LOW.
When the power is stabilized
(In case of S1D15605D11B ,
Release the reset state. (RES pin = HIGH)
Initialized state (Default) *1
*
S1D15606D11B , S1D15607D11B ,
*
*
S1D15608D11B and S1D15609D11B )
*
*
Arrange to start the power saver within
5ms after releasing the reset state.
(In case of other models) execute the
procedures from turning on the power
to setting the power control in 5ms.
Power saver START (multiple commands) *8
Function setup by command input (User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Power saver OFF *8
Arrange to start power control
setting within 5ms after turning
OFF the power saver.
Function setup by command input (User setup)
(16) Power control setting *7
This concludes the initialization
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.
*1: 6. Description of functions; “Resetting circuit” (The contents of DDRAM can be variable even in the
initial setting (Default) at the reset state.)
*2: 7. Command description; “(11) LCD bias setting”
*3: 7. Command description; “(8) ADC selection”
*4: 7. Command description; “(15) Common output state selection”
*5: 6. Description of functions; “Power circuit” & “(17) Command description; Setting the built-in
resistance radio for regulation of the V5 voltage”
*6: 6. Description of functions; “Power circuit” & “(18) Command description; Electronic volume control”
*7: 6. Description of functions; “Power circuit” & “(16) Command description; Power control setting”
*8: 7. The power saver ON state can either be in sleep state or stand-by state.
Command description; “Power saver START (multiple commands)”
Rev. 2.4a
EPSON
8–59
S1D15605 Series
(2) Data Display
End of initialization
Function setup by command input (User setup)
(2) Display start line set *9
(3) Page address set *10
(4) Column address set *11
Notes: Reference items
*9: Command Description; Display start line set
Function setup by command input (User setup)
(6) Display data write *12
*10: Command Description; Page address set
*11: Command Description; Column address set
*12: Command Description; Display data write
*13: Command Description; Display ON/OFF
Avoid displaying all the data at the data
display start (when the display is ON) in
white.
Function setup by command input (User setup)
(1) Display ON/OFF *13
End of data display
(3) Power OFF *14
• In case of S1D15605D11B , S1D15606D11B , S1D15607D11B , S1D15608D11B and S1D15609D11B ,
*
*
*
*
*
Optional status
Function setup by command input (User setup)
(20) Power save *15
Set the time (
the VDD - VSS power (VDD - VSS = 1.8 V) longer
than the time ( ) when the potential of V ~ V
becomes below the threshold voltage
(approximately 1 V) of the LCD panel.
t
L
) from reset active to turning off
t
H
5
1
Reset active (RES pin = LOW)
For
event. When
between V and VDD to reduce it.
t
H
, refer to the <Reference Data> of this
t
H
is too long, insert a resistor
V
DD – VSS power OFF
5
• In case of other models,
Set the time (tL) from power save to turning off
the VDD - VSS power (VDD - VSS = 1.8 V) longer
than the time (tH) when the potential of V5 ~ V1
becomes below the threshold voltage
Optional status
(approximately 1V) of the LCD panel.
Function setup by command input (User setup)
(20) Power save *15
• tH is determined depending on the voltage
regulator external resistors Ra and Rb and the
time constant of V5 ~ V1 smoothing capacity C2.
• When an internal resistor is used, it is
recommended to insert a resistor R between
VDD and V5 to reduce tH.
VDD – VSS power OFF
Notes: Reference items
*14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply
VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has
still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning
off the power, observe the following basic procedures:
• After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below
the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS).
6. Description of Function, 6.7 Power Circuit
*15: After inputting the power save command, be sure to reset the function using the RES terminal until the
power supply VDD - VSS is turned off. 7. Command Description (20) Power Save
*16: After inputting the power save command, do not reset the function using the RES terminal until the
power supply VDD - VSS is turned off. 7. Command Description (20) Power Save
8–60
EPSON
Rev. 2.4a
S1D15605 Series
(4) Refresh
It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of
unexpected noise.
Refresh sequence
NOP command
Set all commands to the ready state
(Including default state setting.)
Refreshing of DRAM
Precautions on Turning off the power
• In case of S1D15605D11B , S1D15606D11B , S1D15607D11B , S1D15608D11B and S1D15609D11B ,
*
*
*
*
*
Observe Paragraph 1) as the basic rule.
<Turning the power (VDD - VSS) off>
1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing
capacity of V5 ~ V1) and the driver’s discharging capacity.
Power
save Reset Power Off
t
L
VDD
1.8 V
RES
V
DD
DD
SEG
Since the power (VDD-VSS) is
cut off, the output comes not
to be fixed.
V
COM
V1
V2
V3
V4
V5
About 1 V: Below Vth of the LCD panel
t
H
For tH, see Figure 29.
Rev. 2.4a
EPSON
8–61
S1D15605 Series
<Turning the power (VDD - VSS) off : When command control is not possible.>
2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method. tH is
determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging
capacity.
Reset
Power Off
t
L
V
DD
1.8 V
RES
VDD
SEG
Since the power (VDD-VSS) is
cut off, the output comes not
be fixed.
VDD
COM
V
V
V
V
V
1
2
3
4
5
About 1 V: Below Vth of the LCD panel
t
H
For tH, see Figure 29.
<Reference Data>
V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset.
V5 voltage falling (discharge) time (tH) after the process of operation → reset.
100
V
DD-VSS(V)
1.8
2.4
3.0
50
4.0
5.0
0
0.5
1.0
C2: V
1
to V
5
capacity (uF)
Figure 29
8–62
EPSON
Rev. 2.4a
S1D15605 Series
• In case of other models than the above
<Turning the power (VDD - VSS) off>
Power save (The LCD powers (VDD - VSS) are off.) -> Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software. tH is determined according to the external capacity C (smoothing
capacity of V5 to V1) and the external resisters Ra + Rb (for V5 voltage regulation)
Power Power
save
Off
t
L
V
DD
1.8 V
SEG
Since the power (VDD-VSS) is
cut off, the output comes not
be fixed.
COM
V
V
V
V
V
1
2
3
4
5
About 1 V: Below Vth of the LCD panel
t
H
tH is determined depending on the time
constant of (Ra + Rb) C.
Rev. 2.4a
EPSON
8–63
S1D15605 Series
9. ABSOLUTE MAXIMUM RATINGS
Unless otherwise noted, VSS = 0 V
Table 17
Symbol
Parameter
Power Supply Voltage
Conditions
Unit
V
VDD
–0.3 to +7.0
Power supply voltage (2)
(VDD standard)
VSS2
–7.0 to +0.3
–6.0 to +0.3
–4.5 to +0.3
V
With Triple step-up
With Quad step-up
Power supply voltage (3) (VDD standard)
Power supply voltage (4) (VDD standard)
Input voltage
V5, VOUT
V1, V2, V3, V4
VIN
–18.0 to +0.3
V5 to +0.3
V
V
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–40 to +85
V
Output voltage
VO
V
Operating temperature
TOPR
°C
Storage temperature
TCP
Bare chip
TSTR
–55 to +100
–55 to +125
°C
V
CC
V
V
DD
SS
V
V
DD
GND
SS2, V1 to V4
V
5, VOUT
System (MPU) side
S1D15605 Series chip side
Figure 30
Notes and Cautions
1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference.
2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5.
3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover,
it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of
the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative
impact on the LSI reliability as well.
8–64
EPSON
Rev. 2.4a
S1D15605 Series
10. DC CHARACTERISTICS
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = –40 to 85°C
Table 18
Rating
Typ.
—
Applicable
Units
Item
Symbol
Condition
Min.
Max.
Pin
Operating Recom-
Voltage (1) mended
Voltage
VDD
2.7
3.3
V
V
VDD*1
Possible
1.8
—
5.5
VDD*1
Operating
Voltage
Operating Recom-
Voltage (2) mended
Voltage
VSS2
VSS2
(Relative to VDD)
–3.3
–6.0
—
—
–2.7
–1.8
V
V
VSS2
VSS2
Possible
(Relative to VDD)
Operating
Voltage
Operating Possible
Voltage (3) Operating
Voltage
V5
(Relative to VDD)
(Relative to VDD)
(Relative to VDD)
–16.0
0.4 × V5
V5
—
—
—
–4.5
VDD
V
V
V
V5 *2
V1, V2
V3, V4
Possible
Operating
Voltage
Possible
V1, V2
V3, V4
0.6 × V5
Operating
Voltage
High-level Input
Voltage
Low-level Input
Voltage
VIHC
VILC
0.8 × VDD
—
—
VDD
V
V
*3
*3
VSS
0.2 × VDD
High-level Output
Voltage
Low-level Output
Voltage
VOHC
VOLC
IOH = –0.5 mA
IOL = 0.5 mA
0.8 × VDD
—
—
VDD
V
V
*4
*4
VSS
0.2 × VDD
Input leakage
current
Output leakage
current
ILI
VIN = VDD or VSS
–1.0
–3.0
—
—
1.0
3.0
µA
µA
*5
*6
ILO
Liquid Crystal Driver
ON Resistance
RON
Ta = 25°C
(Relative To VDD) V5 = –8.0 V
V5 = –14.0 V
—
—
2.0
3.2
3.5
5.4
kΩ
kΩ
SEGn
COMn *7
Static Consumption
Current
Output Leakage
Current
ISSQ
I5Q
—
0.01
5
µA
VSS, VSS2
V5 = –18.0 V
(Relative To VDD)
—
0.01
15
µA
V5
Input Terminal
Capacitance
CIN
Ta = 25°C f = 1 MHz
—
5.0
8.0
pF
Oscillator
Frequency Oscillator
Internal
fOSC
fCL
Ta = 25°C
18
18
22
22
26
26
kHz
kHz
*8
S1D15605*****/15607*****
External
Input
CL
Internal
Oscillator
External
Input
fOSC
fCL
Ta = 25°C
27
14
33
17
39
20
kHz
kHz
*8
S1D15606*****/15608*****/
15609*****
CL
Rev. 2.4a
EPSON
8–65
S1D15605 Series
Table 19
Rating
Typ.
—
Applicable
Pin
Item
Symbol
Condition
Units
Min.
Max.
Input voltage
VSS2 With Triple
(Relative To VDD)
VSS2 With Quad
(Relative To VDD)
–6.0
–1.8
V
V
VSS2
–4.5
—
—
–1.8
—
VSS2
VOUT
Supply Step-up VOUT (Relative to VDD)
output voltage
Circuit
–18.0
V
V
V
Voltage regulator VOUT (Relative to VDD)
Circuit Operating
Voltage
–18.0
–16.0
—
—
–6.0
–4.5
VOUT
V5 *9
Voltage Follower
Circuit Operating
Voltage
V5
(Relative to VDD)
Base Voltage
VREG0 Ta = 25°C
VREG1 (Relative to VDD) –0.2%/°C
–0.05%/°C –2.04 –2.10 –2.16
V
V
*10
*10
–4.65
–4.9
–5.15
8–66
EPSON
Rev. 2.4a
S1D15605 Series
• Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF
Current consumed by total ICs when an external power supply is used.
Table 20 Display Pattern OFF
Ta = 25°C
Rating
Item
Symbol
Condition
Units Notes
Min. Typ. Max.
IDD (1)
VDD = 5.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
—
—
—
—
—
—
—
—
—
18
16
13
11
9
8
7
12
10
30
27
22
19
15
13
12
20
17
µA
*11
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****/
S1D15609*****
Table 21 Display Pattern Checker
Ta = 25°C
Rating
Item
Symbol
Condition
Units Notes
Min. Typ. Max.
IDD (1)
VDD = 5.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 3.0 V, V5 – VDD = –11.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
VDD = 5.0 V, V5 – VDD = –8.0 V
VDD = 3.0 V, V5 – VDD = –8.0 V
—
—
—
—
—
—
—
—
—
23
21
17
14
12
11
10
15
13
38
35
29
24
20
18
17
25
22
µA
*11
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****/
S1D15609*****
• Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON
The values of curret consumed in all the IC including internal power supply circuit.
Table 22 Display Pattern OFF
Ta = 25°C
Rating
Item
Symbol
Condition
Units Notes
Min. Typ. Max.
IDD (2)
V
V
DD = 5.0 V, Triple step-up voltage. Normal Mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
67 112 µA *12
114 190
81 135
138 230
35 59
64 107
43 72
84 140
72 121
128 214
26 44
60 100
29 49
73 122
37 62
67 112
46 77
87 145
S1D15605*****
5
– VDD = –11.0 V
High-Power Mode
V
DD = 3.0 V, Quad step-up voltage. Normal Mode
V
5
– VDD = –11.0 V
VDD = 5.0 V, Double step-up voltage. Normal Mode
– VDD = –8.0 V
DD = 3.0 V, Triple step-up voltage. Normal Mode
High-Power Mode
S1D15606*****
V
5
High-Power Mode
V
V
5
– VDD = –8.0 V
DD = 3.0 V, Quad step-up voltage. Normal Mode
– VDD = –11.0 V
VDD = 5.0 V, Double step-up voltage. Normal Mode
High-Power Mode
V
V
5
High-Power Mode
S1D15607*****
V
5
– VDD = –8.0 V
DD = 3.0 V, Triple step-up voltage. Normal Mode
– VDD = –8.0 V
VDD = 5.0 V, Double step-up voltage. Normal Mode
High-Power Mode
V
V
5
High-Power Mode
S1D15608*****/
S1D15609*****
V
5
– VDD = –8.0 V
DD = 3.0 V, Triple step-up voltage. Normal Mode
– VDD = –8.0 V
High-Power Mode
V
V
5
High-Power Mode
Rev. 2.4a
EPSON
8–67
S1D15605 Series
Table 23 Display Pattern Checker
Ta = 25°C
Rating
Item
Symbol
Condition
Units Notes
Min. Typ. Max.
IDD (2)
V
V
DD = 5.0 V, Triple step-up voltage. Normal Mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
81 135 µA *12
127 212
96 160
153 255
41 69
71 119
51 85
92 154
85 142
142 237
32 53
62 103
44 73
89 148
44 74
74 127
54 90
95 159
S1D15605*****
5
– VDD = –11.0 V
High-Power Mode
V
DD = 3.0 V, Quad step-up voltage. Normal Mode
V
5
– VDD = –11.0 V
VDD = 5.0 V, Double step-up voltage. Normal Mode
– VDD = –8.0 V
DD = 3.0 V, Triple step-up voltage. Normal Mode
High-Power Mode
S1D15606*****
V
5
High-Power Mode
V
V
5
– VDD = –8.0 V
DD = 3.0 V, Quad step-up voltage. Normal Mode
– VDD = –11.0 V
VDD = 5.0 V, Double step-up voltage. Normal Mode
High-Power Mode
V
V
5
High-Power Mode
S1D15607*****
V
5
– VDD = –8.0 V
DD = 3.0 V, Triple step-up voltage. Normal Mode
– VDD = –8.0 V
VDD = 5.0 V, Double step-up voltage. Normal Mode
High-Power Mode
V
V
5
High-Power Mode
S1D15608*****/
S1D15609*****
V
5
– VDD = –8.0 V
DD = 3.0 V, Triple step-up voltage. Normal Mode
– VDD = –8.0 V
High-Power Mode
V
V
5
High-Power Mode
• Consumption Current at Time of Power Saver Mode, VSS = 0 V, VDD = 3.0 V ± 10%
Table 24
Ta = 25°C
Rating
Min. Typ. Max.
Item
Sleep mode
Symbol
Condition
Units Notes
IDDS1
IDDS2
IDDS1
IDDS2
IDDS1
IDDS2
IDDS1
—
—
—
—
—
—
—
0.01
4
5
8
5
8
5
6
5
µA
µA
µA
µA
µA
µA
µA
S1D15605*****
Standby Mode S1D15605*****
Sleep mode
0.01
4
S1D15606*****
Standby Mode S1D15606*****
Sleep mode
0.01
3
S1D15607*****
Standby Mode S1D15607*****
S1D15608*****/
Sleep mode
0.01
S1D15609*****
IDDS2
—
4
8
µA
Standby Mode S1D15608*****/
S1D15609*****
TBD: To Be Determined
8–68
EPSON
Rev. 2.4a
S1D15605 Series
Reference Data 1
• Dynamic Consumption Current (1) During LCD Display Using an External Power Supply
40
Conditions: Internal power supply OFF
External power supply in use
S1D15605/S1D15606 (–11.0V):
V5 – VDD = –11.0 V
S1D15606 (–8.0V)/S1D15607/
S1D15608/S1D15609:
V5 – VDD = –8.0 V
Display pattern: OFF
30
20
10
0
S1D15605
Ta = 25°C
S1D15606 (–11.0V)
S1D15608/S1D15609 (–8.0V)
S1D15606 (–8.0V)
S1D15607
Note: *11
0
2
4
6
8
V
DD [V]
Figure 31
40
30
20
10
0
Conditions: Internal power supply OFF
External power supply in use
S1D15605/S1D15606 (–11.0V):
V5 – VDD = –11.0 V
S1D15606 (–8.0V)/S1D15607/
S1D15608/S1D15609:
V5 – VDD = –8.0 V
S1D15605
Display pattern: Checker
Ta = 25°C
S1D15606 (–11.0V)
S1D15608/S1D15609 (–8.0V)
S1D15606 (–8.0V)
S1D15607
Note: *11
0
2
4
6
8
VDD [V]
Figure 32
Rev. 2.4a
EPSON
8–69
S1D15605 Series
Reference Data 2
• Dynamic Consumption Current (2) During LCD display using the internal power supply
Conditions: Internal power supply ON
S1D15605/S1D15606 (×4, –11.0V)/
S1D15608/S1D15609 (×4, –11.0V):
4× step-up voltage: V – VDD = –11.0 V
S1D15606 (×3, –8.0V)/S1D15607/
S1D15608/S1D15609 (×3, –8.0V):
140
120
100
80
5
3× step-up voltage: V
Normal mode
5 – VDD = –8.0 V
S1D15605
S1D15608/15609 (x4, –11.0V)
S1D15606 (x4, –11.0V)
Display pattern: OFF
Ta = 25°C
S1D15608/S1D15609 (x3, –8.0V)
60
S1D15606 (x3, –8.0V)
40
S1D15607
Note: *12
20
0
0
2
4
6
8
V
DD [V]
Figure 33
Conditions: Internal power supply ON
S1D15605/S1D15606 (×4, –11.0V)/
S1D15608/S1D15609 (×4, –11.0V):
4× step-up voltage: V – VDD = –11.0 V
5
120
100
80
60
40
20
0
S1D15606 (×3, –8.0V)/S1D15607/
S1D15608/S1D15609 (×3, –8.0V):
S1D15605
3× step-up voltage: V5 – VDD = –8.0 V
Normal mode
Display pattern: Checker
S1D15608/15609 (x4, –11.0V)
S1D15606 (x4, –11.0V)
Ta = 25°C
S1D15608/S1D15609 (x3, –8.0V)
S1D15606 (x3, –8.0V)
S1D15607
Note: *12
0
2
4
6
8
V
DD [V]
Figure 34
8–70
EPSON
Rev. 2.4a
S1D15605 Series
Reference Data 3
• Dynamic Consumption Current (3) During access
10
This figure indicates the consumption
current while the checker pattern is
constantly written through fCYC
.
If there is no access, then only (1) remains.
Conditions: Internal power supply OFF,
external power supply used
S1D15605:
1
V
DD – VSS = 3.0 V, V5=–11.0 V
S1D15606/S1D15607/
S1D15608/S1D15609:
V
DD – VSS = 3.0 V, V5=–8.0 V
Ta = 25°C
0.1
S1D15605
S1D15606
S1D15607
S1D15608/S1D15609
0.01
0.001
0.01
0.1
1
10
fCYC[MHz]
Figure 35
Reference Data 4
• Operating voltage range of VSS and V5 systems
–20
S1D15605 Series Note: *2
–16
–15
Operating range
–10
–7.2
–5
0
–4.5
1.8
3.0
5.5
0
2
4
6
8
VDD[V]
Figure 36
Rev. 2.4a
EPSON
8–71
S1D15605 Series
• The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame
Rate Frequency fFR
Table 25
Item
fCL
fFR
When the internal oscillator circuit is used
fOSC
fOSC
S1D15605*****
S1D15606*****
S1D15607*****
S1D15608*****
S1D15609*****
____
_____
×
4
4
65
When the internal oscillator circuit is not used External input (fCL)
fCL
____
260
When the internal oscillator circuit is used
fOSC
fOSC
____
_____
×
8
8
49
When the internal oscillator circuit is not used External input (fCL)
fCL
____
196
When the internal oscillator circuit is used
fOSC
fOSC
____
_____
×
8
8
33
When the internal oscillator circuit is not used External input (fCL)
fCL
____
264
When the internal oscillator circuit is used
fOSC
fOSC
____
_____
×
55
8
8
When the internal oscillator circuit is not used External input (fCL)
fCL
____
220
When the internal oscillator circuit is used
fOSC
fOSC
____
_____
×
8
8
53
When the internal oscillator circuit is not used External input (fCL)
fCL
____
212
(fFR is the liquid crystal alternating current period, and not the FR signal period.)
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are
sudden fluctuations to the voltage while the MPU is being accessed.
*2 The operating voltage range for the VDD system and the V5 system is as shown in Figure 36. This applies
when the external power supply is being used.
*3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF,
RES, IRS, and HPM terminals.
*4 The D0 to D7, FR, FRS, DOF, and CL terminals.
*5 The A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, and HPM terminals.
*6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF terminals are in a high impedance state.
*7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or
COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating
voltage (3) range.
RON = 0.1 V/∆ I (Where ∆ I is the current that flows when 0.1 V is applied while the power supply is ON.)
*8 See Table 9-7 for the relationship between the oscillator frequency and the frame rate frequency.
*9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
*10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the S1D15605/S1D15606/
S1D15607 chips, the temperature range can come in three types as VREG options: (1) approximately–0.05%/°C,
(2) –0.2%/°C, and (3) external input.
*11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned
on.
The S1D15605 is 1/9 biased, S1D15606/S1D15608/S1D15609 is 1/8 biased and S1D15607 is 1/6 biased.
Does not include the current due to the LCD panel capacity and wiring capacity.
Applicable only when there is no access from the MPU.
*12 It is the value on a model having the VREG option temperature gradient is –0.05%/°C when the V5 voltage
regulator internal resistor is used.
8–72
EPSON
Rev. 2.4a
S1D15605 Series
11. TIMING CHARACTERISTICS
(1) System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
t
AW8
t
AH8
CS1
(CS2="1")
t
CYC8
*1
*2
t
CCLR, tCCLW
WR, RD
t
CCHR, tCCHW
CS1
(CS2="1")
t
f
t
r
WR, RD
t
DS8
t
DH8
D0 to D7
(Write)
t
ACC8
t
OH8
D0 to D7
(Read)
Figure 37
Table 26
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
ns
System cycle time
A0
tCYC8
166
—
ns
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
30
70
30
30
—
—
—
—
ns
ns
ns
ns
Data setup time
Address hold time
D0 to D7
tDS8
tDH8
30
10
—
—
ns
ns
RD access time
Output disable time
tACC8
tOH8
CL = 100 pF
—
5
70
50
ns
ns
Rev. 2.4a
EPSON
8–73
S1D15605 Series
Table 27
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
ns
System cycle time
A0
tCYC8
300
—
ns
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
60
120
60
—
—
—
—
ns
ns
ns
ns
60
Data setup time
Address hold time
D0 to D7
tDS8
tDH8
40
15
—
—
ns
ns
RD access time
Output disable time
tACC8
tOH8
CL = 100 pF
—
10
140
100
ns
ns
Table 28
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
ns
System cycle time
A0
tCYC8
1000
—
ns
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
120
240
120
120
—
—
—
—
ns
ns
ns
ns
Data setup time
Address hold time
D0 to D7
tDS8
tDH8
80
30
—
—
ns
ns
RD access time
Output disable time
tACC8
tOH8
CL = 100 pF
—
10
280
200
ns
ns
*1
*2
*3
This is in the case of making the access by WR and RD,setting the CS1=LOW.
This is the case of making the accese by CS1,setting the WR,RD=LOW.
The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns.When using the
system cycle time at high speed, they are specified for (tr + tf) ≤ (tCYC8-tCCLR-tCCHR).
All timings are specified based on the 20 and 80% of VDD.
tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and
WR,RD are at the LOW level.
*4
*5
8–74
EPSON
Rev. 2.4a
S1D15605 Series
(2) System Bus Read/Write Characteristics 2 (6800 Series MPU)
A0
R/W
t
AW6
t
AH6
CS1
(CS2="1")
t
CYC6
*1
*2
t
EWHR, tEWHW
E
t
EWLR, tEWLWW
CS1
(CS2="1")
t
r
t
f
E
t
DS6
t
DH6
D0 to D7
(Write)
t
ACC6
t
OH6
D0 to D7
(Read)
Figure 38
Table 29
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Address hold time
Address setup time
A0
tAH6
tAW6
0
0
—
—
ns
ns
System cycle time
A0
tCYC6
166
—
ns
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
30
10
—
—
ns
ns
Access time
Output disable time
tACC6
tOH6
CL = 100 pF
—
10
70
50
ns
ns
Enable HIGH pulse Read
E
E
tEWHR
tEWHW
tEWLR
tEWLW
70
30
—
—
ns
ns
time
Write
Enable LOW pulse Read
30
30
—
—
ns
ns
time
Write
Rev. 2.4a
EPSON
8–75
S1D15605 Series
Table 30
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Address hold time
Address setup time
A0
tAH6
tAW6
0
0
—
—
ns
ns
System cycle time
A0
tCYC6
300
—
ns
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
40
15
—
—
ns
ns
Access time
Output disable time
tACC6
tOH6
CL = 100 pF
—
10
140
100
ns
ns
Enable HIGH pulse Read
E
E
tEWHR
tEWHW
tEWLR
tEWLW
120
60
—
—
ns
ns
time
Enable LOW pulse Read
time Write
Write
60
60
—
—
ns
ns
Table 31
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Address hold time
Address setup time
A0
tAH6
tAW6
0
0
—
—
ns
ns
System cycle time
A0
tCYC6
1000
—
ns
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
80
30
—
—
ns
ns
Access time
Output disable time
tACC6
tOH6
CL = 100 pF
—
10
280
200
ns
ns
Enable HIGH pulse Read
time Write
Enable LOW pulse Read
time Write
E
E
tEWHR
tEWHW
tEWLR
tEWLW
240
120
—
—
ns
ns
120
120
—
—
ns
ns
*1
*2
*3
This is in the case of making the access by E, setting the CS1=LOW.
This is the case of making the accese by CS1,setting the E=HIGH.
The rise and fall times ((tr and tf) of the input signal are specified for less than 15 ns.When using the
system cycle time at high speed, they are specified for (tr + tf) ≤ (tCYC6-tEWLW-tEWHW) or (tr + tf) ≤
(tCYC6-tEWLR-tEWHR).
All timings are specified based on the 20 and 80% of VDD.
tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and E
is at the HIGH level.
*4
*5
8–76
EPSON
Rev. 2.4a
S1D15605 Series
(3) The Serial Interface
t
CSS
t
CSH
CS1
(CS2="1")
t
SAS
t
SAH
A0
t
SCYC
t
SLW
SCL
t
SHW
t
f
t
r
t
SDS
t
SDH
SI
Figure 39
Table 32
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Serial Clock Period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
200
75
75
—
—
—
ns
ns
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
50
100
—
—
ns
ns
Data setup time
Data hold time
50
50
—
—
ns
ns
CS-SCL time
CS
tCSS
tCSH
100
100
—
—
ns
ns
Rev. 2.4a
EPSON
8–77
S1D15605 Series
Table 33
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Serial Clock Period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
250
100
100
—
—
—
ns
ns
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
150
150
—
—
ns
ns
Data setup time
Data hold time
100
100
—
—
ns
ns
CS-SCL time
CS
tCSS
tCSH
150
150
—
—
ns
ns
Table 34
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C )
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Serial Clock Period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
400
150
150
—
—
—
ns
ns
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
250
250
—
—
ns
ns
Data setup time
Data hold time
150
150
—
—
ns
ns
CS-SCL time
CS
tCSS
tCSH
250
250
—
—
ns
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
8–78
EPSON
Rev. 2.4a
S1D15605 Series
(4) Display Control Output Timing
CL
(OUT)
t
DFR
FR
Figure 40
Table 35
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C)
Rating
Units
Item
FR delay time
Signal Symbol
FR
Condition
CL = 50 pF
Min.
Typ.
Max.
tDFR
—
10
40
ns
Table 36
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Rating
Units
Item
FR delay time
Signal Symbol
FR
Condition
Min.
Typ.
Max.
tDFR
CL = 50 pF
—
20
80
ns
Table 37
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C)
Rating
Units
Item
FR delay time
Signal Symbol
FR
Condition
Min.
Typ.
Max.
tDFR
CL = 50 pF
—
50
200
ns
*1 Valid only when the master mode is selected.
*2 All timing is based on 20% and 80% of VDD.
Rev. 2.4a
EPSON
8–79
S1D15605 Series
Reset Timing
t
RW
RES
t
R
Internal
status
During reset
Reset complete
Figure 41
Table 38
(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C)
Rating
Units
Item
Signal Symbol
Condition
Min.
—
Typ.
—
Max.
0.5
Reset time
tR
µs
µs
Reset LOW pulse width
RES
tRW
0.5
—
—
Table 39
(VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C)
Rating
Units
Item
Signal Symbol
Condition
Min.
—
Typ.
—
Max.
1
Reset time
tR
µs
µs
Reset LOW pulse width
RES
tRW
1
—
—
Table 40
(VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C)
Rating
Units
Item
Signal Symbol
Condition
Min.
—
Typ.
—
Max.
1.5
Reset time
tR
µs
µs
Reset LOW pulse width
RES
tRW
1.5
—
—
*1 All timing is specified with 20% and 80% of VDD as the standard.
8–80
EPSON
Rev. 2.4a
S1D15605 Series
12. THE MPU INTERFACE (REFERENCE EXAMPLES)
The S1D15605 Series can be connected to either 80 × 86 Series MPUs or to 6800 Series MPUs. Moreover, using the
serial interface it is possible to operate the S1D15605 series chips with fewer signal lines.
The display area can be enlarged by using multiple S1D15605 Series chips. When this is done, the chip select signal
can be used to select the individual ICs to access.
(1) 8080 Series MPUs
V
DD
V
CC
VDD
C86
P/S
A0
A0
A1 to A7
IORQ
CS1
CS2
Decoder
RESET
D0 to D7
RD
D0 to D7
RD
WR
RES
WR
RES
GND
VSS
VSS
Figure 42-1
(2) 6800 Series MPUs
V
DD
V
CC
VDD
C86
P/S
A0
A0
A1 to A15
VMA
CS1
CS2
Decoder
RESET
D0 to D7
E
D0 to D7
E
R/W
R/W
RES
RES
GND
VSS
V
SS
Figure 42-2
(3) Using the Serial Interface
VDD or
V
SS
V
CC
VDD
C86
P/S
A0
A0
CS1
CS2
A1 to A7
Decoder
RESET
Port 1
Port 2
RES
SI
SCL
RES
GND
VSS
V
SS
Figure 42-3
Rev. 2.4a
EPSON
8–81
S1D15605 Series
13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE)
The liquid crystal display area can be enlarged with ease through the use of multiple S1D15605 Series chips. Use a same
equipment type.
(1) S1D15605 (master) ↔ S1D15605 (slave)
V
DD
M/S
M/S
FR
CL
FR
CL
DOF
DOF
Output
Input
V
SS
Figure 43
8–82
EPSON
Rev. 2.4a
S1D15605 Series
14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES)
The liquid crystal display area can be enlarged with ease through the use of multiple S1D15605 Series chips.
Use a same equipment type, in the composition of these chips.
(1) Single-chip Structure
132 x 65 Dots
COM
SEG
S1D15605 Series
COM
Master
Figure 44-1
(2) Double-chip Structure, #1
264 x 65 Dots
COM
SEG
SEG
COM
S1D15605 Series
Master
S1D15605 Series
Slave
Figure 44-2
Rev. 2.4a
EPSON
8–83
S1D15605 Series
15. A SAMPLE TCP PIN ASSIGNMENT
S1D15605T00B TCP Pin Layout
*
Note: The following does not specify dimensions of the TCP pins.
An example
FR
FR
CL
FRS
DOF
CS1
CS2
RES
A0
COM S
COM 63
•
•
WR,R/W
RD, E
D0
•
•
D1
D2
•
D3
COM 33
D4
D5
COM 32
D6, SCL
D7, SI
SEG 131
V
DD
SS
SS2
OUT
SEG 130
V
•
V
V
•
CAP3-
CAP1+
CAP1-
CAP2-
CAP2+
VRS
•
•
•
SEG 1
V
DD
SEG 0
V
V
V
V
V
1
2
3
4
5
COM S
COM 0
•
VR
•
V
DD
M/S
CLS
C86
P/S
•
•
•
HPM
IRS
COM 30
COM 31
8–84
EPSON
Rev. 2.4a
S1D15605 Series
16. EXTERNAL VIEW OF TCP PINS
( M o l d , m a r k i n g a r e a ) ( M o l d , m a r k i n g a r e a )
Rev. 2.4a
EPSON
8–85
相关型号：
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