S24VP04S-ATE7 [ETC]
4K Serial E2PROM with a Precision Low-VCC Lockout Circuit; 4K串行E2PROM具有高精度低VCC锁定电路
| 型号： | S24VP04S-ATE7 |
| 厂家： | 
ETC |
| 描述： | 4K Serial E2PROM with a Precision Low-VCC Lockout Circuit |
| 文件： | 总12页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S U MMIT
S24VP04
3 and 5 Volt Systems
MICROELECTRONICS, Inc.
4K Serial E2PROM with a Precision Low-VCC Lockout Circuit
FEATURES
OVERVIEW
•
•
•
Voltage Protection™
The S24VP04 is a 4K-bit serial E2PROM memory inte-
grated with a precision VCC sense circuit. The sense
circuit will disable write operations whenever VCC falls
below the VLOCK voltage. It is fabricated using SUMMIT’s
advanced CMOS E2PROM technology and is suitable for
both 3 and 5 volt systems.
Precision Low-VCC Write Lockout
All Write Operations Inhibited When VCC Falls
below VLOCK
•
•
•
One 3Volt and Two 5Volt System Versions
– VLOCK = 2.6V+.1V/-.05V
– VLOCK = 4.25V +.25V/-0.0V
– VLOCK = 4.50 +.25V/-0.0V
100% Compatible with Industry Standard I2C™
Devices
The S24VP04 is internally organized as 512 x 8. It fea-
tures the I2C serial interface and software protocol allow-
ing operation on a simple two-wire bus.
– Bi-directional data transfer protocol
– Standard 100kHz and 400kHz Transfer Rates
16-Byte Page-Write Mode
– Minimizes total write time per byte
1,000,000 Program/Erase Cycles
•
•
•
100 Year Data Retention
Commercial Industrial Temperature Range
BLOCK DIAGRAM
V
8
7
CC
RESET
PULSE
GENERATOR
5KHz
Oscillator
NC
+
-
V
TRIP
RESET
CONTROL
4
GND
1.26V
MODE
DECODE
WRITE
CONTROL
SCL
SDA
6
5
ADDRESS
DECODER
NC
NC
NC
1
3
2
E PROM
MEMORY
ARRAY
DATA I/O
2
2008 ILL2 1.2
SUMMIT MICROELECTRONICS, Inc.
•
300 Orchard City Drive, Suite 131
•
Campbell, CA 95008
•
Telephone 408-378-6461
•
Fax 408-378-6586
•
www.summitmicro.com
Characteristics subject to change without notice
© SUMMIT MICROELECTRONICS, Inc. 1998
2008 1.4 5/15/98
1
S24VP04
PIN CONFIGURATIONS
Address Inputs A0, A1, A2- Device Address Inputs
These inputs are unused by the S24VP04; however, to
ensure proper operation they should be left unconnected
or tied to ground. The should not be tied high.
Plastic Dual-in-line
“P” Package
A0
A1
1
2
3
4
8
7
6
5
V
CC
ENDURANCE AND DATA RETENTION
DC
The S24VP04 is designed for applications requiring
1,000,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 1,000,000
erase/write cycles.
A2
SCL
SDA
GND
JEDEC Small Outline
“S” Package
DEVICE OPERATION
1
2
3
4
8 V
CC
A0
A1
APPLICATIONS
DC
7
6
The S24VP04 was designed specifically for applications
where the integrity of the stored data is paramount. In
recent years, as the operating voltage range of serial
E2PROMs has widened, most semiconductor manufac-
turers have arbitrarily eliminated their VCC sense circuits.
TheS24VP04willprotectyourdatabyguaranteeingwrite
lockout below the selected VCC Lockout voltage.
SCL
A2
5 SDA
GND
2008 ILL1 1.2
VCC Lockout
The S24VP04 has an on-board precision VCC sense
circuit. Whenever VCC is below VLOCK, the S24VP04 will
disable the internal write circuitry. The VCC lockout circuit
will ensure a higher level of data integrity than can be
expected from industry standard devices that have either
a very loose specification or no VCC lockout specification.
PIN NAMES
A0, A1,A2
SDA
Address Inputs
Serial Data I/O
Serial Clock Input
Don’t Care
SCL
DC
GND
VCC
Ground
Supply Voltage
During a power-on sequence all writes will be inhibited
belowtheVLOCK levelandwillcontinuetobeheldinawrite
inhibit state for approximately 200ms after VCC reaches,
then stays at or above VLOCK. The 200ms delay provides
a buffer space for the microcontroller to complete its
power-on initialization routines (reading is OK) while still
protecting against inadvertent writes.
PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remainstablewhileSCLisHIGH.IntheREADmode,data
is clocked out on the falling edge of SCL.
During a power-down sequence initiation of writes will be
inhibited whenever VCC falls below VLOCK. This will guard
against the system’s microcontroller performing an inad-
vertent write within the ‘danger zone’. (see AN001)
Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
changeonlywhenSCLisLOW,exceptSTARTandSTOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
2008 1.4 5/15/98
2
S24VP04
Vcc
SDA
RESET
SCL
Master
Transmitter/
Receiver
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
(24VP04)
(µC/ µP)
2008 ILL 3 1.1
FIGURE 1. TYPICAL SYSTEM CONFIGURATION
SCL
Data must
remain stable
while clock
is HIGH.
Data must
remain stable
while clock
is HIGH.
Change
of data
allowed
SDA In
t
SU:DAT
t
HD:DAT
tHD:DAT
2008 ILL4 1.0
FIGURE 2. INPUT DATA PROTOCOL
SCL
STOP
Condition
START
Condition
SDA In
2008 ILL5 1.0
FIGURE 3. START AND STOP CONDITIONS
2008 1.4 5/15/98
3
S24VP04
SCL from
Master
1
9
8
Start
Condition
Data Output
from
t
AA
Transmitter
Data Output
from
ACKnowledge
tAA
Receiver
2008 ILL6 1.0
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER
CHARACTERISTICS OF THE I2C BUS
General Description
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
The I2C bus was designed for two-way, two-line serial the master or the slave, will release the bus after transmit-
communicationbetweendifferentintegratedcircuits. The ting eight bits. During the ninth clock cycle, the receiver
two lines are: a serial data line (SDA), and a serial clock will pull the SDA line LOW to ACKnowledge that it re-
line (SCL). The SDA line must be connected to a positive ceived the eight bits of data (See Figure 4).
supply by a pull-up resistor, located somewhere on the
The S24VP04 will respond with an ACKnowledge after
bus (See Figure 1). Data transfer between devices may
recognition of a START condition and its slave address
be initiated with a START condition only when SCL and
byte. If both the device and a write operation are selected,
SDA are HIGH (bus is not busy).
the S24VP04 will respond with an ACKnowledge after the
Input Data Protocol
receipt of each subsequent 8-bit word.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition (See
Figure 2).
In the READ mode, the S24VP04 transmits eight bits of
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S24VP04willcontinuetotransmitdata.IfanACKnowledge
is not detected, the S24VP04 will terminate further data
START and STOP Conditions
When both the data and clock lines are HIGH, the bus is transmissions and awaits a STOP condition before return-
saidtobenotbusy.AHIGH-to-LOWtransitiononthedata ing to the standby power mode.
line, while the clock is HIGH, is defined as the “START”
Device Addressing
condition. A LOW-to-HIGH transition on the data line,
Following a start condition the master must output the
while the clock is HIGH, is defined as the “STOP” condi-
address of the slave it is accessing. The most significant
tion (See Figure 3).
four bits of the slave address are the device type identifier
(see figure 5). For the S24VP04 this is fixed as 1010[B].
DEVICE OPERATION
The S24VP04 is a 16,384-bit serial E2PROM. The device
supports the I2C bidirectional data transmission protocol.
The protocol defines any device that sends data onto the
busasa“transmitter”andanydevicewhich receivesdata
as a “receiver.” The device controlling data transmission
is called the “master” and the controlled device is called
the “slave.” In all cases, the S24VP04 will be a “slave”
device, since it never initiates any data transfers.
DEVICE
IDENTIFIER
HIGH ORDER
WORD ADDRESS
S2
S1
BS
1
0
1
0
(A8)
2008 ILL7 1.0
FIGURE 5. SLAVE ADDRESS BYTE
2008 1.4 5/15/98
4
S24VP04
The next two bits are don’t care. The S24VP04 will
respond to all commands for device 1010.
Uponreceiptofthewordaddress, theS24VP04responds
with an ACKnowledge. After receiving the next byte of
data, it again responds with an ACKnowledge. The mas-
ter then terminates the transfer by generating a STOP
condition, at which time the S24VP04 begins the internal
write cycle.
Bank Select Bit
The next bit of the serial stream is the bank select bit. It is
used by the host to toggle between the two 2K-bit banks
of memory. It is, in effect, the most significant bit of the
word address, or A8.
While the internal write cycle is in progress, the S24VP04
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 6 for the
address, ACKnowledge and data transfer sequence.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.
Page WRITE
The S24VP04 is capable of a 16-byte page write opera-
tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
words of data. After the receipt of each word, the
S24VP04 will respond with an ACKnowledge.
WRITE OPERATIONS
The S24VP04 allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (tWR). The
page write operation allows up to 16 bytes in the same
The S24VP04 automatically increments the address for
subsequent data words. After the receipt of each word,
the four low order address bits are internally incremented
byone. Thehighorderfivebitsoftheaddressbyteremain
constant. Should the master transmit more than sixteen
words, prior to generating the STOP condition, the ad-
dress counter will “roll over,” and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 6 for the address, ACKnowledge and data
transfer sequence.
page to be written during tWR
.
Byte WRITE
After the slave address is sent (to identify the slave
device, specify high order word address and a read or
write operation), a second byte is transmitted which
contains the low 8 bit addresses of any one of the 512
words in the array.
If single byte-write only,
Stop bit issued here.
Acknowledges Transmitted from
24VP04 to Master Receiver
Acknowledges Transmitted from
24043 to Master Receiver
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SDA
Bus
A
2
A
1
B
S
R
W
Word Address
Data Byte n
Data Byte n+1
Data Byte n+15
Activity
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
0
S
T
O
P
S
T
A
R
T
Device
Type
Address
A2,A1,BS
Read/Write
0= Write
Slave Address
Master Sends Read
Request to Slave
Master Writes Word
Address to Slave
Master Writes
Data to Slave
Master Writes
Data to Slave
Master Writes
Data to Slave
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Slave Receiver
Slave Receiver
Slave Receiver
Slave Receiver
Slave Receiver
Slave Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Master Receiver
Master Receiver
Master Receiver
Master Receiver
Master Receiver
2008 ILL8 1.0
Shading Denotes
24VP04
SDA Output Active
FIGURE 6. PAGE/BYTE WRITE MODE
2008 1.4 5/15/98
5
S24VP04
Acknowledge Polling
READ OPERATIONS
When the S24VP04 is performing an internal WRITE
operation, it will ignore any new START conditions. Since Read operations are initiated with the R/W bit of the
the device will only return an acknowledge after it accepts identification field set to “1.” There are four different read
the START, the part can be continuously queried until an options:
acknowledgeisissued, indicatingthattheinternalWRITE
1. Current Address Byte Read
cycle is complete.
2. Random Address Byte Read
To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 7).
3. Current Address Sequential Read
4. Random Address Sequential Read
Current Address Byte Read
Internal WRITE Cycle
In Progress;
Begin ACK Polling
TheS24VP04containsaninternaladdresscounterwhich
maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
S24VP04receivestheslaveaddressfieldwiththeR/Wbit
set to “1,” it issues an acknowledge and transmits the
8-bit word stored at address location n+1.
Issue Start
Issue Slave
Address and
R/W = 0
Issue Stop
ACK
Returned?
No
The current address byte read operation only accesses
a single byte of data. The master does not acknowledge
the transfer, but does generate a stop condition. At this
point, the S24VP04 discontinues data transmission. See
Figure 8 for the address acknowledge and data transfer
sequence.
Yes (Internal WRITE Cycle is completed)
Next
operation a
WRITE?
No
Yes
Issue Byte
Address
Issue Stop
Await Next
Command
Proceed with
WRITE
2008 ILL9 1.0
FIGURE 7. ACKNOWLEDGE POLLING
A
C
K
A
2
A
1
B
S
R
W
Data Byte
1
SDA Bus Activity
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1 0 1 0
1
S
T
A
R
T
S
T
O
P
Device
Type
Address
A2,A1,BS
Read/Write
1= Read
Lack of ACK (low)
from Master
determines last
data byte to be read
Slave Address
Slave sends
Data to Master
Master sends Read
request to Slave
Slave Transmitter
to
Shading Denotes
Master Transmitter
to
24VP04
Master Receiver
SDA Output Active
Slave Receiver
2008 ILL 10 1.0
FIGURE 8. CURRENT ADDRESS BYTE READ MODE
2008 1.4 5/15/98
6
S24VP04
Random Address Byte Read
After the word address acknowledge is received by the
Random address read operations allow the master to master, the master immediately reissues a start condition
access any memory location in a random fashion. This followed by another slave address field with the R/W bit
operation involves a two-step process. First, the master set to READ. The S24VP04 will respond with an acknowl-
issues a write command which includes the start condi- edge and then transmit the 8-data bits stored at the
tion and the slave address field (with the R/W bit set to addressed location. At this point, the master does not
WRITE) followed by the address of the word it is to read. acknowledgethetransmissionbutdoesgeneratethestop
This procedure sets the internal address counter of the condition. The S24VP04 discontinues data transmission
S24VP04 to the desired address.
and reverts to its standby power mode. See Figure 9 for
the address, acknowledge and data transfer sequence.
A
C
K
A
C
K
A
C
K
A
2
A
1
B
S
R
W
A
2
A
1
B
S
R
W
Word Address
Data Byte
SDA Bus
Activity
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
0
1 0 1 0
1
1
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Device
Device
Type
Address
A2,A1,BS
A2,A1,BS
Type
Address
Read/Write
0= Write
Read/Write
1= Read
Lack of ACK (low)
from Master
determines last
data byte to be read
Slave Address
Slave Address
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Slave Transmitter
to
Slave Receiver
Slave Receiver
Slave Receiver
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
24VP04
SDA Output Active
2008 ILL11 1.0
FIGURE 9. RANDOM ADDRESS BYTE READ MODE
2008 1.4 5/15/98
7
S24VP04
Sequential READ
Sequential READs can be initiated as either a current
address READ or random access READ. The first word is
transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, themasternowrespondswithanACKnowledge,
indicating that it requires additional data from the
S24VP04. The S24VP04 continues to output data for
each ACKnowledge received. The master terminates the
sequential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.
During a sequential read operation, the internal address
counter is automatically incremented with each acknowl-
edge signal. For read operations, all address bits are
incremented, allowing the entire array to be read using a
single read command. After a count of the last memory
address, the address counter will ‘roll-over’ and the
memory will continue to output data. See Figure 10 for the
address, acknowledge and data transfer sequence.
Lack of
Acknowledge from
Master Receiver
Acknowledge from
Master Receiver
Acknowledges from 24VP04
A
C
K
A
C
K
A
C
K
A
C
SDA Bus
Activity
A
2
A
1
B
S
R
W
A
2
A
1
B
S
R
W K
Word Address
First Data Byte
Last Data Byte
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
0
1 0 1 0
1
1
S
T
S
T
A
R
T
S
T
O
P
Device
Type
Device
Type
A
A2,A1,BS
A2,A1,BS
R Address
T
Address
Read/Write
0= Write
Read/Write
1= Read
Lack of ACK (low)
determines last
data byte to be read
Slave Address
Slave Address
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Slave sends
Data to Master
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Slave Receiver
Slave Receiver
Slave Receiver
Master Receiver
Master Receiver
Slave Transmitter
to
Master Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Master Receiver
Slave Receiver
Master Receiver
Master Receiver
2008 ILL 12 1.0
Shading Denotes
24VP04
SDA Output Active
FIGURE 10. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
2008 1.4 5/15/98
8
S24VP04
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................................................................................................................ -40°C to +85°C
Storage Temperature ..................................................................................................................... -65°C to +125°C
Soldering Temperature (less than 10 seconds) ...............................................................................................300°C
Supply Voltage ............................................................................................................................................ 0 to 6.5V
Voltage on Any Pin ...................................................................................................................... -0.3V to VCC+0.3V
ESD Voltage (JEDEC method) ...................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
S24VP04, T = -40°C to +85°C, V = 5V + 10%
A
CC
S24VP04-3, T = -40°C to +85°C, V = 2.7V to 5.5V
A
CC
Symbol
ICC
Parameter
Conditions
Min
Max
Units
mA
SCL = CMOS Levels @ 100KHz
SDA = Open
All other inputs = GND or VCC
V
=5.5V
3
CC
Supply Current (CMOS)
Standby Current (CMOS)
VCC =3.3V
VCC =5.5V
2
mA
50
ISB
SCL = SDA = VCC
µA
µA
µA
All other inputs = GND
V
=3.3V
25
10
CC
ILI
Input Leakage
VIN = 0 To VCC
ILO
VIL
VIH
VOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
VOUT = 0 To VCC
10
µA
V
S0, S1, S2, SCL, SDA, RESET
S0, S1, S2, SCL, SDA
IOL = 3mA
0.3xVCC
0.7xVCC
V
0.4
V
2008 PGM T1 1.0
AC ELECTRICAL CHARACTERISTICS
S24VP04, T = -40°C to +85°C, V = 5V + 10%
A
CC
2.7V to 4.5V
4.5V to 5.5V
S24VP04-3, T = -40°C to +85°C, V = 2.7V to 5.5V
A
CC
Symbol
Parameter
Conditions
Min
Max
Min
Max
400
Units
fSCL
SCL Clock Frequency
Clock Low Period
0
100
KHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
tLOW
tHIGH
tBUF
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
1.3
0.6
1.3
0.6
0.6
0.6
0.2
0.2
Clock High Period
Bus Free Time
Before New Transmission
tSU:STA
tHD:STA
tSU:STO
tAA
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock to Output
SCL Low to SDA Data Out Valid
3.5
0.9
tDH
Data Out Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
SCL Low to SDA Data Out Change
tR
1000
300
300
300
tF
tSU:DAT
tHD:DAT
TI
250
0
100
0
Noise Spike Width
@ SCL, SDA Inputs
Noise Suppression Time Constant
100
10
100
10
tWR
Write Cycle Time
ms
2008 PGM T2 1.0
2008 1.4 5/15/98
9
S24VP04
CAPACITANCE
T = 25°C, f = 100KHz
A
Symbol
Parameter
Max
Units
CIN
Input Capacitance
Output Capacitance
5
8
pF
COUT
pF
2008 PGM T3 1.0
t
R
t
H IGH
tLOW
tSU:STO
tF
SCL
tSU:SDA
tHD:SDA
t
HD:DAT
t
SU:DAT
t
BUF
SDA In
tDH
tAA
SDA Out
2008 ILL 13 1.0
FIGURE 11. BUS TIMING
VLOCK CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
T = -40°C to +85°C
A
S24VP04-2.7
S24VP04–A
S24VP04–B
Symbol
Parameter
Min
2.55
130
Max
Min
Max
4.50
270
5
Min
4.50
130
Max
Unit
V
V
Write Lockout Voltage Level
Power-Up Write Delay
2.70
20
5
4.25
130
4.75
270
5
LOCK
t
t
t
ms
µs
PUW
Delay to V
LDLY
LOCKOUT
Glitch Filter
30
30
30
ns
GLITCH
2008 PGM T4 1.3
2008 1.4 5/15/98
10
S24VP04
t
GLITCH
V
LOCK
t
t
LDLY
PUW
t
t
LDLY
PUW
V
CC
V
V
V
Internal Action
LOCKOUT
LOCKOUT
LOCKOUT
2008 ILL 14 1.0
FIGURE 12. VLOCK OUTPUT TIMING
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP.
.050 (1.270) TYP.
8 Places
.157 (4.00)
.150 (3.80)
.275 (6.99) TYP.
.030 (.762) TYP.
8 Places
1
.196 (5.00)
.189 (4.80)
FOOTPRINT
.061 (1.75)
.053 (1.35)
.020 (.50)
.010 (.25)
x45°
.0098 (.25)
.004 (.127)
.035 (.90)
.016 (.40)
.0192 (.49)
.0138 (.35)
.244 (6.20)
.228 (5.80)
.05 (1.27) TYP.
8pn JEDEC SOIC ILL.2
2008 1.4 5/15/98
11
S24VP04
8 Pin PDIP (Type P) Package
.375
(9.525)
.250
PIN 1 INDICATOR
(6.350)
.300 (7.620)
.070 (1.778)
5°-7°TYP.
(4 PLCS)
.0375 (0.952)
.015 (.381) Min.
0°-15°
SEATING PLANE
.130 (3.302)
.060 ± .005
(1.524) ± .127
TYP.
.009 ± .002
(.229 ± .051)
.100 (2.54)
.350 (8.89)
TYP.
.130 (3.302)
.018 (.457)
TYP.
8pn PDIP/P ILL.3
ORDERING INFORMATION
S24VP04
P
I -2.7 TE7
Tape and Reel Option
TE7 = 500/reel
Base Part Number
TE13 = 2000/reel
Package
P = 8 Lead PDIP
S = 8 Lead 150mil SOIC
Operating Voltage Range
A = 4.5V to 5.5V V
B = 4.5V to 5.5V V
Min. @ 4.25V
Min. @ 4.50V
LOCK
LOCK
2.7 = 2.7V to 5.5V V
Min. @ 2.55V
LOCK
Operating Temperature Range
Blank = 0°C to +70°C
I = -40°C to +85°C
2008 ILL15 1.0
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
I2C is a trademark of Philips Corporation.
© Copyright 1998 SUMMIT Microelectronics, Inc.
2008 1.4 5/15/98
12
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