S29C51004T12P [ETC]
4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY; 4兆位（ 524288 ×8位）的5伏CMOS FLASH MEMORY
| 型号： | S29C51004T12P |
| 厂家： | 
ETC |
| 描述： | 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY |
| 文件： | 总16页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Features
Description
The S29C51004T/S29C51004B is a high speed
524,288 x 8 bit CMOS flash memory. Writing or
erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, write enable WE, and output enable OE
controls to eliminate bus contention.
The S29C51004T/S29C51004B offers a combi-
nation of: Boot Block with Sector Erase/Write
Mode. The end of write/erase cycle is detected by
■ 512Kx8-bit Organization
■ Address Access Time: 70, 90, 120 ns
■ Single 5V ± 10% Power Supply
■ Sector Erase Mode Operation
■ 16KB Boot Block (lockable)
■ 1K bytes per Sector, 512 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Write Cycle Time: 35µs (Max)
■ Minimum 10,000 Erase-Program Cycles
■ Low power dissipation
DATA Polling of I/O or by the Toggle Bit I/O .
7
6
TheS29C51004T/S29C51004B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.
Boot block architecture enables the device to
boot from a protected sector located either at the
top (S29C51004T) or the bottom (S29C51004B).
All inputs and outputs are CMOS and TTL
compatible.
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 100 A (Max)
µ
■ Hardware Data Protection
■ Low V Program Inhibit Below 3.5V
CC
■ Self-timed write/erase operations with end-of-cy-
cle detection
– DATA Polling
– Toggle Bit
■ CMOS and TTL Interface
■ Available in one versions
– S29C51004T (Top Boot Block)
The S29C51004T/S29C51004B is ideal for
applications that require updatable code and data
storage.
■ Packages:
– 32-pin Plastic DIP
– 32-pin TSOP-I
– 32-pin PLCC
S29C51004T/S29C51004B V1.0 May 2002
1
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
S
29
C
51 004
T
–
DEVICE
SPEED
OPERATING VOLTAGE
51: 5V
PKG.
P = PDIP
T = TSOP-I
J = PLCC
70: 70ns
90: 90ns
12: 120ns
BOOT BLOCK LOCATION
T: TOP
51004-01
B: BOTTOM
Pin Configurations
Pin Names
A –A
18
Address Inputs
Data Input/Output
Chip Enable
A18
A16
A15
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
0
2
WE
A17
A14
A13
A8
I/O –I/O
0
7
3
4
3
2
1 32 31 30
4
CE
OE
WE
A7
A14
5
29
28
27
26
25
24
23
22
21
5
6
A6
A5
A13
A8
Output Enable
Write Enable
A6
6
7
32-Pin PDIP
Top View
A5
7
A9
8
A4
A9
32 Pin PLCC
Top View
A4
8
A11
OE
9
A3
A11
OE
A10
CE
I/O7
9
A3
V
5V ± 10% Power Supply
Ground
10
11
12
13
A2
CC
10
11
12
13
14
15
16
A2
A10
CE
A1
GND
NC
A1
A0
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
GND
I/O0
No Connect
14 15 16 17 18 19 20
51004-03
51004-02
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
2
3
A13
A14
A17
WE
4
5
6
32-Pin TSOP I
Standard Pinout
Top View
7
V
8
9
CC
GND
I/O2
I/O1
I/O0
A0
A18
A16
A15
A12
A7
10
11
12
13
14
15
16
A1
A6
A5
A2
A4
A3
51004-04
S29C51004T/S29C51004B V1.0 May 2002
2
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Functional Block Diagram
4,194,304 Bit
Memory Cell Array
X-Decoder
A0–A18
Address buffer & latches
Control Logic
Y-Decoder
CE
OE
WE
I/O Buffer & Data Latches
I/O0–I/O7
51004-07
Capacitance (1,2)
Symbol
Parameter
Test Setup
Typ.
Max.
8
Units
pF
C
C
C
Input Capacitance
V
= 0
6
8
8
IN
IN
Output Capacitance
V
= 0
12
pF
OUT
IN2
OUT
Control Pin Capacitance
V
= 0
10
pF
IN
NOTE:
1. Capacitance is sampled and not 100% tested.
2.
T
= 25°C, V = 5V ± 10%, f = 1 MHz.
A
CC
(1)
Latch Up Characteristics
Parameter
Min.
-1
Max.
Unit
V
Input Voltage with Respect to GND on A , OE
+13
+ 1
9
Input Voltage with Respect to GND on I/O, address or control pins
Current
-1
V
V
CC
V
-100
+100
mA
CC
NOTE:
1. Includes all pins except V . Test conditions: V = 5V, one pin at a time.
CC
CC
AC Test Load
+5.0 V
IN3064
or Equivalent
2.7 kΩ
Device Under
Test
IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent
51004-08
CL = 100 pF
6.2 kΩ
S29C51004T/S29C51004B V1.0 May 2002
3
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
(1)
Absolute Maximum Ratings
Symbol
Parameter
Commercial
-2 to +7
Industrial
-2 to +7
Unit
V
V
V
Input Voltage (input or I/O pins)
IN
IN
Input Voltage (A pin, OE)
-2 to +13
-2 to +13
V
9
V
Power Supply Voltage
-0.5 to +5.5
-65 to +125
0 to +70
-0.5 to +5.5
-65 to +150
-40 to + 85
200 (Max.)
V
CC
T
Storage Temerpature (Plastic)
Operating Temperature
°C
°C
mA
STG
OPR
OUT
T
(2)
I
Short Circuit Current
200 (Max.)
NOTE:
1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Parameter
Name
Parameter
Test Conditions
Min.
—
Max.
0.8
—
Unit
V
V
V
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
Read Current
V
V
V
V
V
V
= V Min.
CC
IL
CC
= V Max.
2
V
IH
CC
CC
I
I
= GND to V , V = V Max.
—
±1
µA
µA
V
IL
OL
IN
CC
CC
CC
= GND to V , V = V Max.
—
±10
0.4
—
OUT
CC
CC
CC
V
V
= V Min., I = 2.1mA
—
OL
CC
CC
CC
OL
= V Min, I = -400µA
2.4
—
V
OH
CC
OH
I
CE = OE = V , WE = V , all I/Os open,
30
mA
CC1
IL
IH
Address input = V /V , at f = 1/t Min.,
IL IH
RC
V
= V Max.
CC
CC
I
I
I
Write Current
CE = WE = VIL, OE = V , V = V Max.
—
—
40
1
mA
mA
µA
V
CC2
IH
CC
CC
TTL Standby Current
CMOS Standby Current
CE = OE = WE = V , V = V Max.
IH CC CC
SB
CE = OE = WE = V – 0.3V, V = V Max.
—
100
12.5
50
SB1
CC
CC
CC
V
Device ID Voltage for A
CE = OE = V , WE = V
IH
11.5
—
H
9
9
IL
I
Device ID Current for A
CE = OE = V , WE = V , A9 = V Max.
µA
H
IL
IH
H
S29C51004T/S29C51004B V1.0 May 2002
4
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
AC Electrical Characteristics
Read Cycle
-70
-90
-12
Parameter
Name
Parameter
Min.
70
—
—
—
0
Max.
—
Min.
90
—
—
—
0
Max.
—
Min.
120
—
—
—
0
Max.
—
Unit
ns
t
Read Cycle Time
RC
t
Address Access Time
70
70
35
—
90
90
45
—
120
120
60
ns
AA
t
Chip Enable Access Time
Output Enable Access Time
CE Low to Output Active
OE Low to Output Active
OE or CE High to Output in High Z
Output Hold from Address Change
ns
ACS
t
ns
OE
t
—
ns
CLZ
t
0
—
0
—
0
—
ns
OLZ
t
0
30
—
0
40
—
0
50
ns
DF
t
0
0
0
—
ns
OH
Program (Erase/Program) Cycle
Parameter
-70
-90
-12
Name
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
t
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
70
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
35
10
3.0
90
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
35
10
3.0
120
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
35
10
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µ s
ms
sec
WC
t
AS
t
45
0
45
0
50
0
AH
t
CS
t
CE Hold Time
0
0
0
CH
t
OE Setup Time
0
0
0
OES
t
OE High Hold Time
WE Pulse Width
WE Pulse Width High
Data Setup Time
Data Hold Time
0
0
0
OEH
t
35
20
30
0
45
30
30
0
50
35
30
0
WP
t
WPH
t
DS
t
DH
t
t
t
Programming Cycle
Sector Erase Cycle
Chip Erase Cycle
—
—
—
—
—
—
—
—
—
WHWH1
WHWH2
WHWH3
S29C51004T/S29C51004B V1.0 May 2002
5
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Waveforms of Read Cycle
tRC
ADDRESS
tAA
tCE
CE
tOE
tDF
OE
tOLZ
WE
tCLZ
tOH
HIGH-Z
I/O
HIGH-Z
VALID DATA OUT
tAA
VALID DATA OUT
51004-09
Waveforms of WE Controlled-Program Cycle
3rd bus cycle
tWC
tAS
PA(2)
5555H
PA
ADDRESS
tRC
tCH
tAH
CE
OE
tWHWH1
tWP
tOES
WE
tDF
tWPH
tDS
tCS
tOE
tDH
PD(3)
(1)
DOUT
I/O
A0H
I/O7
tOH
51004-10
NOTES:
1. I/O : The output is the complement of the data written to the device.
7
2. PA: The address of the memory location to be programmed.
3. PD: The data at the byte address to be programmed.
S29C51004T/S29C51004B V1.0 May 2002
6
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Waveforms of CE Controlled-Program Cycle
tWC
5555H
PA
tAS
tAH
PA(1)
ADDRESS
tRC
WE
OE
tWP
tWHWH1
CE
I/O
tDF
tWPH
tDS
tOES
tOE
tDH
PD(2)
DOUT
A0H
I/O7
tOH
51004-11
(1)
Waveforms of Erase Cycle
(5555H for Chip Erase)
SA
tWC
tAS
2AAAH
5555H
5555H
tAH
5555H
2AAAH
ADDRESS
CE
OE
WE
tWP
2
3
tWPH
tWHWH
tCS
tDS
(10H for
tDH
Chip Erase)
AAH
55H
80H
AAH
55H
30H
I/O
51004-12
NOTES:
1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.
3. SA: The sector address for Sector Erase.
S29C51004T/S29C51004B V1.0 May 2002
7
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Waveforms of DATA Polling Cycle
tCH
CE
tDF
tOE
OE
tOEH
tCE
WE
tOH
tWHWH1 (2 or 3)
HIGH-Z
VALID DATA OUT
I/O7
I/O7
I/O7
HIGH-Z
VALID DATA OUT
INVALID
I/O0-I/O6
I/O0-I/O6
51004-13
Waveforms of Toggle Bit Cycle
CE
tOEH
WE
OE
I/O6
stop toggling
tWHWH1 (2 or 3)
51004-14
S29C51004T/S29C51004B V1.0 May 2002
8
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
S29C51004B
Functional Description
S29C51004T
The S29C51004T/S29C51004B consists of 512
equally-sized sectors of 1K bytes each. The 16 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.
7FFFFH
7C000H
16KB Boot Block
1 KB
1 KB
1 KB
The S29C51004 is available in two versions: the
S29C51004T with the Boot Block address starting
from 7C000H to 7FFFFH, and the S29C51004B
with the Boot Block address starting from 00000H
to 3FFFFH.
1 KB
1 KB
03FFFH
00000H
16KB Boot Block
1 KB
00000H
Read Cycle
51004-15
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
16KB Boot Block = 32 Sectors
During the byte write cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte write cycle
can be CE controlled or WE controlled.
Output Disable
Sector Erase Cycle
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
The S29C51004T/S29C51004B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
and the sector erase command (see Table 2). A
sector must be first erased before it can be re-
written. While in the internal erase mode, the
device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit status.
The S29C51004T/S29C51004B is shipped fully
erased (all bits = 1).
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE input state.
Byte Write Cycle
The S29C51004T/S29C51004B is programmed
on a byte-by-byte basis. The byte write operation is
initiated by using a specific four-bus-cycle
sequence: two unlock program cycles, a program
setup command and program data program cycles
(see Table 2).
Table 1. Operation Modes Decoding
Decoding Mode
Read
CE
OE
WE
A
A
A
I/O
READ
PD
0
0
0
1
1
1
9
9
9
V
V
V
V
IH
A
A
A
A
A
A
IL
IL
IH
IL
Byte Write
V
V
IH
IL
Standby
V
X
X
X
X
X
HIGH-Z
CODE
CODE
X
Autoselect Device ID
Autoselect Manufacture ID
Enabling Boot Block Protection Lock
Disabling Boot Block Protection Lock
Output Disable
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IH
IH
IH
IL
IL
H
H
H
H
V
IL
V
V
V
V
X
X
H
IL
IL
IH
V
X
X
X
X
X
H
H
V
V
V
X
HIGH-Z
IL
IH
NOTES:
1. X = Don’t Care, V = HIGH, V = LOW, V = 12.5V Max.
IH
IL
H
2. PD: The data at the byte address to be programmed.
S29C51004T/S29C51004B V1.0 May 2002
9
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Table 2. Command Codes
First Bus
Second Bus
Third Bus
Fourth Bus
Fifth Bus
Six Bus
Program Cycle
Program Cycle
Program Cycle
Program Cycle
Program Cycle
Program Cycle
Command
Sequence
Address Data Address Data Address Data Address Data
Address Data Address Data
Read
Read
XXXXH
5555H
5555H
F0H
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
F0H RA(1)
RD(2)
See table 3 for detail.
Autoselect
Mode
90H
Byte
5555H
5555H
AAH 2AAAH
55H
5555H
A0H PA
PD(4)
Program
Chip Erase
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
80H
80H
5555H
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
SA(5)
10H
30H
Sector Erase 5555H
NOTES:
1. RA: Read Address
2. RD: Read Data
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
5. SA(5): Sector Address
Chip Erase Cycle
Toggle Bit (I/O )
6
The S29C51004T/S29C51004B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
The S29C51004T/S29C51004B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O toggling between 1 and 0. Once the program is
6
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
Boot Block Protection Enabling/Disabling
The S29C51004T/S29C51004B features
hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin LOW. The sector protection is
disabled when high voltage is applied to OE, CE
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.
Program Cycle Status Detection
There are two methods for determining the state
of the S29C51004T/S29C51004B during a
program (erase/write) cycle: DATA Polling (I/O )
7
and Toggle Bit (I/O ).
6
DATA Polling (I/O )
7
The S29C51004T/S29C51004B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
Autoselect Mode
The S29C51004T/S29C51004B features an
Autoselect mode to identify boot block locking
status, device ID and manufacturer ID.
complement of the loaded data on I/O . Once the
7
program cycle is completed, I/O will show true
7
data, and the device is then ready for the next
cycle.
Entering Autoselect mode is accomplished by
applying a high voltage (VH) to the A9 Pin, or
through a sequence of commands (as shown in
table 2). Device will exit this mode once high
voltage on A9 is removed or another command is
loaded into the device.
S29C51004T/S29C51004B V1.0 May 2002
10
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Boot Block Protection Status
Manufacturer ID
In Autoselect mode, performing a read at
address location 3CXX2H (S29C51004T) or
0CXX2H (S29C51004B) will indicate boot bloc
protection status. If the data is 01H, the boot block
is protected. If the data is 00H, the boot block is
unprotected. This is also shown is table 3.
In Autoselect mode, performing a read at
address XXXX0H will determine the manufacturer
ID.40H is the manufacturer code for SyncMOS
Flash.
Hardware Data Protection
V
Detection: the program operation is inhibited
CC
Device ID
when VCC is less than 3.5V.
In Autoselect mode, performing a read at
address XXX1H will determine whether the device
is a Top Boot Block device or a Bottom Boot Block
device. If the data is 03H, the device is a Top Boot
Block. If the data is A3H, the device is a Bottom
Boot Block device (see Table 3).
Noise Protection: a CE or WE pulse of less than
5ns will not initiate a program cycle.
Program Inhibit: holding any one of OE LOW, CE
HIGH or WE HIGH inhibits a program cycle.
Table 3. Autoselect Decoding
Address
Decoding Mode
Boot Block
Top
A
A
A –A
A
–A
Data I/O –I/O
0
IL
IL
IH
1
IH
IH
2
13
14
17
0
7
Boot Block Protection
V
V
V
V
X
X
X
V
01H: protected
IH
Bottom
Top
V
00H: unprotected
IL
Device ID
V
V
X
03H
A3H
40H
IL
Bottom
Manufacture ID
V
V
X
X
IL
IL
NOTE:
1. X = Don’t Care, V = HIGH, V = LOW.
IH
IL
S29C51004T/S29C51004B V1.0 May 2002
11
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Byte Program Algorithm
Chip/Sector Erase Algorithm
Write Byte-Write
Write Erase
Command Sequence
Command Sequence
Add/Data
Add/Data
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Four Bus
Cycle
Sequence
5555H/A0H
PA/PD
Six Bus
Cycle
Sequence
Data Polling or Toggle bit
successfully completed
or tWTWH (2 or 3) timeout
5555H/10H (Chip Erase)
SA/30H (Sector Erase)
Writing
Completed
Data Polling or Toggle bit
successfully completed
or tWTWH (2 or 3) timeout
Erase Completed
51004-16
S29C51004T/S29C51004B V1.0 May 2002
12
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
DATA Polling Algorithm
Toggle Bit Algorithm
Read I/O7
Read I/O6
Address = PBA(1)
No
Read I/O6
I/O7 = Data
Yes
Yes
I/O6 Toggle
No
Program
Done
Program
Done
51004-17
NOTE:
1. PBA: The byte address to be programmed.
S29C51004T/S29C51004B V1.0 May 2002
13
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Package Diagrams
32-pin Plastic DIP
1.660 MAX.
15° MAX
INDEX-1
EJECTOR MARK
.600 TYP
0.545/0.555
INDEX-2
+.004
– .0004
.010
.050 MAX
0.210 MAX
0.120 MIN
.100
TYP
+.006
– .002
+.012
– 0
0.010 MIN
.018
.047
+.012
.032
– 0
32-pin PLCC
20 19 18 17 16 15 14
21
22
23
13
12
11
.590 ± .005
24
25
26
27
28
29
10
9
.550 ± .003
8
7
6
5
30 31 32
1
2
3
4
.045X45°
.450 ± .003
.490 ± .005
.136 ± .003
.110
.046 ± .003
.025
.050 TYP
30°
.017
3° - 6°
.420 ± .003
3° - 6°
3° - 6°
S29C51004T/S29C51004B V1.0 May 2002
14
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
32-pin TSOP-I
Units in inches
Detail “A”
0.787 ± 0.008
0.010
0.315 TYP.
(0.319 MAX.)
0.024 ± 0.004
0.724 TYP. (0.728 MAX.)
0.035 ± 0.002
SEATING
PLANE
0.047 MAX.
0.032 TYP.
See Detail “A”
0.020 MAX.
0.020 SBC
0.005 MIN.
0.007 MAX.
0.003 MAX
0.009 ± 0.002
S29C51004T/S29C51004B V1.0 May 2002
15
SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Sales Office :
4th Floor, No. 1, Creation Rd. 1,
Science-Based Industrial Park,
Hsinchu, Taiwan 30077
Tel : 886-3-5792988
Fax : 886-3-5792960
Note :
1. Publication date : November 1998 Rev. A , May 2002 Rev. B
2. All data and specification are subject changed with Program
(Erase/Program) Cycle as below description :
a. Chip erase time : 2.0 sec → 3.0 sec maximum.
b. Byte program time : 20 usec → 35 usec maximum
S29C51004T/S29C51004B V1.0 May 2002
16
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