S80016LK7MK7FB-8A [ETC]
SYVCHRONOUS DRAM; SYVCHRONOUS DRAM
| 型号： | S80016LK7MK7FB-8A |
| 厂家： | 
ETC |
| 描述： | SYVCHRONOUS DRAM |
| 文件： | 总9页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128Mb: x4, x8, x16
SDRAM 3.3V
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS: Vdd = 3.3V ± 10%V, Temp. = 25° to 70 °C
Supply Current
OPERATING CURRENT: ACTIVE mode, burst = 1, READ or WRITE, tRC > tRC
(MIN), one bank active, CL=3
Symbol
Icc1
-75A
165
-8A
140
Units
mA
Notes
1, 2, 3, 4
STANDBY CURRENT: POWER-DOWN mode, CKE = LOW,
Standard parts
Idd2
9
9
mA
32
no accesses in progress
Self refresh parts
Idd2
Icc3
Icc4
3
75
75
3
60
50
mA
mA
mA
32
1, 2, 3, 4
1, 2, 3, 4
STANDBY CURRENT: CS# = HIGH, CKE = HIGH, all banks idle
STANDBY CURRENT: CS# = HIGH, CKE = HIGH, all banks active after tRCD met,
no accesses in progress.
OPERATING CURRENT: BURST mode after tRCD met, continuous burst, READ,
WRITE, all banks active, CL=3
Icc5
165
145
mA
1, 2, 3, 4
AUTO REFRESH CURRENT tRC > tRC (MIN)
AUTO REFRESH CURRENT tRC=15.6us
SELF REFRESH CURRENT (Self refresh parts only, part M)
CL = 3
CL = 3
Icc6
Icc7
Idd8
265
50
3
245
50
3
mA
mA
mA
1, 2, 3, 4
1, 2, 3, 4
Notes
1. All voltages referenced to Vss.
2. An initial pause of 100 ms is required after power-up, followed by two AUTO REFRESH commands, before proper device operation
is ensure. (Vdd and VddQ must be powered-up simultaneously Vss and VssQ must be at the same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
3. Icc specifications are tested after the device is properly initialized. tCK= 10ns for –8 and tCK=7.5ns for –75A.
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
SpecTek reserves the right to change products or
specifications without notice. Ó 2001, 2002, 2004 SpecTek
3
www.spectek.com
128Mb: x4, x8, x16
SDRAM 3.3V
AC ELECTRICAL CHARACTERISTICS: Vdd = 3.3V ± 10%V, Temp. = 25° to 70°C
AC CHARACTERISTICS
PARAMETER
Access time from CLK (positive edge) CL = 3
Access time from CLK (positive edge) CL = 2
Address hold time
Address setup time
CLK high level width
CLK low level width
Clock cycle time CL = 3
Clock cycle time CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
-75A
MIN
-75A
MAX
5.4
-8A
MIN
-8A
MAX
6
SYMBOL
tAC
UNITS
ns
NOTES
tAC
tAH
tAS
tCH
tCL
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8
1.5
2.5
2.5
7.5
N/A
0.8
1.5
0.8
1.5
0.8
1.5
1
2
3
3
10
1
2
1
2
1
2
Data-in setup time
tDS
ns
Data-out high impedance time
Data-out low impedance time
Data-out hold time
ACTIVE to PRECHARGE command period
AUTO REFRESH to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4096 cycles)
PRECHARGE command period
ACTIVE bank A to bank B command period
Transition time
tHZ
tLZ
tOH
tRAS
tRC
tRCD
tREF
tRP
tRRD
tT
tWR
tXSR
tCCD
tCKED
tPED
9
16K
64
2
9
16K
64
2
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
tCK
tCK
tCK
tCK
4
1
2.7
44
60
22.5
2
3
50
80
30
22.5
15
0.3
20
8
1
1
1
30
20
0.3
20
8
1
1
1
Write recovery time
3
Exit SELF REFRESH to ACTIVE command
READ/WRITE command to READ/WRITE command
CKE to clock disable or power down entry mode
CKE to clock enable or power down exit setup
1
2
2
AC ELECTRICAL CHARACTERISTICS: Vdd = 3.3V ± 10%V, Temp. = 25° to 70°C
AC CHARACTERISTICS
-75A
-75A
-8
-8
PARAMETER
DQM to input data delay
WRITE command to input data delay
Data-in to ACTIVATE command w/ Auto precharge
Data-in to precharge
SYMBOL
tDQD
tDWD
tDAL
MIN
MAX
MIN
MAX
UNITS
tCK
tCK
tCK
tCK
NOTES
0
0
5
2
0
0
5
2
1
1
3
tDPL
2, 3
Last data-in to precharge command
LOAD MODE REGISTER command to command
Data-out to high impedance from precharge
tRDL
tMRD
tROH
2
2
3
2
2
3
tCK
tCK
tCK
1
1
1
NOTES:
1. Clocks required specified by JEDEC functionality and not dependent on any timing parameter.
2. Timing actually specified by tCKS, clock(s) specified as a reference only at a minimum cycle rate.
3. Timing actually specified by tWR plus tRP clock(s) specified as a reference only at a minimum cycle rate.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. The last valid data
element will meet tOH before going high-Z.
5. Based on tCK = 10ns for –8 and tCK = 7.5ns for –75a
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
SpecTek reserves the right to change products or
specifications without notice. Ó 2001, 2002, 2004 SpecTek
4
www.spectek.com
128Mb: x4, x8, x16
SDRAM 3.3V
54-PIN PLASTIC TSOP (400 mil)
(Package TK)
NOTE: 1. All dimensions in millimeters MAX/MIN or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
SpecTek reserves the right to change products or
specifications without notice. Ó 2001, 2002, 2004 SpecTek
5
www.spectek.com
128Mb: x4, x8, x16
SDRAM 3.3V
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
SpecTek reserves the right to change products or
specifications without notice. Ó 2001, 2002, 2004 SpecTek
6
www.spectek.com
128Mb: x4, x8, x16
SDRAM 3.3V
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
SpecTek reserves the right to change products or
specifications without notice. Ó 2001, 2002, 2004 SpecTek
7
www.spectek.com
128Mb: x4, x8, x16
SDRAM 3.3V
FBGA “FB” PACKAGE
60-pin, 8mm x 16mm
NOTE: 1. All dimensions in millimeters.
2. Recommended Pad size for PCB is 0.33mm±0.025mm.
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
SpecTek reserves the right to change products or
specifications without notice. Ó 2001, 2002, 2004 SpecTek
8
www.spectek.com
128Mb: x4, x8, x16
SDRAM 3.3V
PART NUMBERS FOR PRODUCT PRIOR TO DECEMBER 2004
Options:
Marking:
Architecture:
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
S40032LK8
S80016LK7
S16008LK9
Voltage and Refresh:
3.3V, Auto Refresh
LK
MK
3.3V, Self or Auto Refresh1
Device Configuration:
32 Meg x 4
16 Meg x 8
8
7
9
8 Meg x 16
Package Types:
54-pin plastic TSOP (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
TW
FB2
FC2
Timing Types:
PC100 (3-3-3)
PC133 (3-3-3)
-8A
-75A
Part number example:
S80016LK7TW-8A
NOTES: 1. Only when specified. Consult Sales
2. Not available in x16 configuration
http://www.spectek.com/menus/part_guides.asp
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
SpecTek reserves the right to change products or
specifications without notice. Ó 2001, 2002, 2004 SpecTek
9
www.spectek.com
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