SCG4501 [ETC]
Synchronous Clock Generators; 同步时钟发生器型号: | SCG4501 |
厂家: | ETC |
描述: | Synchronous Clock Generators |
文件: | 总16页 (文件大小:1034K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SCG4501
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Features
• ± 32 ppm Capture/Pull-In Range
• Phase Locked Output Frequency Control
• Intrinsically Low Jitter Crystal Oscillator
• LVPECL Outputs with Disable Function
• Dual Input References
• LOR & LOL combined alarm output
• Force Free Run Function
• Automatic Free Run operation on loss of
both References A & B
• Input Duty Cycle Tolerant
• 3.3V dc Power Supply
• Small Size: 1 Square Inch
Bulletin
SG040
Page
1 of 16
Revision
P01
Date
13 NOV 03
Issued By
MBatts
General Description
Maximum Dimension Package Outline
The SCG4501 is a mixed-signal phase locked loop
generating LVPECL outputs from an intrinsically low
jitter, voltage controlled, crystal oscillator. The LVPECL
outputs may be disabled.
Figure 1
The SCG4501 can lock to one of two external
references, which is selectable using the SELAB input
select pin. The unit has a fast acquisition time of about
1.5 seconds and it is tolerant of different reference duty
cycles.
The SCG4501 includes an alarm output that
indicates deviations from normal operation. If a Loss-
of-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FRstatus
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to 20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1” x 1.025” x .45” on a
6 layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Block Diagram
Figure 2
10 kΩ
FREE RUN STATUS
FORCE
FREE RUN
10 kΩ
ALARM
33 Ω
Q
REFA
8 KHz PHASE
ALIGNER
LOW JITTER
33 Ω
DPFD
ANALOG
FILTER
VCXO
REFB
QN
1 / N
SEL AB
10 kΩ
OPTIONAL
REFERENCE
OUTPUT
33 Ω
ENABLE/
TRI-STATE
10 kΩ
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
-0.5
Nominal
Maximum
+4.0
Units
Volts
Volts
°C
Notes
1.0
Vcc
Vi
Power Supply Voltage
Input Voltage
-
-
-
-0.5
+5.5
1.0
Ts
Storage Temperature
-65.0
+100
1.0
Preliminary Data Sheet #: SG040
Page 2 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Operating Specifications
Table 2
Symbol
Parameter
Minimum
Nominal
Maximum
3.465
280
Units
Volts
mA
Notes
2.0
Vcc
Power Supply Voltage
Power Supply Current
Temperature Range
Free Run Frequency
Capture/pull-in range
Jitter Filter Bandwidth
3.135
170
0
3.3
Icc
230
4.0
To
-
-
-
-
70
°C
Ffr
-20
-32
-
20
ppm
ppm
Hz
Fcap
Fbw
Tjtol
32
10
3.0
Input Jitter Tolerance
(Input Jitter Frequencies ≥ 10 Hz)
31.25
1
-
-
-
-
µs
8 kHz Ref. units
µs 19.44 MHz Ref. units
Taq
Typical Acquisition Time Data
Acquisition from a cold power-up:
Phase lock within 12ns:
Phase lock settled:
50
220
<1.5
sec
sec
sec
Alarm time:
Acquisition from Free Run:
Phase lock within 12ns:
Phase lock settled:
50
220
sec
sec
Alarm time:
Typically no alarm
Frequency lock with a 20PPM reference frequency step: Typically 0.5s.
Phase lock during a switch between equal frequency references: Typically 0.5s, no alarm should be issued
Trf
Output Rise and Fall Time (20% 80%)
Output Duty Cycle
100
40
225
50
350
60
ps
%
4.0
DC
MTIEsr
MTIE at Synchronization Rearrangement
Dynamic Offset Range (0°- 25°)
Dynamic Offset Range (25°- 70°)
GR-253-CORE.1999 R5-136
5.0, 6.0
-50
-50
-
-
50
50
ns
ns
Output Jitter Specifications
Table 3
Jitter BW 10 Hz - 1 MHz
SONET Jitter BW 12 kHz - 20 MHz
Frequency (MHz)
77.76
pS (RMS)
10 Typ.
10 Typ.
10 Typ.
m UI
pS (RMS)
m UI
0.776 Typ.
1.250 Typ.
1.556 Typ.
1 Max.
0.076 Max.
125.00
1 Max.
0.125 Max.
0.156 Max.
155.52
1 Max.
NOTES:
1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF)
3.0 3db loop response.
4.0 50-ohm load biased to 1.3 volts.
5.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing.
6.0 If the selected reference is removed system response to the ALARM must be less than 10µs.
Preliminary Data Sheet #: SG040 Page 3 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Input And Output Characteristics
Table 4
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
CMOS Input and Output Characteristics
Vih
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
2.0
0.0
-
-
-
-
-
-
-
-
5.5
0.8
10
10
-
V
Vil
V
Tio
Cl
ns
pF
V
Output Capacitance
-
Voh
Vol
Tir
High Level Output Voltage
Low Level Output Voltage
Input Reference Pulse Width
2.4
-
0.4
-
V
12.5
ns
PECL Output Characteristics
Voh
High Level PECL Voltage
2.27
2.34
1.51
-
2.52
1.68
10
V
Vol
Low Level PECL Voltage
Output Capacitance
1.49
V
Cl
-
-
pF
ps
Tskew
Differential Output Skew
50
-
Input Selection / Output Response
Table 5
INPUTS
REFA
OUTPUTS
ALARM
NOTE
RESET
ENABLE SELAB
REFB
X
FR
X
X
1
FRstatus
Q
X
0
QN
1
X
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
X
X
X
0
1
0
1
1
0
X
X
1
X
1
0
0
0
0
0
0
1
X
X
X
0
0
1
0
1
0
1
X
1
FR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FR
RA
RB
U
A
A
0
A
A
0
NA
NA
A
A
0
A
0
RB
U
NA
NA
NA
0
A
0
RA
FR
NA
0
NOTES:
A
Active
FR Free Run Mode
NA Not Active
RA Locked to Reference A
RB Locked to Reference B
U
X
Unstable (due to conditions shown, switch to active reference or Free Run)
Don’t care
Preliminary Data Sheet #: SG040
Page 4 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical MTIE Measurement
Figure 3
Typical TDEV Measurement
Figure 4
Preliminary Data Sheet #: SG040 Page 5 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical MTIE at Synchronization Rearrangement. Reference B Equal to Inverse of
Reference A, No Modulation.
Figure 5
Preliminary Data Sheet #: SG040
Page 6 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Pin Description
Table 6
Pin #
Pin Name
Pin Information
Note
9.0
1
ENABLE/TRI-STATE
VCXO Enable. (Enable = 0, Disable = 1 = CMOS Outputs Tri-stated)
No Connection, Internal Factory Programming Input.
No Connection, Internal Factory Programming Input.
CMOS Reference Frequency Input.
Input Reference Select Pin. (REFA = 0, REFB = 1)
RESET. (RESET = 1)
2
TCK
TDO
REFA
SELAB
RESET
REFB
Vee
8.0
3
8.0
4
5
9.0
9.0
6
7
CMOS Reference Frequency Input.
Ground.
8
9
FRstatus
Vcc
Free Run Status. (FR = 1)
10
11
12
13
14
15
16
17
18
Supply Voltage relative to ground.
N/C
No Connection. (Optional Reference Output Available)
Loss of Reference / Lock alarm. (Alarm = 1)
Force Free Run. (Phase Lock = 0, Free Run = 1)
No Connection, Internal Factory Programming Input.
No Connection, Internal Factory Programming Input.
LVPECL Complementary Output.
8.0, 8.1
ALARM
FR
9.0
8.0
8.0
TDI
TMS
QN
Vee
Ground.
Q
LVPECL Output.
NOTES
8.0 Do not connect pin
8.1 Contact a Sales Representative for availibilty
and use of optional reference output
9.0 Input pulled to ground
Circuit Board Footprint & Keepout Recommendations
Figure 6
0.8650
[21.97 mm]
0.0650
[1.65 mm]
Keep Out
Area
0.8400
[21.34 mm]
1.0400
[26.42 mm]
0.1000
[2.54 mm]
0.1000
[2.54 mm]
0.0350
[0.89 mm]
1.0700
[27.18 mm]
Preliminary Data Sheet #: SG040 Page 7 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Reference Condition Alarm Timing
Figure 7
Start-up
Region
Alarm Output
(LOR + LOL)
LOR
(Internal Signal)
4
LOL
(Internal Signal)
2
1
1
Phase Detector
(Internal Signal)
3
External Reference
(Selected Input A or B)
Internal Reference
(Internal Signal)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
AlarmTiming Legend
Use for all alarm timing diagrams
Table 7
19.44 MHz Reference Input Units
< 1 µsec
8 kHz Reference Input Units
< 31.25 µsec
1
2
3
4
5
1 µsec
31.25 µsec
> 1 µsec
> 31.25 µsec
LOR is active when LOL is active
Minimum pulse width = 2 µsec
125 µsec wide range
Minimum pulse width = 62.5 µsec
During Start-up, The LOL Alaram will pulse
during the few seconds of operation
Start-up Region
Preliminary Data Sheet #: SG040
Page 8 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Lock Condition Alarm Timing
Figure 8
Alarm Output
(LOR + LOL)
LOR
(Internal Signal)
LOL
(Internal Signal)
5
1
1
1
1
1
Phase Detector
(Internal Signal)
3
3
External Reference
(Selected Input A or B)
Internal Reference
(Internal Signal)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Preliminary Data Sheet #: SG040 Page 9 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when both are good signals
Figure 9
Ref A
Ref B
Alarm
LOL portion of
Alarm is
Blanked
0.5 sec
Sel A/B
New Reference
Qualification time
Switch from A to B when Reference B is lost
Figure 10
Ref A
Ref B
Alarm
~8ns
Sel A/B
Preliminary Data Sheet #: SG040
Page 10 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B after Reference A is lost
Figure 11
Ref A
Ref B
Alarm
Blanked
Alarm
156.25µs (8 kHz Ref units)
126µs (19.44 MHz Ref units)
Sel A/B
New Reference
Qualification time
Switch from A to B when A is out of range
Figure 12
Out of
Range
Ref A
Ref B
Alarm
In
Range
Alarm
Blanked
Sel A/B
New Reference
Qualification time
Preliminary Data Sheet #: SG040 Page 11 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when B is out of range
Figure 13
Switch from A to B when B is out of range
In
Range
Ref A
Ref B
Alarm
Out of
Range
Alarm
Blanked
SEL A/B
New Reference
Qualification Time
0.5 sec.
Switch from A to B when B is out of range
Figure 14
Ref A
Ref B
Alarm
Alarm
Blanked
Sel A/B
New Reference
Qualification time
Free Run
Status
Preliminary Data Sheet #: SG040
Page 12 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended PECL Termination
Figure 15
3.3 VDC
3.3 VDC
3.3 VDC
130Ω
82Ω
Vcc
Q
Vcc
50Ω Transmission Line
50Ω Transmission Line
D
SCGXXXX
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
GND
GND
130Ω
82Ω
3.3 VDC
3.3 VDC
Vcc - 2 VDC
50Ω
Vcc
Q
Vcc
D
50Ω Transmission Line
50Ω Transmission Line
SCGXXXX
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
GND
GND
50Ω
Vcc - 2 VDC
3.3 VDC
3.3 VDC
150Ω
Vcc
Q
Vcc
D
50Ω Transmission Line
50Ω Transmission Line
SCGXXXX
LVPECL
OUTPUT
LVPECL
INPUT
100Ω
QN
DN
GND
GND
150Ω
If PECL outputs do not drive a long line (< 0.5”),
a single 150Ω termination resistor to ground may be used for each pin.
Preliminary Data Sheet #: SG040 Page 13 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Tape and Reel Packaging
Figure 16
Preliminary Data Sheet #: SG040
Page 14 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Solder Profile
Figure 17
250
200
150
100
50
Temp
(C˚)
0
1
2
3
4
5
6
7
8
Time(minutes)
Recommended Reflow Profile
Peak Temp:217C˚
MaxRiseSlope:1.5C˚/Sec
Time Above150C˚:100Sec
Model ComparisonTable
Table 8
Max
Model
Input
Duty
Oscillator Output
Notes
Ref Freq
SCG4500 8 kHz/8 kHz
SCG4501 8 kHz/8 kHz
SCG4510 3@1.544 MHz
SCG4520 3@19.44 MHz
SCG4540 3@10 kHz
Cycle
(Synchronized Output)
40/60
40/60
40/60
40/60
40/60
77.76 MHz,155.52 MHz,125 MHz
77.76 MHz,155.52 MHz,125 MHz
155.52 MHz
Basic Model
±±3 ꢀꢀp Pullꢁ-n ranꢂe
77.76 MHz,155.52 MHz
16±.84 MHz
Other low jitter line card solutions from Connor-Winfield
SCG51 Series
Single input, jitter filtered with Free Run, 1 CMOS and 3 LVPECL outputs up to 622.08 MHz.
Single input, frequency selectable, LVPECL clock smoothers from 77.76 to 777.76 MHz.
Single input, jitter filtered with 20ppm Free Run, CMOS outputs from 8 kHz to 125.0 MHz.
Dual input, jitter filtered with Free Run, CMOS outputs from 8 kHz to 125.0 MHz.
Single input, jitter filtered with Dual LVPECL outputs.
SCG102A/104A
SCG2000 Series
SCG2500 Series
SCG3000 Series
SCG4000 Series
SCG4600 Series
Single input, jitter filtered with 20ppm Free Run, LVPECL outputs from 77.76 MHz to 180 MHz.
Dual input, jitter filtered with Free Run, 1 CML differential pair output up to 622.08 MHz.
Preliminary Data Sheet #: SG040 Page 15 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Revision
P00
Revision Date
12/20/01
Note
Preliminary Release
Updated to V3.01
P01
11/13/03
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明