SDU01G64H3BJ2SA-50R [ETC]
1024MB DDR . unbuffered DDR1 UDIMM;
| 型号： | SDU01G64H3BJ2SA-50R |
| 厂家： | 
ETC |
| 描述： | 1024MB DDR . unbuffered DDR1 UDIMM 双倍数据速率 |
| 文件： | 总13页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Rev.1.0
18.09.2012
1024MB DDR – unbuffered DDR1 UDIMM
Features:
.
184-pin 64-bit unbuffered Dual-In-Line Double
Data Rate Synchronous DRAM module
Module organization: dual rank 128M x 64
VDD = 2.5V ±0.2V, VDDQ 2.5V ±0.2V
184PIN UDIMM
SDU01G64H3BJ2SA-xxR
1GByte in TSOP Technology
RoHS compliant
.
.
.
.
.
.
.
VDD = 2.6V ±0.1V, VDDQ 2.6V ±0.1V (DDR400)
2.5V I/O ( SSTL_2 compatible)
Serial Presence Detect with EEPROM
Gold-contact pads
Options:
This module is fully pin and functional compatible
to the JEDEC PC-3200 spec. and JEDEC-
Standard MO-206. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of
Hazardous Substances (RoHS)]
.
Data Rate / Latency
DDR 400 MT/s CL3
DDR 333 MT/s CL2.5
Marking
-50
-60
.
.
Module density
1024MB with 16 dies and 2 ranks
Standard Grade (TA)
0°C to 70°C
.
DDR-SDRAM component base: Samsung
K4H510838J DIE rev. J
.
.
.
.
.
64Mx8 DDR1 SDRAM in TSOP66 package
Internal, pipelined double-data-rate (DDR)
2n pre-fetch architecture
DLL to align DQ and DQS transitions with CK
Bidirectional data strobe (DQS)
Environmental Requirements:
transmitted/received with data, source-
synchronous data capture
.
Operating temperature (TA)
Standard Grade
.
.
.
.
.
.
.
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Four internal banks for concurrent operation
Data mask (DM) for masking write data
Programmable burst length: 2,4 or 8
Adjustable data-output drive strength
Auto Refresh (CBR) and Self Refresh, 8k
Refresh every 64ms
0°C to 70°C
.
.
.
.
.
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
Figure: mechanical dimensions1
1682 PSI (up to 5000 ft.) at 50°C
5.250 ( 133.35 )
.080 ( 2.03 ) R
.080 ( 2.03 ) R
.049 ( 1.25 ) R
.096 ( 2.45 )
PIN 92 ( PIN 184 on
Backside )
PIN 1 ( PIN 93 on
Backside )
2.893 ( 73.50 )
4.744 ( 120.50 )
1
if no tolerances specified ± 0.15mm
Swissbit AG
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Page 1
of 13
Data Sheet
Rev.1.0
18.09.2012
This Swissbit module family is industry standard 184-pin 8-byte Double Date rate synchronous SDRAM Dual-In-line
Memory Modules (DIMMs), which are organized as x64 high speed memory arrays designed for use in non-parity
applications. DIMMs are assembled in TSOP Technology. The passive devices and the EEPROM are SMD
components.
The DIMM use serial presence detects (SPD) implemented via serial EEPROM using the two-pin-I2C protocol. The
first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
All Swissbit DIMMs provide a high performance, flexible 8-byte interface in a 133.35mm long footprint.
All modules of the extended temperature grade have seen special tests during the manufacturing process to
ensure proper operation according to the field of operation as stated in the environmental conditions.
Module Configuration
Row
Addr.
Column
Addr.
Module
Bank Select
Organization
DDR SDRAMs used
Device Bank Addr.
Refresh
128M x 64bit 16 x 64M x 8bit (512Mbit)
13
BA0, BA1
11
8k
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 30(high) x 4.00 [max] (thickness)
Product Parameters
Part Number
Module Density
1024MB
Transfer Rate
3.2 GB/s
Clock Cycle/Data bit rate
5.0ns/400MT/s
Latency
3.0-3-3
SDU01G64H3BJ2SA-50R
SDU01G64H3BJ2SA-60R
1024MB
2.7 GB/s
6.0ns/333MT/s
2.5-3-3
Pin Name
A0 – A12
Address Inputs
BA0, BA1
DQ0 – DQ63
DM0 – DM7
RAS#
Bank Address Inputs
Data Input/Output
Input Data Mask
Row Address Strobe
CAS#
Column Address Strobe
Read / Write Enable
Clock Enable
WE#
CKE0 – CKE1
CK0 – CK1
CK0# – CK1#
DQS0 – DQS7
Clock Inputs, positive line
Clock Inputs, negative line
Data strobes
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Page 2
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Data Sheet
Rev.1.0
18.09.2012
S0# – S1#
VDD
Chip Select
Power (2.5V± 0.2V)
VDDQ
DQ Power (2.5V±0.2V)
SPD Power
VDDSPD
VREF
Input/Output Reference
Ground
VSS
SCL
Clock for Presence Detect
Serial Data Out for Presence Detect
Slave Address Select Bus for Presence Detect
No Connection
SDA
SA0 – SA2
NC
Pin Configuration
Front Side
PIN Name PIN #
Back Side
PIN Name PIN #
PIN #
1
PIN Name
DQS8
A0
PIN #
93
PIN Name
VREF
DQ0
VSS
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
VSS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
VSS
2
94
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
DM8
A10
3
NC
95
4
DQ1
DQS0
DQ2
VDD
VSS
96
NC
5
NC
97
VDDQ
NC
6
BA1
98
7
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
99
VSS
8
DQ3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
DQ36
DQ37
VDD
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
VSS
NC
DM4
DQ38
DQ39
VSS
DQ8
DQ9
DQS1
VDDQ
NC
VDDQ
DQ12
DQ13
DM1
VDD
BA0
DQ35
DQ40
VDDQ
/WE
DQ44
/RAS
DQ45
VDDQ
/S0
NC
DQ14
DQ15
NC
VSS
DQ41
/CAS
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VDDQ
NC
NC
DQS5
DQ42
DQ43
VDD
DM5
VSS
DQ20
A12
DQ46
DQ47
NC
VSS
NC
DQ21
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Page 3
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Data Sheet
Rev.1.0
18.09.2012
Front Side
PIN Name
Back Side
PIN Name PIN #
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
PIN #
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
PIN Name
DQ48
DQ49
VSS
PIN #
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
PIN Name
VSS
A11
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VDDQ
DQ52
DQ53
NC
A9
DM2
VDD
DQ18
A7
NC
DQ22
A8
VDDQ
DQ19
A5
NC
VDD
VDDQ
DQS6
DQ50
DQ51
VSS
DQ23
VSS
DM6
DQ54
DQ55
VDDQ
NC
DQ24
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ25
DQS3
A4
NC
DQ60
DQ61
VSS
DQ56
DQ57
VDD
VDD
DQ26
DQ27
A2
DQ30
VSS
DM7
DQ62
DQ63
VDDQ
SA0
DQS7
DQ58
DQ59
VSS
DQ31
NC
VSS
A1
NC
NC
NC
VDDQ
CK0
/CK0
SA1
NC
SDA
SCL
SA2
VDD
VDDSPD
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Page 4
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Data Sheet
Rev.1.0
18.09.2012
FUNCTIONAL BLOCK DIAGRAMM 1024MByte DDR SDRAM DIMM 2RANKS; NON-ECC
Swissbit AG
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Page 5
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Data Sheet
Rev.1.0
18.09.2012
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ + 70°C ; VDD = +2.5V ± 0.2V, VDDQ = +2.5V ± 0.2V) see Note 1 on Page 9
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
SYMBOL
VDD
MIN
2.3
2.3
MAX
2.7
2.7
UNITS
V
V
V
V
V
V
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
0.49 x VDDQ
VREF – 0.04
VREF + 0.15
-0.3
0.51x VDDQ
VREF + 0.04
VDD + 0.3
VREF – 0.15
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤1.35V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
II
-10
-10
10
10
µA
µA
IOZ
(DQS are disabled; 0V ≤ VOUT ≤ VDDQ
)
OUTPUT LEVELS:
High Current (VOUT = VDDQ-0.373V,minimum VREF,
minimum VTT
Low Current (VOUT =0.373V, maximum VREF,
maximum VTT
IOH
IOL
-16.8
16.8
-
-
mA
mA
)
)
AC INPUT OPERATING CONDITIONS
(0°C ≤ TA ≤ + 70°C ; VDD = +2.5V ± 0.2V, VDDQ = +2.5V ± 0.2V) see Note 1 on Page 9
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
I/O Reference Voltage
SYMBOL
VIH (AC)
MIN
VREF + 0.310
-
MAX
-
VREF - 0.310
0.51x VDDQ
UNITS
V
V
V
VIL (AC)
VREF(AC)
0.49 x VDDQ
CAPACITANCE
PARAMETER
SYMBOL
C10
MIN
4.0
18.0
18.0
10.0
18.0
MAX
5.0
27.0
27.0
14.0
27.0
UNITS
pF
Input/Output Capacitance: DQ, DQS
Input Capacitance: Command and Address
Input Capacitance: /S 0,1
Input Capacitance: CK, /CK
Input Capacitance: CKE
C11
C11
C12
C13
pF
pF
pF
pF
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Page 6
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Data Sheet
Rev.1.0
18.09.2012
IDD Specifications AND CONDITIONS
(0°C ≤ TA ≤ + 70°C ; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
Parameter
max.
& Test Condition
Symbol
3200-3.0-3-3
2700-2.5-3-3
Unit
OPERATING CURRENT *) : One device bank; Active-
Precharge;
IDD0
mA
1000
880
tRC= tRC (Min); tCK = tCK (Min); DQ, DM and DQS inputs
changing
once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT :*)
One device bank; Active-Read-Precharge;
Burst = 2; tRC= tRC (Min);
IDD1
mA
1440
1120
tCK = tCK (Min);IOUT = 0mA;
Address and control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: IDD2P
All device banks idle;
Power-down mode;
mA
mA
80
80
tCK = tCK (Min); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device
banks idle;
IDD2F
480
480
tCK = tCK (Min); CKE= HIGH; Address and other control
inputs changing once per clock cycle.
VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One
device bank active; Power-down mode; tCK = tCK
(Min);CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE =
HIGH; One device bank; Active-Precharge; tRC= tRAS
(Max); tCK = tCK (Min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT:
IDD3P
mA
mA
720
960
480
720
IDD3N
IDD4R
mA
mA
3000
1440
1160
1240
Burst = 2; Reads; Continous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK = tCK (Min);
IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous IDD4W
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (Min);
DQ, DM, and DQS inputs changing twice per clock
cycle
AUTO
REFRESH
CURRENT
tRC = tRC (Min)
tRC = 7.8125µs
IDD5
IDD6
IDD7
IDD8
mA
mA
3520
80
3280
80
SELF REFRESH CURRENT: CKE ≤ 0.2V
mA
mA
48
48
OPERATING CURRENT*): Four device bank interleaving
READs (BL =4) with auto precharge, tRC = tRC (Min);
tCK = tCK (Min); Address and control inputs change only during
Active READ, or WRITE commands
3080
2920
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
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Page 7
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Data Sheet
Rev.1.0
18.09.2012
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TA ≤ + 70°C ; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
AC CHARACTERISTICS
PARAMETER
Access window of DQS CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL=2.0
3200-3.0-3-3
2700-2.5-3-3
SYMBOL
tAC
MIN
-0.50
0.45
0.45
7.5
MAX
MIN
-0.70
0.45
0.45
7.5
MAX
+0.70
0.55
0.55
13.0
13.0
-
Unit
ns
tCK
+0.50
0.55
0.55
13.0
13.0
13.0
tCH
tCL
TCK (2.0)
TCK (2.5)
TCK (3.0)
tCK
6.0
5.0
6.0
-
ns
ns
CL=2.5
CL=3.0
DQ and DM input hold time relative
to DQS
DQ and DM input setup time relative
to DQS
DQ and DM input pulse width
( for each input )
Access window of DQS from
CK/CK#
0.40
0.40
1.75
-0.6
-
0.45
0.45
1.75
-0.6
-
ns
ns
ns
ns
tDH
tDS
tDIPW
-
-
-
-
+0.6
+0.6
tDQSCK
tDQSH
tDQSL
DQS input high pulse width
DQS input low pulse width
0.35
0.35
-
-
0.35
0.35
-
-
tCK
tCK
DQS –DQ skew, DQS to last DQ
valid, per group, per access
Write command to first DQS latching
transition
DQS falling edge to CK rising- setup
time
DQS falling edge from CK rising-
hold time
Half clock period
-
0.40
-
0.45
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDQSQ
tDQSS
tDSS
tDSH
tHP
0.72
0.2
0.2
1.28
0.75
0.2
0.2
1.25
-
-
-
-
tch,
tcl
tch,
tcl
-
-
Data-out high-impedance window
from CK/CK#
Data-out low-impedance window
from CK/CK#
Address and control input hold time
( fast slew rate )
Address and control input setup time
( fast slew rate )
Address and control input hold time
( slow slew rate )
Address and control input setup time
( slow slew rate )
LOAD MODE REGISTER command
cycle time
Adress and control input pulse width
(for each input)
+0.7
+0.7
tHZ
-0.7
0.6
0.6
0.7
0.6
10
-
-
-
-
-
-
-
-0.7
0.75
0.75
0.8
-
-
-
-
-
-
-
tLZ
tIHF
tISF
tIHS
0.8
tISS
12
tMRD
tIPW
2.2
2.2
DQ-DQS hold, DQS to first DQ to go
non-valid, per access
Data hold skew factor
tHP - tQHS
tHP - tQHS
ns
ns
tQH
-
0.5
-
0.6
tQHS
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Page 8
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Data Sheet
Rev.1.0
18.09.2012
AC CHARACTERISTICS
3200-3.0-3-3
2700-2.5-3-3
PARAMETER
ACTIVE to PRECHARGE command
SYMBOL
tRAS
MIN
40
MAX
70.000
MIN
42
MAX
70.000
Unit
ns
ACTIVE to READ with Auto
precharge
command
ACTIVE to ACTIVE/AUTO
REFRESH
ns
tRAP
15
55
-
-
15
60
-
ns
tRC
-
command period
AUTO REFRESH command period
ns
ns
ns
tCK
tCK
ns
70
15
15
0.9
0.4
-
-
-
72
15
15
0.9
0.4
-
-
-
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b
command
1.1
0.6
1.1
0.6
10
-
12
-
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command
delay
tCK
ns
tCK
ns
tCK
0.25
0
0.4
15
-
-
0.25
0
0.4
15
-
-
tWPRE
tWPRES
tWPST
tWR
0.6
-
0.6
-
tWTR
2
-
1
-
N/A
Data valid output window
REFRESH to REFRESH command
interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
tQH - tDQSQ
tQH - tDQSQ
ns
µs
tREFC
-
-
70.3
7.8
-
-
70.3
7.8
tREFI
µs
85 °C < TCASE ≤ 95°C
3.9
-
3.9
-
tREFI (IT)
tVTD
tXSNR
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ
command
Exit SELF REFRESH to READ
command
ns
ns
0
0
70
-
-
75
-
-
tCK
tXSRD
200
200
Note 1: Values for AC timing, IDD, and electrical AC and DC characteristics might have been collected within the
standard temperature range and at nominal reference/supply voltage levels, but the related specifications and
device operation are guaranteed for the full voltage range specified and for the corresponding field of operation
according to the actual temperature grade of the module (extended E, I or W; refer to the environmental conditions
for more details).
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Page 9
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Data Sheet
Rev.1.0
18.09.2012
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
NUMBER OF SPD BYTES USED
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
NUMBER OF ROW ADDRESSES ON ASSEMBLY
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
NUMBER OF PHYSICAL BANKS ON DIMM
MODULE DATA WIDTH
3200-3.0-3-3
2700-2.5-3-3
0
1
2
3
4
5
6
7
8
9
0x80
0x08
0x07
0x0D
0x0B
0x02
0x40
0x00
0x04
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS (VDDQ
SDRAM CYCLE TIME, (tCK
(CAS LATENCY =2.5 (2700, 2100) ; CL=3* (3200)
SDRAM ACCESS FROM CLOCK, (tAC
)
)
0x50
0x65
0x60
0x70
10
)
(CAS LATENCY =2.5 (2700, 2100); CL=3* (3200))
MODULE CONFIGURATION TYPE
REFRESH RATE/ TYPE
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK- TO- BACK
RANDOM COLUMN ACCESS
11
12
13
14
15
0x00
0x82
0x08
0x00
0x01
16
17
18
19
20
21
22
23
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
CS LATENCY
WE LATENCY
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES: GENERAL
0x0E
0x04
0x18
0x60
0x0C
0x75
0x01
0x02
0x20
0xC0
SDRAM CYCLE TIME, (tCK
(CAS LATENCY=2(2700, 2100) CL=2,5*(3200))
SDRAM ACCESS FROM CK, (tAC
(CAS LATENCY=2(2700, 2100) CL=2.5*(3200)
SDRAM CYCLE TIME, (tCK
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200))
SDRAM ACCESS FROM CK, (tAC
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200)
MINIMUM ROW PRECHARGE TIME, (tRP
MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD
MINIMUM RAS# TO CAS# DELAY, (tRCD
)
24
25
26
)
0x70
0x00
0x00
)
)
27
28
29
30
31
32
33
34
35
)
0x3C
0x28
0x3C
0x28
0x48
0x30
0x48
0x2A
)
)
MINIMUM RAS# PULSE WIDTH, (tRAS
)
MODULE BANK DENSITY
ADDRESS AND COMMAND SETUP TIME, (tIS)
ADDRESS AND COOMAND HOLD TIME, (tIH)
DATA/DATA MASK INPUT SETUP TIME, (tDS
DATA/DATA MASK INPUT HOLD TIME, (tDH
0x80
0x00
0x60
0x60
0x40
0x40
0x80
0x80
0x45
0x45
)
)
36-40 RESERVED
41
42
MIN ACTIVE AUTO REFRESH TIME (tRC
MINIMUM AUTO REFRESH TO ACTIVE/
AUTO REFRESH COMMAND PERIOD, (tRFC)
SDRAM DEVICE MAX CYCLE TIME (tCKMAX
SDRAM DEVICE MAX DQS-DQ SKEW TIME
(tDQSQ
SDRAM DEVICE MAX READ DATA HOLD SKEW
FACTOR (tQHS
)
0x37
0x46
0x28
0x28
0x3C
0x48
0x30
0x2D
43
44
)
)
45
0x50
0x55
)
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 10
of 13
Data Sheet
Rev.1.0
18.09.2012
SERIAL PRESENCE-DETECT MATRIX (continued)
BYTE
DESCRIPTION
3200-3.0-3-3
2700-2.5-3-3
46-61 RESERVED
0x00
0x11
62
63
64
65
66
67
SPD REVISION
CHECKSUM FOR BYTES 0-62
MANUFACTURER`S JEDEC ID CODE
MANUFACTURER`S JEDEC ID CODE
MANUFACTURER`S JEDEC ID CODE
MANUFACTURER`S JEDEC ID CODE
(continued)
0xC0
0x69
7F
7F
7F
DA
0x01
0x02
0x03
Switzerland
Germany
USA
72
MANUFACTURING LOCATION
73-90 MODULE PART NUMBER (ASCII)
“SDU01G64H3BJ2SA-xx”
91
92
93
94
PCB IDENTIFICATION CODE
x
x
x
x
IDENTIFICATION CODE (continued)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
95-98 MODULE SERIAL NUMBER
x
x
Part Number Code
S
1
D
2
U
3
01G 64 H3
B
7
J
8
2
9
SA
10
-
50
11
*
12
R
13
4
5
6
* RoHs compl.
Swissbit AG
SDRAM DDR
184 Pin Unbuffered 2.5V
module capacity (1GByte)
module data width
PCB-Type (BDSA83A)
DDR-400MHz
Chip Vendor (Samsung)
2 Module Ranks
Chip Rev. J
Chip organisation x8
* optional / additional information
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 11
of 13
Data Sheet
Rev.1.0
18.09.2012
Revision History
Revision
1.0
Changes
Date
18.09.2012
Initial Revision
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 12
of 13
Data Sheet
Rev.1.0
18.09.2012
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
Fax:
+41 (0)71 913 03 03
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
Fax:
+49 (0)30 93 69 54 – 0
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
1202 E. Winding Creek Drive
Eagle, ID 83616
USA
Phone:
Fax:
+1 208 870 4525
+1 208 870 4525
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
Fax:
+81 3 5356 3511
+81 3 5356 3512
________________________________
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 13
of 13
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