SED1561 [ETC]
Low-power operation: 8 umA 1 kHz, 6V LCD; 低功耗运行： 8 UMA 1千赫， 6V液晶
| 型号： | SED1561 |
| 厂家： | 
ETC |
| 描述： | Low-power operation: 8 umA 1 kHz, 6V LCD |
| 文件： | 总84页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1560/1/2
Technical Manual
(Preliminary)
S-MOS Systems, Inc.
October, 1996
Version 3.0 (Preliminary)
THIS PAGE INTENTIONALLY BLANK
2
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
Table of Contents
SED1560 Series
TABLE OF CONTENTS
1.0 Overview ................................................................................................................................................... 5
1.1 Description .................................................................................................................................... 7
1.2 Features ........................................................................................................................................ 7
1.3 System Block Diagrams ................................................................................................................ 7
1.4 Block Diagram ............................................................................................................................... 9
2.0 Pin Description....................................................................................................................................... 11
2.1 Power Supply .............................................................................................................................. 13
2.2 LCD Driver Power Supplies......................................................................................................... 13
2.3 Microprocessor Interface ............................................................................................................. 14
2.4 Oscillator and Display Timing Control ......................................................................................... 15
2.5 LCD Driver Outputs ..................................................................................................................... 16
3.0 Electrical Characteristics ...................................................................................................................... 17
3.1 Absolute Maximum Ratings......................................................................................................... 19
3.2 DC Characteristics ...................................................................................................................... 20
3.3 AC Characteristics........................................................................................................................ 24
3.3.1 Reset ............................................................................................................................ 24
3.4 Display Control Timing ................................................................................................................ 25
3.5 System Buses: Read/Write Characteristics I (80-Series MPU)................................................... 27
3.6 System Buses: Read/Write Characteristics II (68-Series MPU).................................................. 28
3.7 Serial Interface ............................................................................................................................ 30
4.0 Functional Description .......................................................................................................................... 33
4.1 Microprocessor Interface ............................................................................................................. 35
4.1.1 Parallel/Serial Interface ................................................................................................ 35
4.1.2 Parallel Interface........................................................................................................... 35
4.1.3 Serial Interface ............................................................................................................. 35
4.1.4 Chip Select Inputs ........................................................................................................ 36
4.2 Data Transfer .............................................................................................................................. 36
4.3 Status Flag .................................................................................................................................. 38
4.4 Display Data RAM ....................................................................................................................... 38
4.5 Column Address Counter ............................................................................................................ 38
4.6 Page Address Register ............................................................................................................... 38
4.7 Initial Display Line Register ......................................................................................................... 40
4.8 Output Selection Circuit............................................................................................................... 40
4.9 SED1560 Output Status .............................................................................................................. 42
4.10 SED1561 Output Status ............................................................................................................ 42
4.11 SED1562 Output Status ............................................................................................................ 43
4.12 Display Timers........................................................................................................................... 43
4.12.1 Line Counter and Display Data Latch Timing ............................................................. 43
4.12.2 FR and SYNC ............................................................................................................. 43
4.12.3 Common Timing Signals ............................................................................................ 43
4.13 Two-frame AC Driver Waveform (SED1561, 1/32 duty)............................................................ 44
4.14 n Line Inverse Driver Waveform (n-5, line inverse register 4) .................................................. 45
4.15 Display Data Latch .................................................................................................................... 46
174-3.0
3
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
SED1560 Series
Table of Contents
4.16 LCD Driver................................................................................................................................. 46
4.17 Display Data Latch Circuit ......................................................................................................... 46
4.18 LCD Driver Circuit ..................................................................................................................... 46
4.19 Oscillator Circuit ........................................................................................................................ 46
4.20 FR Control Circuit ......................................................................................................................46
4.21 Power Supply Circuit ................................................................................................................. 48
4.22 Tripler Boosting Circuit .............................................................................................................. 48
4.23 Voltage Regulation Circuit (Software Contrast Adjustment Function is Not Used) ................... 49
4.24 Voltage Regulation Circuit Using Software Contrast Adjustment Control Function .................. 50
4.25 Precautions on Using the SED1560 Series Software Contrast Adjustment Control Function .. 51
4.26 Liquid Crystal Voltage Generating Circuit ................................................................................. 54
4.27 Reset ......................................................................................................................................... 56
5.0 Commands.............................................................................................................................................. 57
5.1 Command Summary .................................................................................................................. 59
5.2 Command Definitions ................................................................................................................. 60
5.3 Software Contrast Control Register............................................................................................. 67
5.4 Microprocessor Interface ............................................................................................................. 69
5.5 LCD Panel Interface Examples ................................................................................................... 70
5.6 Special Common Driver Configurations ...................................................................................... 72
6.0 Packaging ............................................................................................................................................... 73
6.1 Pad Layout .................................................................................................................................. 75
6.2 SED1560/1/2 TAB Pin Layout ..................................................................................................... 77
6.3 TCP Dimensions (2-sided) .......................................................................................................... 78
6.4 TCP Dimensions (4-sided) .......................................................................................................... 79
6.5 TCP Dimensions (D1561TOC) .................................................................................................... 80
6.6 Pad Profile................................................................................................................................... 81
6.7 BGA Package Dimensions .......................................................................................................... 82
6.8 BGA Pin Assignment ................................................................................................................... 83
6.9 SED1560TQA OL Dimensions .................................................................................................... 84
4
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
1.0
Overview
174-3.0
5
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
6
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
1.0 Overview
1.0 – 1.3
1.1 DESCRIPTION
1.2 FEATURES
TheSED1560SeriesareintelligentCMOSLCDdriver-
controllers with the ability to drive alphanumeric and
graphic displays. The SED1560 Series communicates
with a high-speed microprocessor, such as the Intel
80XX family or the Motorola 68XX family, through
either a serial or an 8-bit parallel interface. It stores the
datasentfromthemicroprocessorinthebuilt-indisplay
data RAM (166 × 65 bits) and generates an LCD drive
signal. These devices incorporate an internal DC/DC
converter to generate the negative voltage needed for
LCDcontrast.Thecontrollersfeaturesoftwarecontrast
adjustment by command setting.
• Low-power operation: 8 µA @ 1 kHz, 6V LCD
• 350µAcurrentconsumptionduringCPUaccess
@ 200 kHz
• Direct interface to both 80XX and 68XX, 5 MHz,
zero wait-state
• On-chip display data RAM (166 × 65 bits)
• On-chip DC/DC converter for LCD voltage
• On-chip voltage regulator and low-power volt-
age follower
• –.17% / °C temperature gradient
• On-chip oscillator with external resistor
• 32 levels of contrast adjustment by software
• Supports master/slave operation
• Selectable output configuration
• 2.4V to 6.0V supply voltage
The three different versions of the SED1560 Series
support the following duty ratios and display sizes:
Model
SED1560
SED1561
SED1562
Duty Ratio
1/65, 1/64, 1/49, 1/48
1/33, 1/32, 1/25, 1/24
1/17, 1/16
SEG × COM
102 × 65
• 3.5V to 16V LCD voltage
134 × 33
• Package: TAB 2 side
TAB 4 side
T0B
TQA
D*A
D*B
B0A
150 × 17
Al pad
Au bump
BGA 225 pad
1.3 SYSTEM BLOCK DIAGRAMS
20 CHAR × 8 LINES
RES
SED1560
CS
CPU
D0 ~ D7
80xx
68xx
174-3.0
7
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
1.3
1.0 Overview
1.3 SYSTEM BLOCK DIAGRAMS (cont.)
COM0~COM32
26 CHAR × 4 LINES
SEG0~SEG133
RES
SED1561
CS
CPU
D0 ~ D7
80xx
68xx
30 CHAR × 2 LINES
RES
SED1562
CS
CPU
D0 ~ D7
80xx
68xx
8
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
1.0 Overview
1.4
1.4 BLOCK DIAGRAM
O00 to O31 O32
to O101 O102 to O165 COM1
VSS
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
Common
and
segment
drivers
Common
Segment
driver
and
segment
drivers
Commons
only
Frame
control
Shift
Shift
register
register
CAP1+
LCD
CAP1–
CAP2+
CAP2–
VR
supply
voltage
generator
166-bit display data latch
Line
address
decoder
I/O
buffer
166 x 65-bit display
data RAM
Line
counter
Output
status
select
T1, T2
Display
initial line
register
166-bit column address decoder
8-bit column address counter
8-bit column address register
FR
SYNC
CL
Page
address
register
Display
timing
CLO
DYO
M/S
generator
OSC1
OSC2
Command
decoder
Bus holder
Status flag
Oscillator
MPU interface
I/O buffer
CS1 CS2 A0 RD WR C86 SI SCL P/S RES
D7 D6 D5 D4 D3 D2 D1 D0
174-3.0
9
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
10
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
2.0
Pin Description
174-3.0
11
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
12
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
2.0 Pin Description
2.1 – 2.2
2.1 POWER SUPPLY
Number of Pins
I/O
Name
VDD
Description
Common to MPU power supply pin VCC
Ground
2
2
Supply
Supply
VSS
11
V1 to V5 LCD driver supply voltages. The voltage determined by the LCD
cell is impedance-converted by a resistive divider or an operational
amplifier for application. Voltage levels are based on VDD. The
voltages must satisfy the following relationship:
Supply
LCD
voltage
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master mode select: bias voltages are generated on-chip.
SED1560
1/9 V5
2/9 V5
7/9 V5
8/9 V5
SED1561
1/7 V5
2/7 V5
5/7 V5
6/7 V5
SED1562
1/5 V5
2/5 V5
3/5 V5
4/5 V5
V1
V2
V3
V4
2.2 LCD DRIVER POWER SUPPLIES
Number of Pins
I/O
O
O
O
O
O
I
Name
Description
1
1
1
1
1
1
CAP1+ DC/DC voltage converter capacitor 1 positive connection
CAP1– DC/DC voltage converter capacitor 1 negative connection
CAP2+ DC/DC voltage converter capacitor 2 positive connection
CAP2– DC/DC voltage converter capacitor 2 negative connection
VOUT
VR
DC/DC voltage converter output
Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
2
I
T1, T2 Liquid crystal power control terminals
Voltage
Regulation
Circuit
Boosting
Circuit
T1
T2
V/F Circuit
L
L
L
H
L
Valid
Valid
Valid
Valid
Valid
Valid*
Valid
Valid
H
H
Invalid
Invalid
Valid
H
Invalid
* V/F circuit current capacity enhancement
174-3.0
13
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
2.3
2.0 Pin Description
2.3 MICROPROCESSOR INTERFACE
Number of Pins
I/O
I/O
I
Name
Description
8
1
D0 to D7 Data is transferred between the controller and MPU via these pins
A0
Control/display data flag input. This is connected to the LSB of the
microprocessor address bus.
• When LOW, the data on D0 to D7 is command data
• When HIGH, the data on D0 to D7 is display data
Reset input. Setting this pin low initializes the SED156X.
1
2
I
I
RES
CS1,
CS2
Chip select inputs. Data input/output is enabled when CS1 is LOW
and CS2 is HIGH.
1
1
1
I
I
I
RD
WR
C86
Read enable input. See note 1.
Write enable input. See note 2.
Microprocessor interface select input.
• LOW when interfacing to 8080-series
• HIGH when interfacing to 6800-series
Serial data input
1
1
I
I
SI
SCL
Serial clock input. Data is read on the rising edge of SCL and
converted to 8-bit parallel data.
1
I
P/S
Parallel/serial data input select
Data/
com-
mand
Operating
Mode
Chip
Select
Data
I/O
Read/
write
Serial
Clock
P/S
D0 to
D7
HIGH
LOW
Parallel
Serial
CS1, CS2
CS1, CS2
A0
A0
RD, WR
—
SI
Write only
SCL
In serial mode, data cannot be read from the RAM, and D0 to D7, HZ,
RD and WR must be HIGH or LOW. In parallel mode, SI and SCL
must be HIGH or LOW.
Notes:
1. Wheninterfacingto8080-seriesmicroprocessors, RDisactive-LOW. Wheninterfacingto6800-seriesmicroprocessors, theyare
active-HIGH.
2. When interfacing to 8080-series microprocessors, WR is active-LOW. When interfacing to 6800-series microprocessors, read
mode is selected when WR is HIGH, and write mode is selected when WR is LOW.
14
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
2.0 Pin Description
2.4
2.4 OSCILLATOR AND DISPLAY TIMING CONTROL
Number of Pins
I/O
Name
Description
2
I
OSC1 Using internal oscillator when M/S = “H”, connect resistor Rf to the
OSC1 and OSC2 pins. The OSC2 pin is used for output of the
oscillator amplifier.
2
1
I/O
I
OSC2 When M/S = “L”: the OSC2 pin is used for input of oscillation signal.
TheOSC1pinshouldbeleftopen.FixtheCL pintotheVSS levelwhen
using the internal oscillator circuit as the display clock.
CL
Display clock input. The line counter increments on the rising edge of
CL, and the display pattern is output on the falling edge. When using
theexternaldisplayclock, OSC1=“H”, OSC2=“L”, andresetthisLSI
by RES pin.
1
1
O
I
CLO
M/S
Display clock output. When using the internal oscillator, the clock
signal is output on this pin. Connect CLO to YSCL on the common
driver.
Master/slave select input. Master produces signals for display, and
slave receives them. This is for display synchronization.
Operating Internal Power
Device
M/S
FR SYNC OSC1 OSC2 DYO
Mode
Oscillator Supply
LOW
HIGH
Slave
OFF
ON
OFF
ON
I
I
Open
I
I
O
O
156X
Master
O
O
O
Note:
I = input mode
O = output mode
1
1
1
I/O
I/O
O
FR
LCD AC drive signal input/output. Output is selected when M/S is
HIGH, and input is selected when M/S is LOW.
SYNC Display sync input/output. Output is selected when M/S is HIGH, and
input is selected when M/S is LOW.
DYO
Start-up output for common driver. Connect to DIO of the common
driver, such as the SED1630.
* SED1630 has a DIO input.
174-3.0
15
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
2.5
2.0 Pin Description
2.5 LCD DRIVER OUTPUTS
Number of Pins
I/O
Name
Description
166
O
O0 to
O165
LCD driver outputs. O0 to O31 and O102 to O165 are selectable
segment or common outputs, determined by a selection command.
O32 to O101 are segment outputs only.
For segment outputs, the ON voltage level is given as shown in the
following table:
LCD ON Voltage
RAM Data
LOW
FR
Normal Display
Inverse Display
LOW
HIGH
LOW
HIGH
V3
V2
V5
VDD
V3
V5
HIGH
VDD
V2
For common outputs, the ON voltage is given as shown in the follow-
ing table:
Scan Data
FR
LCD ON Voltage
LOW
HIGH
LOW
HIGH
V4
V1
LOW
VDD
V5
HIGH
1
O
COM1 LCD driver common output. Common outputs when the “DUTY + 1”
command is executed are as follows:
Device
SED1560
SED1561
SED1562
“DUTY + 1” ON
COM64, COM48
COM32, COM24
COM16
“DUTY + 1” OFF
V1 or V4
V1 or V4
V1 or V4
Common output special for the indicator.
16
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0
Electrical Characteristics
174-3.0
17
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
18
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0 Electrical Characteristics
3.1
3.1 ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
–7.0 to 0.03
Supply voltage range
VSS
V
–6.0 to 0.3
(when triple voltage conversion)
Driver supply voltage range (1)
Driver supply voltage range (2)
Input voltage range
V5
–18.0 to 0.3
V5 to 0.3
V
V
V1, V2, V3, V4
VIN
V0
VSS–0.3 to 0.3
VSS–0.3 to 0.3
–30 to 85
V
Output voltage range
V
Operating temperature range
Storage temperature range (TCP)
Notes:
Topr
Tstr
°C
°C
–55 to 125
1. The voltages shown are based on VDD = 0V.
2. Always keep the condition VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 for voltages V1, V2, V3 and V4.
3. If devices are used over the absolute maximum rating, the LSIs may be destroyed permanently. It is desirable to use them under
theelectricalcharacteristicconditionsforgeneraloperation. Otherwise, amalfunctionoftheLSImaybecausedandLSIreliability
may be affected.
4. For operating temperatures below –30°C, please consult an S-MOS engineer.
174-3.0
19
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.2
3.0 Electrical Characteristics
3.2 DC CHARACTERISTICS
VDD = 0V, VSS = –5 ± 10%, Ta = –30 to +85°C unless otherwise noted.
Applicable
Parameter
Recommended
Symbol
Condition
Min
Typ
Max
Unit
Pin
–5.5
–5.0
–4.5
VSS
Power
operation
VSS
V
voltage (1)
Operational
Operational
Operational
Operational
–6.0
–16.0
—
—
–2.4
–3.5
VSS *1
V5 *2
V1, V2
V3, V4
*3
V5
V
V
V
V
V
V
V
V
V
V
V
Operating
voltage (2)
V1, V2
V3, V4
VIHC1
VIHC2
VIHC1
VIHC2
VILC1
VILC2
VILC1
VILC2
VOHC1
VOHC2
0.4 × V5
V5
—
VDD
—
0.6 × V5
VDD
0.3 × VSS
0.15 × VSS
0.2 × VSS
0.15 × VSS
VSS
—
—
VDD
*4
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
VSS = –2.7V
—
VDD
*3
VSS = –2.7V
—
VDD
*4
—
0.7 × VSS
0.85 × VSS
0.8 × VSS
0.85 × VSS
VDD
*3
VSS
—
*4
VSS = –2.7V
VSS = –2.7V
VSS
—
*3
VSS
—
*4
IOH = –1 mA
0.2 × VSS
—
*5
OSC2
V
V
V
V
IOH = –120 µA 0.2 × VSS
—
VDD
VOHC1 VSS = –2.7V IOH = –0.5 mA 0.2 × VSS
—
VDD
*5
OSC2
VOHC2 VSS = –2.7V IOH = –50 µA
0.2 × VSS
VSS
VSS
VSS
VSS
–1.0
–3.0
—
—
VDD
VOLC1
VOLC2
IOL = 1 mA
—
0.8 × VSS
0.8 × VSS
0.8 × VSS
0.8 × VSS
1.0
*5
OSC2
IOL = 120 µA
—
VOLC1 VSS = –2.7V IOL = 0.5 mA
—
*5
OSC2
VOLC2 VSS = –2.7V IOL = 50 µA
—
Input leakage current
Output leakage current
ILI
VIN = VDD or VSS
—
µA
µA
*6
*7
ILO
—
3.0
V5 = –14.0V
V5 = –8.0V
2.0
3.0
0.00
0.01
5.0
18
16
3.0
O0 ~ O166
*8
LCD driver ON resistance
RON
Ta = 25°C
kΩ
—
4.5
ISSQ
I5Q
—
5.0
µA
µA
pF
VSS
V5
Static power consumption
Input terminal capacity
Oscillator frequency
V5 = –18.0V
—
15.0
CIN
Ta = 25°C
f = 1 MHz
—
8.0
*3 *4
VSS = –5V
VSS = –2.7V
15
22
Rf = 1 MΩ
±2%
fOSC
kHz
*9
11
21
Reset time
tR
1.0
10
—
—
—
—
µs
µs
*10
*11
Reset “L” pulse width
(continued)
tRW
20
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0 Electrical Characteristics
3.2
(continued)
VDD = 0V, VSS = –5 ± 10%, Ta = –30 to +85°C unless otherwise noted.
Applicable
Parameter
Input voltage
Symbol
Condition
Min
Typ
Max
Unit
Pin
VSS
–6.0
—
—
–2.4
—
V
V
*12
Amplified output voltage
VOUT
If amplified 3 times
–18.0
VOUT
Voltage regulator
circuit operation voltage
VOUT
–18.0
—
–6.0
V
VOUT
V5 1 Supplied to SED1560
V5 2 Supplied to SED1561
V5 3 Supplied to SED1562
–16.0
–16.0
–16.0
–2.35
—
—
–6.0
–5.0
V
V
V
V
Voltage follower
operation voltage
*13
—
–4.5
Reference voltage
VREG
Ta = 25°C
–2.5
–2.65
Notes:
* See Notes on page 22.
When dynamic current consumption (I) is displayed; the built-in power supply is on and T1 = T2 = Low.
Test conditions, unless otherwise specified: VDD = 0V, VSS = –5V ±10%, Ta = –30 to 85°C
Parameter
SED1560
Symbol
Condition
Min
Typ
169
124
53
Max
340
250
110
130
Unit Remarks
V5 = –12.5V; 3 times amplified
V5 = –8.0V; 3 times amplified
V5 = –6.0V; 2 times amplified
VSS = –2.7V; 3 times amplified
V5 = –6.0V
µA
µA
SED1561
SED1562
IDD (1)
*16
µA
66
µA
Typical current consumption characteristics
Dynamic current consumption (I), if an external clock and an external power supply are used.
•
Conditions: The built-in power supply is off but
the external one is used.
(µA) 40
SED1560
SED1560 .........V5 = –12.5V
SED1561 .........V5 = –8.0V
SED1562 .........V5 = –6.0V
30
IDD (1)
(ISS +I5)
20
SED1561
SED1562
External clock:
10
0
SED1560 .........fCL = 4 kHz
SED1561 .........fCL = 2 kHz
SED1562 .........fCL = 1 kHz
–1
–2
–3
–4
–5
–6
–7
Remarks:
*14
VSS
(V)
174-3.0
21
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.2
3.0 Electrical Characteristics
Dynamic current consumption (I), if the built-in oscillator and the external power supply are used.
•
Conditions: The built-in power supply is off but the
external one is used.
80
60
40
20
0
(µA)
SED1560 .........V5 = –12.5V
SED1561 .........V5 = –8.0V
SED1562 .........V5 = –6.0V
SED1560
SED1561
IDD (1)
(ISS +I5)
Internal oscillation:
SED1562
SED1560 .........Rf = 1 MΩ
SED1561 .........Rf = 1 MΩ
SED1562 .........Rf = 1 MΩ
Remarks:
*15
–1
–2
–3
–4
–5
–6
–7
VSS
(V)
Dynamic current consumption (I), if the built-in power supply is used.
•
Conditions: The built-in power supply is on and
T1 = T2 = Low.
200
(µA)
SED1560 .........V5 = –12.5V;
3 times amplified
SED1560
SED1561
150
IDD (1)
SED1561 .........V5 = –8.0V;
3 times amplified
100
50
0
SED1562 .........V5 = –6.0V;
2 times amplified
SED1562
Internal oscillation:
SED1560 .........Rf = 1 MΩ
SED1561 .........Rf = 1 MΩ
SED1562 .........Rf = 1 MΩ
–1
–2
–3
–4
–5
–6
–7
VSS
(V)
Remarks:
*16
Notes:
the SED156* is usually operable after “tr” time.
*1. A wide range of operating voltage is possible, but considerable
voltage variation during MPU access is not guaranteed.
*11. Specifies the minimum pulse width of RES signal. The Low pulse
greater than “tRW” must be entered for reset.
*2. TheoperatingvoltagerangeoftheVSS andV5systems(seeFigure
3.3). The operating voltage range is applied if an external power
supply is used.
*12. If the voltage is amplified three times by the built-in power circuit,
theprimarypowerVSS mustbeusedwithintheinputvoltagerange.
*3. Pins A0, D0 to D7, RD (E),WR (R/W), CS1, CS2, FR, SYNC, M/S,
C86, SI, P/S, T1 AND T2.
*13. The V5 voltage can be adjusted within the voltage follower operat-
ing range by the voltage regulator circuit.
*4. Pins CL, SCL, and RES.
*14, 15, 16. Indicates the current consumed by the separate IC. The
current consumption due to the LCD panel capacity and wiring
capacity is not included.
*5. Pins D0 to D7, FR, SYNC, CL0, and DY0
*6. Pins A0, RD (E), WR (R/W), CS1, CS2, CL, M/S, RES, C86, SI,
SCL, P/S, T1, and T2.
The current consumption is shown if the checker is used, the
displayisturnedon, theoutputstatusofCase6isselected, andthe
SED1560 is set to 1/64 duty, the SED1561 is set to 1/32 duty, and
the SED1562 is set to 1/64 duty.
*7. Applied if pins D0 to D7, FR, and SYNC are high impedance.
*8. The resistance when the 0.1 -volt voltage is applied between the
“On” output terminal and each power terminal (V1, V2, V3 or V4).
It must be within the operating voltage (2).
*14. AppliedifanexternalclockisusedandifnotaccessedbytheMPU.
*15. Applied if the built-in oscillation circuit is used and if not accessed
by the MPU.
*9. The relationship between the oscillation frequency, frame and Rf
value (see Figure 3.2).
*16. Applied if the built-in oscillation circuit and the built-in power circuit
are used (T1 = T2 = Low) and if not accessed by the MPU.
*10. “tr”(resettime)indicatestheperiodbetweenthetimewhentheRES
signalrisesandwhentheinternalcircuithasbeenreset. Therefore,
22
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0 Electrical Characteristics
3.2
The relationship between oscillator frequency fOSC
and LCD frame frequency fF is obtained from the
following expression:
Ta = 25°C
VSS = –5V
40
30
20
10
Table 3.1
[KHz]
Device
Duty
1/64
1/48
1/32
1/24
1/16
fF
fOSC
fOSC/256
fOSC/192
fOSC/256
fOSC/192
fOSC/256
SED1560
0
0.5
1.0
Rf [M ]
1.5
2.0
2.5
SED1561
SED1562
Figure 3.1
Oscillator frequency vs. frame vs. Rf
[SED1560 Series]
(fF indicates not fF signal cycle but cycle of LCD AC.)
200
duty 1/64 SED1560
duty 1/48
[Hz]
duty 1/32 SED1561
duty 1/24
100
f
F
duty 1/16 SED1562
0
2
4
6
8
fCL [KHz]
Figure 3.2 External clock (fCL) vs. frame frequency [SED1560 Series]
174-3.0
23
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.2 – 3.3.1
3.0 Electrical Characteristics
10
–20
5.0V
1
–16
–15
2.7V
–13
[mA]
DD (2)
[V]
–10
V5
0.1
I
–5
0
0.01
0
–2
–2.4 –3.0
–4
–6
–8
0.01
0.1
1
10
V
SS [V]
fcyc [MHz]
Figure 3.3
Figure 3.4
Operating voltage range for VSS and V5
Power consumption during CPU access cycle
(IDD [2])
3.3 AC CHARACTERISTICS
3.3.1 Reset
Table 3.5 Reset
Rating
Parameter
Symbol
Condition
Unit
µs
Min
Typ
Max
tR is measured from the rising edge
of RES. The SED156X resumes
normal operating mode after a reset.
Reset time
tR
1.0
—
—
Reset LOW-level
pulsewidth
t
1.0
—
—
µs
RW
24
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0 Electrical Characteristics
3.4
3.4 DISPLAY CONTROL TIMING
CL
tf
tWLCL
tWHCL
tr
tDFR
tDSNC
tDOL
FR
SYNC
tDOH
DYO
tCDH
tCDL
CLO
Figure 3.5 Display control timing
Display Control Input Timing
Parameter
VSS = –5.5 to –4.5V, Ta = –30 to 85°C
Rating
Unit
Symbol
Condition
Min
35
Typ
—
Max
—
CL LOW-level pulsewidth
CL HIGH-level pulsewidth
CL rise time
tWLCL
tWHCL
tr
µs
µs
ns
ns
µs
µs
35
—
—
—
30
30
—
—
CL fall time
tf
—
—
FR delay time
tDFR
tDSNC
–1.0
–1.0
1.0
1.0
SYNC delay time
—
VSS = –4.5 to –2.7V, Ta = –30 to 85°C
Rating
Unit
Parameter
Symbol
Condition
Min
35
Typ
—
Max
—
CL LOW-level pulsewidth
CL HIGH-level pulsewidth
CL rise time
tWLCL
tWHCL
tr
µs
µs
ns
ns
µs
µs
35
—
—
—
40
40
—
—
CL fall time
tf
—
—
FR delay time
tDFR
tDSNC
–1.0
–1.0
1.0
1.0
SYNC delay time
—
1. Effective only when the SED156X is in the master mode.
The FR/SYNC delay time output timing is provided in the
master operation.
2. The FR/SYNC delay time input timing is provided in the
slave operation.
3. Each timing is based on 20% and 80% of VSS.
174-3.0
25
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.4
3.0 Electrical Characteristics
Display Control Output Timing
Parameter
VSS = –5.5 to –4.5V, Ta = –30 to 85°C
Rating
Symbol
Condition
Unit
Min
—
Typ
60
Max
150
150
160
160
FR delay time
tDFR
tDSNC
tDOL
CL = 50 pF
ns
ns
ns
ns
SYNC delay time
CL = 100 pF
—
60
DYO LOW-level delay time
DYO HIGH-level delay time
—
70
tDOH
—
70
CLO to DYO LOW-level
delay time
SED156X operating in
master mode only
tCDL
—
—
40
40
100
100
ns
ns
CLO to DYO HIGH-level
delay time
SED156X operating in
master mode only
t
CDH
VSS = –4.5 to –2.7V, Ta = –30 to 85°C
Rating
Unit
Parameter
Symbol
Condition
Min
—
Typ
120
120
140
140
Max
240
240
250
250
FR delay time
tDFR
tDSNC
tDOL
CL = 50 pF
ns
ns
ns
ns
SYNC delay time
CL = 100 pF
—
DYO LOW-level delay time
DYO HIGH-level delay time
—
tDOH
—
CLO to DYO LOW-level
delay time
SED156X operating in
master mode only
t
—
—
100
100
200
200
ns
ns
CDL
CLO to DYO HIGH-level
delay time
SED156X operating in
master mode only
t
CDH
26
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0 Electrical Characteristics
3.5
3.5 SYSTEM BUSES: READ/WRITE CHARACTERISTICS I (80-SERIES MPU)
tAH8
A0
tAW8
tCYC8
tr
tCCLR
tCCLW
tCCHR
tCCHW
WR, RD, (CS)
tf
tDS8
tDH8
D0 to D7
(Write)
tACC8
tCH8
D0 to D7
(Read)
VSS = –5.0 ± 10%, Ta = –30 to 85°C
Parameter
Address hold time
Address setup time
System cycle time
Signal
Symbol
tAH8
Condition
Min
10
Max
—
—
—
—
—
—
—
—
—
70
50
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A0, CS
tAW8
10
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
200
22
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
WR
RD
WR
RD
77
172
117
20
Data hold time
tDH8
10
RD access time
D0 ~ D7
tACC8
tCH8
CL = 100pF
—
Output disable time
10
Input signal change time
tr, tf
—
174-3.0
27
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.5 – 3.6
3.0 Electrical Characteristics
VSS = –2.7 to –4.5V, Ta = –30 to 85°C
Parameter
Signal
Symbol
tAH8
Condition
Min
25
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
A0, CS
Address setup time
System cycle time
tAW8
25
—
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
450
44
—
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
WR
RD
WR
RD
—
194
394
244
40
—
—
—
—
Data hold time
tDH8
20
—
RD access time
D0 ~ D7
tACC8
tCH8
CL = 100pF
—
140
100
15
Output disable time
Input signal change time
10
tr, tf
—
Notes: 1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC8 – tCCLW – tCCHW) or tr + tf ≤ (tCYC8 –
tCCLR – tCCHR)
2. All signal timings are limited based on 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the RD or WR signal is in the low level.
Ifread/writeoperationisperformedbytheRDorWRsignalwhileCSisactive, itisdeterminedbytheRDorWRsignaltiming.
If read/write operation is performed by CS while the RD or WR signal is in the low level, it is determined by the CS active
timing.
3.6 SYSTEM BUSES: READ/WRITE CHARACTERISTICS II (68-SERIES MPU)
tCYC6
tEWLR
tEWLW
E
tEWHR
tEWHW
tr
tAW6
tAH6
tf
A0, RW
tAH6
tDH6
tDS6
D0 ~ D7
(WRITE)
tACC6
tOH6
D0 ~ D7
(READ)
28
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0 Electrical Characteristics
3.6
VSS = –5.0 ± 10%, Ta = –30 to 85°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Signal
Symbol
tCYC6
tAW6
Condition
Min
200
10
Max
—
—
—
—
—
50
70
—
—
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(A0)
R/W
tAH6
10
tDS6
20
tDH6
10
D0 ~ D7
Output disable time
Access time
tOH6
CL = 100pF
10
tACC6
tEWHR
tEWHW
tEWLR
tEWLW
tr, tf
—
READ
WRITE
READ
WRITE
77
Enable H pulse
width
E
E
22
117
172
—
Enable L pulse
width
Input signal change time
VSS = –2.7 to +4.5V, Ta = –30 to 85°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Signal
A0, CS
(CS1, CS2)
R/W
Symbol
tCYC6
tAW6
Condition
Min
450
25
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
tAH6
25
—
tDS6
40
—
tDH6
20
—
D0 ~ D7
Output disable time
Access time
tOH6
CL = 100pF
20
100
140
—
tACC5
tEWHR
tEWHW
tEWLR
tEWLW
tr, tf
—
READ
154
44
Enable H pulse
width
E
E
WRITE
READ
—
244
394
—
—
Enable L pulse
width
WRITE
—
Input signal change time
15
Notes: 1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC6 – tEWLW – tEWHW) or tr + tf ≤ (tCYC6
– tEWLR – tEWHR)
2. All signal timings are limited based on 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the E signal is in the high level.
If read/write operation is performed by the E signal while CS is active, it is determined by the E signal timing.
If read/write operation is performed by CS while the E signal is in the high level, it is determined by the CS active timing.
174-3.0
29
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.7
3.0 Electrical Characteristics
3.7 SERIAL INTERFACE
tCSS
tCSH
CS
A0
tSAS
tSAH
tSCYC
tSLW
SCL
tf
tr
tSHW
tSDH
tSDS
SI
30
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
3.0 Electrical Characteristics
3.7
VSS = –5.0 ± 10%, Ta = –30 to 85°C
Parameter
Serial clock cycle
Signal
Symbol
tSCYC
tSHW
tSLW
tSAS
Condition
Min
500
150
150
120
200
120
50
Max
—
—
—
—
—
—
—
—
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL high pulse width
SCL low pulse width
Address setup time
Address hold time
Data setup time
SCL
A0
SI
tSAH
tSDS
tSDH
tCSS
tCSH
tr, tf
Data hold time
30
CS-SCL time
CS
400
—
Input signal change time
VSS = –2.7 to –4.5V, Ta = –30 to 85°C
Parameter
Serial clock cycle
SCL high pulse width
SCL low pulse width
Address setup time
Address hold time
Data setup time
Signal
Symbol
tSCYC
tSHW
tSLW
tSAS
Condition
Min
1000
300
300
250
400
250
100
60
Max
—
—
—
—
—
—
—
—
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
A0
SI
tSAH
tSDS
tSDH
tCSS
tCSH
tr, tf
Data hold time
CS-SCL time
CS
800
—
Input signal change time
Note:
*2. All signal timings are limited based on 20% and 80% of VSS voltage.
174-3.0
31
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
32
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0
Functional
Description
174-3.0
33
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
34
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.0 – 4.1.3
4.1 MICROPROCESSOR INTERFACE
4.1.1 Parallel/Serial Interface
Table 4.1 Parallel/serial Interface Selection
P/S
Input Type
Parallel
Serial
CS1
CS1
CS1
CS2
CS2
CS2
A0
A0
A0
RD
RD
×
WR
WR
×
C86
C86
×
SI
×
SCL
×
D0 to D7
D0 to D7
(Hi-Z)
HIGH
LOW
SI
SCL
× = don’t care
Parallel data can be transferred in either direction
between the controlling microprocessor and the
SED1560 Series via an 8-bit I/O buffer (D0 to D7).
Serialdatacanbesentfromthemicroprocessortothe
SED1560Seriesthroughtheserialdatainput(SI), but
not from the SED1560 Series to the microprocessor.
The parallel or serial interface is selected by
setting P/S as shown in Table 4.1.
Table 4.3 Parallel Data Transfer
Com-
mon Series
6800
8080 Series
Description
A0
1
R/W
RD
0
WR
1
1
0
1
Display data read out
Display data write
Status read
1
1
0
0
0
1
Write to internal register
(command)
0
0
1
0
For the parallel interface, the type of microprocessor
is selected by C86 as shown in Table 4.2.
Table 4.2 Microprocessor Selection for Parallel
Interface
4.1.3 Serial Interface
The serial interface consists of an 8-bit shift register and
a 3-bit counter. These are reset when CS1 is HIGH and
CS2 is LOW. When these states are reversed, serial
data and clock pulses can be received from the micro-
processor on SI and SCL respectively.
MPU
Bus Type
C86
CS1 CS2 A0 RD WR D0 to D7
HIGH 6800-series CS1 CS2 A0
E
R/W D0 to D7
LOW 8080-series CS1 CS2 A0 RD WR D0 to D7
Serial data is read on the rising edge of SCL and must
be input at SI in the sequence D7 to D0. On every
eighth clock pulse, the data is transferred from the
shift register and processed as 8-bit parallel data.
4.1.2 Parallel Interface
A0, WR (or R/W) and RD (or E) determine the type of
parallel data transfer. See Table 4.3.
Input data is display data when A0 is HIGH and com-
mand data when A0 is LOW. A0 is read on the rising
edge of every eighth clock signal. See Figure 4.1.
174-3.0
35
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.1.3 – 4.2
4.0 Functional Description
CS1
CS2
SI
SCL
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
Figure 4.1 Serial interface timing
4.1.4 Chip Select Inputs
Likewise, when the microprocessor writes data to dis-
play data RAM, the data is first stored in the bus buffer
before being written to RAM at the next write cycle.
Data transfer between the microprocessor and the
SED1560 Series is enabled when CS1 is LOW and
CS2 is HIGH. If these pins are set to any other values,
D0 to D7 are in high impedance state and will not
accept data.
When writing data from the microprocessor to RAM,
there is no delay since data is automatically trans-
ferred from the bus buffer to the display data RAM. If
the data rate is required to slow down, the micropro-
cessor can insert a NOP instruction which has the
same effect as executing a wait procedure.
4.2 DATA TRANSFER
To match the timing of the display data RAM and
registers to that of the controlling microprocessor, the
SED1560 Series uses an internal data bus and bus
buffer. When the microprocessor reads the contents
of RAM, the data for the initial read cycle is first stored
inthebusbuffer(dummyreadcycle).Onthenextread
cycle, the data is read from the bus buffer onto the
microprocessor bus. At the same time, the next block
of data is transferred from RAM to the bus buffer.
When a sequence of address sets is executed, a
dummy read cycle must be inserted between each
pair of address sets. This is necessary because the
addresseddatafromtheRAMisdelayedonecycleby
the bus buffer, before it is sent to the microprocessor.
A dummy read cycle is thus necessary after an
address set and after a write cycle.
36
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.2
WR
MPU
N
N+1
N+2
N+3
DATA
Bus
holder
N
N+1
N+2
N+3
Internal
timing
WR
Figure 4.2 Write timing
WR
RD
MPU
N
N
n
n+1
Data read n Data read (n+1)
DATA
Address set
Dummy read
WR
RD
Internal
timing
Column
address
N
N+1
N+2
Bus
holder
N
n
N+1
N+2
Figure 4.3 Read timing
174-3.0
37
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.3 – 4.6
4.0 Functional Description
4.3 STATUS FLAG
4.5 COLUMN ADDRESS COUNTER
The SED1560 Series has a single bit status flag, D7.
When D7 is HIGH, the device is busy and will accept
only a Status Read command. It is not necessary for
the microprocessor to check the status of this bit
before each command, if enough time is allowed for
the last cycle to be completed.
The column address counter is an 8-bit presettable
counter that provides the column address to display
dataRAM. SeeFigure4.4. Itisincrementedby1each
timeareadorwritecommandisreceived.Thecounter
automatically stops at the highest address, A6H. The
contents of the column address counter are changed
bytheColumnAddressSetcommand. Thiscounteris
independent of the page address register.
4.4 DISPLAY DATA RAM
When the Select ADC command is used to select
inverse display operation, the column address de-
coder inverts the relationship between the RAM col-
umn data and the display segment outputs.
The SED1560 Series stores the display data sent
from the microcomputer in the built-in display data
RAM (166 × 65 bits) and generates the LCD drive
signals.Itisa166-column×65-rowaddressablearray
as shown in Figure 4.4.
4.6 PAGE ADDRESS REGISTER
The 65 rows are divided into 8 pages of 8 lines and a
ninth page with a single line (D0 only). Data is read
from or written to the 8 lines of each page directly
through D0 to D7.
The 4-bit page address register provides the page
address to display data RAM. The contents of the
register are changed by the Page Address Set com-
mand.
The microprocessor reads from and writes to RAM
through the I/O buffer. Since the LCD controller oper-
ates independently, data can be written to RAM at the
sametimeasdataisbeingdisplayed, withoutcausing
the LCD to flicker.
Page address 8 (1000) is a special use RAM area for
the indicator.
The time taken to transfer data is very short, because
the microprocessor inputs D0 to D7 correspond to the
LCD common lines as shown in Figure 4.5. Large
display configuration can thus be created using mul-
tiple SED1560 Series devices.
38
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.6
Page
DATA
Line
address
Common
address
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM 1
Column address
address
D0
D1
D2
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
1/64
Start
1/32
Note:
For 1/65
and 1/33 display
duty cycles, page 9
is accessed follow-
ing 1BH and 3BH,
respectively.
0
1
1
0
1
0
1
0
Page 7
Page 8
to
to
to
Figure 4.4 Display data RAM addressing
D0 1
D1 0
D2 1
D3 0
D4 0
COM0
COM1
COM2
COM3
COM4
Figure 4.5 RAM-to-LCD data transfer
174-3.0
39
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.7 – 4.8
4.0 Functional Description
4.7 INITIAL DISPLAY LINE REGISTER
The Initial Display Line register stores the address of
the RAM line that corresponds to the first (normally
the top) line (COM0) of the display. See Figure 4.4.
The contents of this 6-bit register are changed by the
InitialDisplayLinecommand. AtthestartofeachLCD
frame, synchronized with SYNC, the initial line is
copied to the line counter. The line counter is then
incremented on the CL clock signal once for every
display line. This generates the line addresses for the
transferofthe166bitsofRAMdatatotheLCDdrivers.
the six different LCD driver arrangements.
The necessary LCD driver voltage is automatically
allocated to the COM/SEG dual outputs when their
function is determined by the output selection circuit.
The SED1560 selects Case 1, 2 or 6 while the
SED1561 selects Case 3, 4, 5 or 6. The COM/SEG
output status for the SED1562 is fixed and so cannot
be selected.
If a 1/65 or 1/33 display duty cycle is selected by the
DUTY+1 command, the line address corresponding
to the 65th or 33rd SYNC signal is changed and the
indicator special-use line address is selected. If the
DUTY+1 command is not used, the indicator special-
use line address is not selected.
When COM outputs are assigned to the output driv-
ers, the unused RAM area is not available. However,
all RAM column addresses can still be accessed by
the microprocessor.
Since duty setting and output selection are inde-
pendent, the appropriate duty must be selected for
each case.
Cases 1 to 6 are determined according to the three
lowest bits in the output status register in the output
selection circuit. The COM output scanning direction
can be selected by setting bit D3 in the output status
register to “H” or “L”.
4.8 OUTPUT SELECTION CIRCUIT
The number of common (COM) and segment (SEG)
driver outputs can be selected to fit different LCD
panel configurations by the output selection circuit.
There are 70 segment-only outputs (O32 to O101)
and 96 common or segment dual outputs (O0 to O31
and O102 to O165). A command selects the status of
the dual common/segment outputs. Figure 4.6 shows
When the DUTY+1 command is executed, pin
COM1 becomes as shown in Figure 4.4 irrel-
evant to output selection.
ADC
(D0)
L
H
0
165
165
Column address
0
Display data RAM
Case 1
Case 2
Case 3
Case 4
Case 5
Case 6
SED1562
102 segments
64 commons
32 commons
32 commons
32 commons
102 segments
134 segments
134 segments
32 commons
134 segments
166 segments
150 segments
16 commons
16 commons
16 commons
O0
O15
O31
O101
O133
O149
O165
Figure 4.6 Output configuration selection
40
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.8
Since master/slave operation and the output selec-
tion circuit are completely independent in the
SED1560 Series, a chip on either the master or
slave side can be allocated to the COM output
function in multi-chip configuration.
The LCD driver outputs shown in Table 4.5 become
ineffective when the SED1560 or SED1561 is used
with 1/48 or 1/24 duty, respectively. In this case,
ineffective outputs are used in the open state.
Table 4.4
SED1560
SED1561
SED1562
1/16
Duty
1/64
1/48
1/32
1/24
COMI function
COM64
COM48
COM32
COM24
COM16
Table 4.5
Output Status Register
Ineffective Output
D3
0
D2
1
D1
0
D0
1
O150 ~ O165
O102 ~ O117
O150 ~ O165
O16 ~ O31
Case 1
1
1
0
1
SED1560
0
1
1
0
Case 2
Case 3
Case 4
Case 5
1
1
1
0
0
0
1
1
O0 ~ O7
1
0
1
1
O23 ~ O31
0
0
1
0
O158 ~ O165
O134 ~ O141
O158 ~ O165
O8 ~ O15
SED1561
1
0
1
0
0
0
0
1
1
0
0
1
174-3.0
41
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.9 – 4.10
4.0 Functional Description
4.9 SED1560 OUTPUT STATUS
The SED1560 selects any output status from Cases 1, 2 and 6.
1/64 Duty (Display Area 102 × 64)
Status Register
LCD Driver Output
Case
D3 D2 D1 D0 O0
O31 O32
O101 O102
COM0
O133 O134
O165
COM63
COM0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
COM63
0
COM31
COM32
COM0
COM63
SEG102
SEG102
SEG166
COM32
COM31
COM63
COM0
2
6
1
—
1/48 Duty (Display Area 102 × 48)
Status Register
Case
LCD Driver Output
O101 O102
COM0
D3 D2 D1 D0 O0
O31 O32
O133 O134
COM47
O165
COM0
COM0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
COM47
0
COM31
COM0
SEG102
SEG102
SEG166
COM32 47
COM31
2
6
1
COM32 47
—
4.10 SED1561 OUTPUT STATUS
The SED1561 selects any output status from Cases 3, 4, 5 and 6.
1/32 Duty (Display Area 134 × 32)
Status Register
LCD Driver Output
Case
D3 D2 D1 D0 O0 O15 O16 O31 O32
O133 O134 149 150 O165
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
COM31
COM0
COM0
SEG134
SEG134
3
4
COM31
0
SEG134
SEG134
COM0
COM31
COM0
1
COM31
0
15 COM0
COM16 31
SEG134
SEG134
SEG166
COM16 31
15 COM0
5
6
1
—
42
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.10 – 4.12.3
1/24 Duty (Display Area 134 × 24)
Status Register
Case
LCD Driver Output
D3 D2 D1 D0 O0 O15 O16 O31 O32
O133 O134 149 150 O165
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
COM23
COM0
SEG134
SEG134
3
4
COM0 COM23
0
SEG134
SEG134
COM0
COM23
1
COM23 COM0
0
15 COM0
16 23
SEG134
SEG134
SEG166
16 23
5
6
1
15 COM0
—
4.11 SED1562 OUTPUT STATUS
COM/SEG output status of the SED1562 is fixed.
1/16 Duty (Display Area 150 × 16)
LCD Driver Output
SEG150
O0
O149 O150
O165
15
COM0
4.12 DISPLAY TIMERS
4.12.1 Line Counter and Display Data Latch
Timing
SYNC synchronizes the timing of the line counter and
common timers. It is also needed to synchronize the
frame period and a 50% duty clock.
The display clock, CL, provides the timing signals for
the line counter and the display data latch. The RAM
line address is generated synchronously using the
displayclock. Thedisplaydatalatchsynchronizesthe
166-bit display data with the display clock.
In a multiple-chip configuration, FR and SYNC are
inputs. The SYNC signal from the master synchro-
nizesthelinecounterandcommontimingoftheslave.
4.12.3 Common Timing Signals
The timing of the LCD panel driver outputs is
independent of the timing of the input data from
the microprocessor.
The internal common timing and the special-use
common driver start signal, DYO, are generated from
CL. As shown in Figures 4.7 and 4.8, DYO outputs a
HIGH-level pulse on the rising edge of the CL clock
pulse that precedes a change on SYNC. DYO is
generated by both the SED1560 Series devices,
regardless of whether the device is in master or slave
mode. However, when operating in slave mode, the
devicedutyandtheexternalSYNCsignalmustbethe
same as that of the master. In a multiple-chip configu-
ration, FR and SYNC must be supplied to the slave
from the master.
4.12.2 FR and SYNC
The LCD AC signal, FR, and the synchronization
signal, SYNC, are generated from the display clock.
The FR controller generates the timing for the LCD
panel driver outputs. Normally, 2-frame wave pat-
terns are generated, but n-line inverse wave patterns
can also be generated. These produce a high-quality
display if n is based on the LCD panel being used.
174-3.0
43
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.13
4.0 Functional Description
Table 4.6 Master and Slave Timing Signal Status
Part Number
Mode
FR
SYNC
CLO
DYO
CL
Output
Master Output Output
Output
SED1560
Series
High
Slave
Input
Input Imped- Output
ance
4.13 TWO-FRAME AC DRIVER WAVEFORM (SED1561, 1/32 DUTY)
31 32
1
2
3
4
5
6
27 28 29 30 31 32
1
2
3
4
5
CL
SYNC
FR
DYO
VDD
V1
V2
COM0
COM1
V3
VDD
V1
V2
V3
RAM
data
VDD
V2
V3
SEG n
V5
Figure 4.7 Frame driver timing for duty 1/32
44
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.14
4.14 n LINE INVERSE DRIVER WAVEFORM (n=5, LINE INVERSE REGISTER 4)
31 32
1
2
3
4
5
6
27 28 29 30 31 32
1
2
3
4
5
CL
SYNC
FR
DYO
VDD
V1
V4
V5
COM0
COM1
VDD
V1
V4
V5
RAM
data
VDD
V2
V3
SEG n
V5
Note: When n = 5, the line inversion register is set to 4.
Figure 4.8 Line inverse driver timing
174-3.0
45
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.15 – 4.20
4.0 Functional Description
4.15 DISPLAY DATA LATCH
4.19 OSCILLATOR CIRCUIT
Display data is transferred from RAM to the LCD
drivers through the display data latch. This latch is
controlled by the Display ON/OFF, Display All Points
ON/OFF and Normal/Inverse Display commands.
The low power consumption type CR oscillator
adjusting the oscillator frequency by use of only
oscillator resistor Rf is used as a display timing
signal source or clock for the voltage raising circuit
of the LCD power supply.
These commands do not alter the data.
The oscillator circuit is available only in the master
operationmode.Whenasignalfromtheoscillatorcircuit
is used for display clock, fix the CL pin to the VSS level.
When the oscillator circuit is not used, fix the OSC1 or
OSC2 pin to the VDD or VSS level, respectively.
4.16 LCD DRIVER
The LCD driver converts RAM data into the 167
outputs that drive the LCD panel. There are 70 seg-
ment outputs, 96 segment or common dual outputs,
and a COM1 output for the indicator display.
The oscillator signal frequency is divided and output
from the CL0 pin as display clock. The frequency is
divided to one-fourth, one-eighth, or one-sixteenth in
the SED1560, SED1561, or SED1562, respectively.
Two shift registers for the common/segment drivers
are used to ensure that the common outputs are out-
put in the correct sequence. The driver output volt-
ages depend on the display data, the common scan-
ning signal and FR.
4.20 FR CONTROL CIRCUIT
The LCD driver voltage supplied to the LCD driver
outputs is selected using FR signal.
4.17 DISPLAY DATA LATCH CIRCUIT
The display data latch circuit temporarily stores the
output display data from the display data RAM to
the LCD driver circuit in each common period.
Since the Normal/Inverse Display, Display ON/
OFF and Display All Points ON/OFF commands
control the data in this latch, the data in the display
data RAM remains unchanged.
4.18 LCD DRIVER CIRCUIT
This multiplexer generates 4-value levels for the LCD
driver, having 167 outputs of 70 SEG outputs, 96
SEG/COM dual outputs and a COM output for the
indicator display. The SEG/COM dual outputs have a
shift register and sequentially transmit COM scan-
ning signals. The LCD driver voltage is output accord-
ing to the combination of display data, COM scanning
signal and FR signal. Figure 4.9 shows a typical SEG/
COM output waveform.
46
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.20
VDD
VSS
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
FR
(SYNC)
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM0
COM1
COM2
SEG0
SEG1
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0SEG1SEG2SEG3SEG4
V4
V5
V5
V4
V3
V2
V1
COM0
to
SEG0
VDD
–V1
–V2
–V3
–V4
–V5
V5
V4
V3
V2
V1
COM0
to
VDD
–V1
–V2
–V3
–V4
–V5
SEG1
Figure 4.9 Example of segment and common timing
174-3.0
47
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.21 – 4.22
4.0 Functional Description
When (T1, T2) = (H, L), the boosting circuit does not
work and open the boosting circuit terminals (CAP1+,
CAP1–, CAP2+ and CAP2–) and apply liquid crystal
driving voltage to the VOUT terminals from outside.
4.21 POWER SUPPLY CIRCUIT
The SED1560 Series has an internal DC/DC con-
verter to generate LCD bias voltages. The internal
power supply circuit can be used only when the
controlleroperatesinmastermode. Thepowercircuit
consists of a triple boosting circuit, a voltage regula-
tion circuit and a low power voltage follower circuit.
When (T1, T2) = (H, H), the boosting circuit and
voltage regulation circuit do not work and open the
boosting circuit terminals and the VR terminals and
applyliquidcrystaldrivingvoltagetotheV5,andleave
the VOUT pin open.
The power circuit built into SED1560 Series is set for
smaller scale liquid crystal panels and it is not suit-
able when the picture element is larger or to drive a
liquid crystal panel with larger indication capacity
using multiple chips. It is recommended that an exter-
nal power supply is used when using a liquid crystal
panel with a larger load capacity.
4.22 TRIPLER BOOSTING CIRCUIT
By connecting capacitors C1 between CAP1+ and
CAP1–, CAP2+ and CAP2– and VSS – VOUT, the
electric potential between VDD – VSS is boosted to the
triple toward negative side and outputted from the
VOUT terminal. When a double boosting is required,
disconnectthecapacitorbetweenCAP2+andCAP2–
and short-circuit the CAP2– and VOUT terminals to
obtainoutputboostedtothedoubleoutoftheVOUT (or
CAP2–) terminal.
Thepowersupplycircuitcanbecontrolledbythebuilt-
in power ON/OFF command. When the built-in power
is turned off, the boosting circuit, voltage regulation
circuit and voltage follower circuit all go open. In this
case, the liquid crystal driving voltage V1, V2, V3, V4
and V5 should be supplied from outside and the
terminalsCAP1+, CAP1–, CAP2+, CAP2–, VOUT and
VR should be kept opened.
Signals from the oscillation circuit are used in the
boosting circuit and it then is necessary that the
oscillation circuit is in operation.
Various functions of the power circuit can be selected
by combinations of the setting of the T1 and T2. It is
also possible to make a combined use of the external
powersupplyandaportionofthefunctionsofthebuilt-
in power supply.
Electricpotentialsbytheboostingfunctionsareshown
in Figure 4.10 and 4.11.
Table 4.7
Voltage
Converter
Circuit
Voltage
Converter
Circuit
Voltage
Regulation
Circuit
External
Voltage
Input
Voltage
Regulation
Terminals
V/F
Circuit
T1
T2
Terminals
L
L
L
H
L
O
O
X
X
O
O
O
X
O
O
O
O
—
—
H
H
VOUT
V5
OPEN
OPEN
H
OPEN
48
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.22 – 4.23
VDD = 0V
(VCC = +5V) VDD = 0V
(GND) VSS = –5V
VSS = –5V
VOUT = 2vss = –10V
V
OUT = 3
v
= –15V
ss
Figure 4.10
Electric potentials of double boosting
Figure 4.11
Electric potentials of triple boosting
4.23 VOLTAGE REGULATION CIRCUIT (SOFTWARE CONTRAST ADJUSTMENT FUNCTION IS
NOT USED)
The voltage regulation circuit renders a temperature
gradient, after VREG output, of about –0.17% /°C, but
when any other temperature gradient is needed,
connect a thermistor in series with the output voltage
regulating resistors.
The boosted voltage coming out from VOUT is ad-
justed to become the liquid crystal driving voltage V5
via the voltage regulation circuit. V5 voltage can be
regulated within a range of |V5| < |VOUT| by adjust-
ment of resistors Ra and Rb and it may be calculated
by the following equation:
Since the VR terminal has a high input impedance, it
is necessary to take some noise suppression mea-
sures, such as using the shortest length wiring or
shielded wiring.
Rb
Ra
V5 = (1 +
) VREG
Equation 4.1
wherein VREG is the constant voltage source inside
the IC and the voltage is constant at VREG ≈ 2.5V.
Voltage regulation of the V5 output is made by con-
necting variable resistors between VR, VDD and V5.
For fine adjustment of the V5 voltage, a combination
of fixed resistors R1 and R3 and a variable resistor R2
is needed.
VDD
VREG
Ra
+
Examples of settings of R1, R2, and R3:
V5
–
VR
• R1 + R2 + R3 = 5 MΩ (determined by the
current required to flow between VDD and V5)
• Voltage variation range by R2: –11V ~ –13V
(determined based on the characteristics of
the liquid crystal being used)
Rb
Figure 4.12
Voltage regulation circuit
Using the above conditions and Equation 4.1, the
following calculations can be made:
R1 = 0.947 MΩ
R2 = 0.174 MΩ
R3 = 3.879 MΩ
174-3.0
49
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.24
4.0 Functional Description
4.24 VOLTAGE REGULATION CIRCUIT USING SOFTWARE CONTRAST ADJUSTMENT
CONTROL FUNCTION
By using software contrast adjustment control function, it is possible to control the liquid crystal driving
voltage V5 by inputting corresponding commands to adjust the contrast of the liquid crystal display.
With such an electronic contrast control function, setting 5-bit data to the electronic contrast control
register will make available 32 states of voltages from which one voltage level can be selected for the
liquid crystal driving voltage V5.
When using the software contrast control function, it is necessary to execute built-in power supply on
command after one of (T1, T2) = (L, L), (T1, T2) = (L, H), or (T1, T2) = (H, L) is set.
Example of Constant Setting When Using the Software Contrast Adjustment Control Function
(1) Determine a V5 voltage setting range by the electronic contrast control.
Liquid crystal driving voltage ...........................V5 – 10V max. to –15V min.
V5 variable voltage width ................................4V
(2) Determine Rb.
Rb = V5 variable voltage width / IREF
Rb = 4V / 6.5µA
(32 states IREF ≈ 6.5µA constant-current value)
(16 states IREF ≈ 3.2µA constant-current value)
= 615 kΩ
(3) Determine Ra.
VREG
(For VREG and V5 set voltage, absolute values are used.)
Ra =
(V5 set voltage max – VREG) / Rb
2.5V
Ra =
(10V – 2.5V) / 615Ω
= 205 kΩ
(4) Adjust Ra.
Set the electronic contrast control register value to (D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0) or (0, 1, 1,
1, 1), and adjust the Ra value to the optimum contrast.
To set the voltage value by the software contrast adjustment control to the 16 states, fix the data D4 of
the electronic contrast control register to L and set data in D3 to D0. At this time, set IREF ≈ 3.2µA and
determine Ra and Rb according to the above steps (1) to (4).
Because IREF is a simplified constant-current source, it is necessary to consider the variation of
maximum ±40% as manufacturing dispersion. The temperature dependency of IREF becomes ∆IREF ≈
–0.0525µA/°C (in the variable voltage 32 states) or ∆IREF ≈ –0.0234 µA/°C (variable voltage 16 states).
Determine Ra and Rb for the LCD to be used, by taking the above dispersion and variations due to
temperatures into consideration.
When using the software contrast adjustment control function, Ra must be a variable resistance and the
50
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.24 – 4.25
optimum contrast adjustment described in (4) must be made for each IC chip in order to compensate
the V5 voltage value due to the dispersion of VREG and IREF.
When the contrast control function is not used, set the register value to (D4, D3, D2, D1, D0) = (0, 0,
0, 0, 0) by the RES signal or electronic contrast control register set command.
4.25 PRECAUTIONS ON USING THE SED1560 SERIES SOFTWARE CONTRAST ADJUSTMENT
CONTROL FUNCTION
The SED1560 Series is provided with a software contrast adjustment control function having up to 32
levels to control the regulator. The V5 voltage, when the software contrast control function is used, is
represented by the following expression:
V5 = (1 + Rb / Ra). VREG + Rb × ∆IREF
By this expression, the software contrast control function controls an increment of V5 voltage by means
of the current source IREF built into the IC. (In the case of 32 levels, ∆IREF = IREF / 32).
The V5 minimum voltage is set by the resistance ratio of the externally-installed Ra and Rb, and the
voltage step width by the software contrast control is determined by the resistance value of Rb.
The reference voltage VREG and current source IREF built into the SED1560 Series are kept constant
against voltage variations.
However, IC manufacturing dispersion and variations due to temperatures are caused as shown below.
VREG = 2.5V ± 0.15V
VREG = –0.17%/°C
IREF = –0.0234 µA/°C
IREF = –0.0525 µA/°C
IREF = 3.2µA ± 40% (for 16 levels)
6.5µA ± 40% (for 32 levels)
Example of Constant Setting
Conditions: Center value .............................VDD – V5 = 8.5V
Variable voltage width...............3.2V
Variable voltage level................32 levels
(1) Determination of Rb.
VDD
Rb = V5 variable voltage width / IREF
= 3.2V / 6.5µA
VREG
= 492 kΩ
Ra
VR
+
–
V5
Rb
174-3.0
51
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.25
4.0 Functional Description
(2) Determination of Ra.
VREG
Ra =
(V5 minimum set voltage – VREG) / Rb
2.5V
=
{(8.5V – 3.2V/2) – 2.5V} / 492kΩ
= 280 kΩ
(3) Temperature dependency of V5 when VREG = 2.5V and IREF = 6.5µA (32 levels).
V5 minimum set voltage (V5 min) = 8.5V – 3.2V/2 = 6.9V
Ta = 25°C
V5 max = V5 minimum set voltage + Rb × IREF
= 6.9V + 492kΩ × 6.5 µA
= 10.1V ....................................... 1
V5 typ
= (V5 max + V5 min) / 2
= (10.1V + 6.9V) / 2
= 8.5V ......................................... 2
Ta = –10°C
V5 min = (1 + Rb / Ra) × VREG (Ta = –10°C)
= (1 + 492kΩ / 280kΩ) × 2.5V × {1 + (–0.17%/°C) × (–10°C – 25°C)}
= 7.3V ......................................... 3
V5 max = V5 min + Rb × IREF (Ta = –10°C)
= 7.3V + 492kΩ × {6.5µA + (–0.0525 µA/°C) × (–10°C – 25°C)}
= 11.4V ....................................... 4
V5 typ
= (V5 max + V5 min) / 2
= (11.4V + 7.3V) / 2
= 9.35V ....................................... 5
Ta = 50°C
V5 min = (1 + Rb / Ra) × VREG (Ta = 50°C)
= (1 + 492kΩ / 280kΩ) × 2.5V × {1 + (–0.17%/°C) × (50°C – 25°C)}
= 6.6V ......................................... 6
V5 max = V5 min + Rb × IREF (Ta = 50°C)
= 6.6V + 492kΩ × {6.5µA + (–0.0525 µA/°C) × (50°C – 25°C)}
= 9.15V ....................................... 7
V5 typ
= (V5 max + V5 min) / 2
= (9.15V + 6.6V) / 2
= 7.9V ......................................... 8
52
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.25
To set the number of variable voltage levels to 16, specify IREF = 3.2µA.
•
Margin calculation is performed by considering the dispersion of VREG and VREF according to the
same procedure as (3). From this margin calculation, it is made clear that the center value of V5 is
affected by variations of VREG and IREF.
•
Accordingly, it is necessary to set the electronic contrast control register value to (D4, D3, D2, D1,
D0) = (1, 0, 0, 0, 0) or (0, 1, 1, 1, 1) and adjust the Ra value to the optimum contrast.
•
•
The voltage step width by the electronic contrast control is changed by the dispersion of IREF. It is
necessary to consider that supposing that 0.2V/STEP is set by TYP value, the maximum variation
of 0.12V to 0.28V occurs.
SED 1560 Series
14
(V)
12
4
•
1
10
•
2
5
8
°
•
°
7
8
°
3
6
V5
6
4
2
0
V5 max
V5 typ
V5 min
•
°
–20
–10
0
10
20
Ta
30
40
50
60
(°C)
Example of V5 voltage when using SED1560 Series electronic contrast control
174-3.0
53
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.25 – 4.26
4.0 Functional Description
Since the IREF is a simplified constant current source,
when using the electronic contrast control function, it
becomes necessary to make adjustment to the opti-
mumcontrastasgivenintheaboveitem(4),witheach
of the IC chips, using the Ra as a variable resistor.
Table 4.8
Type
Liquid Crystal Driving Voltage
1/9 of the bias voltage
SED1560
SED1561
SED1562
1/7 of the bias voltage
1/5 of the bias voltage
When not using the software contrast adjustment
control function, set the register to (D3, D2, D1, D0)
= (0, 0, 0, 0) using the RES signal or by means of the
software contrast adjustment control register set-
ting command.
Table 4.9 Reference Setting Value
Reference set values:
SED1560 .....V5 ≈ –11 ~ –13V
4.26 LIQUID CRYSTAL VOLTAGE
GENERATING CIRCUIT
SED1561 .....V5 ≈ –7 ~ –9V
SED1562 .....V5 ≈ –5 ~ –7V (Variable)
A V5 potential is resistively divided within the IC to
causeV1, V2, V3andV4potentialsneededfordriving
ofliquidcrystals.TheV1,V2,V3andV4potentialsare
further converted in the impedance by the voltage
follower before being supplied to the liquid crystal
driving circuit.
SED1560
0.47µF~
1.0µF~
1.0µF~
1MΩ
SED1561
0.47µF~
0.47µF~
0.47µF~
700KΩ
SED1562
0.47µF~
0.47µF~
0.47µF~
500KΩ
C1
C2
R1
R2
R3
200KΩ
4MΩ
200KΩ
200KΩ
1.6MΩ
700KΩ
The liquid crystal driving voltage is fixed with each
type (see Table 4.8).
LCD
SIZE
32 × 51
mm
16 × 67
mm
8 × 75
mm
DOT
64 × 102
32 × 134
16 × 150
As shown in Figure 4.13, it needs to connect, exter-
nally, 5unitsofvoltagestabilizingcapacitorsC2tothe
liquid crystal power terminals. When selecting such
capacitor C2, make actual liquid crystal displays
matching to the display capacity of the liquid crystal
display panel, before determining the capacitance as
the constant value for voltage stabilization.
54
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.0 Functional Description
4.26
Rf
Rf *1
VDD
VDD
OSC1 OSC2
M/S
OSC1 OSC2
M/S
VSS
CL
VSS
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
C1
C1
VSS
C1
R3
R1
V5
VR
V5
SED156X
V
R
R2
SED156X
*2
VDD
VDD
V1
V2
V3
V4
V5
V1
V2
V3
V4
V5
External
supply
voltage
C2
Figure 4.14
Figure 4.13
When external LCD power supply is used
When the built-in power supply is used
*1 Connect oscillator feedback resistor Rf as
short as possible and place it close to the
IC for preventing a malfunction.
*2 Use short wiring or shielded cables for the
VR pin due to high input impedance.
*3 Determine C1 and C2 depending on the
sizeoftheLCDpaneldriven. Youmustset
these values so that the LCD driving volt-
age becomes stable. Set (T1, T2) = (H, L)
and supply an external voltage to VOUT.
Display the LCD heavy load pattern and
determine C2 so that the LCD driving
voltages (V1 to V5) become stable. How-
ever, it is necessary to make every C2
capacitance value equal. Then, set (T1,
T2) = (L, L) and determine C1.
*4 The “LCD SIZE” indicates the vertical
and horizontal length of the LCD panel
display area.
174-3.0
55
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
4.27
4.0 Functional Description
4.27 RESET
When power is turned ON, the SED1560 Series is
initializedontherisingedgeofRES.Initialsettingsare
as follows:
1. Display
: OFF
2. Display mode
: Normal
: OFF
3. n-line inversion
4. Duty cycle
: 1/64
5. ADC select
: Normal
: OFF
6. Read/write modify
7. On-chip power supply
8. Serial interface register
9. Display initial line register
10. Column address counter
11. Page address register
12. Output selection circuit
13. n-line inversion register
14. Software contrast setting
: OFF
: Cleared
: Line 1
: 0
: Page 0
: Case 6
: 16
: zero
TheRESpinshouldbeconnectedtothemicroproces-
sor reset terminal so that both devices are reset at the
same time. RES must be LOW for at least 1 µs to
correctly reset the SED1560 Series. Normal opera-
tion starts 1 µs after the rising edge on RES.
If the SED1560 Series is not properly initialized when
power is turned ON, it can lock itself into a state that
cannot be cancelled.
When the Reset command is used, only initial set-
tings 9 to 14 are active.
56
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.0
Commands
174-3.0
57
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
58
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.0 Commands
5.1
5.1 COMMAND SUMMARY
A0, RD and WR identify the data bus commands.
Interpretation and execution of commands are syn-
chronized to the internal clock. Since a busy check is
normallynotneeded,commandscanbeprocessedat
high speed. When the serial interface is used, the
order of data entry is D7 to D0.
Table 5.1
Code
Command
Description
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Turns the display ON and OFF.
D = 0 OFF
Display ON/OFF
0
1
0
1
0
1
0
1
1
1
D
D = 1 ON
Sets the display RAM line address for
COM0.
Initial display line
Page address set
0
0
0
1
1
1
0
0
0
0
1
0
1
0
0
Display line address
1
0
1
1
Page address
Sets the RAM page address register.
Column address set
(upper four bits)
Column address
upper four bits
Sets the column address register upper
four bits.
Column address set
(lower four bits)
Column address
lower four bits
Sets the column address register lower
four bits.
0
1
0
0
0
0
0
Read status
0
1
1
0
1
0
1
0
1
Status
0
0
0
0
Reads out status information.
Writes to display RAM.
Write display data
Read display data
Write data
Read data
Reads from display RAM.
Sets the display RAM segment output.
Select ADC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
D
D
D = 0 Normal
D = 1 Inverse
Normal/inverse
display
Sets the LCD display mode.
D = 0 Normal
D = 1 Inverse
Sets the segments display mode.
D = 0 Normal
D = 1 All display segments ON
Display all points
ON/OFF
0
1
0
1
0
1
0
0
1
0
D
Sets the LCD controller duty (1).
D = 0, D=1 See Table 5.3
Select duty
Duty + 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
D
D
Sets the LCD controller duty (2).
D = 0 Normal
D = 1 Duty + 1
Number of
inverted items
Sets the number of inverted lines in the in-
versionregisterfortheinversioncontroller.
Set n-line inversion
Cancel n-line inversion
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
Cancels line inversion display mode.
Sets modified read mode. The column
address counter is not incremented when
reading.
Read Modify Write
End
0
1
0
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
Cancels modified read mode.
Power-on
completion
Completes the turn-on sequence of built-
in power supply
Reset
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
0
Resets the internal registers.
Sets the common and segment output
status register.
Output status set
Output status
LCD power supply
ON/OFF
Turns the power supply ON and OFF.
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
0
D
D = 0 OFF
D = 1 ON
Software contrast
setting
Electronic contrast control Setting the V5 output voltage to the elec-
tronic contrast control register.
resistance value
A complex command to turn off the display
and light all indicators.
Power save
174-3.0
59
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.2 – 5.2.4
5.2 Command Definitions
5.2 COMMAND DEFINITIONS
5.2.1 Display ON/OFF
A3
0
A2
0
A1
0
A0
0
Page
Alternately turns the display ON and OFF.
R/W
0
1
2
3
4
5
6
7
8
0
0
0
1
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
0
1
0
1
0
1
0
1
1
1
D
0
0
1
1
Note:
D = 0 Display OFF
D = 1 Display ON
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
5.2.2 Initial Display Line
1
0
0
0
Loads the RAM line address of the initial display line,
COM0, into the initial display line register. The RAM
display data becomes the top line of the LCD screen.
It is followed by the higher number lines in ascending
order, corresponding to the duty cycle. The screen
can be scrolled using this command by incrementing
the line address.
5.2.4 Column Address Set
Loads the RAM column address from the micropro-
cessor into the column address register. The column
address is divided into two parts—4 high-order bits
and 4 low-order bits.
R/W
When the microprocessor reads or writes display
data to or from RAM, column addresses are auto-
matically incremented, starting with the address
stored in the column address register and ending
with address 166.
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
A5 A4 A3 A2 A1 A0
A5
0
A4
0
A3
0
A2
A1
0
A0 Line Address
0
0
0
0
1
0
0
1
0
0
0
0
The page address is not incremented automatically.
R/W
0
0
0
1
2
↓
↓
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
1
1
1
1
1
1
1
0
1
62
63
0
1
0
0
0
0
1
A7 A6 A5 A4
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
5.2.3 Page Address Set
0
1
0
0
0
0
0
A3 A2 A1 A0
Loads the RAM page address from the microproces-
sor into the page address register. A page address,
along with a column address, defines a RAM location
for writing or reading display data. When the page
address is changed, the display status is not affected.
Column
Address
A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
↓
0
0
0
0
0
0
0
1
0
1
Page address 8 is a special use RAM area for the
indicator. Only D0 is available for data exchange.
↓
1
0
1
0
0
1
0
1
165
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
1
A3 A2 A1 A0
60
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.2 Command Definitions
5.2.5 – 5.2.9
5.2.5 Read Status
5.2.7 Read Display Data
Indicates to the microprocessor the SED1560 Series
status conditions.
Sends bytes of display data to the microprocessor
from the RAM location specified by the column ad-
dress and page address registers. The column ad-
dress is incremented automatically so that the micro-
processor can continuously read data from the ad-
dressedpage. Adummyreadisrequiredafterloading
an address into the column address register.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
ON/
OFF SET
RE-
BUSY ADC
0
0
1
0
0
0
0
• BUSY - Indicates whether or not the SED1560
Series will accept a command. If BUSY is 1,
thedeviceiscurrentlyexecutingacommand
or is resetting, and no new commands can
be accepted. If BUSY is 0, a new command
can be accepted. It is not necessary for the
microprocessortocheckthestatusofthisbit
if enough time is allowed for the last cycle to
be completed.
Displaydatacannotbereadthroughtheserialinterface.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
Read data
5.2.8 Select ADC
Selects the relationship between the RAM column
addresses and the segment drivers. When reading or
writingdisplaydata,thecolumnaddressisincremented
as shown in Figure 5.4.
• ADC -IndicatestherelationshipbetweenRAM
column addresses and the segment drivers.
If ADC is 1, the relationship is normal and
column address n corresponds to segment
driver n. If ADC is 0, the relationship is
inverted and column address (165 – n) cor-
responds to segment driver n.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
0
0
D
Note:
• ON/OFF - Indicates whether the display is
ON or OFF. If ON/OFF is 1, the display is
OFF. If ON/OFF is 0, the display is ON.
Note that this is the opposite of the Display
ON/OFF command.
D = 0 Rotate right (normal direction)
D = 1 Rotate left (reverse direction)
The output pin relationship can also be changed by the
microprocessor. There are very few restrictions on pin
assignments when constructing an LCD module.
• RESET - Indicates whether initialization is
in process as the result of RES or the
Reset command.
5.2.9 Normal/Inverse Display
Determines whether the data in RAM is displayed
normally or inverted.
5.2.6 Write Display Data
Writes bytes of display data from the microproces-
sor to the RAM location specified by the column
address and page address registers. The column
address is incremented automatically so that the
microprocessor can continuously write data to the
addressed page.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
1
1
D
Note:
D = 0 LCD segment is ON when RAM data is 1 (normal).
D = 1 LCD segment is ON when RAM data is 0 (inverse).
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
Write data
174-3.0
61
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.2.10 – 5.2.14
5.2 Command Definitions
5.2.10 Display All Points ON/OFF
the RAM area corresponding to page address 8, D0.
(Refer to Figure 5.4.)
Turns all LCD points ON independently of the display
data in RAM. The RAM contents are not changed.
In multi-chip configuration, the Duty + 1 command
must be executed to both the master and slave sides.
This command has priority over the normal/inverse
display command.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
R/W
0
1
0
1
0
1
0
1
0
1
D
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
1
0
D
Table 5.3
Note:
D = 0 Normal display status
D = 1 All display segments ON
Model
D
Duty
0
1
0
1
0
1
1/48 or 1/64
1/49 or 1/65
1/24 or 1/32
1/25 or 1/33
1/16
SED1560
If this command is received when the display status is
OFF, the Power Save command is executed.
SED1561
SED1562
5.2.11 Select Duty
1/17
Selects the LCD driver duty.
5.2.13 Set n-line Inversion
Since this is independent from the contents of the
output status register, the duty must be selected
according to the LCD output status.
Selects the number of inverse lines for the LCD AC
controller. The value of n is set between 2 and 16 and
is stored in the n-line inversion register.
In multi-chip configuration, the master and slave de-
vices must have the same duty.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
R/W
0
1
0
0
0
1
1
A3 A2 A1 A0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
0
0
D
A3
0
A2
0
A1
A0
0
Number of Inverted Lines
0
0
1
—
2
Table 5.2
0
0
1
0
0
0
3
Model
D
Duty
1/48
1/64
1/24
1/32
1/16
1/16
↓
↓
0
1
0
1
0
1
SED1560
1
1
1
1
1
1
0
1
15
16
SED1561
SED1562
5.2.14 Cancel n-line Inversion
Cancels n-line inversion and restores the normal 2-
frame AC control. The contents of the n-line inversion
register are not changed.
5.2.12 Duty + 1
R/W
Increasesthedutyby1. If1/48or1/64dutyisselected
in the SED1560, for example, 1/49 or 1/65 is set,
respectively,andCOM1functionsaseithertheCOM48
or COM64 output. The display line always accesses
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
0
0
0
0
0
62
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.2 Command Definitions
5.2.15 – 5.2.17
5.2.15 Modify Read
Following this command, the column address is no
longer incremented automatically by a Read Display
Data command. The column address is still
incremented by the Write Display Data command.
This mode is cancelled by the End command. The
column address is then returned to its value prior to
the Modify Read command. This command makes it
easy to manage the duplication of data from a particu-
lar display area for features such as cursor blinking.
Page address set
Column address set
R/W
Read–modify–write cycle
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
0
Note: the Column Address Set command cannot be used in
modify-read mode.
Dummy read
Data read
5.2.16 End
Cancels the modify read mode. The column address
prior to the Modify Read command is restored.
Data write
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
1
1
1
0
No
Changes
finished?
5.2.17 Reset
Resets the initial display line, column address, page
address, and n-line inversion registers to their initial
values. This command does not affect the display
data in RAM.
Yes
R/W
END
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
0
Figure 5.1
Command sequence for cursor blinking
The reset command does not initialize the LCD power
supply. Only hardware RES can be used to initialize
the power supplies.
Return
Column
address
N
N+1
N+2
N+3
N+m
N
End
Read–modify–write mode set
Figure 5.2
174-3.0
63
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.2.18 – 5.2.20
5.2 Command Definitions
5.2.18 Output Status Set
5.2.20 LCD Power Supply ON/OFF
Selects the common or segment output state of the
LCD driver dual outputs. The A3 bit selects the scan
direction of the outputs.
Turns the SED1560 Series LCD power supply ON or
OFF. When the power supply is ON, the voltage
converter, the voltage regulator circuit and the volt-
age followers are operating. In order for the converter
to function, the oscillator must also be operating.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
R/W
0
1
0
1
1
0
0
A3 A2 A1 A0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
2
0
0
1
4
0
0
5.2.19 Output Status Register
OFF
Available only in the SED1560 and SED1561.
Note:
D = 0 Supply OFF (24H)
D = 1 Supply ON (25H)
This command selects the role of the COM/SEG dual
pins and determines the LCD driver output status.
When an external power supply is used with the
SED1560 Series, the internal supply must be OFF.
The COM output scanning direction can be selected
by setting A3 to “H” or “L”. For details, refer to the
Output Status Circuit in each function description.
If the SED1560 Series is used in a multiple-chip
configuration, an external power supply that meets
the specifications of the LCD panel must be used. An
SED1560 Series operating as a slave must have its
internal power supply turned OFF.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
0
0
A3 A2 A1 A0
A3: Selection of the COM output scanning direction
Table 5.4
Sequence in the Built-In Power ON/OFF Status
Number of
Output
To turn on internal power supply, execute the follow-
ing built-in power supply ON sequence. To turn off
internal power supply, execute the power save se-
quence as shown in the following power supply OFF
status.
A2 A1 A0
COM/SEG
Remarks
Status
Output Pins
Applies to the
SED1560/61
0
0
0
Case 6
SEG 166
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Case 5
Case 4
Case 3
Case 2
Case 1
Case 6
Case 6
SEG 134, COM 32
SEG 134, COM 32
SEG 134, COM 32
SEG 102, COM 64
SEG 102, COM 64
SEG 166
Applies to the
SED1561
Accordingly, to turn on internal power supply again
afterturnitoff(powersave), executethe“PowerSave
Clear Sequence” that is described below.
Applies to the
SED1560
Applies to the
SED1560/61
SEG 166
64
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.2 Command Definitions
5.2.20
Sequence in the Power Save Status
PowerSaveandPowerSaveClearmustbeexecuted
according to the following sequence.
When using an external power supply, likewise, its
function must be stopped before or concurrently
with putting the SED1560 Series into the power
save status so that it may be fixed to the floating or
VDD level. In a configuration in which an exclusive
common driver such as SED1630 is combined with
the SED1560 Series, it is necessary to stop the
external power supply function after putting all the
common output into non-selection level.
To give a liquid crystal driving voltage level by the
externally-installed resistance dividing circuit, the
current flowing in this resistance must be cut before
or concurrently with putting the SED1560 Series
into the power save status so that it may be fixed to
the floating or VDD level.
Power Save Sequence
Power Save Clear Sequence
*3
*2
Output Status Select
command
command
command
C*(H)
AB(H)
25(H)
Display OFF
command
AE(H)
*DUTY+1
Output Status case 6 command
CF(H)
AA(H)
A5(H)
*3
*2
*1
Internal Power Supply ON
*DUTY+1 Clear
Display all ON
command
command
*1
*6
*5
Display All ON Status OFF
(Waiting time)
Power Supply Startup End
command
ED(H)
*1. In the power save sequence, the power
save status is provided after the display all
ON command. In the power save clear se-
quence, the power save status is cleared
after the display all ON status OFF com-
mand.
*5. When internal power supply startup end
command is not executed, current is con-
sumed stationarily. Internal power supply
startup end command must always be used
in a pair with internal power supply ON
command.
*2. When the COMI pin is not used, it is not
necessary to enter the DUTY + 1 command
and DUTY + 1 clear command.
*6. The waiting time depends on the externally-
installedcapacitanceC2(refertoTable5.9).
After the waiting time shown in the graph
above (see bottom of previous page), the
power supply can be started surely.
*3. In the SED1562, it is not necessary to ex-
ecute a command to decide an output sta-
tus.
*4. The display ON command can be executed
anywhere if it is later than the display all ON
status OFF command.
174-3.0
65
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.2.20
5.2 Command Definitions
Internal Power Supply ON Status
Internal Power Supply OFF Status
Reset by RES signal
Display OFF
command
AE(H)
*1
*2
Output Status Select
command
command
command
A*(H)
AB(H)
25(H)
Output Status case 6 command
CF(H)
AA(H)
A5(H)
*DUTY+1
*2
*DUTY+1 Clear
Display all ON
command
command
Internal Power Supply ON
(Waiting time)
*4,5
*3
Power Supply Startup End
command
ED(H)
*1. Regarding the SED1562, it is not neces-
sary to execute a command to decide an
output status.
After the waiting time shown in the graph
below,thepowersupplycanbestartedsurely.
*5. Within the waiting time in internal power
supply ON status, any command other than
internal power supply control commands
such as Power Save, and display ON/OFF
command, display normal rotation/reverse
command, display all ON command, output
status select command and DUTY + 1 clear
command can accept another command
without any problem. RAM read and write
operations can be freely performed.
*2. When the COMI pin is not used, it is not
necessary to enter the DUTY + 1 and DUTY
+ 1 Clear commands.
*3. When the built-in power supply startup
end command is not executed, current is
consumed stationarily. Internal power sup-
ply startup end command must always be
used in a pair with internal power supply
ON command.
*4. The waiting time depends on the externally-
installedcapacitanceC2(refertoTable5.9).
120
(mS)
100
V5 voltage conditions
80
Waiting
1/9 bias
1/9 bias V5 = –6.0 to –16.0 V
1/7 bias V5 = –5.0 to –12.0 V
1/5 bias V5 = –4.5 to –8.0 V
time
60
40
20
1/7 bias
1/5 bias
0
0.5
1.0
Capacitance C2
(µF)
66
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.3 Software Contrast Control Register
5.3 – 5.3.2
(a) The oscillator and power supply circuits are
stopped.
5.3 SOFTWARE CONTRAST CONTROL
REGISTER
(b) The LCD driver is stopped and segment and
commondriveroutputsoutputtheVDD level.
Through these commands, the liquid crystal driving
voltage V5 is output from the voltage regulation circuit
of the built-in liquid crystal power supply, in order to
adjust the contrast of the liquid crystal display.
(c) An input of an external clock is inhibited and
OSC2 enters the high-impedance state.
(d) The display data and operation mode be-
fore execution of the power save com-
mand are held.
By setting data to the 5-bit register, one of the 32
voltage statuses may be selected for the liquid crystal
driving voltage V5. External resistors are used for
setting the voltage regulation range of the V5. For
details refer to the paragraph of the voltage regulation
circuit in the clause for the explanation of functions.
(e) All LCD driver voltages are fixed to the
VDD level.
The power save mode is cancelled by entering either
the Display ON command or the Display All Points
OFFcommand(displayoperationstate). Whenexter-
nalvoltagedriverresistorsareusedtosupplytheLCD
driver voltage level, the current through them must be
cut off by the power save signal.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0
A4 A3 A2 A1 A0
A4 A3 A2 A1 A0
| V5 |
0
0
0
↓
1
0
0
Small (as the absolute value)
If an external power supply is used, it must be
turned OFF using the power save signal in the
same manner, and voltage levels must be fixed to
the floating or VDD level.
↓
1
1
1
1
Large (as the absolute value)
When not using the electronic contrast control func-
tion, set to (0, 0, 0, 0).
5.3.2 Connection between LCD Drivers
The LCD display area can be increased by using
the SED1560 Series in a multiple-chip configura-
tion or with the SED1560 Series special common
driver (SED1630).
5.3.1 Power Save (Complex Command)
If the Display All Points ON command is specified in
the display OFF state, the system enters the power
save status, reducing the power consumption to ap-
proximate the static power consumption value. The
internal state in the power save status is as follows:
VDD
FR
FR
M/S
SED156X
(Master)
SED1630
SYNC
DIO
YSCL
OSC1 OSC2 CL CLO DYO
Rf
VSS
Figure 5.3 Application with external driver: SED156X – SED1630
174-3.0
67
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.3.2
5.3 Electronic Contrast Control Register
VDD
SED156X
(Master)
SED156X
(Slave)
M/S
FR
FR
M/S
SYNC
SYNC
VSS
OSC1 OSC2 CL CLO DYO
OSC1 OSC2 CL CLO DYO
VSS
VSS
Rf
VDD
SED156X
(Master)
SED156X
(Slave)
M/S
FR
FR
M/S
SYNC
SYNC
OSC1 OSC2 CL CLO DYO
OSC1 OSC2 CL CLO DYO
VSS
VDD
VSS
Rf
Figure 5.4 SED156X – SED156X (when oscillator circuit is used)
VDD
SED156X
(Master)
SED156X
(Slave)
M/S
FR
FR
M/S
SYNC
SYNC
VSS
OSC1 OSC2 CL CLO DYO
VSS
OSC1 OSC2 CL CLO DYO
VSS
VDD
External clock
Figure 5.5 SED156X – SED156X (External clock)
68
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.4 Microprocessor Interface
5.4
5.4 MICROPROCESSOR INTERFACE
The SED1560 Series communicates with a high-
speed microprocessor, such as the Intel 80XX family
or the Motorola 68XX family, through 8-bit parallel
data transfer. The number of connections to the
microprocessor can be minimized by using a serial
interface. When used in a multiple-chip configuration,
the SED1560 Series is controlled by the chip select
signals from the microprocessor.
VCC
A0
VDD
A0
C86
A0 to A7
CS1
CS2
Decoder
MPU
SED156X
IORQ
D0 to D7
D0 to D7
RD
WR
RES
RD
WR
RES
P/S
GND
VSS
RESET
Figure 5.6 8080-series microprocessors
VCC
VDD
A0
A0
C86
A0 to A15
CS1
CS2
Decoder
MPU
SED156X
VMA
D0 to D7
D0 to D7
E
R/W
RES
E
R/W
RES
P/S
GND
VSS
RESET
Figure 5.7 6800-series microprocessors
174-3.0
69
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.4 – 5.5
5.4 Microprocessor Interface
VCC
VDD
A0
A0
C86
A0 to A7
CS1
CS2
Decoder
VDD
or
MPU
SED156X
GND
PORT1
PORT2
SI
SCL
P/S
RES
RES
GND
VSS
RESET
Figure 5.8 Serial interface
5.5 LCD PANEL INTERFACE EXAMPLES
65 × 102
Segments
SED1560
Commons
(Master)
Case 1
33 × 134
17 × 150
Segments
SED1562
Segments
SED1561
Commons
Commons
(Master)
Case 4
Figure 5.9 Single-chip configurations
70
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.5 LCD Panel Interface Examples
5.5
65 × 268
Segments
SED1560
Segments
SED1560
Commons
(Master)
(Slave)
Case 1
Case 6
33 × 300
Segments
Segments
SED1561
SED1561
(Master)
Commons
(Slave)
Case 4
Case 6
Figure 5.10 Multiple-chip combinations
174-3.0
71
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
5.6
5.6 Special Common Driver Configurations
5.6 SPECIAL COMMON DRIVER CONFIGURATIONS
Commons
SED1630
65 × 166
Segments
SED1560
(Master)
Case 6
Case 6
SED1560
(Master)
Segments
Commons
SED1631
128 × 166
Commons
Segments
SED1560
(Slave)
Case 6
Figure 5.11 Special common driver configurations
72
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.0
Packaging
174-3.0
73
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
THIS PAGE INTENTIONALLY BLANK
74
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.0 Pad Layout
6.1
6.1 PAD LAYOUT
O46
V5
V4
V3
V2
V1
V
V
DD
R
V5
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
SED156X
D6
D5
D4
D3
D2
D1
D0
V
SS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
V
DD
V1
V2
V3
V4
V5
O120
Chip Size
Pad Pitch
: 8.08 × 5.28 mm
: 100 µm (min)
Chip thickness : 625 µm ± 25 µm
Figure 6.1 Pad layout
174-3.0
75
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.1
6.0 Pad Layout
Table 6.1 SED1560 Series Pad Center Coordinates
Pad
No. Name
Pin
Pad
No. Name
Pin
Pad
No. Name
Pin
Pad
No. Name
Pin
X
Y
X
Y
X
Y
X
Y
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
O59 –2411 –2487
O60 –2311 –2487
O61 –2211 –2487
O62 –2111 –2487
O63 –2011 –2487
O64 –1911 –2487
O65 –1811 –2487
O66 –1711 –2487
O67 –1611 –2487
O68 –1511 –2487
O69 –1411 –2487
O70 –1311 –2487
O71 –1211 –2487
O72 –1111 –2487
O73 –1011 –2487
163 O113 2989 –2487
164 O114 3089 –2487
165 O115 3189 –2487
166 O116 3289 –2487
167 O117 3389 –2487
168 O118 3489 –2487
169 O119 3589 –2487
170 O120 3689 –2487
171 O121 3887 –2206
172 O122 3887 –2106
173 O123 3887 –2006
174 O124 3887 –1906
175 O125 3887 –1806
176 O126 3887 –1706
177 O127 3887 –1606
178 O128 3887 –1506
179 O129 3887 –1406
180 O130 3887 –1306
181 O131 3887 –1206
182 O132 3887 –1106
183 O133 3887 –1006
184 O134 3887 –906
185 O135 3887 –806
186 O136 3887 –706
187 O137 3887 –606
188 O138 3887 –506
189 O139 3887 –406
190 O140 3887 –306
191 O141 3887 –206
192 O142 3887 –106
1
2
3
4
5
6
7
8
V5
V4
V3
V2
V1
VDD
M/S
RES
SCL
SI
P/S
CS1
CS2
C86
A0
WR
RD
VSS
D0
D1
D2
D3
D4
D5
D6
3640 2487
3489 2487
3339 2487
3188 2487
3037 2487
2889 2487
2755 2487
2604 2487
2453 2487
2302 2487
2151 2487
2001 2487
1850 2487
1699 2487
1548 2487
1397 2487
1247 2487
1077 2487
945 2487
794 2487
643 2487
493 2487
342 2487
191 2487
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
O5
O6
O7
O8
O9
–3887 1794
–3887 1694
–3887 1594
–3887 1494
–3887 1394
O10 –3887 1294
O11 –3887 1194
O12 –3887 1094
O13 –3887 994
O14 –3887 894
O15 –3887 794
O16 –3887 694
O17 –3887 594
O18 –3887 494
O19 –3887 394
O20 –3887 294
O21 –3887 194
O22 –3887 94
O23 –3887 –6
O24 –3887 –106
O25 –3887 –206
O26 –3887 –306
O27 –3887 –406
O28 –3887 –506
O29 –3887 –606
O30 –3887 –706
O31 –3887 –806
O32 –3887 –906
O33 –3887 –1006
O34 –3887 –1106
O35 –3887 –1206
O36 –3887 –1306
O37 –3887 –1406
O38 –3887 –1506
O39 –3887 –1606
O40 –3887 –1706
O41 –3887 –1806
O42 –3887 –1906
O43 –3887 –2006
O44 –3887 –2106
O45 –3887 –2206
O46 –3711 –2487
O47 –3611 –2487
O48 –3511 –2487
O49 –3411 –2487
O50 –3311 –2487
O51 –3211 –2487
O52 –3111 –2487
O53 –3011 –2487
O54 –2911 –2487
O55 –2811 –2487
O56 –2711 –2487
O57 –2611 –2487
O58 –2511 –2487
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
O74
O75
O76
O77
O78
O79
O80
O81
O82
O83
O84
O85
O86
O87
O88
O89
O90
O91
O92
O93
O94
O95
O96
O97
O98
O99
–911 –2487
–811 –2487
–711 –2487
–611 –2487
–511 –2487
–411 –2487
–311 –2487
–211 –2487
–111 –2487
–11 –2487
89 –2487
189 –2487
289 –2487
389 –2487
489 –2487
589 –2487
689 –2487
789 –2487
889 –2487
989 –2487
1089 –2487
1189 –2487
1289 –2487
1389 –2487
1489 –2487
1589 –2487
40
2487
D7
DYO
CLO
–111 2487
–261 2487
–412 2487
29 SYNC –563 2487
30
31
32 OSC2 –1015 2487
33 OSC1 –1166 2487
34
35
36
37 CAP1+ –1789 2487
38 CAP1– –1939 2487
39 CAP2+ –2090 2487
40 CAP2– –2241 2487
41
42
43
44
45
46
47
48
49
50
51
52
53
54
FR
CL
–714 2487
–865 2487
193 O143 3887
194 O144 3887
–6
94
195 O145 3887 194
196 O146 3887 294
197 O147 3887 394
198 O148 3887 494
199 O149 3887 594
200 O150 3887 694
201 O151 3887 794
202 O152 3887 894
203 O153 3887 994
204 O154 3887 1094
205 O155 3887 1194
206 O156 3887 1294
207 O157 3887 1394
208 O158 3887 1494
209 O159 3887 1594
210 O160 3887 1694
211 O161 3887 1794
212 O162 3887 1894
213 O163 3887 1994
214 O164 3887 2094
215 O165 3887 2194
216 COMI 3887 2294
T2
T1
VSS
–1317 2487
–1468 2487
–1638 2487
VOUT
V5*
VR
VDD
V1
V2
V3
V4
V5
O0
O1
O2
O3
O4
–2392 2487
–2543 2487
–2674 2487
–2844 2487
–2995 2487
–3146 2487
–3297 2487
–3447 2487
–3598 2487
–3887 2294
–3887 2194
–3887 2094
–3887 1994
–3887 1894
150 O100 1689 –2487
151 O101 1789 –2487
152 O102 1889 –2487
153 O103 1989 –2487
154 O104 2089 –2487
155 O105 2189 –2487
156 O106 2289 –2487
157 O107 2389 –2487
158 O108 2489 –2487
159 O109 2589 –2487
160 O110 2689 –2487
161 O111 2789 –2487
162 O112 2889 –2487
* One V5 output is used for the LCD driver supply voltage; the other is used for the electronic volume control.
76
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.2 SED1560 Series TAB Pin Layout
6.2
6.2 SED1560/1/2 TAB PIN LAYOUT
This drawing is not for specifying the TAB outline shape.
O0
V5
V4
V3
V2
V1
V
V
DD
R
V5
V
OUT
CAP2–
CAP2+
CAP1–
CAP1+
V
SS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
SED156X
TOP
VIEW
D4
D3
D2
D1
D0
V
SS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
V
DD
V1
V2
V3
V4
V5
O165
COMI
Figure 6.2 SED1560 Series TAB pin layout
174-3.0
77
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.3
6.3 TCP Dimensions (2-sided)
6.3 TCP DIMENSIONS (2-SIDED) SED156XT0B
NC x 2
00
8.8
NC
V5
V4
V3
V2
V1
1.5
V
DD
R
V
V5
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
D4
D3
D2
D1
D0
VSS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
VDD
V1
V2
V3
V4
V5
NC
4.40
NC x 2
COM1
0165
0.5
5.34
15.16
28.98 ± 0.04
2.70
Figure 6.3 TCP dimensions (2-sided)
78
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.4 TCP Dimensions (4-sided)
6.4
6.4 TCP DIMENSIONS (4-SIDED) SED156XT0A
0.30
D1560
0.60
D1560
25.95
31.82
34.9750
Figure 6.4 TCP dimensions (4-sided)
174-3.0
79
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.5
6.5 TCP Dimensions (D1561TOC)
6.5 TCP DIMENSIONS (SED1561TOC)
0.01
28.98±
0.07
8.50 (SR)
10.23 (SR)
6.66 (SR)
5.34
2.54
(SR)
2.39
(SR)
NCX2
COM1
0165
4.40
•
•
•
NC
V5
V4
V3
V2
V1
VDD
M/S
RES
SCL
SI
P/S
CS1
CS2
C86
A0
WR
RD
VSS
D0
D1
D2
D3
5.28 (IC)
D4
D5
D6
D7
DYO
CLO
SYNC
FR
MAX 8.28
1.98±0.01
CL
OSC2
OSC1
T2
T1
VSS
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
V5
VR
VDD
V1
1.5
V2
V3
V4
V5
NC
•
•
•
00
NCX2
MAX 1.50
MAX 1.50
MAX 1.50
MAX 1.50
Figure 6.5 TCP dimensions (D1561TOC)
80
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.6 Pad Profile
6.6
6.6 PAD PROFILE
TBD
174-3.0
81
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.7
6.7 BGA Package Dimensions
6.7 BGA PACKAGE DIMENSIONS
D
D1
15
14
13
12
11
10
9
SED1560BOA
8
7
6
5
4
INDEX
3
4–C2
2
1
4–C1
Q P N M L K J H G F E D C B A
Ø2
A2
A1
A
e
øb
Figure 6.7 Plastic BGA 225pin
Table 6.2 BGA 225pin package dimensions
Dimension in Millimeters
Symbol
Dimension in inches*
Nom.
Min.
0.6
Nom.
0.75
2.13
0.6
1.53
25°
1.5
1.2
1.5
24
Max.
0.90
Min.
Max.
øb
(0.024)
(0.030)
(0.084)
(0.024)
(0.060)
(25°)
(0.035)
A
A1
0.5
0.7
(0.020)
(0.057)
(0.027)
(0.064)
A2
1.43
1.63
θ2
C1
(0.059)
(0.047)
(0.059)
(0.945)
(0.945)
(1.063)
(1.063)
C2
e
D1
23.9
23.9
24.1
24.1
(0.941)
(0.941)
(0.948)
(0.948)
E1
24
D
E
27
27
* for reference
82
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.8 BGA Pin Assignment
6.8
6.8 BGA PIN ASSIGNMENT
SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 N/C
pad# pin name
pin#
B-2
D-4
B-1
C-2
F-6
D-3
C-1
D-2
G-6
E-4
D-1
E-3
E-2
F-5
E-1
F-4
F-3
F-2
F-1
G-4
G-3
G-2
G-1
G-5
H-3
H-1
H-2
H-4
J-5
pad# pin name
pin#
R-2
P-3
K-6
N-4
R-3
P-4
K-7
M-5
R-4
N-5
P-5
L-6
R-5
M-6
N-6
P-6
R-6
M-7
N-7
P-7
R-7
L-7
M-8
P-8
R-8
N-8
L-9
pad# pin name
pin#
K-10
M-13
N-15
M-14
J-10
L-12
M-15
L-13
L-14
K-11
L-15
K-12
K-13
K-14
K-15
J-12
J-13
J-14
J-15
J-11
L-8
pad# pin name
pin#
D-12
B-14
A-15
C-13
A-14
B-13
E-11
C-12
A-13
B-12
F-9
D-11
A-12
C-11
B-11
E-10
A-11
D-10
C-10
B-10
A-10
D-9
C-9
B-9
A-9
E-9
D-8
B-8
A-8
C-8
E-7
A-7
B-7
C-7
D-7
A-6
B-6
C-6
D-6
A-5
E-6
B-5
C-5
A-4
D-5
F-7
B-4
A-3
C-4
E-5
B-3
A-2
C-3
A-1
1
2
V5
V4
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
05
06
07
08
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
COMI
J-7
H-7
G-7
J-8
H-8
G-8
J-9
3
V3
4
V2
5
V1
09
6
7
8
9
VDD
M/S
/RES
SCL
SI
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
H-9
G-9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
P/S
/CS1
CS2
C86
A0
/WR
/RD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
DYO
CLO
SYNC
FR
K-8
H-10
H-11
H-6
H-5
F-8
R-9
P-9
N-9
E-8
H-12
H-14
H-15
H-13
G-11
G-15
G-14
G-13
G-12
F-15
F-14
F-13
F-12
E-15
F-11
E-14
E-13
D-15
E-12
G-10
D-14
C-15
D-13
F-10
C-14
B-15
J-1
J-2
J-3
J-4
CL
M-9
R-10
P-10
N-10
M-10
R-11
L-10
P-11
N-11
R-12
M-11
K-9
P-12
R-13
N-12
L-11
P-13
R-14
N-13
R-15
P-14
M-12
P-15
N-14
OSC2
OSC1
T2
K-1
K-2
K-3
K-4
L-1
K-5
L-2
L-3
M-1
L-4
J-6
M-2
N-1
M-3
L-5
N-2
P-1
N-3
R-1
P-2
M-4
T1
VSS
CAP1+
CAP1−
CAP2+
CAP2−
VOUT
V5
VR
VDD
V1
V2
V3
V4
V5
00
01
02
03
04
174-3.0
83
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
6.9
6.9 SED1560TQA OL Dimensions
6.9 SED1560TQA OL DIMENSIONS
100% Sn
110 +/– 15uM
[90(+10,–20uM)]
190uM
0.5 +/–0.1uM
25 +/–1uM
CU
CU
Adhesive
300uM
Polymide Film
Figure 6.8 SED1560TQA OL Dimensions
S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the
information herein and (2) the use of the information or a portion thereof in any application,
including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The
information herein is subject to change without notice from S-MOS.
October 1996
© Copyright 1996 S-MOS Systems, Inc.
Printed in U.S.A.
174-3.0
84
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明