SEU02G72D4BH2MT-30R [ETC]
2GB ECC DDR2 â SDRAM DIMM;
| 型号： | SEU02G72D4BH2MT-30R |
| 厂家： | 
ETC |
| 描述： | 2GB ECC DDR2 â SDRAM DIMM 动态存储器 双倍数据速率 |
| 文件： | 总16页 (文件大小：664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Rev.1.2
03.01.2013
2GB ECC DDR2 – SDRAM DIMM
Features:
.
240-pin 72-bit Dual-In-Line Double Data Rate
synchronous DRAM Module with ECC support
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
240 Pin ECC UDIMM
SEU02G72D4BH2MT-XXR
2GByte in FBGA Technology
RoHS compliant
.
.
.
.
.
.
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Gold-contact pad
Options:
This module is fully pin and functional compatible to
the JEDEC PC2-5300 spec. and JEDEC- Standard
MO-237. (see www.jedec.org)
.
Data Rate / Latency
DDR2 667 MT/s CL5
DDR2 533 MT/s CL4
Marking
-30
.
The pcb and all components are manufactured
-37
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
.
Module Density
2048MB with 18 dies and 2 ranks
.
DDR2 - SDRAM component Micron
MT47H128M8CF-25 DIE-Rev.H
.
Standard Grade
(TA)
(TC)
0°C to 70°C
0°C to 85°C
.
.
.
.
.
.
.
.
.
.
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent operation
Programmable CAS latency (CL)
*) The refresh rate has to be doubled when 85°C<TC<95°C
Posted CAS additive latency (AL)
Environmental Requirements:
WRITE latency = READ latency – 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
.
Operating temperature (AMBIENT)
Standard Grade
Grade W
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
0°C to 70°C
-40°C to 95°C
.
.
.
.
.
Figure: mechanical dimensions1
1682 PSI (up to 5000 ft.) at 50°C
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 16
Data Sheet
Rev.1.2
03.01.2013
This Swissbit module is an industry standard 240-pin 8-byte DDR2 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
EEPROM using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
are utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Row
Addr.
Device Bank Column
Module
Bank Select
Organization
DDR2 SDRAMs used
Refresh
Addr.
Addr.
256M x 72bit
18 x 128M x 8bit (1024Mbit)
14
BA0, BA1, BA2
10
8k
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 28(high) x 4 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SEU02G72D4BH2MT-30R
SEU02G72D4BH2MT-37R
2048 MB
2048 MB
5.3 GB/s
4.2 GB/s
3.0ns/667MT/s
3.75ns/533MT/s
5300-555
4200-444
Pin Name
A0-9, A11 – A13
A10/AP
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
BA0 – BA2
DQ0 – DQ63
CB0 – CB7
DM0-DM8
DQS0 – DQS8
DQS0# - DQS8#
RAS#
ECC check bits
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
CAS#
WE#
CKE0 – CKE1
S0#, S1#
Clock Enable
Chip Select
CK0 – CK1
CK0# – CK1#
Clock Inputs, positive line
Clock Inputs, negative line
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 16
Data Sheet
Rev.1.2
03.01.2013
VDD
SDRAM core power supply (1.8V± 0.1V)
SDRAM I/O Driver power supply (1.8V± 0.1V)
Input / Output Reference
VDDQ
VREF
VSS
Ground
VDDSPD
SCL
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
SDA
SA0 – SA2
ODT0, ODT1
NC
No Connection
Pin Configuration
PIN #
1
Front Side
PIN #
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Back Side
VSS
PIN #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front Side
A4
PIN #
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
Back Side
VREF
VSS
VDDQ
A3
2
DQ4
VDDQ
A2
3
DQ0
DQ5
A1
4
DQ1
VSS
VDD
VDD
5
VSS
DM0 (DQS9)
NC (DQS9#)
VSS
VSS
CK0
6
DQS0#
DQS0
VSS
VSS
CK0#
VDD
7
VDD
8
DQ6
NC (Par_In)
VDD
A0
9
DQ2
DQ7
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DQ3
VSS
A10/AP
BA0
BA1
VSS
DQ12
VDDQ
DQ8
DQ13
VDDQ
WE#
CAS#
VDDQ
S1#
RAS#
S0#
DQ9
VSS
VSS
DM1 (DQS10)
NC (DQS10#)
VSS
VDDQ
DQS1#
DQS1
VSS
ODT0
A13
CK1
ODT1
VDDQ
VSS
VDD
NC (RESET)
NC
CK1#
VSS
VSS
DQ36
DQ37
VSS
VSS
DQ14
DQ32
DQ33
VSS
DQ10
DQ11
VSS
DQ15
VSS
DM4 (DQS13)
NC (DQS13#)
VSS
DQ20
DQS4#
DQS4
VSS
DQ16
DQ17
VSS
DQ21
VSS
DQ38
DQ39
VSS
DM2 (DQS11)
NC (DQS11#)
VSS
DQ34
DQ35
VSS
DQS2#
DQS2
VSS
DQ44
DQ45
VSS
DQ22
DQ40
DQ41
VSS
DQ18
DQ19
VSS
DQ23
VSS
DM5 (DQS15)
NC (DQS15#)
DQ28
DQS5#
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 16
Data Sheet
Rev.1.2
03.01.2013
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front Side
DQ24
DQ25
VSS
PIN #
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back Side
PIN #
93
Front Side
DQS5
VSS
PIN #
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back Side
DQ29
VSS
VSS
DQ46
94
DM3 (DQS12)
NC (DQS12#)
VSS
95
DQ42
DQ43
VSS
DQ47
DQS3#
DQS3
VSS
96
VSS
97
DQ52
DQ30
DQ31
VSS
98
DQ48
DQ49
VSS
DQ53
DQ26
DQ27
VSS
99
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
NC (CK2)
NC (CK2#)
VSS
CB4
SA2
CB0
CB5
NC (TEST)
VSS
CB1
VSS
DM6 (DQS15)
NC (DQS15#)
VSS
VSS
DM8 (DQS17)
NC (DQS17#)
VSS
DQS6#
DQS6
VSS
DQS8#
DQS8
VSS
DQ54
CB6
DQ50
DQ51
VSS
DQ55
CB2
CB7
VSS
CB3
VSS
DQ60
VSS
VDDQ
DQ56
DQ57
VSS
DQ61
VDDQ
CKE0
VDD
CKE1
VDD
VSS
DM7 (DQS16)
NC (DQS16#)
VSS
NC (A15)
NC (A14)
VDDQ
DQS7#
DQS7
VSS
BA2
NC (Par_Out)
VDDQ
A11
DQ62
A12
DQ58
DQ59
VSS
DQ63
A9
VSS
A7
VDD
VDDSPD
SA0
VDD
A8
SDA
A5
A6
SCL
SA1
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 16
Data Sheet
Rev.1.2
03.01.2013
FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR2 SDRAM ECC DIMM,
2 RANKS AND 18 COMPONENTS
CKE1
ODT1
S1
CKE0
ODT0
S0
CS ODT CKE
CS ODT CKE
CS ODT CKE
CS ODT CKE
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
D0
D9
D4
D13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 0
I/O 1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
CS ODT CKE
CS ODT CKE
CS ODT CKE
DQS1
DQS5
DQS5
DM5
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS1
DM1
D1
D10
D5
D14
DQ8
I/O 0
I/O 1
I/O 0
I/O 1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 0
I/O 1
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
CS ODT CKE
CS ODT CKE
CS ODT CKE
DQS2
DQS
DQS
DM
DQS
DQS
DM
DQS6
DQS
DQS
DM
DQS
DQS
DM
DQS2
DM2
DQS6
DM6
D2
D11
D6
D15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 0
I/O 1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
CS ODT CKE
CS ODT CKE
CS ODT CKE
DQS3
DQS7
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS3
DM3
DQS7
DM7
D3
D12
D7
D16
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 0
I/O 1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS ODT CKE
CS ODT CKE
DQS8
DQS
DQS
DM
DQS
DQS
DM
DQS8
DM8
D8
D17
VDDSPD
VREF
SPD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 0
I/O 1
D0-D17
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
VDD / VDDQ
D0-D17
VSS
D0-D17/SPD
SCL
SDA
Serial PD
BA0-BA2
A0-A13
BA0-BA2: SDRAM D0-D17
A0-A13: SDRAM D0-D17
SA0
SA1
SA2
RAS
CAS
WE
RAS: SDRAM D0-D17
CAS: SDRAM D0-D17
WE: SDRAM D0-D17
WP
SA2
SA0
SA1
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 16
Data Sheet
Rev.1.2
03.01.2013
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
SYMBOL
VDD
VDDQ
VDDL
VIN, VOUT
MIN
-1.0
-0.5
-0.5
-0.5
MAX
UNITS
2.3
2.3
2.3
2.3
V
V
V
V
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
II
µA
Command/Address
RAS#, CAS#, WE#, S#, CKE
-40
40
CK, CK#
DM
-20
-5
20
5
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
µA
)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
-16
16
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
VDD
MIN
1.7
1.7
NOM
1.8
1.8
MAX
1.9
1.9
UNITS
V
V
V
VDDQ
VDDL
VDDL Supply Voltage
1.7
1.8
1.9
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF
VTT
VIH (DC)
VIL (DC)
0.49 x VDDQ
VREF – 0.04
VREF + 0.125
-0.3
0.50 x VDDQ
VREF
0.51x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.125
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
MIN
VREF + 0.25
-
MAX
-
VREF - 0.25
UNITS
V
V
VIL (AC)
CAPACITANCE
At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 6
of 16
Data Sheet
Rev.1.2
03.01.2013
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
Parameter
max
5300-5-5-5 4200-4-4-4
Symbol
Unit
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
IDD0
mA
873
783
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
IDD1
mA
963
918
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address inputs changing once every two clock
cycles; Data Pattern is same as IDD4W
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and Address bus
inputs are not changing; DQ’s are floating at VREF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
IDD2P
mA
mA
126
990
126
738
IDD2Q
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing; DQ’s
are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once per
clock cycle
IDD2N
IDD3P
IDD3N
mA
mA
mA
1080
810
ACTIVE POWER-DOWN
CURRENT:
Fast PDN Exit
MR[12] = 0
810
324
720
324
All device banks open; tCK = tCK
(IDD); CKE is LOW; All Control and
Address bus inputs are not
Slow PDN Exit
MR[12] = 1
changing; DQ’s are floating at VREF
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
1260
1080
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once per
clock cycle
OPERATING READ CURRENT:
IDD4R
mA
1503
1368
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address
bus inputs are changing once every two clock cycles; DQ
inputs changing once per clock cycle
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 7
of 16
Data Sheet
Rev.1.2
03.01.2013
Parameter
max
5300-5-5-5 4200-4-4-4
Symbol
Unit
& Test Condition
OPERATING WRITE CURRENT:
IDD4W
mA
1503
1323
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
IDD5
mA
4860
4500
tCK = tCK (IDD); refresh command at every tRFC (IDD) interval,
CKE is HIGH, CS# is HIGH between valid commands; All
other Control and Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per clock
cycle
SELF REFRESH CURRENT:
IDD6
mA
mA
126
126
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are floating at
VREF
OPERATING CURRENT*) :
Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL
IDD7
2763
2673
= CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC
tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
=
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during DESELECT;
DQ inputs changing once per clock cycle
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE
LOW) mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
CL (IDD
tRCD (IDD
tRC (IDD
tRRD (IDD
tCK (IDD
tRAS MIN (IDD
tRAS MAX (IDD
tRP (IDD
tRFC (IDD
5300-5-5-5
4200-4-4-4
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
)
5
15
60
7.5
3.0
45
70’000
15
4
15
60
7.5
3.75
45
70’000
15
127.5
)
)
)
)
)
)
)
)
127.5
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Page 8
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Data Sheet
Rev.1.2
03.01.2013
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
5300-5-5-5
4200-4-4-4
MIN MAX
Unit
SYMBOL
tCK (5)
tCK (4)
tCK (3)
tCH
MIN
MAX
8.0
8.0
Clock cycle time
CL = 5
3.0
3.75
5.0
-
-
ns
ns
ns
tCK
tCK
CL = 4
CL = 3
3.75
5.0
8.0
8.0
8.0
CK high-level width
CK low-level width
Half clock period
0.48
0.48
min
0.52
0.52
0.48
0.48
min
0.52
0.52
tCL
tHP
-
-
ps
ns
ns
ns
(tCH, tCL)
(tCH, tCL)
Access window (output) of DQS
from CK/CK#
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
tAC
tHZ
tLZ
-0.45
+0.45
-0.50
+0.50
+0.45
(= tAC max)
+0.50
(= tAC max)
-
-
-0.45
+0.45
-0.50
+0.50
(= tAC min) (= tAC max) (= tAC min) (= tAC max)
DQ and DM input setup time
relative to DQS
tDSa
0.30
0.30
0.10
-
-
-
-
0.35
0.35
0.10
-
-
-
-
ns
ns
ns
ns
DQ and DM input hold time
relative to DQS
DQ and DM input setup time
relative to DQS
tDHa
tDSb
DQ and DM input hold time
relative to DQS
DQ and DM input pulse width
( for each input )
tDHb
0.175
0.35
0.225
0.35
tDIPW
-
0.34
-
-
0.4
-
tCK
ns
ns
Data hold skew factor
tQHS
tQH
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
Data valid output window
tHP - tQHS
tHP - tQHS
tQH
-
tQH -
tDVW
-
-
ns
tDQSQ
0.35
0.35
tDQSQ
0.35
0.35
DQS input high pulse width
DQS input low pulse width
-
-
-
-
tCK
tCK
tDQSH
tDQSL
DQS output access time from
CK/CK#
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS –DQ skew, DQS to last
DQ valid, per group, per access
DQS read preamble
tDQSCK
-0.40
0.2
0.2
-
+0.40
-0.45
0.2
0.2
-
+0.45
ns
tCK
tCK
ns
tDSS
-
-
-
-
tDSH
tDQSQ
0.24
0.30
0.9
0.4
0.35
0
1.1
0.6
-
0.9
0.4
0.25
0
1.1
0.6
-
tCK
tCK
tCK
ns
tRPRE
tRPST
tWPRE
tWPRES
tWPST
tDQSS
DQS read postamble
DQS write preamble
DQS write preamble setup time
DQS write postamble
Positive DQS latching edge to
associated clock edge
Write command to first DQS
latching transition
-
-
0.4
0.6
0.4
0.6
tCK
- 0.25
+ 0.25
- 0.25
+ 0.25 tCK
WL-
tDQSS
WL+
tDQSS
WL-
tDQSS
WL+
tCK
tDQSS
Address and control input pulse
width ( for each input )
Address and control input setup
time
tIPW
tISa
0.6
0.4
-
-
0.6
0.5
-
-
tCK
ns
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Page 9
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Data Sheet
Rev.1.2
03.01.2013
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
5300-5-5-5
4200-4-4-4
MIN MAX Unit
SYMBOL MIN
MAX
Address and control input hold
time
Address and control input setup
time
Address and control input hold
time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same
bank) command period
ACTIVE bank a to ACTIVE
bank b command
ACTIVE to READ or WRITE
delay
Four bank Activate period
ACTIVE to PRECHARGE
command
tIHa
tISb
tIHb
0.4
-
0.5
-
-
ns
ns
0.20
-
0.25
0.275
2
-
-
-
0.375
2
-
-
-
ns
tCK
ns
tCCD
tRC
55
55
tRRD
tRCD
7.5
-
7.5
-
ns
-
15
37.5
45
15
37.5
45
-
-
ns
ns
-
tFAW
tRAS
70’000
70’000 ns
Internal READ to precharge
command delay
Write recovery time
Auto precharge write recovery
+ precharge time
tRTP
7.5
15
-
-
-
7.5
15
tWR +
tRP
-
-
-
ns
ns
ns
tWR
tDAL
tWR
+
tRP
Internal WRITE to READ
command delay
PRECHARGE command period
PRECHARGE ALL command
period
tWTR
7.5
-
-
-
7.5
-
-
-
ns
ns
ns
15
15
tRP
tRPA
tRP + tCK
tRP + tCK
LOAD MODE command cycle
time
CKE low to CK, CK# uncertainty
REFRESH to ACTIVE or
REFRESH to REFRESH
command interval
tMRD
2
-
2
-
tCK
tCK
tIS + tCK + tIH
tIS + tCK + tIH
tDELAY
tRFC
127.5
70’000
127.5
70’000 ns
Average periodic refresh
interval
-
-
7.8
-
-
7.8
µs
tREFI
(0°C<= T
<= 85 °C)
CASE
3.9
-
3.9
-
µs
ns
(85°C<= T
<= 95 °C)
tREFI (IT)
CASE
Exit SELF REFRESH to non-
READ command
Exit SELF REFRESH to READ
command
Exit SELF REFRESH timing
reference
ODT turn-on delay
tRFC(min)
+ 10
tRFC(min)
+ 10
tXSNR
tXSRD
tISXR
tAOND
200
tIS
-
-
200
tIS
-
-
tCK
ps
tCK
ps
tCK
ps
2
2
2
2
tAC(max)
+ 1,000
tAC(max)
+ 1,000
tAON
tAC(min)
2.5
tAC(min)
2.5
ODT turn-on
ODT turn-off delay
ODT turn-off
2.5
tAC(max)
+ 600
2.5
tAC(max)
+ 600
tAOFD
tAOF
tAC(min)
tAC(min)
2 x tCK
tAC(max)
+ 1,000
+
2 x tCK +
tAC(max)
+ 1,000
tAONPD
tAC(min)
+ 2,000
tAC(min)
+ 2,000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
ps
ps
2.5 x tCK
+tAC(max)
+ 1,000
2.5 x tCK
tAC(max)
+ 1,000
+
tAOFPD
tAC(min)
+ 2,000
tAC(min)
+ 2,000
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Page 10
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Data Sheet
Rev.1.2
03.01.2013
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
ODT to power-down entry latency
ODT power-down exit latency
ODT enable from MRS
command
5300-5-5-5
MIN MAX
4200-4-4-4
MIN MAX Unit
SYMBOL
tANPD
tAXPD
3
-
3
-
-
tCK
tCK
ns
8
-
8
TMOD
12
-
12
-
Exit active power-down to
READ command, MR [bit 12 =
0]
Exit active power-down to
READ command, MR [bit 12 =
1]
tCK
tXARD
2
-
-
2
-
tCK
tXARDS
7 – AL
6 – AL
-
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
tCK
tCK
tXP
2
3
-
-
2
3
-
-
tCKE
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Page 11
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Data Sheet
SERIAL PRESENCE-DETECT MATRIX
Rev.1.2
03.01.2013
BYTE
DESCRIPTION
NUMBER OF SPD BYTES USED
5300-5-5-5
4200-4-4-4
0
1
2
3
4
5
6
7
8
0x80
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
0x08
0x08
0x0e
0x0a
0x61
0x48
0x00
0x05
NUMBER OF ROW ADDRESSES ON ASSEMBLY
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
DIMM HIGHT AND MODULE RANKS
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS (VDDQ
)
SDRAM CYCLE TIME, (tCK ) [max CL]
CAS LATENCY = 5 (5300), CL = 4 (4200)
9
0x30
0x45
0x3d
0x50
SDRAM ACCESS FROM CLOCK, (tAC) [max CL]
CAS LATENCY = 5 (5300); CL = 4 (4200)
10
11
12
13
14
MODULE CONFIGURATION TYPE
REFRESH RATE / TYPE
0x02
0x82
0x08
0x08
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK-TO-BACK
RANDOM COLUMN ACCESS
15
0x00
16
17
18
19
20
21
22
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
MODULE THICKNESS
0x0c
0x08
0x38
0x18
0x01
0x02
0x00
DDR2 DIMM TYPE
SDRAM MODULE ATTRIBUTES
0x03
0x3d
0x01
0x50
SDRAM DEVICE ATTRIBUTES: Weak Driver and 50 ODT
SDRAM CYCLE TIME, (tCK) [max CL – 1]
CAS LATENCY = 4 (5300), CL = 3 (4200)
23
24
25
26
SDRAM ACCESS FROM CK, (tAC) [max CL – 1]
CAS LATENCY = 4 (5300), CL = 3 (4200)
0x45
0x50
0x45
0x50
0x00
0x00
SDRAM CYCLE TIME, (tCK) [max CL – 2]
CAS LATENCY = 3 (5300)
SDRAM ACCESS FROM CK, (tAC) [max CL – 2]
CAS LATENCY = 3 (5300)
27
28
29
30
31
MINIMUM ROW PRECHARGE TIME, (tRP
MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD
MINIMUM RAS# TO CAS# DELAY, (tRCD
)
0x3c
0x1e
0x3c
0x2d
0x01
)
)
MINIMUM RAS# PULSE WIDTH, (tRAS
)
MODULE BANK DENSITY
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Page 12
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Data Sheet
Rev.1.2
03.01.2013
SERIAL PRESENCE-DTECT MATRIX (continued)
BYTE
32
DESCRIPTION
ADDRESS AND COMMAND SETUP TIME, (tISb
5300-5-5-5
4200-4-4-4
0x25
)
0x20
0x27
33
ADDRESS AND COMMAND HOLD TIME, (tIHb
)
0x37
34
DATA / DATA MASK INPUT SETUP TIME, (tDSb
)
0x10
35
DATA / DATA MASK INPUT HOLD TIME, (tDHb
WRITE RECOVERY TIME, (tWR
WRITE to READ Command Delay, (tWTR
)
0x17
0x22
36
)
0x3c
0x1e
0x1e
0x00
0x06
0x3c
37
)
38
READ to PRECHARGE Command Delay, (tRTP
Mem Analysis Probe
)
39
40
Extension for Bytes 41 and 42
41
MIN ACTIVE AUTO REFRESH TIME, (tRC)
MINIMUM AUTO REFRESH TO ACTIVE /
AUTO REFRESH COMMAND PERIOD, (tRFC)
42
0x7f
43
44
45
46
SDRAM DEVICE MAX CYCLE TIME, (tCKMAX
)
0x80
SDRAM DEVICE MAX DQS-DQ SKEW TIME, (tDQSQ
)
0x18
0x22
0x1e
0x28
SDRAM DEVICE MAX READ DATA HOLD SKEW FACTOR, (tQHS
)
PLL Relock Time
0x00
0x00
0x13
47-61 Optional Features, not supported
62
63
SPD REVISION
CHECKSUM FOR BYTES 0-62
0x00
0xab
64-66 MANUFACTURER`S JEDEC ID CODE
67 MANUFACTURER`S JEDEC ID CODE (continued)
68-71 MANUFACTURER`S JEDEC ID CODE (continued)
72 MANUFACTURING LOCATION
73-90 MODULE PART NUMBER (ASCII)
0x7f
0xda
0x00
1 Switzerland | 2 Germany | 3 USA
“SEU02G72D4BH2MT-xx”
91
92
93
94
PCB IDENTIFICATION CODE
X
X
IDENTIFICATION CODE (continued)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
X
X
95-98 MODULE SERIAL NUMBER
99-127 MANUFACTURER-SPECIFIC DATA (RSVD)
128-255 Open for customer use
X
0x00
0xff
Part Number Code
S
1
E
2
U
3
02G 72 D4
B
7
H
8
2
9
MT
10
-
30
11
*
12
R
13
4
5
6
*RoHs compl.
Swissbit AG
SDRAM DDR2
240 Pin Unbuffered 1.8V
Depth (2GB)
DDR2-667MT/s
Chip Vendor (MICRON)
2 Module Ranks
Chip Rev. H
Width
PCB-Type (8132d)
Chip organisation x8
* optional / additional information
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Page 13
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Data Sheet
Rev.1.2
03.01.2013
Revision History
Revision
1.0
Changes
Date
Initial Revision
06.07.2010
29.11.2010
03.01.2013
1.1
DDR2-400 Speed-Grade deleted
dimension drawing changed
1.2
Swissbit AG
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Page 14
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Data Sheet
Rev.1.2
03.01.2013
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
Fax:
+41 (0)71 913 03 03
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
Fax:
+49 (0)30 93 69 54 – 0
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
1117 E Plaza Drive Unit E Suites 105/205
Eagle, ID 83616
USA
Phone:
Fax:
+1 208 258-6254
+1 208 938-4525
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
Fax:
+81 3 5356 3511
+81 3 5356 3512
________________________________
Swissbit AG
Industriestrasse 4
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Page 15
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Data Sheet
Rev.1.2
03.01.2013
Declaration of Conformity
We
Manufacturer:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
declare under our sole responsibility that the product
Product Type:
Brand Name:
Product Series:
Part Number:
2GB DDR2 ECC UDIMM
SWISSMEMORY™
DDR2 UDIMM
SEU02G72D4BH2MT-xxR
to which this declaration relates is in conformity with the following directives:
2002/96/EC Category 3 (WEEE)
following the provisions of Directive
Restriction of the use of certain hazardous substances 2011/65/EU
Swissbit AG, Januar 2013
Manuela Kögel
Head of Quality Management
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: info@swissbit.com
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