SLN04G64E1BK2MT-DCRT [ETC]
4096MB DDR3L . SDRAM SO-DIMM;
| 型号： | SLN04G64E1BK2MT-DCRT |
| 厂家： | 
ETC |
| 描述： | 4096MB DDR3L . SDRAM SO-DIMM 动态存储器 双倍数据速率 |
| 文件： | 总17页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Rev.1.0
22.11.2012
4096MB DDR3L – SDRAM SO-DIMM
Features:
204 Pin SO-DIMM
.
204-pin 64-bit DDR3 Small Outline Dual-In-Line Double
Data Rate Synchronous DRAM module
Module organization: dual rank 512M x 64
VDD = 1.35V and 1.5V
SLN04G64E1BK2MT-xxRT
4GByte in FBGA Technology
RoHS compliant
.
.
.
.
.
.
VDDQ = 1.35V and 1.5V
SSTL_15 compatible
Fly-by-bus with termination for C/A & CLK bus
On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
Options:
.
Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1600 MT/s CL11
Marking
-CC
.
.
Gold-contact pads
This module is fully pin and functional compatible to the
JEDEC PC3-12800 spec. and JEDEC- Standard MO-268.
(see www.jedec.org)
-DC
.
Module Density
4096MB with 16 dies and 2 rank
.
The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
.
Standard Grade
(TA)
(TC)
0°C to 70°C
0°C to 85°C
.
DDR3 - SDRAM component Micron
MT41K256M8DA-125 DIE-Rev.K
.
.
.
256Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit prefetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
*) The refresh rate has to be doubled when 85°C<TC<95°C*) T
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for improved
.
Environmental Requirements:
signal integrity.
.
Operating temperature (ambient)
Standard Grade
.
.
.
Refresh. Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
0°C to 70°C
.
.
.
.
.
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
Figure: mechanical dimensions1
1682 PSI (up to 5000 ft.) at 50°C
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 17
Data Sheet
Rev.1.0
22.11.2012
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the SO-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Row
Addr.
Device Bank
Addr.
Column
Addr.
Module
Bank Select
Organization
DDR3 SDRAMs used
Refresh
512M x 64bit
16 x 256M x 8bit
(2048Mbit)
15
BA0, BA1, BA2
10
8k
S0#, S1#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
Module Density Transfer Rate Clock Cycle/Data bit rate
Latency
SLN04G64E1BK2MT-CCRT
SLN04G64E1BK2MT-DCRT
4096 MB
4096 MB
10.6 GB/s
12.8 GB/s
1.5ns / 1333MT/s
1.25ns / 1600MT/s
9-9-9
11-11-11
Pin Name
A0-9, A11 – A14
A10/AP
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
BA0 – BA2
DQ0 – DQ63
DM0-DM7
DQS0 - DQS7
DQS0# - DQS7#
RAS#
Data Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
CAS#
WE#
CKE0 – CKE1
S0# - S1#
Clock Enable
Chip Select
CK0 – CK1
CK0# - CK1#
Clock Inputs, positive line
Clock Inputs, negative line
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 17
Data Sheet
Rev.1.0
22.11.2012
Event#
VDD
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
Supply Voltage (1.35V -0.067V/+0.1V and 1.5V ± 0.075V)
Reference voltage: DQ, DM (VDD/2)
VREFDQ
VREFCA
VSS
Reference voltage: Control, command, and address (VDD/2)
Ground
VTT
Termination voltage: Used for control, command, and address (VDD/2).
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
VDDSPD
SCL
SDA
Serial Data Out for Presence Detect
SA0 – SA1
ODT0 – ODT1
NC
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
Frontside
PIN#
1
Symbol
PIN#
53
55
57
59
61
63
65
67
69
71
Symbol
DQ19
VSS
PIN#
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
Symbol
CK0#
VDD
PIN#
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Symbol
VSS
VREFDQ
VSS
3
DQ42
DQ43
VSS
5
DQ0
DQ1
VSS
DQ24
DQ25
VSS
A10/AP
BA0
7
9
VDD
DQ48
DQ49
VSS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
DM0
VSS
DM3
WE#
CAS#
VDD
VSS
DQ2
DQ3
VSS
DQ26
DQ27
VSS
DQS6#
DQS6
VSS
A13
S1#
KEY
DQ8
DQ9
VSS
VDD
DQ50
DQ51
VSS
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
CKE0
VDD
NC (TEST)
VSS
DQS1#
DQS1
VSS
NC
DQ32
DQ33
VSS
DQ56
DQ57
VSS
BA2
VDD
DQ10
DQ11
VSS
A12/BC#
A9
DQS4#
DQS4
VSS
DM7
VSS
VDD
A8
DQ58
DQ59
VSS
DQ16
DQ17
VSS
DQ34
DQ35
VSS
A5
VDD
A3
SA0
DQS2#
DQS2
VSS
DQ40
DQ41
VSS
VDDSPD
SA1
A1
VDD
CK0
VTT
DQ18
153
DM5
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 17
Data Sheet
Rev.1.0
22.11.2012
Backside
PIN#
2
Symbol
VSS
PIN#
54
56
58
60
62
64
66
68
70
72
Symbol
PIN#
Symbol
CK1#
VDD
PIN#
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Symbol
VSS
VSS
DQ28
DQ29
VSS
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
4
DQ4
DQ46
DQ47
VSS
6
DQ5
BA1
8
VSS
RAS#
VDD
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
DQS0#
DQS0
VSS
DQS3#
DQS3
VSS
DQ52
DQ53
VSS
S0#
ODT0
VDD
DQ6
DQ30
DQ31
VSS
DM6
VSS
DQ7
ODT1
NC
VSS
DQ54
DQ55
VSS
KEY
DQ12
DQ13
VSS
VDD
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
CKE1
VDD
VREFCA
VSS
DQ60
DQ61
VSS
DM1
NC (A15)
A14
VDD
A11
A7
DQ36
DQ37
VSS
NC (RESET#)
VSS
DQS7#
DQS7
VSS
DQ14
DQ15
VSS
DM4
VSS
VDD
A6
DQ38
DQ39
VSS
DQ62
DQ63
VSS
DQ20
DQ21
VSS
A4
VDD
A2
DQ44
DQ45
VSS
EVENT#
SDA
DM2
VSS
A0
SCL
DQ22
VDD
DQS5#
VTT
DQ23
CK1
154
DQS5
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 17
Data Sheet
Rev.1.0
22.11.2012
FUNCTIONAL BLOCK DIAGRAMM 4096MB DDR3 SDRAM SODIMM,
2 RANK AND 16 COMPONENTS
S1
S0
DQS4
DQS4
DM4
DQS0
DQS0
DM0
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM DQS DQS
CS
I/O 0
DM
DM
DM
DM
DQS DQS
CS
I/O 0
DM DQS DQS
CS
I/O 0
DM DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
D8
D4
D0
ZQ
ZQ
ZQ
ZQ
DQS1
DQS1
DM1
DQS1
DQS1
DM1
CS
DQS DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM DQS DQS
CS
DM DQS DQS
CS
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D13
D9
D5
D1
ZQ
ZQ
ZQ
ZQ
DQS2
DQS2
DM2
DQS2
DQS2
DM2
CS
DQS DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM DQS DQS
CS
DM DQS DQS
CS
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D14
D10
D6
D2
ZQ
ZQ
ZQ
ZQ
DQS3
DQS3
DM3
DQS3
DQS3
DM3
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM DQS DQS
CS
DQS DQS
CS
DM DQS DQS
CS
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D15
D11
D7
D3
ZQ
ZQ
ZQ
ZQ
BA0-BA2
A0-A14
BA0-BA2: SDRAM D0-D15
A0-A14: SDRAM D0-D15
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of the JEDED document.
5. For each DRAM, a unique ZQ resistor is connected to
GND. The ZQ resistor is 240O±1%.
VDDSPD
VDD/VDDQ
SPD
RAS
CAS
WE
ODT0
ODT1
RAS: SDRAM D0-D15
CAS: SDRAM D0-D15
WE: SDRAM D0-D15
ODT: SDRAM D0-D7
ODT: SDRAM D8-D15
D0-D15
D0-D15
VREFDQ
VREFCA
VSS
D0-D15
D0-D15
CKE0
CKE1
CK0,CK1
CK0,CK1
RESET
CKE: SDRAM D0-D7
CKE: SDRAM D8-D15
CK: SDRAM D0-D15
CK: SDRAM D0-D15
RESET: SDRAM D0-D15
6. Refer to associated figure for SPD details.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 17
Data Sheet
Rev.1.0
22.11.2012
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
VDD
VDDQ
VIN, VOUT
MIN
-0.4
-0.4
-0.4
MAX
UNITS
1.975
1.975
1.975
V
V
V
Voltage on any pin relative to VSS
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
II
µA
Command/Address
RAS#, CAS#, WE#, S#, CKE
-16
16
CK, CK#
DM
-16
-2
16
2
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
µA
)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
-8
8
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
VDD
MIN
1.283
1.283
NOM
1.35
1.35
0.50 x VDDQ
0.50 x VDDQ
MAX
1.450
1.450
UNITS
V
V
V
V
V
V
VDDQ
VREF
VTT
VIH (DC90)
VIL (DC90)
I/O Reference Voltage
0.49 x VDDQ
0.49 x VDDQ-20mV
VREF + 90mV
-0.3
0.51x VDDQ
0.51x VDDQ+20mV
VDDQ + 0.3
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF – 90mV
Under 1.5V operation this DDR3L device operates in accordance to the following specification:
SGN04G64E1BM2MT-XXRT
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC135) VREF + 135mV
VIL (AC135)
MIN
MAX
-
VREF – 135mV
UNITS
V
V
-
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 6
of 17
Data Sheet
Rev.1.0
22.11.2012
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283V – 1.45V)
Parameter
max.
Symbol
IDD0
Unit
& Test Condition
12800 CL11
10600 CL9
OPERATING CURRENT *) :
One device bank Active-Precharge;
mA
576
536
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
mA
IDD1
696
656
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
Fast Exit
PRECHARGE POWER-DOWN
CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and
Address bus inputs are not changing; DQ’s
are floating at VREF
mA
IDD2P
528
192
528
448
192
448
Slow Exit
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
mA
mA
IDD2Q
PRECHARGE STANDBY CURRENT:
All device banks idle;
IDD2N
560
480
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN CURRENT:
mA
mA
IDD3P
752
832
672
752
All device banks open; tCK = tCK (IDD); CKE is LOW; All
Control and Address bus inputs are not changing; DQ’s
are floating at VREF (always fast exit)
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
IDD3N
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
mA
IDD4R
1216
1096
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 7
of 17
Data Sheet
Rev.1.0
22.11.2012
Parameter
max.
Symbol
IDD4W
Unit
& Test Condition
12800 CL11
10600 CL9
976
OPERATING WRITE CURRENT:
mA
mA
1096
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
IDD5
3040
2960
tCK = tCK (IDD); refresh command at every tRFC (IDD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
mA
mA
IDD6
192
192
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are
floating at VREF
OPERATING CURRENT*) :
IDD7
1856
1736
Four device bank interleaving READs, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
CL (IDD
tRCD (IDD
tRC (IDD
tRRD (IDD
tCK (IDD
tRAS MIN (IDD
tRAS MAX (IDD
tRP (IDD
tRFC (IDD
Unit
12800 CL11
11
10600 CL9
9
)
tCK
ns
ns
ns
ns
ns
ns
ns
ns
13.75
48.75
6
1.25
35
70’200
13.75
160
13.5
49.5
6
1.5
36
70’200
13.5
160
)
)
)
)
)
)
)
)
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Page 8
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Data Sheet
Rev.1.0
22.11.2012
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283V – 1.45V)
AC CHARACTERISTICS
PARAMETER
12800 CL11
10600 CL9
SYMBOL
tCK (11)
tCK (10)
tCK (9)
tCK (8)
tCK (7)
tCK (6)
tCK (5)
tAA
MIN
1.25
1.5
MAX
-
MIN
-
MAX
-
Unit
Clock cycle time
CL = 11
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
<1.875
<1.875
<2.5
<2.5
3.3
1.5
1.5
1.875
1.875
2.5
<1.875
<1.875
<2.5
<2.5
3.3
1.5
1.875
1.875
2.5
ns
3.0
3.3
3.0
3.3
Internal READ command to first
data
13.75
-
13.5
-
CK high-level width
CK low-level width
0.47
0.47
0.53
0.53
0.47
0.47
0.53
0.53
tCK
tCK
t
t
CH (avg)
CL (avg)
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
tHZ
-
225
225
-
250
250
ps
ps
tLZ
-450
-500
DQ and DM input setup time
relative to DQS VREF=1V/ns
tDS1V
160
-
180
-
ps
DQ and DM input hold time
relative to DQS VREF=1V/ns
DQ and DM input pulse width
( for each input )
DQS, DQS# to DQ skew, per
access
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
DQS input high pulse width
tDH1V
tDIPW
tDQSQ
tQH
145
360
-
-
165
400
-
-
ps
ps
ps
-
100
-
-
125
-
tCK
(AVG)
tCK
0.38
0.38
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tDQSH
tDQSL
DQS input low pulse width
tCK
DQS, DQS# rising to/from CK,
CK#
DQS, DQS# rising to/from CK,
CK# when DLL disabled
tDQSCK
-225
1
225
-250
1
250
ps
tDQSCK
DLL_DIS
10
-
10
-
ns
tCK
tCK
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
tDSS
0.18
0.18
0.2
0.2
tDSH
-
-
DQS read preamble
0.9
0.3
0.9
0.3
Note1
Note2
0.9
0.3
0.9
0.3
Note1
Note2
tCK
tCK
tCK
tCK
tRPRE
tRPST
tWPRE
tWPST
tDQSS
DQS read postamble
DQS write preamble
DQS write postamble
Positive DQS latching edge to
associated clock edge
Address and control input pulse
width ( for each input )
CTRL, CMD, Addr setup to CK,
CK#
-
-
-
-
- 0.27
560
45
+ 0.27
- 0.25
620
65
+ 0.25
tCK
ps
ps
ps
tIPW
-
-
-
-
-
-
tIS(Base)
tIS(1V)
CTRL, CMD, Addr setup to CK,
220
240
CK#
VREF @ 1V/ns
1
2
The maximum preamble is bound by tLZDQS (MAX)
The maximum postamble is bound by tHZDQS (MAX)
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Page 9
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Data Sheet
Rev.1.0
22.11.2012
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283V – 1.45V)
AC CHARACTERISTICS
PARAMETER
12800 CL11
10600 CL9
SYMBOL
MIN
MAX
MIN
MAX
Unit
CTRL, CMD, Addr hold to CK,
CK#
120
-
140
-
ps
tIH(Base)
CTRL, CMD, Addr hold to CK,
220
4
-
-
-
240
4
-
-
-
ps
tCK
ns
tIH(1V)
tCCD
tRC
CK#
VREF @ 1V/ns
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank)
command period
48.75
49.5
ACTIVE to ACTIVE minimum
command period
ACTIVE to READ or WRITE
delay
max
max
ns
ns
ns
ns
tRRD
tRCD
tFAW
tRAS
4nCK,6ns
4nCK,6ns
-
-
13.75
13.5
Four bank
Activate period
1K Page size
2K Page size
30
40
-
-
30
45
-
-
ACTIVE to PRECHARGE
command
35
70’200
36
70’200
Internal READ to precharge
command delay
Write recovery time
Auto precharge write recovery +
precharge time
max
max
-
-
-
-
-
-
ns
ns
ns
tRTP
tWR
tDAL
4nCK,7.5ns
4nCK,7.5ns
15
15
tWR + tRP/tCK
tWR + tRP/tCK
Internal WRITE to READ
command delay
PRECHARGE command period
LOAD MODE command cycle
time
max
max
-
-
-
-
-
-
ns
ns
tCK
tWTR
tRP
4nCK,7.5ns
4nCK,7.5ns
13.75
4
13.5
4
tMRD
REFRESH to ACTIVE or
REFRESH to REFRESH
command interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
160
70’200
160
70’200
ns
µs
tRFC
-
-
7.8
3.9
-
-
7.8
3.9
tREFI
tREFI (IT)
tAON
85 °C < TCASE ≤ 95°C
RTT turn-on from ODTL on
reference
RTT turn-on from ODTL off
reference
Asynchronous RTT turn-on delay
(power Down with DLL off)
Asynchronous RTT turn-off delay
(power Down with DLL off)
RTT dynamic change skew
-225
225
-250
250
ps
tCK
ns
0.3
2
0.7
8,5
0.3
2
0.7
8,5
tAOF
tAONPD
2
8,5
0.7
2
8,5
0.7
ns
tAOFPD
tADC
0.3
0.3
tCK
Exit self refresh to commands
not requiring a locked DLL
max
5nCK,tR
FC + 10ns
max
5nCK,tR
FC + 10ns
-
-
ns
tXS
Write levelling setup from rising
CK, CK# crossing to rising DQS,
DQS# crossing
Write levelling setup from rising
DQS, DQS# crossing to rising
CK, CK# crossing
-
165
165
-
195
195
ps
tWLS
-
-
ps
tWLH
First DQS, DQS# rising edge
DQS, DQS# delay
-
-
40
25
-
-
40
25
tCK
tCK
tWLMRD
tWLDQSEN
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Page 10
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Data Sheet
Rev.1.0
22.11.2012
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283V – 1.45V)
AC CHARACTERISTICS
PARAMETER
12800 CL11
10600 CL9
SYMBOL
MIN
MAX
MIN
MAX Unit
Exit reset from CKE HIGH to a
valid command
max
max
tXPR
-
-
tCK
5nCK,
5nCK,
tRFC + 10ns
tRFC + 10ns
Begin power supply ramp to
power supplies stable
RESET# LOW to power supplies
stable
RESET# LOW to I/O and RTT
High-Z
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
ms
t
VDDPR
-
0
-
200
200
20
-
-
0
-
200
200
20
-
ms
ns
tRPS
tIOz
tXP
max
3nCK,6ns
max
3nCK,6ns
tCK
tCK
max
3nCK,
5ns
max
3nCK,
5.625ns
tCKE
-
-
Temperature Sensor with Serial Presence-Detect EEPROM
SCL
SDA
WP/EVENT
EVENT
R1
0Ω
SA0
SA0
SA1
SA2
SA1
Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions
Parameter / Condition
Supply voltage
Symbol
VDDSPD
IDD
VIH
VIL
MIN
+3
MAX
+3.6
+2.0
VDDSPD +1
550
Unit
V
mA
V
mV
mV
µA
°C
Supply current: VDD = 3.3V
Input high voltage: Logic 1; SCL, SDA
Input low voltage: Logic 0; SCL, SDA
Output low voltage: IOUT= 2.1mA
Input current
+1.45
-
-
-5.0
TBD
TBD
VOL
IIN
400
5.0
Temperature sensing range
Temperature sensor accuracy
TBD
TBD
°C
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Page 11
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Data Sheet
Rev.1.0
22.11.2012
A.C. Characteristics of Temperature Sensor
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Symbol Parameter / Condition
MIN
10
MAX
Unit
kHz
ns
fSCL
tBUF
tF
SCL clock frequency
400
Bus Free Time Between STOP and START
SDA fall time
1300
300
300
ns
tR
SDA rise time
ns
Data hold time (accepted for Input Data)
Data Hold Time (guaranteed for Output Data)
Start condition hold time
0
ns
tHD:DAT
300
600
600
1300
100
600
600
25
900
ns
tH:STA
tHIGH
tLOW
ns
High Period of SCL
ns
Low Period of SCL
ns
tSU:DAT
tSU:STA
tSU:STO
tTIMEOUT
tI
Data setup time
ns
Start condition setup time
ns
Stop condition setup time
ns
SMBus SCL Clock Low Timeout
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
35
ms
ns
100
5
tWR
ms
ms
tPU
Power-up Delay to Valid Temperature Recording
100
Temperature Characteristics of Temperature Sensor
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Parameter
Test Conditions/Comments
+75°C ≤ TA ≤ +95°C, active range
+40°C ≤ TA ≤ +125°C, monitor range
MAX
Unit
°C
°C
°C
Bits
°C
±1.0
±2.0
±3.0
12
0.0625
100
Temperature Reading Error
Class B, JC42.4 compliant
-40°C ≤ TA ≤ +125°C, sensing range
ADC Resolution
Temperature Resolution
Conversion Time
Ms
°C/W
Thermal Resistance1 θJA
Junction-to-Ambient (Still Air)
92
1 Power Dissipation is defined as PJ = (TJ − TA)/θJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2-layer PCB.
Slave Address Bits of Temperature Sensor
Device
Device Type Identifier
Select Address Signals R/W#
b71
1
b6
0
b5
1
b4
0
b3
A2
A2
b2
A1
A1
b1
A0
A0
b0
EEPROM
R/W#
R/W#
Temp. Sensor
0
0
1
1
1 The most significant bit, b7, is sent first.
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Page 12
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Data Sheet
Rev.1.0
22.11.2012
SERIAL PRESENCE-DETECT MATRIX
12800 CL11
10600 CL9
Byte
Byte Description
0
1
CRC RANGE, EEPROM BYTES, BYTES USED
SPD REVISON
0x92
0x11
0x0B
0x03
0x03
0x19
0x02
0x09
0x03
0x11
0x01
0x08
2
DRAM DEVICE TYPE
3
MODULE TYPE (FORM FACTOR)
SDRAM DEVICE DENSITY & BANKS
SDRAM DEVICE ROW & COLUMN COUNT
MODULE NOMINAL VOLTAGE, VDD
MODULE RANKS & DEVICE DQ COUNT
ECC TAG & MODULE MEMORY BUS WIDTH
FINE TIMEBASE DIVIDEND/DIVISOR
MEDIUM TIMEBASE DIVIDEND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MEDIUM TIMEBASE DIVISOR
MIN SDRAM CYCLE TIME (tCK MIN
)
0x0A
0xFE
0x0C
0x7E
BYTE 13 RESERVED
0x00
CAS LATENCIES SUPPORTED (CL4 => CL11)
CAS LATENCIES SUPPORTED (CL12 => CL18)
0x00
0x69
0x78
0x69
0x30
0x69
0x11
MIN CAS LATENCY TIME (tAA MIN
MIN WRITE RECOVERY TIME (tWR MIN
MIN RAS# TO CAS# DELAY (tRCD MIN
MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN
)
)
)
)
MIN ROW PRECHARGE DELAY (tRP MIN
)
UPPER NIBBLE FOR tRAS & tRC
MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN
)
0x18
0x81
0x20
0x89
MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN
MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB
MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB
)
0x00
0x05
0x3C
MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN
)
MIN INTERNAL READ TO PRECHARGE CMD DELAY
(tRTP MIN)
27
0x3C
28
29
30
31
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB
SDRAM DEVICE OUTPUT DRIVERS SUPPORTED
SDRAM DEVICE THERMAL & REFRESH OPTIONS
0x00
0xF0
0x83
0x05
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Page 13
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Data Sheet
Rev.1.0
22.11.2012
12800-999
10600 CL9
Byte
Byte Description
32
33-59
60
DDR3-MODULE THERMAL SENSOR
BYTES 32-59 RESERVED
0x80
0x00
0x0F
0x11
0x01
MODULE HEIGHT (NOMINAL)
MODULE THICKNESS (MAX)
REFERENCE RAW CARD ID
61
62
63
64-116
117
ADDRESS MAPPING EDGE CONECTOR TO DRAM
BYTES 64-116 RESEVED
0x00
0x00
0x83
MODULE MFR ID (LSB)
118
MODULE MFR ID (MSB)
0Xda
0x01 (Switzerland)
0x02 (Germany)
0x03 (USA)
119
MODULE MFR LOCATION ID
120
121
MODULE MFR YEAR
MODULE MFR WEEK
X
X
122-125 MODULE SERIAL NUMBER
126-127 CRC
X
0x3833
0xEDED
128-145 MODULE PART NUMBER
"SLN04G64E1BK2MT-xx"
146
147
148
149
MODULE DIE REV
X
MODULE PCB REV
X
DRAM DEVICE MFR ID (LSB)
DRAM DEVICE MFR (MSB)
0x80
0x2C
0x00
0Xff
150-175 MFR RESERVED BYTES 150-175
176-255 CUSTOMER RESERVED BYTES 176-255
Part Number Code
S
1
L
2
N
3
04G 64 E1
B
7
K
8
2
9
MT
10
-
DC
11
*
12
R
13
**
14
4
5
6
*RoHs compl.
DDR3-1600MT/s
Swissbit AG
SDRAM DDR3L
204 Pin SoDIMM
Depth (4GB)
Chip Vendor (Micron)
2 Module Rank
Chip Rev. K
Width
PCB-Type (S3D3E100)
Chip organisation x8
* optional / additional information
** T= thermal sensor
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Page 14
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Data Sheet
Rev.1.0
22.11.2012
Revision History
Revision
1.0
Changes
Date
22.11.2012
Initial Revision
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Page 15
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Data Sheet
Rev.1.0
22.11.2012
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
Fax:
+41 (0)71 913 03 03
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
Fax:
+49 (0)30 93 69 54 – 0
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
1117 E Plaza Drive Unit E Suites 105/205
Eagle, ID 83616
USA
Phone:
Fax:
+1 208 258-6254
+1 208 938-4525
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
Fax:
+81 3 5356 3511
+81 3 5356 3512
________________________________
Swissbit AG
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Page 16
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Data Sheet
Rev.1.0
22.11.2012
Declaration of Conformity
We
Manufacturer:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
declare under our sole responsibility that the product
Product Type:
Brand Name:
Product Series:
Part Number:
4GB DDR3L SODIMM
SWISSMEMORY™
DDR3L SODIMM
SLN04G64E1BK2MT-xxxRT
to which this declaration relates is in conformity with the following directives:
2002/96/EC Category 3 (WEEE)
following the provisions of Directive
Restriction of the use of certain hazardous substances
2011/65/EU
Swissbit AG, November 2012
Manuela Kögel
Head of Quality Management
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
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Fax: +41 (0) 71 913 03 15
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eMail: info@swissbit.com
Page 17
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