SSD1305Z3_技术文档

SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

SSD1305

Advance Information

132 x 64 Dot Matrix

OLED/PLED Segment/Common Driver with Controller

This document contains information on a new product. Specifications and information herein are subject to change

without notice.

http://www.solomon-systech.com

SSD1305

Rev 2.0

P 1/71

Oct 2008

Appendix: IC Revision history of SSD1305 Specification

Change Items

Version

Effective Date

1.0

Change to Advance Info.

27-Mar-06

1.1

Revise command 91h

28-Apr-06

Add a note on the capacitor value in Section 13 Application Example

Add I2C Interface

1.2

1.3

1.4

1.5

1.6

1.7

Revise CL pin description in Table 7-1

Revise Figure 10-6

26-Jun-06

17-Aug-06

06-Sep-06

22-Sep-06

21-Dec-06

16-May-07

Revise section 8.1.2 & Section 13

Add Figure 10-7

Remove software reset command (E2h)

Revise command 26h/27h/29h/2Ah (Set time interval between each scroll step)

Revise Figure 14-1 Application Example

Revise Die thickness to 457um from 475um

Revise “Bump Size” of pin “127-147, 294-314”

Revise Figure 10-6 ,Figure 8-5 , Figure 13-4

Add light sensitive note In Section 11 – Maximum ratings

Revise Note 2 in Section 8.10 Power ON/OFF sequence by adding the word

“disable”

Add China RoHS disclaimer at the last page.

1.8

1.9

For SPI/6800/8080 MCU interface, change the Rise / Fall time (tR/tF) to max. 40ns

Revise typo in SSD1305T6R1 dwg on P.68

pitch: From 0.85 change to 0.845

02-Aug-07

23-May-08

Add SSD1305Z3 in ordering information & add die tray

Revise CL pin to “connected to VSS” in Section 8.3

Revise typo in page 42 : from “upper column address is 00h” to “upper column

address is 10h”

27-Oct-08

2.0

Add IC revision history on spec

Solomon Systech

Oct 2008 P 2/71

Rev 2.0 SSD1305

CONTENTS

1

GENERAL DESCRIPTION.................................................................................................... 8

FEATURES ............................................................................................................................... 8

ORDERING INFORMATION................................................................................................ 8

BLOCK DIAGRAM................................................................................................................. 9

DIE PAD FLOOR PLAN....................................................................................................... 10

PIN ARRANGEMENT .......................................................................................................... 13

2

3

4

5

6

6.1

6.2

SSD1305T6R1 PIN ASSIGNMENT.........................................................................................................................13

SSD1305T7R1 PIN ASSIGNMENT.........................................................................................................................15

7

8

PIN DESCRIPTION............................................................................................................... 17

FUNCTIONAL BLOCK DESCRIPTIONS ......................................................................... 19

8.1

MCU INTERFACE SELECTION...............................................................................................................................19

8.1.1

8.1.2

8.1.3

8.1.4

MCU Parallel 6800-series Interface...............................................................................................................19

MCU Parallel 8080-series Interface...............................................................................................................20

MCU Serial Interface......................................................................................................................................22

MCU I²C Interface..........................................................................................................................................22

COMMAND DECODER ..........................................................................................................................................25

OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR......................................................................................26

FR SYNCHRONIZATION ........................................................................................................................................27

RESET CIRCUIT....................................................................................................................................................27

SEGMENT DRIVERS / COMMON DRIVERS .............................................................................................................28

GRAPHIC DISPLAY DATA RAM (GDDRAM)......................................................................................................30

AREA COLOR DECODER.......................................................................................................................................31

SEG/COM DRIVING BLOCK ................................................................................................................................32

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10 POWER ON AND OFF SEQUENCE .........................................................................................................................33

9

COMMAND TABLE.............................................................................................................. 34

9.1

DATA READ / WRITE ...........................................................................................................................................40

10

COMMAND DESCRIPTIONS ............................................................................................. 41

10.1 FUNDAMENTAL COMMAND .................................................................................................................................41

10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) ......................................................41

10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh) .....................................................41

10.1.3 Set Memory Addressing Mode (20h)...............................................................................................................41

10.1.4 Set Column Address (21h) ..............................................................................................................................42

10.1.5 Set Page Address (22h)...................................................................................................................................43

10.1.6 Set Display Start Line (40h~7Fh) ...................................................................................................................44

10.1.7 Set Contrast Control for BANK0 (81h)...........................................................................................................44

10.1.8 Set Brightness for Area Color Banks (82h).....................................................................................................44

10.1.9 Set Look Up Table (LUT) (91h).....................................................................................................................44

10.1.10

10.1.11

10.1.12

10.1.13

10.1.14

10.1.15

10.1.16

10.1.17

10.1.18

Set Bank Color of BANK1 to BANK16 (PAGE0) (92h) ..............................................................................45

Set Bank Color of BANK17 to BANK32 (PAGE0) (93h) ............................................................................45

Set Segment Re-map (A0h/A1h) ..................................................................................................................45

Entire Display ON (A4h/A5h)...................................................................................................................45

Set Normal/Inverse Display (A6h/A7h).......................................................................................................45

Set Multiplex Ratio (A8h)............................................................................................................................45

Reserved (AAh) ...........................................................................................................................................45

Dim Mode setting (ABh) .............................................................................................................................45

Master Configuration (ADh).......................................................................................................................45

SSD1305

Rev 2.0

P 3/71

Oct 2008

Solomon Systech

10.1.19

10.1.20

10.1.21

10.1.22

10.1.23

10.1.24

10.1.25

10.1.26

10.1.27

10.1.28

10.1.29

10.1.30

10.1.31

Set Display ON/OFF (ACh/AEh/AFh) ........................................................................................................46

Set Page Start Address for Page Addressing Mode (B0h~B7h)..................................................................46

Set COM Output Scan Direction (C0h/C8h)...............................................................................................46

Set Display Offset (D3h) .............................................................................................................................46

Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)....................................................................49

Set Area Color Mode ON/OFF & Low Power Display Mode (D8h)..........................................................49

Set Pre-charge Period (D9h)......................................................................................................................49

Set COM Pins Hardware Configuration (DAh)..........................................................................................50

Set V_COMHDeselect Level (DBh) .................................................................................................................52

Enter Read Modify Write (E0h) ..................................................................................................................52

NOP (E3h) ..................................................................................................................................................53

Exit Read Modify Write (EEh) ....................................................................................................................53

Status register Read....................................................................................................................................53

10.2 GRAPHIC ACCELERATION COMMAND..................................................................................................................54

10.2.1 Horizontal Scroll Setup (26h/27h) ..................................................................................................................54

10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah)..........................................................................55

10.2.3 Deactivate Scroll (2Eh)...................................................................................................................................56

10.2.4 Activate Scroll (2Fh).......................................................................................................................................56

10.2.5 Set Vertical Scroll Area(A3h) .........................................................................................................................57

11

MAXIMUM RATINGS.......................................................................................................... 58

DC CHARACTERISTICS..................................................................................................... 59

AC CHARACTERISTICS..................................................................................................... 60

APPLICATION EXAMPLE.................................................................................................. 65

PACKAGE INFORMATION................................................................................................ 66

12

13

14

15

15.1 SSD1305Z DIE TRAY INFORMATION...................................................................................................................66

15.2 SSD1305T6R1 DETAIL DIMENSION....................................................................................................................67

15.3 SSD1305T7R1 DETAIL DIMENSION....................................................................................................................69

15.4 SSD1305Z3 DIE TRAY INFORMATION.................................................................................................................70

Solomon Systech

Oct 2008 P 4/71

Rev 2.0 SSD1305

TABLES

TABLE 3-1 : ORDERING INFORMATION................................................................................................... 8

TABLE 5-1 : SSD1305Z BUMP DIE PAD COORDINATES....................................................................... 12

TABLE 6-1 : SSD1305T6R1 PIN ASSIGNMENT TABLE......................................................................... 14

TABLE 6-2 : SSD1305T7R1 PIN ASSIGNMENT .................................................................................... 16

TABLE 7-1 : PIN DESCRIPTION ............................................................................................................. 17

TABLE 7-2 : MCU BUS INTERFACE PIN SELECTION ............................................................................. 18

TABLE 8-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE........................ 19

TABLE 8-2 : CONTROL PINS OF 6800 INTERFACE .................................................................................. 19

TABLE 8-3 : CONTROL PINS OF 8080 INTERFACE (FORM 1) .................................................................. 21

TABLE 8-4 : CONTROL PINS OF 8080 INTERFACE (FORM 2) .................................................................. 21

TABLE 8-5 : CONTROL PINS OF SERIAL INTERFACE .............................................................................. 22

TABLE 9-1: COMMAND TABLE............................................................................................................. 34

TABLE 9-2 : READ COMMAND TABLE .................................................................................................. 40

TABLE 9-3 : ADDRESS INCREMENT TABLE (AUTOMATIC)..................................................................... 40

TABLE 10-1 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH NO REMAP ........... 47

TABLE 10-2 :EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH REMAP ................. 48

TABLE 10-3 : COM PINS HARDWARE CONFIGURATION....................................................................... 50

TABLE 10-4 : EXAMPLE OF READ MODIFY WRITE MODE .................................................................... 53

TABLE 11-1 : MAXIMUM RATINGS (VOLTAGE REFERENCED TO V_SS) .................................................. 58

TABLE 12-1 : DC CHARACTERISTICS ................................................................................................... 59

TABLE 13-1 : AC CHARACTERISTICS ................................................................................................... 60

TABLE 13-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS.......................... 61

TABLE 13-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS.......................... 62

TABLE 13-4 : SERIAL INTERFACE TIMING CHARACTERISTICS .............................................................. 63

TABLE 13-5 :I²C INTERFACE TIMING CHARACTERISTICS ..................................................................... 64

SSD1305

Rev 2.0

P 5/71

Oct 2008

Solomon Systech

FIGURES

FIGURE 4-1 : SSD1305 BLOCK DIAGRAM.............................................................................................. 9

FIGURE 5-1 : SSD1305Z DIE DRAWING............................................................................................... 10

FIGURE 5-2 : SSD1305Z ALIGNMENT MARKS DIMENSION.................................................................. 11

FIGURE 6-1 : SSD1305T6R1 PIN ASSIGNMENT ................................................................................... 13

FIGURE 6-2 : SSD1305T7R1 PIN ASSIGNMENT ................................................................................... 15

FIGURE 8-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ......................................... 20

FIGURE 8-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE .......................... 20

FIGURE 8-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE............................ 20

FIGURE 8-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ .......................... 21

FIGURE 8-5 : WRITE PROCEDURE IN SPI MODE..................................................................................... 22

FIGURE 8-6 : I²C -BUS DATA FORMAT................................................................................................... 23

FIGURE 8-7 : DEFINITION OF THE START AND STOP CONDITION........................................................... 24

FIGURE 8-8 : DEFINITION OF THE ACKNOWLEDGEMENT CONDITION..................................................... 25

FIGURE 8-9 : DEFINITION OF THE DATA TRANSFER CONDITION ........................................................... 25

FIGURE 8-10 : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR ............................................... 26

FIGURE 8-11 : SEGMENT OUTPUT WAVEFORM IN THREE PHASES......................................................... 28

FIGURE 8-12 : SEGMENT OUTPUT WAVEFORM FOR TWO DIFFERENT COLORS LUT SETTING................ 28

FIGURE 8-13 : EXAMPLE OF SEGMENT OUTPUT WAVEFORM OF MONOCHROME DISPLAY SECTION

UNDER MONOCHROME MODE......................................................................................................... 29

FIGURE 8-14 : EXAMPLE OF SEGMENT OUTPUT WAVEFORM OF AREA COLOR DISPLAY SECTION UNDER

AREA COLOR MODE........................................................................................................................ 29

FIGURE 8-15 : GDDRAM PAGES STRUCTURE OF SSD1305................................................................. 30

FIGURE 8-16 : ENLARGEMENT OF GDDRAM (NO ROW RE-MAPPING AND COLUMN-REMAPPING) ....... 30

FIGURE 8-17 : EXAMPLE OF AREA COLOR ASSIGNMENT ON A 132X64 OLED PANEL ........................... 31

FIGURE 8-18 : I_REFCURRENT SETTING BY RESISTOR VALUE ............................................................... 32

FIGURE 8-19 : THE POWER ON SEQUENCE........................................................................................... 33

FIGURE 8-20 : THE POWER OFF SEQUENCE ......................................................................................... 33

FIGURE 10-1 : ADDRESS POINTER MOVEMENT OF PAGE ADDRESSING MODE ....................................... 41

FIGURE 10-2 : EXAMPLE OF GDDRAM ACCESS POINTER SETTING IN PAGE ADDRESSING MODE (NO

ROW AND COLUMN-REMAPPING) ................................................................................................... 41

FIGURE 10-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESSING MODE........................... 42

FIGURE 10-4 : ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESSING MODE ............................... 42

FIGURE 10-5 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT................................ 43

FIGURE 10-6 : SEGMENT CURRENT VS CONTRAST SETTING.................................................................. 44

FIGURE 10-7 :TRANSITION BETWEEN DIFFERENT MODES ..................................................................... 46

FIGURE 10-8 : TYPICAL OSCILLATOR FREQUENCY ADJUSTMENT BY D5 COMMAND (V_DD=2.8V)........ 49

FIGURE 10-9 : HORIZONTAL SCROLL EXAMPLE: SCROLL RIGHT BY 4 COLUMNS ................................ 54

FIGURE 10-10 : HORIZONTAL SCROLL EXAMPLE: SCROLL LEFT BY 2 COLUMNS ................................. 54

FIGURE 10-11 : HORIZONTAL SCROLLING SETUP EXAMPLE .................................................................. 54

FIGURE 10-12 : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING SETUP EXAMPLES.................. 55

FIGURE 10-13 : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING EXAMPLE: WITH SETTING IN

MUX RATIO .................................................................................................................................. 56

FIGURE 10-14 : VERTICAL SCROLL AREA SETUP EXAMPLES ................................................................. 57

FIGURE 13-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS ....................................... 61

FIGURE 13-2 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS (FORM 1) ................................. 62

FIGURE 13-3 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS (FORM 2) ................................. 62

FIGURE 13-4 : SERIAL INTERFACE CHARACTERISTICS .......................................................................... 63

FIGURE 13-5 : I²C INTERFACE TIMING CHARACTERISTICS ................................................................... 64

FIGURE 14-1 : APPLICATION EXAMPLE OF SSD1305T6R1.................................................................. 65

Solomon Systech

Oct 2008 P 6/71

Rev 2.0 SSD1305

FIGURE 15-1 SSD1305Z DIE TRAY INFORMATION ............................................................................... 66

FIGURE 15-2 SSD1305T6R1 DETAIL DIMENSION ............................................................................... 67

FIGURE 15-3 SSD1305T7R1 DETAIL DIMENSION ............................................................................... 69

FIGURE 15-4 SSD1305Z3 DIE TRAY INFORMATION ............................................................................. 70

SSD1305

Rev 2.0

P 7/71

Oct 2008

Solomon Systech

1

GENERAL DESCRIPTION

The SSD1305 is a CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-

matrix graphic display system. It consists of 132 segments and 64 commons that can support a maximum

display resolution of 132x64. There are 4-color selections to support monochrome or area color OLED/PLED.

This IC is designed for Common Cathode type OLED panel.

The SSD1305 embeds with contrast control, display RAM and oscillator, which reduces the number of

external components and power consumption. It has 256-step brightness control and separate power for I/O

interface logic. It is suitable for many compact portable applications, such as mobile phone sub-display,

calculator and MP3 player, etc.

2

FEATURES

•

Resolution: 132 x 64 dot matrix panel

Area color support with 4 Color Selection and 64 steps per color

Power supply:

o

V

_DD= 2.4V to 3.5V

V_CC= 7.0V to 15.0V

_DDIO= 1.6V to V_DD

for IC logic

for Panel driving

for MCU interface

V

•

Segment maximum source current: 320uA

Common maximum sink current: 45mA

Embedded 132 x 64 bit SRAM display buffer

256-step Contrast Control

8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface,

I²C Interface

•

Row Re-mapping and Column Re-mapping

Continuous Horizontal, Vertical and Diagonal Scrolling

Dim Mode operations

Programmable Frame Frequency and Multiplexing Ratio

On-Chip Oscillator

Low power consumption

Wide range of operating temperatures: -40 to 85 °C

3

ORDERING INFORMATION

Table 3-1 : Ordering Information

Ordering Part Number SEG COM Package Form Reference Remark

• Min SEG pad pitch: 52um

• Min COM pad pitch: 45um

SSD1305Z

132 64

Gold Bump Die Page 10, 66

•

35mm film, 4 sprocket hole

Folding TAB

8-bit 80 / 8-bit 68 / SPI / I²C interface

SEG lead pitch 0.120mm x 0.998 =0.11976mm

COM lead pitch 0.120mm x 0.998 =0.11976mm

35mm film, 4 sprocket hole

SSD1305T6R1

TAB

Page 13 ,67

Page 15, 69

Folding TAB

8-bit 80 / 8-bit 68 / SPI / I²C interface

SEG lead pitch 0.120mm x 0.998 =0.11976mm

COM lead pitch 0.120mm x 0.998 =0.11976mm

SSD1305T7R1

SSD1305Z3

132 64

Gold Bump Die Page 70

•

Die Thickness : 300 um ± 25 um

Solomon Systech

Oct 2008 P 8/71

Rev 2.0 SSD1305

4

BLOCK DIAGRAM

Figure 4-1 : SSD1305 Block Diagram

SSD1305

Rev 2.0

P 9/71

Oct 2008

Solomon Systech

5

DIE PAD FLOOR PLAN

Figure 5-1 : SSD1305Z Die Drawing

Pad 1

Alignment marks

(For details dimension please see p.9)

Position Size

T shape (-3240, 139) 75um x 75um

+ shape (3240, 139) 75um x 75um

Die Size

8.2mm x 1.2mm

457 um ± 25 um

65 um

Die Thickness

Min I/O pad pitch

Min SEG pad pitch

52 um

Min COM pad pitch 45 um

Bump Height

Nominal 15 um

Bump Size

Pad #

X [um] Y [um]

1, 126, 148, 293

18-109

2-5, 122-125, 149-151, 290-292 50

6-17, 110-121,152-289

127-147, 294-314

94

42

50

70

50

94

32

94

Y

X

SSD1305Z

Pad 1,2,3,…->126

Gold Bumps face up

Solomon Systech

Oct 2008 P 10/71

Rev 2.0 SSD1305

Figure 5-2 : SSD1305Z Alignment Marks Dimension

SSD1305

Rev 2.0

P 11/71

Oct 2008

Solomon Systech

Table 5-1 : SSD1305Z Bump Die Pad Coordinates

Pad no.

1

2

3

4

5

6

7

8

Pad Name

NC

X-pos

-3980.5

-3821.5

-3746.5

-3671.5

-3596.5

-3537.5

-3492.5

-3447.5

-3402.5

-3357.5

-3312.5

Y-pos

-546.0

-524.0

Pad no.

81

82

83

84

85

86

87

88

Pad Name

VDDIO

D0

D1

D2

D3

VSS

D4

D5

D6

D7

VSS

X-pos

1137.5

1202.5

1267.5

1332.5

1397.5

1462.5

1527.5

1592.5

1657.5

1722.5

1787.5

Y-pos

-536.0

Pad no.

161

162

163

164

165

166

167

168

169

170

171

Pad Name

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

X-pos

3117.6

3065.7

3013.7

2961.7

2909.8

2857.8

2805.9

2753.9

2701.9

2650.0

2598.0

Y-pos

479.1

Pad no.

241

242

243

244

245

246

247

248

249

250

251

Pad Name

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

SEG94

SEG95

SEG96

X-pos

-1091.2

-1143.1

-1195.1

-1247.0

-1299.0

-1351.0

-1402.9

-1454.9

-1506.8

-1558.8

-1610.8

Y-pos

479.1

NC

COM53

COM54

COM55

COM56

COM57

COM58

9

10

11

89

90

91

12

13

14

COM59

COM60

COM61

-3267.5

-3222.5

-3177.5

-524.0

92

93

94

CLS

VDDIO

1852.5

1917.5

1982.5

-536.0

172

173

174

SEG17

SEG18

SEG19

2546.1

2494.1

2442.1

479.1

252

253

254

SEG97

SEG98

SEG99

-1662.7

-1714.7

-1766.6

479.1

15

16

17

18

19

20

21

COM62

COM63

NC

-3132.5

-3087.5

-3042.5

-2957.5

-2892.5

-2827.5

-2762.5

-524.0

-536.0

95

96

97

98

99

VDD

2047.5

2112.5

2177.5

2242.5

2307.5

2372.5

2437.5

-536.0

175

176

177

178

179

180

181

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

2390.2

2338.2

2286.3

2234.3

2182.3

2130.4

2078.4

479.1

255

256

257

258

259

260

261

SEG100

SEG101

SEG102

SEG103

SEG104

SEG105

SEG106

-1818.6

-1870.6

-1922.5

-1974.5

-2026.4

-2078.4

-2130.4

479.1

NC

IREF

VCC

VCOMH

VCC

100

101

22

23

24

VCOMH

VLSS

-2697.5

-2632.5

-2567.5

-536.0

102

103

104

VCC

2502.5

2567.5

2632.5

-536.0

182

183

184

SEG27

SEG28

SEG29

2026.5

1974.5

1922.5

479.1

262

263

264

SEG107

SEG108

SEG109

-2182.3

-2234.3

-2286.2

479.1

25

26

27

28

VLSS

VSS

TR11

-2502.5

-2437.5

-2372.5

-2307.5

-536.0

105

106

107

108

VCC

VLSS

2697.5

2762.5

2827.5

2892.5

-536.0

185

186

187

188

SEG30

SEG31

SEG32

SEG33

1870.6

1818.6

1766.7

1714.7

479.1

265

266

267

268

SEG110

SEG111

SEG112

SEG113

-2338.2

-2390.2

-2442.1

-2494.1

479.1

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

TR10

TR9

TR8

TR7

TR6

VSS

TR5

TR4

TR3

TR2

TR1

TR0

VSS

VSSB

GDR

VDDB

FB

VBREF

BGGND

VSS

VDDB

VCIR

VDD

VDDIO

VCC

VDDIO

BS0

-2242.5

-2177.5

-2112.5

-2047.5

-1982.5

-1917.5

-1852.5

-1787.5

-1722.5

-1657.5

-1592.5

-1527.5

-1462.5

-1397.5

-1332.5

-1267.5

-1202.5

-1137.5

-1072.5

-1007.5

-942.5

-877.5

-812.5

-747.5

-682.5

-617.5

-552.5

-487.5

-422.5

-357.5

-292.5

-227.5

-162.5

-97.5

-536.0

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

NC

2957.5

3042.5

3087.5

3132.5

3177.5

3222.5

3267.5

3312.5

3357.5

3402.5

3447.5

3492.5

3537.5

3596.5

3671.5

3746.5

3821.5

3980.5

3856.5

3766.5

3676.5

3585.2

3533.3

3481.3

-536.0

-524.0

-546.0

-468.4

-423.4

-378.4

-333.4

-288.4

-243.4

-198.4

-153.4

-108.4

-63.4

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

1662.7

1610.8

1558.8

1506.9

1454.9

1402.9

1351.0

1299.0

1247.1

1195.1

1143.1

1091.2

1039.2

987.3

935.3

883.3

831.4

779.4

727.5

675.5

623.5

571.6

519.6

467.7

415.7

363.7

259.8

207.9

155.9

103.9

52.0

479.1

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

SEG114

SEG115

SEG116

SEG117

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

SEG126

SEG127

SEG128

SEG129

SEG130

SEG131

NC

-2546.0

-2598.0

-2650.0

-2701.9

-2753.9

-2805.8

-2857.8

-2909.8

-2961.7

-3013.7

-3065.6

-3117.6

-3169.6

-3221.5

-3273.5

-3325.4

-3377.4

-3429.4

-3481.3

-3533.3

-3585.2

-3676.5

-3766.5

-3856.5

-3980.5

479.1

501.1

431.6

386.6

341.6

296.6

251.6

206.6

161.6

116.6

71.6

COM31

COM30

COM29

COM28

COM27

COM26

COM25

COM24

COM23

COM22

COM21

NC

COM20

COM19

COM18

COM17

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

COM8

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

NC

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

-18.4

26.6

71.6

116.6

161.6

206.6

251.6

296.6

341.6

386.6

431.6

501.1

479.1

0.0

-52.0

-103.9

-155.9

-207.8

-259.8

-311.8

-363.7

-415.7

-467.6

-519.6

-571.6

-623.5

-675.5

-727.4

-32.5

32.5

97.5

162.5

227.5

292.5

357.5

422.5

487.5

552.5

617.5

682.5

26.6

-18.4

-63.4

-108.4

-153.4

-198.4

-243.4

-288.4

-333.4

-378.4

-423.4

-468.4

VSS

BS1

VDDIO

BS2

VSS

FR

CL

VSS

NC

75

76

77

78

79

80

CS#

RES#

D/C#

VSS

747.5

812.5

877.5

942.5

1007.5

1072.5

-536.0

155

156

157

158

159

160

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

3429.4

3377.4

3325.5

3273.5

3221.5

3169.6

479.1

235

236

237

238

239

240

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

-779.4

-831.4

-883.3

-935.3

-987.2

-1039.2

479.1

(WR#)

R/W#

E(RD#)

Solomon Systech

Oct 2008 P 12/71

Rev 2.0 SSD1305

6

PIN ARRANGEMENT

6.1 SSD1305T6R1 pin assignment

Figure 6-1 : SSD1305T6R1 Pin Assignment

SSD1305

Rev 2.0

P 13/71

Oct 2008

Solomon Systech

Table 6-1 : SSD1305T6R1 Pin Assignment Table

Pin #

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Name

NC

VCC

VCOMH

IREF

D7

D6

D5

D4

D3

D2

D1

D0

E(RD#)

R/W#

D/C#

RES#

CS#

FR

BS2

BS1

VDDIO

VDD

VCIR

BGGND

VBREF

NC

Pin #

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

Name

SEG123

SEG122

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

SEG99

SEG98

SEG97

SEG96

SEG95

SEG94

SEG93

SEG92

SEG91

SEG90

SEG89

SEG88

SEG87

SEG86

SEG85

SEG84

SEG83

SEG82

SEG81

SEG80

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

Pin #

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Name

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

NC

Pin #

241

242

243

244

245

246

247

248

249

Name

COM50

COM52

COM54

COM56

COM58

COM60

COM62

NC

17

18

19

97

98

99

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

100

101

102

103

104

105

106

107

108

109

110

FB

VDDB

GDR

VSS

NC

111

112

113

NC

COM63

COM61

COM59

COM57

COM55

COM53

COM51

COM49

COM47

COM45

COM43

COM41

COM39

COM37

COM35

COM33

COM31

COM29

COM27

COM25

COM23

COM21

COM19

COM17

COM15

COM13

COM11

COM9

COM7

COM5

COM3

COM1

NC

SEG131

SEG130

SEG129

SEG128

SEG127

SEG126

SEG125

SEG124

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

NC

COM0

COM2

COM4

COM6

COM8

COM10

COM12

COM14

COM16

COM18

COM20

COM22

COM24

COM26

COM28

COM30

COM32

COM34

COM36

COM38

COM40

COM42

COM44

COM46

COM48

Solomon Systech

Oct 2008 P 14/71

Rev 2.0 SSD1305

6.2 SSD1305T7R1 pin assignment

Figure 6-2 : SSD1305T7R1 Pin Assignment

SSD1305

Rev 2.0

P 15/71

Oct 2008

Solomon Systech

Table 6-2 : SSD1305T7R1 Pin Assignment

Pin #

1

2

3

4

5

6

7

8

Name

NC

VCC

VCOMH

IREF

D7

D6

D5

D4

D3

D2

D1

D0

E/RD#

R/W#

D/C#

RES#

CS#

NC

BS2

BS1

VDD

NC

VBREF

NC

FB

VDDB

GDR

VSS

NC

Pin #

81

Name

SEG123

SEG122

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

SEG99

SEG98

SEG97

SEG96

SEG95

SEG94

SEG93

SEG92

SEG91

SEG90

SEG89

SEG88

SEG87

SEG86

SEG85

SEG84

SEG83

SEG82

SEG81

SEG80

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

Pin #

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Name

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

NC

Pin #

241

242

243

244

245

246

247

248

249

Name

COM50

COM52

COM54

COM56

COM58

COM60

COM62

NC

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

NC

COM63

COM61

COM59

COM57

COM55

COM53

COM51

COM49

COM47

COM45

COM43

COM41

COM39

COM37

COM35

COM33

COM31

COM29

COM27

COM25

COM23

COM21

COM19

COM17

COM15

COM13

COM11

COM9

COM7

COM5

COM3

COM1

NC

SEG131

SEG130

SEG129

SEG128

SEG127

SEG126

SEG125

SEG124

NC

COM0

COM2

COM4

COM6

COM8

COM10

COM12

COM14

COM16

COM18

COM20

COM22

COM24

COM26

COM28

COM30

COM32

COM34

COM36

COM38

COM40

COM42

COM44

COM46

COM48

Solomon Systech

Oct 2008 P 16/71

Rev 2.0 SSD1305

7

PIN DESCRIPTION

Key: I = Input, O =Output, IO = Bi-directional (input/output), P = Power pin

Table 7-1 : Pin Description

Pin Name

Pin Type Description

V_DD

P

Power supply pin for core logic operation.

V_DDIO

P

Power supply for interface logic level. It should be match with MCU interface voltage

level. V_DDIOmust always be equal or lower than V_DD

.

V_CC

P

Power supply for panel driving voltage. This is also the most positive power voltage supply

pin.

V_SS

P

O

This is a ground pin.

V_LSS

V_COMH

This is an analog ground pin. It should be connected to V_SSexternally.

The pin for COM signal deselected voltage level.

A capacitor should be connected between this pin and V_SS.

BGGND

V_DDB

V_SSB

P

O

I

This pin must be connected to ground.

This is a reserved pin. It must be connected to V_DD

.

This is a reserved pin. It must be connected to V_SS.

GDR

FB

This is a reserved pin. It should be kept NC (i.e. Float during normal operation).

MCU bus interface selection pins. Please refer to Table 7-2 for the details of setting.

V_BREF

V_CIR

P

O

I

BS[2:0]

I_REF

I

This is segment output current reference pin.

A resistor should be connected between this pin and V_SSto maintain the I_REFcurrent at

10uA. Please refer to Figure 8-18 for the details of resistor value.

FR

CL

O

I

This pin outputs RAM write synchronization signal. Proper timing between MCU data

writing and frame display timing can be achieved to prevent tearing effect.

It should be kept NC if it is not used. Please refer to Section 8.4 for details usage.

This is external clock input pin.

When internal clock is enabled (i.e. HIGH in CLS pin), this pin is not used and should be

connected to V_SS. When internal clock is disabled (i.e. LOW in CLS pin), this pin is the

external clock source input pin.

CLS

I

This is internal clock enable pin. When it is pulled HIGH (i.e. connect to V_DDIO), internal

clock is enabled. When it is pulled LOW, the internal clock is disabled; an external clock

source must be connected to the CL pin for normal operation.

RES#

This pin is reset signal input. When the pin is LOW, initialization of the chip is executed.

Keep this pin HIGH (i.e. connect to V_DDIO) during normal operation.

SSD1305

Rev 2.0

P 17/71

Oct 2008

Solomon Systech

Pin Name

Pin Type Description

CS#

This pin is the chip select input. (active LOW)

I

D/C#

This is Data/Command control pin. When it is pulled HIGH (i.e. connect to V_DDIO), the data

at D[7:0] is treated as data. When it is pulled LOW, the data at D[7:0] will be transferred to

the command register.

In I²C mode, this pin acts as SA0 for slave address selection.

For detail relationship to MCU interface signals, please refer to the Timing Characteristics

Diagrams: Figure 13-1 to Figure 13-5.

E (RD#)

I

When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E)

signal. Read/write operation is initiated when this pin is pulled HIGH (i.e. connect to V_DDIO

and the chip is selected.

)

When connecting to an 8080-microprocessor, this pin receives the Read (RD#) signal. Read

operation is initiated when this pin is pulled LOW and the chip is selected.

When serial interface is selected, this pin must be connected to V_SS.

R/W#(WR#) I

This is read / write control input pin connecting to the MCU interface.

When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write

(R/W#) selection input. Read mode will be carried out when this pin is pulled HIGH (i.e.

connect to V_DDIO) and write mode when LOW.

When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write

operation is initiated when this pin is pulled LOW and the chip is selected.

When serial interface is selected, this pin must be connected to V_SS.

D[7:0]

IO

These are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus.

When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will be

the serial data input: SDIN and D2 should be left opened.

When I²C mode is selected, D2, D1 should be tied together and serve as SDA_out, SDA_inin

application and D0 is the serial clock input, SCL.

TR0-TR11

-

Testing reserved pins. It should be kept NC.

SEG0 ~

SEG131

O

These pins provide Segment switch signals to OLED panel. They are in high impedance

stage when display is OFF.

COM0 ~

COM63

O

-

These pins provide Common switch signals to OLED panel. They are in high impedance

state when display is OFF.

NC

This is dummy pin. Do not group or short NC pins together.

Table 7-2 : MCU Bus Interface Pin Selection

Pin Name I²C

6800-

8080-

Serial

Interface parallel

interface

parallel

interface

(8 bit)

Note

BS0

BS1

BS2

0

1

0

1

0

1

0

⁽¹⁾0 is connected to V_SS

⁽²⁾1 is connected to V_DDIO

Solomon Systech

Oct 2008 P 18/71

Rev 2.0 SSD1305

8

FUNCTIONAL BLOCK DESCRIPTIONS

8.1 MCU Interface selection

SSD1305 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface

mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[2:0] pins

(please refer to Table 7-2 for BS[2:0] setting).

Table 8-1 : MCU interface assignment under different bus interface mode

Pin Name Data/Command Interface

Bus

Control Signal

Interface

8-bit 8080

8-bit 6800

SPI

D7

D6

D5

D4

D3

D[7:0]

D2

D1

D0

E

RD#

E

R/W# CS#

WR# CS#

R/W# CS#

D/C# RES#

SA0 RES#

Tie LOW

NC

SDIN SCLK Tie LOW

CS#

I²C

SDA_OUTSDA_INSCL Tie LOW

8.1.1 MCU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#.

A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.

A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.

The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.

Table 8-2 : Control pins of 6800 interface

Function

E

↓

R/W# CS#

D/C#

L

Write command

Read status

Write data

L

H

L

H

L

H

Read data

H

Note

⁽¹⁾↓ stands for falling edge of signal

H stands for HIGH in signal

L stands for LOW in signal

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline

processing is internally performed which requires the insertion of a dummy read before the first actual display

data read. This is shown in Figure 8-1.

SSD1305

Rev 2.0

P 19/71

Oct 2008

Solomon Systech

Figure 8-1 : Data read back procedure - insertion of dummy read

R/W#

E

N

n

n+1

n+2

Databus

Write column

address

Dummy read

Read 1st data

Read 2nd data

Read 3rd data

8.1.2 MCU Parallel 8080-series Interface

The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#.

A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.

A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.

A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.

Figure 8-2 : Example of Write procedure in 8080 parallel interface mode

CS#

WR#

D[7:0]

D/C#

high

RD#

low

Figure 8-3 : Example of Read procedure in 8080 parallel interface mode

CS#

RD#

D[7:0]

D/C#

high

WR#

low

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Oct 2008 P 20/71

Rev 2.0 SSD1305

Table 8-3 : Control pins of 8080 interface (Form 1)

Function

RD#

H

WR#

CS#

L

D/C#

L

H

Write command

Read status

Write data

Read data

↑

H

↑

H

↑

H

↑

Note

⁽¹⁾↑ stands for rising edge of signal

(2)

H stands for HIGH in signal

L stands for LOW in signal

Refer to Figure 13-2 for Form 1 8080-Series MPU Parallel Interface Timing Characteristics

(3)

(4)

Alternatively, RD# and WR# can be keep stable while CS# serves as the data/command latch signal.

Table 8-4 : Control pins of 8080 interface (Form 2)

Function

RD# WR# CS# D/C#

Write command

Read status

Write data

Read data

H

L

H

L

H

L

H

L

H

↑

L

Note

⁽¹⁾↑ stands for rising edge of signal

⁽²⁾H stands for HIGH in signal

⁽³⁾L stands for LOW in signal

⁽⁴⁾Refer to Figure 13-3 for Form 2 8080-Series MPU Parallel Interface Timing Characteristics

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline

processing is internally performed which requires the insertion of a dummy read before the first actual display

data read. This is shown in Figure 8-4.

Figure 8-4 : Display data read back procedure - insertion of dummy read

WR#

RD#

Databus

N

n

n+1

n+2

Write column

address

Dummy read

Read 1st data

Read 2nd data

Read 3rd data

SSD1305

Rev 2.0

P 21/71

Oct 2008

Solomon Systech

8.1.3 MCU Serial Interface

The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as

SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and

R/W# can be connected to an external ground.

Table 8-5 : Control pins of Serial interface

Note

Function

Write command Tie LOW

Write data Tie LOW

E(RD#)

R/W#(WR#) CS# D/C# D0

⁽¹⁾↑ stands for rising edge of signal

⁽²⁾H stands for HIGH in signal

⁽³⁾L stands for LOW in signal

Tie LOW

L

↑

H

SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C#

is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data

RAM (GDDRAM) or command register in the same clock.

Under serial mode, only write operations are allowed.

Figure 8-5 : Write procedure in SPI mode

CS#

D/C#

SDIN/

SCLK

DB1

DB2

DBn

SCLK(D0)

SDIN(D1)

D7

D6

D5

D4

D3

D2

D1

D0

8.1.4 MCU I²C Interface

The I²C communication interface consists of slave address bit SA0, I²C-bus data signal SDA (SDA_OUT/D₂for

output and SDA_IN/D₁for input) and I²C-bus clock signal SCL (D₀). Both the data and clock signals must be

connected to pull-up resistors. RES# is used for the initialization of device.

a) Slave address bit (SA0)

SSD1305 has to recognize the slave address before transmitting or receiving any information by the

I²C-bus. The device will respond to the slave address following by the slave address bit (“SA0” bit)

and the read/write select bit (“R/W#” bit) with the following byte format,

b₇b₆b₅b₄b₃b₂b₁b₀

0 1 1 1 1 0 SA0 R/W#

“SA0” bit provides an extension bit for the slave address. Either “0111100” or “0111101”, can be

selected as the slave address of SSD1305. D/C# pin acts as SA0 for slave address selection.

“R/W#” bit is used to determine the operation mode of the I²C-bus interface. R/W#=1, it is in read

mode. R/W#=0, it is in write mode.

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Oct 2008 P 22/71

Rev 2.0 SSD1305

b) I²C-bus data signal (SDA)

SDA acts as a communication channel between the transmitter and the receiver. The data and the

acknowledgement are sent through the SDA.

It should be noticed that the ITO track resistance and the pulled-up resistance at “SDA” pin becomes

a voltage potential divider. As a result, the acknowledgement would not be possible to attain a valid

logic 0 level in “SDA”.

“SDA_IN” and “SDA_OUT” are tied together and serve as SDA. The “SDA_IN” pin must be connected to

act as SDA. The “SDA_OUT” pin may be disconnected. When “SDA_OUT” pin is disconnected, the

acknowledgement signal will be ignored in the I²C-bus.

c) I²C-bus clock signal (SCL)

The transmission of information in the I²C-bus is following a clock signal, SCL. Each transmission of

data bit is taken place during a single clock period of SCL.

8.1.4.1 I²C-bus Write data

The I²C-bus interface gives access to write data and command into the device. Please refer to Figure 8-6 for

the write mode of I²C-bus in chronological order.

Figure 8-6 : I²C -bus data format

Note:

Co – Continuation bit

D/C# – Data / Command Selection bit

ACK – Acknowledgement

SA0 – Slave address bit

R/W# – Read / Write Selection bit

S – Start Condition / P – Stop Condition

Write mode

Control byte

Data byte

Control byte

Data byte

0 1 1 1 1 0

0 1 1 1 1

n ≥ 0 bytes

MSB ……………….LSB

Slave Address

1 byte

m ≥ 0 words

0 1 1 1 1 0

SSD1305

Slave Address

0 0 0 0 0 0

Control byte

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Oct 2008

Solomon Systech

8.1.4.2 Write mode for I²C

1) The master device initiates the data communication by a start condition. The definition of the start

condition is shown in Figure 8-7. The start condition is established by pulling the SDA from HIGH to

LOW while the SCL stays HIGH.

2) The slave address is following the start condition for recognition use. For the SSD1305, the slave

address is either “b0111100” or “b0111101” by changing the SA0 to LOW or HIGH (D/C pin acts as

SA0).

3) The write mode is established by setting the R/W# bit to logic “0”.

4) An acknowledgement signal will be generated after receiving one byte of data, including the slave

address and the R/W# bit. Please refer to the Figure 8-8 for the graphical representation of the

acknowledge signal. The acknowledge bit is defined as the SDA line is pulled down during the HIGH

period of the acknowledgement related clock pulse.

5) After the transmission of the slave address, either the control byte or the data byte may be sent across

the SDA. A control byte mainly consists of Co and D/C# bits following by six “0” ‘s.

a. If the Co bit is set as logic “0”, the transmission of the following information will contain

data bytes only.

b. The D/C# bit determines the next data byte is acted as a command or a data. If the D/C# bit is

set to logic “0”, it defines the following data byte as a command. If the D/C# bit is set to logic

“1”, it defines the following data byte as a data which will be stored at the GDDRAM. The

GDDRAM column address pointer will be increased by one automatically after each data

write.

6) Acknowledge bit will be generated after receiving each control byte or data byte.

7) The write mode will be finished when a stop condition is applied. The stop condition is also defined

in Figure 8-7. The stop condition is established by pulling the “SDA in” from LOW to HIGH while

the “SCL” stays HIGH.

Figure 8-7 : Definition of the Start and Stop Condition

t_SSTOP

t_HSTART

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

Solomon Systech

Oct 2008 P 24/71

Rev 2.0 SSD1305

Figure 8-8 : Definition of the acknowledgement condition

DATA OUTPUT

BY TRANSMITTER

Non-acknowledge

DATA OUTPUT

BY RECEIVER

Acknowledge

SCL FROM

MASTER

1

2

8

9

S

Clock pulse for acknowledgement

START

Condition

Please be noted that the transmission of the data bit has some limitations.

1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the “HIGH”

period of the clock pulse. Please refer to the Figure 8-9 for graphical representations. Except in start or

stop conditions, the data line can be switched only when the SCL is LOW.

2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors.

Figure 8-9 : Definition of the data transfer condition

SDA

SCL

Data line is

stable

Change of data

8.2 Command Decoder

This module determines whether the input data is interpreted as data or command. Data is interpreted based

upon the input of the D/C# pin.

If D/C# pin is HIGH, D[7:0] is interpreted as display data written to Graphic Display Data RAM (GDDRAM).

If it is LOW, the input at D[7:0] is interpreted as a command. Then data input will be decoded and written to

the corresponding command register.

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Oct 2008

Solomon Systech

8.3 Oscillator Circuit and Display Time Generator

Figure 8-10 : Oscillator Circuit and Display Time Generator

Internal

Oscillator

Fosc

M

U

X

CLK

DCLK

Divider

Display

Clock

CL

CLS

This module is an on-chip LOW power RC oscillator circuitry. The operation clock (CLK) can be generated

either from internal oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is

pulled HIGH, internal oscillator is chosen and CL should be connected to V_SS. Pulling CLS pin LOW disables

internal oscillator and external clock must be connected to CL pins for proper operation. When the internal

oscillator is selected, its output frequency Fosc can be changed by command D5h A[7:4].

The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D”

can be programmed from 1 to 16 by command D5h

DCLK = F_OSC/ D

The frame frequency of display is determined by the following formula.

F_osc

F_FRM

=

D× K × No.of Mux

where

•

D stands for clock divide ratio. It is set by command D5h A[3:0]. The divide ratio has the range from 1 to

16.

•

K is the number of display clocks per row. The value is derived by

K = Phase 1 period + Phase 2 period + BANK0 pulse width

= 2 + 2 + 50 = 54 at power on reset

(Please refer to Section 8.6 “Segment Drivers / Common Drivers” for the details of the “Phase”)

•

Number of multiplex ratio is set by command A8h. The power on reset value is 63 (i.e. 64MUX).

F

_OSCis the oscillator frequency. It can be changed by command D5h A[7:4]. The higher the register

setting results in higher frequency.

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Oct 2008 P 26/71

Rev 2.0 SSD1305

8.4 FR synchronization

FR synchronization signal can be used to prevent tearing effect.

One frame

FR

100%

Memory

Access

Process

0%

Time

Fast write MCU

Slow write MCU

SSD1305 displaying memory updates to OLED screen

The starting time to write a new image to OLED driver is depended on the MCU writing speed. If MCU can

finish writing a frame image within one frame period, it is classified as fast write MCU. For MCU needs

longer writing time to complete (more than one frame but within two frames), it is a slow write one.

For fast write MCU: MCU should start to write new frame of ram data just after rising edge of FR pulse and

should be finished well before the rising edge of the next FR pulse.

For slow write MCU: MCU should start to write new frame ram data after the falling edge of the 1^stFR pulse

and must be finished before the rising edge of the 3^rdFR pulse.

8.5 Reset Circuit

When RES# input is LOW, the chip is initialized with the following status:

1. Display is OFF

2. 132 x 64 Display Mode

3. Normal segment and display data column address and row address mapping (SEG0 mapped to

address 00h and COM0 mapped to address 00h)

4. Shift register data clear in serial interface

5. Display start line is set at display RAM address 0

6. Column address counter is set at 0

7. Normal scan direction of the COM outputs

8. Contrast control register is set at 80h

9. Normal display mode (Equivalent to A4h command)

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Oct 2008

Solomon Systech

8.6 Segment Drivers / Common Drivers

Segment drivers deliver 132 current sources to drive the OLED panel. The driving current can be adjusted

from 0 to 320uA with 256 steps. Common drivers generate voltage-scanning pulses.

The segment driving waveform is divided into three phases:

1. In phase 1, the OLED pixel charges of previous image are discharged in order to prepare for next

image content display.

2. In phase 2, the OLED pixel is driven to the targeted voltage. The pixel is driven to attain the

corresponding voltage level from V_SS. The period of phase 2 can be programmed in length from 1 to

15 DCLKs. If the capacitance value of the pixel of OLED panel is larger, a longer period is required

to charge up the capacitor to reach the desired voltage.

3. In phase 3, the OLED driver switches to use current source to drive the OLED pixels and this is the

current drive stage. SSD1305 employs PWM (Pulse Width Modulation) method to control the

brightness of area color A, B, C, D color individually. The longer the waveform in current drive

stage is, the brighter is the pixel and vice versa.

Figure 8-11 : Segment Output Waveform in three phases

Longer phase 3 =>

Segment

brighter pixel

V_SS

Time

Phase: 1 2

3

After finishing phase 3, the driver IC will go back to phase 1 to display the next row image data. This three-

step cycle is run continuously to refresh image display on OLED panel.

The length of phase 3 for area colors: A,B,C and monochrome BANK0 can be configured by command 91h

“Set Look Up Table”. There are 64 steps available for each color but the one of color D is fixed at 64. The

unit of the step is in DCLK.

For example, the look up table for area color A, B, is set to 20, 40 DCLKs respectively. Color B is set to be

brighter than color A. Then the result segment output waveform of these two colors is shown below.

Figure 8-12 : Segment Output Waveform for two different colors LUT setting

Color A

Color B

20 DCLKs

40 DCLKs

Segment

44 DCLKs

24 DCLKs

64 DCLKs (fixed)

V_SS

64 DCLKs (fixed)

Time

Solomon Systech

Oct 2008 P 28/71

Rev 2.0 SSD1305

In phase 3, the segment output waveforms under the monochrome mode and area color mode are different.

In monochrome mode, if the length of current drive pulse width is set to 50, after finishing 50 DCLKs in

current drive phase, the driver IC will go back to phase 1 for next row display.

Figure 8-13 : Example of Segment Output Waveform of monochrome display section under monochrome mode

50 DCLKs

Segment

V_SS

Time

In area color mode, the phase 3 of both BANK0 and area color banks (BANK1 to BANK32) are fixed into 64

DCLKs. For instance, if the length of the pulse width is set to 50, then after the end of 50 DCLKs of current

drive phase, the segment waveform will be gone to V_SSlevel and the driver is still in current drive phase.

This phase will be end after 64 DCLKs from the start of the phase is passed. And then the drive goes back to

phase 1 for next row display. Figure 8-14 shows the example of the segment output waveform of area color

display section when the pulse width of area color is set to 50.

Figure 8-14 : Example of Segment Output Waveform of area color display section under area color mode

50 DCLKs

Segment

V_SS

Time

64 DCLKs

(fixed)

64 DCLKs

(fixed)

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Rev 2.0

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Oct 2008

Solomon Systech

8.7 Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is

132 x 64 bits and the RAM is divided into eight pages, from PAGE0 to PAGE7, as shown in Figure 8-15. In

GDDRAM, PAGE0 and PAGE1 are belonged to area color section with resolution 132x16. PAGE2 to

PAGE7 are used for monochrome 132x48 dot matrix display.

Figure 8-15 : GDDRAM pages structure of SSD1305

PAGE0, BANK1

PAGE0, BANK16

PAGE1, BANK32

PAGE1, BANK17

Row re-mapping

PAGE0 (COM 63-COM56)

PAGE0 (COM0-COM7)

PAGE1 (COM 55-COM48)

PAGE2 (COM47-COM40)

PAGE3 (COM39-COM32)

PAGE4 (COM31-COM24)

PAGE1 (COM8-COM15)

PAGE2 (COM16-COM23)

PAGE3 (COM24-COM31)

PAGE4 (COM32-COM39)

PAGE5 (COM40-COM47)

BANK0 (Background)

PAGE2 – PAGE7

PAGE5 (COM23-COM16)

PAGE6 (COM15-COM8)

PAGE6 (COM48–COM55)

PAGE7 (COM56-COM63)

PAGE7 (COM 7-COM0)

SEG0 ---------------------------------------------------------------SEG131

Column re-mapping SEG131 ---------------------------------------------------------------SEG0

When one data byte is written into GDDRAM, all the rows image data of the same page of the current column

are filled (i.e. the whole column (8 bits) pointed by the column address pointer is filled.). Data bit D0 is

written into the top row, while data bit D7 is written into bottom row as shown in Figure 8-16.

Figure 8-16 : Enlargement of GDDRAM (No row re-mapping and column-remapping)

....................

COM16

COM17

LSB D0

:

PAGE2

....................

COM23

MSB D7

Each lattice represents one bit of image data

Solomon Systech

Oct 2008 P 30/71

Rev 2.0 SSD1305

For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software as

shown in Figure 8-15.

For vertical shifting of the display, an internal register storing the display start line can be set to control the

portion of the RAM data to be mapped to the display (command D3h).

8.8 Area Color Decoder

The 132x64 display matrix is divided into 8 pages. The first two pages, PAGE0 and PAGE1, are divided into

32 banks. BANK16 and BANK32 consist of a display area of 12x8 pixels. Other banks (BANK0 to BANK15

& BANK17 to BANK31) have matrices of 8x8 pixels. Each bank can be programmed to any one of the four

colors (color A, B, C and D) as the example shown in Figure 8-17. Detailed operation can be referred to

command 92h in Table 9-1.

Figure 8-17 : Example of area color assignment on a 132x64 OLED panel

BANK1

BANK16

8

12

8

A B C D A A A A A A A A A A D C

C A B C D B B B B B B B B D A

8

B

BANK32

BANK17

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Oct 2008

Solomon Systech

8.9 SEG/COM Driving block

This block is used to derive the incoming power sources into the different levels of internal use voltage and

current.

•

V_CCis the most positive voltage supply.

V

_COMHis the Common deselected level. It is internally regulated.

_LSSis the ground path of the analog and panel current.

I

_REFis a reference current source for segment current drivers I_SEG. The relationship between reference

current and segment current of a color is:

I

_SEG= Contrast / 256 x I_REFx scale factor

in which

the contrast (0~255) is set by Set Contrast command 81h; and

the scale factor is 32 by default.

The magnitude of I_REFis controlled by the value of resistor, which is connected between I_REFpin and

Vss as shown in Figure 8-18. It is recommended to set I_REFto 10uA+/- 2uA so as to achieve I_SEG

320uA at maximum contrast 255.

=

Figure 8-18 : I_REFCurrent Setting by Resistor Value

SSD1305

I

_REF(voltage at

I_REF~ 10uA

R1

this pin =

V_CC– 3)

V_SS

Since the voltage at I_REFpin is V_CC– 3V, the value of resistor R1 can be found as below.

R1 = (Voltage at I_REF– V_SS) / I_REF= (V_CC– 3) / 10uA ≈ 910kΩ for V_CC= 12V.

Solomon Systech

Oct 2008 P 32/71

Rev 2.0 SSD1305

8.10 Power ON and OFF sequence

The following figures illustrate the recommended power ON and power OFF sequence of SSD1305 (assume

V_DDand V_DDIOare at the same voltage level).

Power ON sequence:

1. Power ON V_DD,V_DDIO.

2. After V_DD, V_DDIObecome stable, set RES# pin LOW (logic low) for at least 3us (t₁) ⁽⁴⁾and then HIGH

(logic high).

(1)

3. After set RES# pin LOW (logic low), wait for at least 3us (t₂). Then Power ON V_CC.

4. After V_CCbecome stable, send command AFh for display ON. SEG/COM will be ON after 100ms

(t_AF).

Figure 8-19 : The Power ON sequence

ON V_CCSend AFh command for Display ON

ON V_DD,V_DDIORES#

V

_DD,V_DDIO

GND

t₁

RES#

GND

t₂

V_CC

GND

t_AF

ON

SEG/COM

OFF

Power OFF sequence:

1. Send command AEh for display OFF.

(1), (2), (3)

2. Power OFF V_CC.

3. Wait for t_OFF. Power OFF V_DD,V_DDIO..(where Minimum t_OFF=0ms ⁽⁵⁾, Typical t_OFF=100ms)

Figure 8-20 : The Power OFF sequence

Send command AEh for display OFF OFF V_CC

V_CC

OFF V_DD,V_DDIO

GND

t_OFF

V

_DD,V_DDIO

GND

Note:

⁽¹⁾Since an ESD protection circuit is connected between V_DD, V_DDIOand V_CC, V_CCbecomes lower than V_DDwhenever

V_DD, V_DDIOis ON and V_CCis OFF as shown in the dotted line of V_CCin Figure 8-19 and Figure 8-20.

(2)

V

should be kept float (disable) when it is OFF.

CC

⁽³⁾Power Pins (V_DD, V_CC) can never be pulled to ground under any circumstance.

⁽⁴⁾The register values are reset after t₁.

(5)

V

should not be Power OFF before V_CCPower OFF.

DD

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Oct 2008

Solomon Systech

9

COMMAND TABLE

Table 9-1: Command Table

(D/C#=0, R/W#(WR#) = 0, E(RD#=1) unless specific setting is stated)

Fundamental Command Table

D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

Description

0

00~0F

0

X₃X₂X₁X₀Set Lower Column Set the lower nibble of the column start address

Start Address for

Page Addressing

Mode

register for Page Addressing Mode using X[3:0] as

data bits. The initial display line register is reset to

0000b after RESET.

0

10~1F

0

1

X₃X₂X₁X₀Set Higher Column Set the higher nibble of the column start address

Start Address for

Page Addressing

Mode

register for Page Addressing Mode using X[3:0] as

data bits. The initial display line register is reset to

0000b after RESET.

0

20

A[1:0]

0

*

0

*

1

*

0

*

0

*

0

*

0

Set Memory

A[1:0] = 00b, Horizontal Addressing Mode

A[1:0] = 01b, Vertical Addressing Mode

A[1:0] = 10b, Page Addressing Mode (RESET)

A[1:0] = 11b, Invalid

Addressing Mode

A₁A₀

0

21

0

1

0

1

Set Column Address Setup column start and end address

A[7:0] : Column start address, range : 0-131d,

(RESET=0d)

A[7:0] A₇A₆A₅A₄A₃A₂A₁A₀

B[7:0] B₇B₆B₅B₄B₃B₂B₁B₀

B[7:0]: Column end address, range : 0-131d,

(RESET =131d)

0

22

A[2:0]

B[2:0]

0

*

0

*

1

*

0

*

0

*

0

1

0

Set Page Address

Setup page start and end address

A[2:0] : Page start Address, range : 0-7d, (RESET =

A₂A₁A₀

B₂B₁B₀

0d)

B[2:0] : Page end Address, range : 0-7d, (RESET =

7d)

0

40~7F

0

1

0

X₅X₄X₃X₂X₁X₀Set Display Start LineSet display RAM display start line register from 0-63

using X₅X₃X₂X₁X₀.

Display start line register is reset to 000000b during

RESET.

0

81

0

1 Set Contrast Control Double byte command to select 1 out of 256 contrast

For BANK0

steps. Contrast increases as the value increases.

(RESET = 80h)

A[7:0] A₇A₆A₅A₄A₃A₂A₁A₀

0

82

1

0

1

0

Set Brightness For

Area Color Banks

Double byte command to select 1 out of 256

brightness steps. Brightness increases as the value

increases. (RESET = 80h)

A[7:0] A₇A₆A₅A₄A₃A₂A₁A₀

0

91

1

*

0

*

0

1

0

1 Set Look Up Table Set current drive pulse width of BANK0, Color A, B

(LUT)

and C.

X[5:0]

A[5:0]

B[5:0]

C[5:0]

X₅X₄X₃X₂X₁X₀

A₅A₄A₃A₂A₁A₀

B₅B₄B₃B₂B₁B₀

C₅C₄C₃C₂C₁C₀

BANK0: X[5:0] = 31… 63; for pulse width set to

32 ~ 64 clocks (RESET = 110001b)

Color A: A[5:0] same as above (RESET = 111111b)

Color B: B[5:0] same as above (RESET = 111111b)

Color C: C[5:0] same as above (RESET = 111111b)

Note

⁽¹⁾Color D pulse width is fixed at 64 clocks pulse.

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Oct 2008 P 34/71

Rev 2.0 SSD1305

Fundamental Command Table

D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

Description

0

92

1

0

1

0

1

0

Set Bank Color of

BANK1 to BANK16 the 4 colors : A, B, C and D .

(PAGE0)

Set the bank color of BANK1~BANK16 to any one of

A[7:0] A₇A₆A₅A₄A₃A₂A₁A₀

B[7:0] B₇B₆B₅B₄B₃B₂B₁B₀

C[7:0] C₇C₆C₅C₄C₃C₂C₁C₀

D[7:0] D₇D₆D₅D₄D₃D₂D₁D₀

A[1:0] : 00b, 01b, 10b, or 11b for Color = A, B, C or

D of BANK1

A[3:2] : 00b, 01b, 10b, or 11b for Color = A, B, C or

D of BANK2

:

D[5:4]: 00b, 01b, 10b, or 11b for Color = A, B, C or D

of BANK15

D[7:6]: 00b, 01b, 10b, or 11b for Color = A, B, C or D

of BANK16

0

93

1

0

1

0

1

Set Bank Color of

BANK17~BANK32 of the 4 colors: A, B, C and D.

(PAGE1)

Set the bank color of BANK17~BANK32 to any one

A[7:0] A₇A₆A₅A₄A₃A₂A₁A₀

B[7:0] B₇B₆B₅B₄B₃B₂B₁B₀

C[7:0] C₇C₆C₅C₄C₃C₂C₁C₀

D[7:0] D₇D₆D₅D₄D₃D₂D₁D₀

A[1:0] : 00b, 01b, 10b, or 11b for Color = A, B, C or

D of BANK17

A[3:2] : 00b, 01b, 10b, or 1b1 for Color = A, B, C or

D of BANK18

:

D[5:4]: 00b, 01b, 10b, or 11b for Color = A, B, C or D

of BANK31

D[7:6]: 00b, 01b, 10b, or 11b for Color = A, B, C or D

of BANK32

0

A0/A1

A4/A5

1

0

1

0

1

0

X₀Set Segment Re-map X[0]=0b: column address 0 is mapped to SEG0

(RESET)

X[0]=1b: column address 131 is mapped to SEG0

X₀Entire Display ON X₀=0b: Resume to RAM content display (RESET)

Output follows RAM content

X₀=1b: Entire display ON

Output ignores RAM content

0

A6/A7

1

0

1

0

1

X₀Set Normal/Inverse X[0]=0b: Normal display (RESET)

Display

0 in RAM: OFF in display panel

1 in RAM: ON in display panel

X[0]=1b: inverse display

0 in RAM: ON in display panel

1 in RAM: OFF in display panel

0

A8

A[5:0]

1

*

0

*

1

0

1

0

Set Multiplex Ratio Set MUX ratio to N+1 MUX

N=A[5:0] : from 16MUX to 64MUX, RESET=

A₅A₄A₃A₂A₁A₀

111111b (i.e. 64MUX)

A[5:0] from 0 to 14 are invalid entry.

0

AA

1

0

1

0

1

0

1

0

1

Reserved

0

AB

A[3:0]

1

*

0

*

1

*

0

*

Dim mode setting

A[3:0] : Reserved (set as 0000b)

B [7:0] : Set contrast for BANK0, valid range 0-255d,

please refer to command 81h

C [7:0] : Set brightness for color bank, valid range 0-

255d, please refer to command 82h

A₃A₂A₁A₀

B[7:0] B₇B₆B₅B₄B₃B₂B₁B₀

C[7:0] C₇C₆C₅C₄C₃C₂C₁C₀

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Fundamental Command Table

D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

Description

0

AD

A[7:0]

1

0

1

0

1

0

1

A₀

Master Configuration A[0]=0b, Select external V_CCsupply (RESET)

A[0]=1b, Reserved

0

AC

AE

AF

1

0

1

0

1

A₁A₀Set Display ON/OFF ACh = Display ON in dim mode

AEh = Display OFF (sleep mode) (RESET)

AFh = Display ON in normal mode

0

B0~B7

C0/C8

1

0

1

0

1

0

X₂X₁X₀Set Page Start

Address for Page

Set GDDRAM Page Start Address (PAGE0~PAGE7)

for Page Addressing Mode using X[2:0].

Addressing Mode

X₃

0

Set COM Output

Scan Direction

X[3]=0b: normal mode (RESET) Scan from COM0 to

COM[N –1]

X[3]=1b: remapped mode. Scan from COM[N~1] to

COM0

Where N is the Multiplex ratio.

0

D3

A[5:0]

1

*

1

*

0

1

0

1

Set Display Offset

Set vertical shift by COM from 0~63.

The value is reset to 00h after RESET.

A₅A₄A₃A₂A₁A₀

0

D5

1

0

1

0

1

0

1

Set Display Clock

Divide

A[3:0] : Define the divide ratio (D) of the display

clocks (DCLK):

A[7:0] A₇A₆A₅A₄A₃A₂A₁A₀

Ratio/Oscillator

Frequency

Divide ratio= A[3:0] + 1, RESET is 0000b

(divide ratio = 1)

A[7:4] : Set the Oscillator Frequency, F_OSC. Oscillator

Frequency increases with the value of

A[7:4] and vice versa. RESET is 0111b

Range:0000b~1111b

Frequency increases as setting value increases.

Refer to section 10.1.23 for details.

0

D8

D9

1

0

1

0

1

0

X₂

0

X₀

Set Area Color Mode X[5:4]= 00b (RESET) : monochrome mode

ON/OFF & Low

X[5:4]= 11b Area Color enable

X₅X₄

Power Display Mode

X[2]=0b and X[0]=0b: Normal power mode(RESET)

X[2]=1b and X[0]=1b: Set low power display mode

0

1

0

1

0

1

Set Pre-charge Period A[3:0] : Phase 1 period of up to 15 DCLK clocks

(RESET=2h); 0 is invalid entry

A[7:0] A₇A₆A₅A₄A₃A₂A₁A₀

A[7:4] : Phase 2 period of up to 15 DCLK clocks

(RESET=2h); 0 is invalid entry

0

DA

1

0

1

0

1

0

1

0

Set COM Pins

Hardware

Configuration

X[4]=0b, Sequential COM pin configuration

X[4]=1b(RESET), Alternative COM pin configuration

X₅X₄

X[5]=0b(RESET), Disable COM Left/Right remap

X[5]=1b, Enable COM Left/Right remap

Please refer to Table 10-3 for details.

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Fundamental Command Table

D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

Description

0

DB

A[5:2]

1

0

1

0

1

0

1

0

1

0

Set V_COMHDeselect

Level

A[5:2] Hex

V _COMHdeselect level

A₅A₄A₃A₂

code

0000b 00h

~ 0.43 x V_CC

1101b 34h

1111b 3Ch

~ 0.77 x V_CC(RESET)

~ 0.83 x V_CC

0

E0

1

0

Enter Read Modify Enter the Read Modify Write mode.

Write

Details please refer to section 10.1.28.

0

E3

EE

1

0

1

0

1

0

NOP

Command for no operation

Exit Read Modify

Write

Exit the Read Modify Write mode (Please refer to

command E0h)

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Graphic Acceleration Command Table

D/C#Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

Description

0

26/27

0

*

0

*

1

*

0

*

0

*

1

X₀Horizontal Scroll X[0]=0, Right Horizontal Scroll

Setup

X[0]=1, Left Horizontal Scroll

A[2:0]

B[2:0]

C[2:0]

D[2:0]

A₂

B₂

C₂

D₂

A₁

B₁

C₁

D₁

A₀

B₀

C₀

D₀

A[2:0] : Set number of column scroll offset

000b No horizontal scroll

001b Horizontal scroll by 1 column

010b Horizontal scroll by 2 columns

011b Horizontal scroll by 3 columns

100b Horizontal scroll by 4 columns

Other values are invalid.

B[2:0] : Define start page address

000b – PAGE0 011b – PAGE3 110b – PAGE6

001b – PAGE1 100b – PAGE4 111b – PAGE7

010b – PAGE2 101b – PAGE5

C[2:0] : Set time interval between each scroll step in

terms of frame frequency

000b – 6 frames

001b – 32 frames

010b – 64 frames

011b – 128 frames

100b – 3 frames

101b – 4 frames

110b – 2 frame

111b – Invalid

D[2:0] : Define end page address

000b – PAGE0 011b – PAGE3 110b – PAGE6

001b – PAGE1 100b – PAGE4 111b – PAGE7

010b – PAGE2 101b – PAGE5

The value of D[2:0] must be larger or equal

to B[2:0]

0

29/2A

A[2:0]

B[2:0]

C[2:0]

D[2:0]

E[5:0]

0

*

0

*

1

*

0

*

1

*

0

X₁

A₁

B₁

C₁

D₁

E₁

X₀Continuous

X₁X₀=01b : Vertical and Right Horizontal Scroll

X₁X₀=10b : Vertical and Left Horizontal Scroll

Vertical and

Horizontal Scroll

Setup

A₂

B₂

C₂

D₂

E₂

A₀

B₀

C₀

D₀

E₀

A[2:0] : Set number of column scroll offset

000b No horizontal scroll

001b Horizontal scroll by 1 column

010b Horizontal scroll by 2 columns

011b Horizontal scroll by 3 columns

100b Horizontal scroll by 4 columns

Other values are invalid.

E₅E₄E₃

B[2:0] : Define start page address

000b – PAGE0 011b – PAGE3 110b – PAGE6

001b – PAGE1 100b – PAGE4 111b – PAGE7

010b – PAGE2 101b – PAGE5

C[2:0] : Set time interval between each scroll step in

terms of frame frequency

000b – 6 frames

001b – 32 frames

010b – 64 frames

011b – 128 frames

100b – 3 frames

101b – 4 frames

110b – 2 frame

111b – Invalid

D[2:0] : Define end page address

000b – PAGE0 011b – PAGE3 110b – PAGE6

001b – PAGE1 100b – PAGE4 111b – PAGE7

010b – PAGE2 101b – PAGE5

The value of D[2:0] must be larger or equal

to B[2:0]

E[5:0] : Vertical scrolling offset

e.g. E[5:0]= 01h refer to offset =1 row

E[5:0] =3Fh refer to offset =63 rows

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Oct 2008 P 38/71

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Graphic Acceleration Command Table

D/C#Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

Description

0

2E

0

1

0

1

0

Deactivate scroll Stop scrolling that is configured by command

26h/27h/29h/2Ah.

Note

(1)

After sending 2Eh command to deactivate the scrolling

action, the ram data needs to be rewritten.

0

2F

0

1

0

1

Activate scroll

Start scrolling that is configured by the scrolling setup

commands :26h/27h/29h/2Ah with the following valid

sequences:

Valid command sequence 1: 26h ;2Fh.

Valid command sequence 2: 27h ;2Fh.

Valid command sequence 3: 29h ;2Fh.

Valid command sequence 4: 2Ah ;2Fh.

For example, if “26h; 2Ah; 2Fh.” commands are

issued, the setting in the last scrolling setup command,

i.e. 2Ah in this case, will be executed. In other words,

setting in the last scrolling setup command overwrites

the setting in the previous scrolling setup commands.

0

A3

A[5:0]

B[6:0]

1

*

0

*

1

0

A₂

B₂

1

A₁

B₁

1

A₀

B₀

Set Vertical ScrollA[5:0] : Set No. of rows in top fixed area. The No. of

Area

A₅A₄A₃

rows in top fixed area is referenced to the

B₆B₅B₄B₃

top of the GDDRAM (i.e. row 0).[RESET =

0]

B[6:0] : Set No. of rows in scroll area. This is the

number of rows to be used for vertical

scrolling. The scroll area starts in the first

row below the top fixed area. [RESET = 64]

Note

⁽¹⁾A[5:0]+B[6:0] <= MUX ratio

(2)

B[6:0] <= MUX ratio

^(3a)Vertical scrolling offset (E[5:0] in 29h/2Ah) <

B[6:0]

^(3b)Set Display Start Line (X5X4X3X2X1X0 of

40h~7Fh) < B[6:0]

⁽⁴⁾The last row of the scroll area shifts to the first row

of the scroll area.

⁽⁵⁾For 64d MUX display

A[5:0] = 0, B[6:0]=64 : whole area scrolls

A[5:0]= 0, B[6:0] < 64 : top area scrolls

A[5:0] + B[6:0] < 64 : central area scrolls

A[5:0] + B[6:0] = 64 : bottom area scrolls

Please refer to Figure 10-14 for details.

Note

⁽¹⁾“*” stands for “Don’t care”.

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Table 9-2 : Read Command Table

Description

Bit Pattern

Command

D₇D₆D₅D₄D₃D₂D₁D₀

D[7] : Reserve

Status Register Read

D[6] : “1” for display OFF / “0” for display ON

D[5] _:Reserve

D[4]

D[3]

D[2]

D[1]

D[0]

Reserve

:

Note

⁽¹⁾Patterns other than those given in the Command Table are prohibited to enter the chip as a command; as unexpected

results can occur.

9.1 Data Read / Write

To read data from the GDDRAM, select HIGH for both the R/W# (WR#) pin and the D/C# pin for 6800-

series parallel mode and select LOW for the E (RD#) pin and HIGH for the D/C# pin for 8080-series parallel

mode. No data read is provided in serial mode operation.

In normal data read mode the GDDRAM column address pointer will be increased automatically by one after

each data read.

Also, a dummy read is required before the first data read.

To write data to the GDDRAM, select LOW for the R/W# (WR#) pin and HIGH for the D/C# pin for both

6800-series parallel mode and 8080-series parallel mode. The serial interface mode is always in write mode.

The GDDRAM column address pointer will be increased automatically by one after each data write.

Table 9-3 : Address increment table (Automatic)

D/C#

R/W# (WR#)

Comment

Address Increment

0

1

0

1

0

1

Write Command

Read Status

Write Data

No

Yes

Read Data

Yes ⁽¹⁾

Note

⁽¹⁾If read-data command is issued in read-modify-write mode no address increase occurs.

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10 COMMAND DESCRIPTIONS

10.1 Fundamental Command

10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh)

This command specifies the lower nibble of the 8-bit column start address for the display data RAM under

Page Addressing Mode. The column address will be incremented by each data access. Please refer to Section

Table 9-1 and Section 10.1.3 for details.

10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh)

This command specifies the higher nibble of the 8-bit column start address for the display data RAM under

Page Addressing Mode. The column address will be incremented by each data access. Please refer to Section

Table 9-1 and Section 10.1.3 for details.

10.1.3 Set Memory Addressing Mode (20h)

There are 3 different memory addressing mode in SSD1305: page addressing mode, horizontal addressing

mode and vertical addressing mode. This command sets the way of memory addressing into one of the above

three modes. In there, “COL” means the graphic display data RAM column.

Page addressing mode (A[1:0]=10xb)

In page addressing mode, after the display RAM is read/written, the column address pointer is increased

automatically by 1. If the column address pointer reaches column end address, the column address pointer is

reset to column start address and page address pointer is not changed. Users have to set the new page and

column addresses in order to access the next page RAM content The sequence of movement of the PAGE and

column address point for page addressing mode is shown in Figure 10-1.

Figure 10-1 : Address Pointer Movement of Page addressing mode

COL0

:

COL 1

:

…..

:

COL 130 COL 131

PAGE0

PAGE1

:

PAGE6

PAGE7

In normal display data RAM read or write and page addressing mode, the following steps are required to

define the starting RAM access pointer location:

•

Set the page start address of the target display location by command B0h to B7h.

Set the lower start column address of pointer by command 00h~0Fh.

Set the upper start column address of pointer by command 10h~1Fh.

For example, if the page address is set to B2h, lower column address is 03h and upper column address is 10h,

then that means the starting column is SEG3 of PAGE2. The RAM access pointer is located as shown in

Figure 10-2. The input data byte will be written into RAM position of column 3.

Figure 10-2 : Example of GDDRAM access pointer setting in Page Addressing Mode (No row and column-

remapping)

SEG0

SEG3 (Starting column)

SEG131

RAM access pointer

COM16

COM17

LSB D0

Each lattice represents

one bit of image data

:

PAGE2

(Starting page)

....................

COM23

MSB D7

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Horizontal addressing mode (A[1:0]=00b)

In horizontal addressing mode, after the display RAM is read/written, the column address pointer is increased

automatically by 1. If the column address pointer reaches column end address, the column address pointer is

reset to column start address and page address pointer is increased by 1. The sequence of movement of the

page and column address point for horizontal addressing mode is shown in Figure 10-3. When both column

and page address pointers reach the end address, the pointers are reset to column start address and page start

address (Dotted line in Figure 10-3.)

Figure 10-3 : Address Pointer Movement of Horizontal addressing mode

COL0

COL 1

…..

COL 130 COL 131

PAGE0

PAGE1

:

PAGE6

PAGE7

Vertical addressing mode: (A[1:0]=01b)

In vertical addressing mode, after the display RAM is read/written, the page address pointer is increased

automatically by 1. If the page address pointer reaches the page end address, the page address pointer is reset

to page start address and column address pointer is increased by 1. The sequence of movement of the page

and column address point for vertical addressing mode is shown in Figure 10-4. When both column and page

address pointers reach the end address, the pointers are reset to column start address and page start address

(Dotted line in Figure 10-4.)

Figure 10-4 : Address Pointer Movement of Vertical addressing mode

COL0

COL 1

…..

:

COL 130 COL 131

PAGE0

PAGE1

:

PAGE6

PAGE7

…..

In normal display data RAM read or write and horizontal / vertical addressing mode, the following steps are

required to define the RAM access pointer location:

•

Set the column start and end address of the target display location by command 21h.

Set the page start and end address of the target display location by command 22h.

Example is shown in Figure 10-5.

10.1.4 Set Column Address (21h)

This triple byte command specifies column start address and end address of the display data RAM. This

command also sets the column address pointer to column start address. This pointer is used to define the

current read/write column address in graphic display data RAM. If horizontal address increment mode is

enabled by command 20h, after finishing read/write one column data, it is incremented automatically to the

next column address. Whenever the column address pointer finishes accessing the end column address, it is

reset back to start column address and the row address is incremented to the next row.

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10.1.5 Set Page Address (22h)

This triple byte command specifies page start address and end address of the display data RAM. This

command also sets the page address pointer to page start address. This pointer is used to define the current

read/write page address in graphic display data RAM. If vertical address increment mode is enabled by

command 20h, after finishing read/write one page data, it is incremented automatically to the next page

address. Whenever the page address pointer finishes accessing the end page address, it is reset back to start

page address.

The figure below shows the way of column and page address pointer movement through the example: column

start address is set to 2 and column end address is set to 129, page start address is set to 1 and page end

address is set to 6; Horizontal address increment mode is enabled by command 20h. In this case, the graphic

display data RAM column accessible range is from column 2 to column 129 and from page 1 to page 6 only.

In addition, the column address pointer is set to 2 and page address pointer is set to 1. After finishing

read/write one pixel of data, the column address is increased automatically by 1 to access the next RAM

location for next read/write operation (solid line in Figure 10-5). Whenever the column address pointer

finishes accessing the end column 129, it is reset back to column 2 and page address is automatically

increased by 1 (solid line in Figure 10-5). While the end page 6 and end column 129 RAM location is

accessed, the page address is reset back to 1 and the column address is reset back to 2 (dotted line in Figure

10-5). .

Figure 10-5 : Example of Column and Row Address Pointer Movement

Col 0

Col 1

Col 2

…..

……. Col 129 Col 130 Col 131

PAGE0

PAGE1

:

PAGE6

PAGE7

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10.1.6 Set Display Start Line (40h~7Fh)

This command sets the Display Start Line register to determine starting address of display RAM, by selecting

a value from 0 to 63. With value equal to 0, RAM row 0 is mapped to COM0. With value equal to 1, RAM

row 1 is mapped to COM0 and so on.

Refer to Table 10-1 for more illustrations.

10.1.7 Set Contrast Control for BANK0 (81h)

This command sets the Contrast Setting of the display. The chip has 256 contrast steps from 00h to FFh. The

segment output current increases as the contrast step value increases. See Figure 10-6 below.

Figure 10-6 : Segment current vs Contrast setting

Segment current vs Contrast setting

350

300

250

Segment output current setting:

Current (uA)

200

Iseg = Cr/256 x I_REFx scale factor

Where:

150

Cr is contrast step

I_REFis reference current equals 10uA

Scale factor =32

100

50

0

00 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF

Contrast setting

10.1.8 Set Brightness for Area Color Banks (82h)

This command sets the Brightness Setting of the display for the area color banks. The chip has 256 brightness

steps from 00h to FFh. The segment output current increases as the brightness step value increases.

This setting does not affect the contrast of BANK0, which is set by command 81h.

10.1.9 Set Look Up Table (LUT) (91h)

The SSD1305 provides 4 color settings - Colors A, B, C and D for the bank color of BANK1 to BANK32

under the area color mode. The color intensity (or grey scale) is defined by the current drive pulse width. This

pulse width setting must be stored in the Look Up Table (LUT). The pulse width of colors A, B, C is

programmable from 32 to 64 DCLKs. The color D is fixed at 64 DCLKs pulse width. For the grey scale in

BANK0, the pulse width is programmable from 32 to 64 DCLKs. Please refer to 91h command in Table 9-1

for details of the LUT setting.

After setting the pulse widths for the color of A, B, C, D and BANK0, the next step is to define the color of

each display area. Each bank can be programmable to any one of the 4 colors (A, B, C and D). The user can

use 92h and 93h commands for the bank color setting. It should be notice that this is only applicable in area

color mode.

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10.1.10 Set Bank Color of BANK1 to BANK16 (PAGE0) (92h)

This command maps the bank color (pulse width) of BANK1~BANK16 to any one of the 4 colors: A, B, C

and D. For details of the setting, please refer to 92h command in Table 9-1.

10.1.11 Set Bank Color of BANK17 to BANK32 (PAGE0) (93h)

This command maps the bank color (pulse width) of BANK17~BANK32 to any one of the 4 colors: A, B, C

and D. For details of the setting, please refer to 93h command in Table 9-1.

10.1.12 Set Segment Re-map (A0h/A1h)

This command changes the mapping between the display data column address and the segment driver. It

allows flexibility in OLED module design. Please refer to Table 9-1.

This command only affects subsequent data input. Data already stored in GDDRAM will have no changes.

10.1.13 Entire Display ON (A4h/A5h)

A4h command enable display outputs according to the GDDRAM contents.

If A5h command is issued, then by using A4h command, the display will resume to the GDDRAM contents.

In other words, A4h command resumes the display from entire display “ON” stage.

A5h command forces the entire display to be “ON”, regardless of the contents of the display data RAM.

10.1.14 Set Normal/Inverse Display (A6h/A7h)

This command sets the display to be either normal or inverse. In normal display a RAM data of 1 indicates an

“ON” pixel while in inverse display a RAM data of 0 indicates an “ON” pixel.

10.1.15 Set Multiplex Ratio (A8h)

This command switches the default 63 multiplex mode to any multiplex ratio, ranging from 16 to 63. The

output pads COM0~COM63 will be switched to the corresponding COM signal.

10.1.16 Reserved (AAh)

This command is reserved.

10.1.17 Dim Mode setting (ABh)

This command contains multiple bits to configure the contrast and brightness of color bank for the display in

dim mode. The brightness setting of color bank can be set different to normal mode (AFh). The display can be

set in dim mode through command ACh.

10.1.18 Master Configuration (ADh)

This command selects the external V_CCpower supply by default. As external V_CCpower supply is selected,

external V_CCpower should be connected to the V_CCpin.

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Oct 2008

Solomon Systech

10.1.19 Set Display ON/OFF (ACh/AEh/AFh)

These single byte commands are used to turn the OLED panel display ON or OFF.

When the display is ON, the selected circuits by Set Master Configuration command will be turned ON.

When the display is OFF, those circuits will be turned OFF and the segment and common output are in high

impedance state.

These commands set the display to one of the three states:

o

ACh : Dim Mode Display ON

AEh : Display OFF

AFh : Normal Brightness Display ON

where the dim mode settings are controlled by command ABh.

Figure 10-7 :Transition between different modes

Normal mode

AFh

AEh

ACh

AEh

ACh

Dim mode

Sleep mode

10.1.20 Set Page Start Address for Page Addressing Mode (B0h~B7h)

This command positions the page start address from 0 to 7 in GDDRAM under Page Addressing Mode.

Please refer to Table 9-1 and Section 10.1.3 for details.

10.1.21 Set COM Output Scan Direction (C0h/C8h)

This command sets the scan direction of the COM output, allowing layout flexibility in the OLED module

design. Additionally, the display will show once this command is issued. For example, if this command is

sent during normal display then the graphic display will be vertically flipped immediately. Please refer to

Table 10-3 for details.

10.1.22 Set Display Offset (D3h)

This is a double byte command. The second command specifies the mapping of the display start line to one of

COM0~COM63 (assuming that COM0 is the display start line then the display start line register is equal to 0).

For example, to move the COM16 towards the COM0 direction by 16 lines the 6-bit data in the second byte

should be given as 010000b. To move in the opposite direction by 16 lines the 6-bit data should be given by

64 – 16, so the second byte would be 100000b.

The following two tables (Table 10-1, Table 10-2) show the example of setting the command C0h/C8h and

D3h.

Solomon Systech

Oct 2008 P 46/71

Rev 2.0 SSD1305

Table 10-1 : Example of Set Display Offset and Display Start Line with no Remap

Output

64

56

Set MUX ratio(A8h)

Normal

0

Normal

8

0

Normal

0

8

Normal

0

Normal

8

0

Normal

0

8

COM Normal / Remapped (C0h / C8h)

Display offset (D3h)

Display start line (40h - 7Fh)

Hardware

pin name

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

Row0

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

RAM8

RAM9

Row8

Row9

RAM8

RAM9

Row0

Row1

RAM8

RAM9

Row0

Row1

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

RAM8

RAM9

Row8

Row9

RAM8

RAM9

Row0

Row1

RAM8

RAM9

Row1

Row2

Row3

Row4

Row5

Row6

Row7

Row8

Row9

Row10 RAM10 Row2

Row11 RAM11 Row3

Row12 RAM12 Row4

Row13 RAM13 Row5

Row14 RAM14 Row6

Row15 RAM15 Row7

Row16 RAM16 Row8

Row17 RAM17 Row9

RAM10 Row2

RAM11 Row3

RAM12 Row4

RAM13 Row5

RAM14 Row6

RAM15 Row7

RAM16 Row8

RAM17 Row9

Row10 RAM10 Row2 RAM10

Row11 RAM11 Row3 RAM11

Row12 RAM12 Row4 RAM12

Row13 RAM13 Row5 RAM13

Row14 RAM14 Row6 RAM14

Row15 RAM15 Row7 RAM15

Row16 RAM16 Row8 RAM16

Row17 RAM17 Row9 RAM17

COM10 Row10 RAM10 Row18 RAM18 Row10 RAM18 Row10 RAM10 Row18 RAM18 Row10 RAM18

COM11 Row11 RAM11 Row19 RAM19 Row11 RAM19 Row11 RAM11 Row19 RAM19 Row11 RAM19

COM12 Row12 RAM12 Row20 RAM20 Row12 RAM20 Row12 RAM12 Row20 RAM20 Row12 RAM20

COM13 Row13 RAM13 Row21 RAM21 Row13 RAM21 Row13 RAM13 Row21 RAM21 Row13 RAM21

COM14 Row14 RAM14 Row22 RAM22 Row14 RAM22 Row14 RAM14 Row22 RAM22 Row14 RAM22

COM15 Row15 RAM15 Row23 RAM23 Row15 RAM23 Row15 RAM15 Row23 RAM23 Row15 RAM23

COM16 Row16 RAM16 Row24 RAM24 Row16 RAM24 Row16 RAM16 Row24 RAM24 Row16 RAM24

COM17 Row17 RAM17 Row25 RAM25 Row17 RAM25 Row17 RAM17 Row25 RAM25 Row17 RAM25

COM18 Row18 RAM18 Row26 RAM26 Row18 RAM26 Row18 RAM18 Row26 RAM26 Row18 RAM26

COM19 Row19 RAM19 Row27 RAM27 Row19 RAM27 Row19 RAM19 Row27 RAM27 Row19 RAM27

COM20 Row20 RAM20 Row28 RAM28 Row20 RAM28 Row20 RAM20 Row28 RAM28 Row20 RAM28

COM21 Row21 RAM21 Row29 RAM29 Row21 RAM29 Row21 RAM21 Row29 RAM29 Row21 RAM29

COM22 Row22 RAM22 Row30 RAM30 Row22 RAM30 Row22 RAM22 Row30 RAM30 Row22 RAM30

COM23 Row23 RAM23 Row31 RAM31 Row23 RAM31 Row23 RAM23 Row31 RAM31 Row23 RAM31

COM24 Row24 RAM24 Row32 RAM32 Row24 RAM32 Row24 RAM24 Row32 RAM32 Row24 RAM32

COM25 Row25 RAM25 Row33 RAM33 Row25 RAM33 Row25 RAM25 Row33 RAM33 Row25 RAM33

COM26 Row26 RAM26 Row34 RAM34 Row26 RAM34 Row26 RAM26 Row34 RAM34 Row26 RAM34

COM27 Row27 RAM27 Row35 RAM35 Row27 RAM35 Row27 RAM27 Row35 RAM35 Row27 RAM35

COM28 Row28 RAM28 Row36 RAM36 Row28 RAM36 Row28 RAM28 Row36 RAM36 Row28 RAM36

COM29 Row29 RAM29 Row37 RAM37 Row29 RAM37 Row29 RAM29 Row37 RAM37 Row29 RAM37

COM30 Row30 RAM30 Row38 RAM38 Row30 RAM38 Row30 RAM30 Row38 RAM38 Row30 RAM38

COM31 Row31 RAM31 Row39 RAM39 Row31 RAM39 Row31 RAM31 Row39 RAM39 Row31 RAM39

COM32 Row32 RAM32 Row40 RAM40 Row32 RAM40 Row32 RAM32 Row40 RAM40 Row32 RAM40

COM33 Row33 RAM33 Row41 RAM41 Row33 RAM41 Row33 RAM33 Row41 RAM41 Row33 RAM41

COM34 Row34 RAM34 Row42 RAM42 Row34 RAM42 Row34 RAM34 Row42 RAM42 Row34 RAM42

COM35 Row35 RAM35 Row43 RAM43 Row35 RAM43 Row35 RAM35 Row43 RAM43 Row35 RAM43

COM36 Row36 RAM36 Row44 RAM44 Row36 RAM44 Row36 RAM36 Row44 RAM44 Row36 RAM44

COM37 Row37 RAM37 Row45 RAM45 Row37 RAM45 Row37 RAM37 Row45 RAM45 Row37 RAM45

COM38 Row38 RAM38 Row46 RAM46 Row38 RAM46 Row38 RAM38 Row46 RAM46 Row38 RAM46

COM39 Row39 RAM39 Row47 RAM47 Row39 RAM47 Row39 RAM39 Row47 RAM47 Row39 RAM47

COM40 Row40 RAM40 Row48 RAM48 Row40 RAM48 Row40 RAM40 Row48 RAM48 Row40 RAM48

COM41 Row41 RAM41 Row49 RAM49 Row41 RAM49 Row41 RAM41 Row49 RAM49 Row41 RAM49

COM42 Row42 RAM42 Row50 RAM50 Row42 RAM50 Row42 RAM42 Row50 RAM50 Row42 RAM50

COM43 Row43 RAM43 Row51 RAM51 Row43 RAM51 Row43 RAM43 Row51 RAM51 Row43 RAM51

COM44 Row44 RAM44 Row52 RAM52 Row44 RAM52 Row44 RAM44 Row52 RAM52 Row44 RAM52

COM45 Row45 RAM45 Row53 RAM53 Row45 RAM53 Row45 RAM45 Row53 RAM53 Row45 RAM53

COM46 Row46 RAM46 Row54 RAM54 Row46 RAM54 Row46 RAM46 Row54 RAM54 Row46 RAM54

COM47 Row47 RAM47 Row55 RAM55 Row47 RAM55 Row47 RAM47 Row55 RAM55 Row47 RAM55

COM48 Row48 RAM48 Row56 RAM56 Row48 RAM56 Row48 RAM48

COM49 Row49 RAM49 Row57 RAM57 Row49 RAM57 Row49 RAM49

COM50 Row50 RAM50 Row58 RAM58 Row50 RAM58 Row50 RAM50

COM51 Row51 RAM51 Row59 RAM59 Row51 RAM59 Row51 RAM51

COM52 Row52 RAM52 Row60 RAM60 Row52 RAM60 Row52 RAM52

COM53 Row53 RAM53 Row61 RAM61 Row53 RAM61 Row53 RAM53

COM54 Row54 RAM54 Row62 RAM62 Row54 RAM62 Row54 RAM54

COM55 Row55 RAM55 Row63 RAM63 Row55 RAM63 Row55 RAM55

-

Row48 RAM56

Row49 RAM57

Row50 RAM58

Row51 RAM59

Row52 RAM60

Row53 RAM61

Row54 RAM62

Row55 RAM63

COM56 Row56 RAM56

COM57 Row57 RAM57

COM58 Row58 RAM58

COM59 Row59 RAM59

COM60 Row60 RAM60

COM61 Row61 RAM61

COM62 Row62 RAM62

COM63 Row63 RAM63

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

Row56 RAM0

Row57 RAM1

Row58 RAM2

Row59 RAM3

Row60 RAM4

Row61 RAM5

Row62 RAM6

Row63 RAM7

-

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

-

Display

examples

(a)

(b)

(c)

(d)

(e)

(f)

(a)

(e)

(b)

(c)

(d)

(RAM)

(f)

SSD1305

Rev 2.0

P 47/71

Oct 2008

Solomon Systech

Table 10-2 :Example of Set Display Offset and Display Start Line with Remap

Output

64

Remap

0

64

Remap

8

0

64

Remap

0

8

48

Remap

0

48

Remap

8

0

48

Remap

0

8

48

Remap

8

Set MUX ratio(A8h)

COM Normal / Remapped (C0h / C8h)

Display offset (D3h)

Hardw are

pin name

COM0

COM1

COM2

COM3

COM4

COM5

COM6

16

Display start line (40h - 7Fh)

Row 63

RAM63

RAM62

RAM61

RAM60

RAM59

RAM58

RAM57

RAM56

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

Row 63

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

Row 47

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

RAM8

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

-

Row 47

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

RAM8

-

Row 62

Row 61

Row 60

Row 59

Row 58

Row 57

Row 56

Row 55

Row 54

Row 53

Row 52

Row 51

Row 50

Row 49

Row 48

Row 47

Row 46

Row 45

Row 44

Row 43

Row 42

Row 41

Row 40

Row 39

Row 38

Row 37

Row 36

Row 35

Row 34

Row 33

Row 32

Row 31

Row 30

Row 29

Row 28

Row 27

Row 26

Row 25

Row 24

Row 23

Row 22

Row 21

Row 20

Row 19

Row 18

Row 17

Row 16

Row 15

Row 14

Row 13

Row 12

Row 11

Row 10

Row 9

Row 62

Row 61

Row 60

Row 59

Row 58

Row 57

Row 56

Row 55

Row 54

Row 53

Row 52

Row 51

Row 50

Row 49

Row 48

Row 47

Row 46

Row 45

Row 44

Row 43

Row 42

Row 41

Row 40

Row 39

Row 38

Row 37

Row 36

Row 35

Row 34

Row 33

Row 32

Row 31

Row 30

Row 29

Row 28

Row 27

Row 26

Row 25

Row 24

Row 23

Row 22

Row 21

Row 20

Row 19

Row 18

Row 17

Row 16

Row 15

Row 14

Row 13

Row 12

Row 11

Row 10

Row 9

Row 46

Row 45

Row 44

Row 43

Row 42

Row 41

Row 40

Row 39

Row 38

Row 37

Row 36

Row 35

Row 34

Row 33

Row 32

Row 31

Row 30

Row 29

Row 28

Row 27

Row 26

Row 25

Row 24

Row 23

Row 22

Row 21

Row 20

Row 19

Row 18

Row 17

Row 16

Row 15

Row 14

Row 13

Row 12

Row 11

Row 10

Row 9

Row 8

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

-

Row 46

Row 45

Row 44

Row 43

Row 42

Row 41

Row 40

Row 39

Row 38

Row 37

Row 36

Row 35

Row 34

Row 33

Row 32

Row 31

Row 30

Row 29

Row 28

Row 27

Row 26

Row 25

Row 24

Row 23

Row 22

Row 21

Row 20

Row 19

Row 18

Row 17

Row 16

Row 15

Row 14

Row 13

Row 12

Row 11

Row 10

Row 9

Row 8

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

-

COM7

COM8

COM9

Row 63

Row 62

Row 61

Row 60

Row 59

Row 58

Row 57

Row 56

Row 55

Row 54

Row 53

Row 52

Row 51

Row 50

Row 49

Row 48

Row 47

Row 46

Row 45

Row 44

Row 43

Row 42

Row 41

Row 40

Row 39

Row 38

Row 37

Row 36

Row 35

Row 34

Row 33

Row 32

Row 31

Row 30

Row 29

Row 28

Row 27

Row 26

Row 25

Row 24

Row 23

Row 22

Row 21

Row 20

Row 19

Row 18

Row 17

Row 16

Row 15

Row 14

Row 13

Row 12

Row 11

Row 10

Row 9

RAM63

RAM62

RAM61

RAM60

RAM59

RAM58

RAM57

RAM56

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

RAM63

RAM62

RAM61

RAM60

RAM59

RAM58

RAM57

RAM56

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

Row 47

Row 46

Row 45

Row 44

Row 43

Row 42

Row 41

Row 40

Row 39

Row 38

Row 37

Row 36

Row 35

Row 34

Row 33

Row 32

Row 31

Row 30

Row 29

Row 28

Row 27

Row 26

Row 25

Row 24

Row 23

Row 22

Row 21

Row 20

Row 19

Row 18

Row 17

Row 16

Row 15

Row 14

Row 13

Row 12

Row 11

Row 10

Row 9

Row 8

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

-

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

RAM8

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

-

Row 47

Row 46

Row 45

Row 44

Row 43

Row 42

Row 41

Row 40

Row 39

Row 38

Row 37

Row 36

Row 35

Row 34

Row 33

Row 32

Row 31

Row 30

Row 29

Row 28

Row 27

Row 26

Row 25

Row 24

Row 23

Row 22

Row 21

Row 20

Row 19

Row 18

Row 17

Row 16

Row 15

Row 14

Row 13

Row 12

Row 11

Row 10

Row 9

Row 8

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

-

RAM63

RAM62

RAM61

RAM60

RAM59

RAM58

RAM57

RAM56

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

-

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

-

Row 8

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

RAM8

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

Row 8

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

-

Row 0

RAM0

Row 8

RAM8

Row 0

RAM8

Display

examples

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(a)

(b)

(c)

(g)

(d)

(e)

(f)

(RAM)

Solomon Systech

Oct 2008 P 48/71

Rev 2.0 SSD1305

10.1.23 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)

This command consists of two functions:

•

Display Clock Divide Ratio (D)(A[3:0])

Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16,

with reset value = 1. Please refer to section 8.3 for the details relationship of DCLK and CLK.

Oscillator Frequency (A[7:4])

Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high. The 4-bit

value results in 16 different frequency settings available as shown below. The default setting is

0111b.

Figure 10-8 : Typical Oscillator frequency adjustment by D5 command (V_DD=2.8V)

Oscillator Frequency vs D5h command setting

600

500

400

300

200

100

0

10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0

D5h setting in hex

Note

⁽¹⁾There is 10% tolerance in the above frequency values

10.1.24 Set Area Color Mode ON/OFF & Low Power Display Mode (D8h)

This command is used to enable area color mode. RESET is monochrome mode. The low power display

mode can reduce power consumption during IC operation.

10.1.25 Set Pre-charge Period (D9h)

This command is used to set the duration of the pre-charge period. The interval is counted in number of

DCLK, where RESET equals 2 DCLKs.

SSD1305

Rev 2.0

P 49/71

Oct 2008

Solomon Systech

10.1.26 Set COM Pins Hardware Configuration (DAh)

This command sets the COM signals pin configuration to match the OLED panel hardware layout. The table

below shows the COM pin configuration under different conditions (for MUX ratio =64):

Table 10-3 : COM Pins Hardware Configuration

Conditions

COM pins Configurations

ROW63

1 Sequential COM pin configuration (DAh X[4] =0)

COM output Scan direction: from COM0 to COM63 (C0h)

Disable COM Left/Right remap (DAh X[5] =0)

ROW32

ROW31

ROW0

132 x 64

COM32

COM0

SSD1305Z

COM31

COM63

Pad 1,2,3,…->126

Gold Bumps face up

2 Sequential COM pin configuration (DAh X[4] =0)

COM output Scan direction: from COM0 to COM63 (C0h)

Enable COM Left/Right remap (DAh X[5] =1)

ROW63

ROW32

ROW31

ROW0

132 x 64

COM0

COM32

SSD1305Z

COM63

COM31

Pad 1,2,3,…->126

Gold Bumps face up

ROW0

3 Sequential COM pin configuration (DAh X[4] =0)

COM output Scan direction: from COM63 to COM0 (C8h)

Disable COM Left/Right remap (DAh X[5] =0)

ROW31

ROW32

ROW63

132 x 64

COM32

COM0

SSD1305Z

COM31

COM63

Pad 1,2,3,…->126

Gold Bumps face up

Solomon Systech

Oct 2008 P 50/71

Rev 2.0 SSD1305

Conditions

COM pins Configurations

4 Sequential COM pin configuration (DAh X[4] =0)

COM output Scan direction: from COM63 to COM0 (C8h)

Enable COM Left/Right remap (DAh X[5] =1)

ROW0

ROW32

ROW31

132 x 64

ROW63

COM0

COM32

SSD1305Z

COM63

COM31

Pad 1,2,3,…->126

Gold Bumps face up

ROW63

ROW61

5 Alternative COM pin configuration (DAh X[4] =1)

COM output Scan direction: from COM0 to COM63 (C0h)

Disable COM Left/Right remap (DAh X[5] =0)

ROW62

132 x 64

ROW2

ROW0

ROW1

COM32

COM0

COM1

COM31

SSD1305Z

COM62

COM63

Pad 1,2,3,…->126

Gold Bumps face up

6 Alternative COM pin configuration (DAh X[4] =1)

COM output Scan direction: from COM0 to COM63 (C0h)

Enable COM Left/Right remap (DAh X[5] =1)

ROW63

ROW62

ROW61

132 x 64

ROW2

ROW0

COM32

ROW1

COM0

COM33

SSD1305Z

COM30

COM31

COM63

Pad 1,2,3,…->126

Gold Bumps face up

SSD1305

Rev 2.0

P 51/71

Oct 2008

Solomon Systech

Conditions

COM pins Configurations

ROW0

7 Alternative COM pin configuration (DAh X[4] =1)

COM output Scan direction: from COM63 to COM0(C8h)

Disable COM Left/Right remap (DAh X[5] =0)

ROW1

ROW2

132 x 64

ROW61

ROW62

ROW63

COM32

COM0

COM1

COM31

SSD1305Z

COM62

COM63

Pad 1,2,3,…->126

Gold Bumps face up

ROW0

8 Alternative COM pin configuration (DAh X[4] =1)

COM output Scan direction: from COM63 to COM0(C8h)

Enable COM Left/Right remap (DAh X[5] =1)

ROW1

ROW2

132 x 64

ROW61

ROW62

ROW63

COM32

COM0

COM33

SSD1305Z

COM30

COM31

COM63

Pad 1,2,3,…->126

Gold Bumps face up

10.1.27 Set V_COMHDeselect Level (DBh)

This command adjusts the V_COMHregulator output.

10.1.28 Enter Read Modify Write (E0h)

This single byte command is used to enter the Read Modify Write mode.

During the Read Modify Write mode:

The RAM address pointer will not be incremented when there is data read.

The RAM address pointer will be increased by one automatically after each data write.

After exit the Read Modify Write Mode by command EEh, the RAM address pointer returns back to the

original location before enter the Read Modify Write mode.

For instance, when reading the data from the RAM and re-writing a new data to the same location, there is no

need to re-enter the column and page addresses again under this mode.

Solomon Systech

Oct 2008 P 52/71

Rev 2.0 SSD1305

Table 10-4 : Example of Read Modify Write Mode

RAM & address pointer (under Horizontal addressing mode)

Condition

Originally, Address Pointer point to address A

Enter Read Modify Write Mode by command E0h

Data read : address pointer does not change

Data Write: address pointer increases by one

automatically after each data write

Data Write: address pointer increases by one

automatically after each data write

Data read : address pointer does not change

Data Write: address pointer increases by one

automatically after each data write

Exit Read Modify Write Mode by command EEh

Address Pointer point to address A after exit Read

Modify Write Mode

10.1.29 NOP (E3h)

No Operation Command

10.1.30 Exit Read Modify Write (EEh)

This single byte command is used to exit the Read Modify Write mode (Please refer to Section 10.1.28. for

details of the Read Modify Write Mode).

10.1.31 Status register Read

This command is issued by setting D/C# ON LOW during a data read (See Figure 13-1 to Figure 13-3 for

parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is

provided for serial mode.

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10.2 Graphic Acceleration Command

10.2.1 Horizontal Scroll Setup (26h/27h)

This command consists of 5 consecutive bytes to set up the horizontal scroll parameters and determines the

scrolling start page, end page and scrolling speed.

Before issuing this command the horizontal scroll must be deactivated (2Eh). Otherwise, RAM content may

be corrupted.

The SSD1305 horizontal scroll is designed for 132 columns scrolling. The following three figures (Figure

10-9, Figure 10-10, Figure 10-11) show the examples of using the horizontal scroll:

Figure 10-9 : Horizontal scroll example: Scroll RIGHT by 4 columns

Original Setting

After one scroll

step

Figure 10-10 : Horizontal scroll example: Scroll LEFT by 2 columns

Original

Setting

After one

scroll step

Figure 10-11 : Horizontal scrolling setup example

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Oct 2008 P 54/71

Rev 2.0 SSD1305

10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah)

This command consists of 6 consecutive bytes to set up the continuous vertical and horizontal scroll

parameters and determines the scrolling start page, end page, scrolling speed and vertical scrolling offset.

The bytes A[2:0], B[2:0], C[2:0] and D[2:0] of command 29h/2Ah are for the setting of the continuous

horizontal scrolling. The byte E[5:0] is for the setting of the continuous vertical scrolling offset. All these

bytes together are for the setting of continuous diagonal (horizontal + vertical) scrolling. If the vertical

scrolling offset byte E[5:0] is set to zero, then only horizontal scrolling is performed (like command 26/27h).

Alternatively, if the byte A[2:0] is set to zero and E[5:0] is not set to zero, then only vertical scrolling is

performed.

Before issuing this command the scroll must be deactivated (2Eh). Otherwise, RAM content may be

corrupted. The following two figures (Figure 10-12 , Figure 10-13) show the examples of using the

continuous vertical and horizontal scroll:

Figure 10-12 : Continuous Vertical and Horizontal scrolling setup examples

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Figure 10-13 : Continuous Vertical and Horizontal scrolling example: With setting in MUX ratio

As shown in Figure 10-13, the whole RAM content is displayed during scrolling regardless of the MUX ratio.

10.2.3 Deactivate Scroll (2Eh)

This command stops the motion of scrolling. After sending 2Eh command to deactivate the scrolling action,

the ram data needs to be rewritten.

10.2.4 Activate Scroll (2Fh)

This command starts the motion of scrolling and should only be issued after the scroll setup parameters have

been defined by the scrolling setup commands :26h/27h/29h/2Ah . The setting in the last scrolling setup

command overwrites the setting in the previous scrolling setup commands.

The following actions are prohibited after the scrolling is activated

1.

2.

RAM access (Data write or read)

Changing the horizontal scroll setup parameters

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Oct 2008 P 56/71

Rev 2.0 SSD1305

10.2.5 Set Vertical Scroll Area(A3h)

This command consists of 3 consecutive bytes to set up the vertical scroll area. For the continuous vertical

scroll function (command 29/2Ah), the number of rows that in vertical scrolling can be set smaller or equal to

the MUX ratio. Figure 10-14 shows some vertical scrolling example with different settings in vertical scroll

area.

Figure 10-14 : Vertical scroll area setup examples

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Solomon Systech

11 MAXIMUM RATINGS

Table 11-1 : Maximum Ratings (Voltage Referenced to V_SS)

Symbol

V_DD

Parameter

Value

-0.3 to +4

Unit

V

Supply Voltage

V_DDIO

V_CC

-0.3 to V_DD+0.5

0 to 16

V

V_SEG

V_COM

V_in

T_A

T_stg

SEG output voltage

COM output voltage

Input voltage

Operating Temperature

Storage Temperature Range

0 to V_CC

V

ºC

0 to 0.9*V_CC

V_SS-0.3 to V_DD+0.3

-40 to +85

-65 to +150

Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the

limits in the Electrical Characteristics tables or Pin Description section

This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal

operation. This device is not radiation protected.

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Oct 2008 P 58/71

Rev 2.0 SSD1305

12 DC CHARACTERISTICS

Condition (Unless otherwise specified):

Voltage referenced to V_SS

V_DD= 2.4 to 3.5V

T_A= 25°C

Table 12-1 : DC Characteristics

Symbol

V_CC

V_DD

Parameter

Operating Voltage

Logic Supply Voltage

Logic Supply Voltage for MCU

interface

Test Condition

-

Min

7

2.4

Typ

-

Max

15

3.5

Unit

V

V_DDIO

-

1.6

-

V_DD

V

V_OH

V_OL

V_IH

V_IL

High Logic Output Level

Low Logic Output Level

High Logic Input Level

Low Logic Input Level

I_OUT= 100uA, 3.3MHz

-

0.9 x V_DDIO

-

0.8 x V_DDIO

-

V

0.1 x V_DDIO

-

0.2 x V_DDIO

-

V_DDIO=1.6V~3.3V, V_DD= 2.4V ~3.5V,

V_CC= 7V~15V

Display OFF, No panel attached

V_DDIO=1.6V~3.3V, V_DD= 2.4V ~3.5V,

V_CC= 7V~15V

Display OFF, No panel attached

V_DDIO=1.6V~3.3V, V_DD= 2.4V ~3.5V,

I

_CCSleep mode Current

I_{CC, SLEEP}

-

10

uA

I

_DDSleep mode Current

I_{DD, SLEEP}

I_DDIOSleep mode Current

V_CC= 7V~15V

I_{DDIO, SLEEP}

Display OFF, No panel attached

V_CCSupply Current

V_DD= 2.7V, V_CC= 12V,

I_REF= 10uA

No loading, Display ON, All

ON

V_DDSupply Current

V_DD= 2.7V, V_CC= 12V,

I_REF= 10uA

I_CC

-

550

100

1000

300

uA

Contrast = FFh

I_DD

No loading, Display ON, All

ON

Contrast=FFh

Contrast=AFh

Contrast=7Fh

Contrast=3Fh

294

320

220

159

79

346

Segment Output Current

-

I_SEG

uA

V_DD=2.7V, V_CC=12V,

I_REF=10uA, Display ON.

Contrast=0Fh

19

Dev = (I_SEG– I_MID)/I_MID

Segment

uniformity

output

current I_MID= (I_MAX+ I_MIN)/2

Dev

-3

-2

-

+3

+2

%

I_SEG[0:131] = Segment current at

contrast = FFh

Adjacent pin output current Adj Dev = (I[n]-I[n+1]) /

uniformity (contrast = FF) (I[n]+I[n+1])

Adj. Dev

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Solomon Systech

13 AC CHARACTERISTICS

Conditions:

Voltage referenced to V_SS

V_DD=2.4 to3.5V

T_A= 25°C

Table 13-1 : AC Characteristics

Test Condition

Oscillation Frequency of Display V_DD= 2.8V

Timing Generator

Symbol Parameter

FOSC

Min Typ

324 360

Max Unit

(1)

kHz

Hz

us

396

Frame Frequency for 64 MUX

Mode

Reset low pulse width

132x64 Graphic Display Mode, Display

ON, Internal Oscillator Enabled

F_OSCx 1/(DxKx64)

FFRM

RES#

-

(2)

3

-

Note

⁽¹⁾FOSC stands for the frequency value of the internal oscillator and the value is measured when command D5h A[7:4] is

in default value.

⁽²⁾D: divide ratio (default value = 1)

K: number of display clocks (default value = 54)

Please refer to Table 9-1 (Set Display Clock Divide Ratio/Oscillator Frequency, D5h) for detailed description

Solomon Systech

Oct 2008 P 60/71

Rev 2.0 SSD1305

Table 13-2 : 6800-Series MCU Parallel Interface Timing Characteristics

(V_DD- V_SS= 2.4V to 3.5V, V_DDIO= V_DD, T_A= 25°C)

Symbol

Parameter

Min Typ

Max

Unit

t_cycle

Clock Cycle Time

300

0

-

ns

t_AS

Address Setup Time

Address Hold Time

Write Data Setup Time

Write Data Hold Time

Read Data Hold Time

Output Disable Time

Access Time

-

ns

t_AH

0

-

t_DSW

t_DHW

t_DHR

t_OH

40

7

-

20

-

70

140

t_ACC

-

Chip Select Low Pulse Width (read)

Chip Select Low Pulse Width (write)

Chip Select High Pulse Width (read)

Chip Select High Pulse Width (write)

120

60

PW_CSL

PW_CSH

-

ns

60

t_R

t_F

Rise Time

Fall Time

-

40

ns

Figure 13-1 : 6800-series MCU parallel interface characteristics

D/C#

t_AS

t_AH

R/W#

E

t_cycle

PW_CSH

PW_CSL

t_R

CS#

t_F

t_DHW

t_DSW

D[7:0](WRITE)

Valid Data

t_ACC

t_DHR

D[7:0](READ)

Valid Data

t_OH

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Solomon Systech

Table 13-3 : 8080-Series MCU Parallel Interface Timing Characteristics

(V_DD- V_SS= 2.4V to 3.5V, V_DDIO= V_DD,T_A= 25°C)

Symbol

t_cycle

t_AS

Parameter

Min

300

10

0

40

7

20

-

120

60

-

Typ

Max

-

70

140

-

Unit

ns

Clock Cycle Time

Address Setup Time

Address Hold Time

Write Data Setup Time

Write Data Hold Time

Read Data Hold Time

Output Disable Time

Access Time

Read Low Time

Write Low Time

Read High Time

Write High Time

-

t_AH

t_DSW

t_DHW

t_DHR

t_OH

t_ACC

t_PWLR

t_PWLW

t_PWHR

t_PWHW

t_R

-

Rise Time

40

-

t_F

Fall Time

-

0

20

t_CS

t_CSH

t_CSF

Chip select setup time

Chip select hold time to read signal

Chip select hold time

Figure 13-2 : 8080-series parallel interface characteristics (Form 1)

Write cycle (Form 1) Read cycle (Form 1)

CS#

t_CSH

CS#

t_CSF

t_CS

D/C#

t_AH

t_AS

t_AH

t_R

t_F

t_R

t_cycle

t_PWHW

t_F

t_cycle

t_PWHR

t_PWLW

t_DSW

WR#

t_PWLR

RD#

t_DHW

t_ACC

t_DHR

D[7:0]

t_OH

Figure 13-3 : 8080-series parallel interface characteristics (Form 2)

Write cycle (Form 2)

Read cycle (Form 2)

t_cycle

t_R

t_F

t_PWLW

t_PWLR

CS#

t_PWHR

t_PWHW

t_CS

D/C#

t_AS

t_AH

t_AS

t_AH

t_CSF

WR#

RD#

t_CSH

t_DSW

t_DHW

t_ACC

t_DHR

D[7:0]

t_OH

Solomon Systech

Oct 2008 P 62/71

Rev 2.0 SSD1305

Table 13-4 : Serial Interface Timing Characteristics

(V_DD- V_SS= 2.4V to 3.5V , V_DDIO= V_DD,T_A= 25°C)

Symbol

t_cycle

t_AS

t_AH

t_CSS

t_CSH

t_DSW

t_DHW

t_CLKL

t_CLKH

t_R

Parameter

Min

250

150

120

60

50

15

100

-

Typ

Max Unit

Clock Cycle Time

Address Setup Time

Address Hold Time

Chip Select Setup Time

Chip Select Hold Time

Write Data Setup Time

Write Data Hold Time

Clock Low Time

Clock High Time

Rise Time

-

ns

-

40

t_F

Fall Time

-

Figure 13-4 : Serial interface characteristics

D/C#

CS#

t_AS

t _AH

t_CSS

t_CSH

t_cycle

t_CLKL

t_CLKH

0)

1)

SCLK(D

SDIN(D

t_F

t_R

t_DSW

Valid Data

t_DHW

CS#

SCLK(D0)

D7

D6

D5

D4

D3

D2

D1

D0

SDIN(D1)

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Oct 2008

Solomon Systech

Conditions:

V

_DD- V_SS= 2.4 to 3.5V

_DDIO= V_DD

T_A= 25°C

Table 13-5 :I²C Interface Timing Characteristics

Symbol Parameter

Min

2.5

Typ

Max

Unit

us

t_cycle

Clock Cycle Time

-

t_HSTART

t_HD

Start condition Hold Time

Data Hold Time (for “SDA_OUT” pin)

Data Hold Time (for “SDA_IN” pin)

Data Setup Time

0.6

0

us

ns

300

100

0.6

ns

t_SD

ns

Start condition Setup Time (Only relevant for a repeated

Start condition)

t_SSTART

us

t_SSTOP

t_R

Stop condition Setup Time

0.6

-

us

ns

us

Rise Time for data and clock pin

Fall Time for data and clock pin

Idle Time before a new transmission can start

300

-

t_F

-

t_IDLE

1.3

Figure 13-5 : I²C interface Timing characteristics

//

SDA

SCL

t_IDLE

t_HD

t_R

t_F

t_HSTART

t_SSTART

t_SSTOP

t_SD

t_CYCLE

Solomon Systech

Oct 2008 P 64/71

Rev 2.0 SSD1305

14 APPLICATION EXAMPLE

Figure 14-1 : Application Example of SSD1305T6R1

The configuration for 6800-parallel interface mode, external V_CCis shown in the following diagram:

(V_DD=2.7V, V_CC=12V, I_REF=10uA)

DISPLAY PANEL

132 x 64

SSD1305T6R1

BGGND

V_CCV_COMHI_REFD[7:0] E (RD#) R/W#(W/R#) D/C# RES# CS# BS1 BS2 V_DDV_DDBGDR V_DDIOFB V_BREFV_SS

V_CIRFR

C3

C2

R1

C1

C4

D[7:0] E (RD#) R/W# (W/R#) D/C# RES# CS#

V_DD

V_DDIO

V_SS

V_CC

V_SS

[GND]

Pin connected to MCU interface: D[7:0], E, R/W#, D/C#, CS#, RES#

Pin internally connected to V_SS: BS0, V_SSB

GDR, V_BREF, FB should be left open.

C1: 4.7uF ⁽¹⁾

C2: 4.7uF ⁽¹⁾

C3: 4.7uF ⁽¹⁾

C4: 4.7uF ⁽¹⁾

R1: 910kΩ, R1= (Voltage at I_REFpin-V_SS)/I_REF

Voltage at I_REFpin = V_CC-3V

Note

⁽¹⁾The capacitor value is recommended value. Select appropriate value against module application.

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Oct 2008

Solomon Systech

15 PACKAGE INFORMATION

15.1 SSD1305Z Die Tray Information

Figure 15-1 SSD1305Z die tray information

Solomon Systech

Oct 2008 P 66/71

Rev 2.0 SSD1305

15.2 SSD1305T6R1 Detail Dimension

Figure 15-2 SSD1305T6R1 Detail Dimension

SSD1305

Rev 2.0

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Oct 2008 P 68/71

Rev 2.0 SSD1305

15.3 SSD1305T7R1 Detail Dimension

Figure 15-3 SSD1305T7R1 Detail Dimension

SSD1305

Rev 2.0

P 69/71

Oct 2008

Solomon Systech

15.4 SSD1305Z3 Die Tray Information

Figure 15-4 SSD1305Z3 die tray information

Solomon Systech

Oct 2008 P 70/71

Rev 2.0 SSD1305

Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without

limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters,

including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not con-

vey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use

as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any

other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.

Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and

hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the

part.

All Solomon Systech Products complied with six (6) hazardous substances limitation requirement per European Union (EU) “Restriction of

Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with

control Marking Symbol

.. Hazardous Substances test report is available upon requested.

http://www.solomon-systech.com

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型号：	SSD1305Z3
厂家：	ETC
描述：	132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller
文件：	总71页 (文件大小：4149K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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