SSD1800Z_技术文档

SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

SSD1800

Advance Information

80x16 + 1 Icon line

LCD Segment / Common Driver with Controller

for Character Display System

This document contains information on a new product. Specifications and information herein are

subject to change without notice.

http://www.solomon-systech.com

SSD1800 Series

Rev 1.0

P 1/42

Mar 2004

Copyright  2004 Solomon Systech Limited

TABLE OF CONTENTS

1

GENERAL DESCRIPTION .................................................................................................................5

FEATURES .........................................................................................................................................5

ORDERING INFORMATION...............................................................................................................5

BLOCK DIAGRAM .............................................................................................................................6

PIN ARRANGEMENT OF SSD1800Z GOLD BUMP DIE..................................................................7

PIN ARRANGEMENT OF SSD1800AV BARE DIE.........................................................................10

PIN DESCRIPTIONS ........................................................................................................................12

FUNCTIONAL BLOCK DESCRIPTIONS.........................................................................................15

VOLTAGE GENERATOR CIRCUIT .................................................................................................24

FRAME FREQUENCY......................................................................................................................25

COMMAND TABLE ..........................................................................................................................26

COMMAND DESCRIPTIONS ...........................................................................................................28

MAXIMUM RATINGS........................................................................................................................33

DC CHARACTERISTICS..................................................................................................................34

AC CHARACTERISTICS..................................................................................................................35

APPLICATION EXAMPLES .............................................................................................................38

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Solomon Systech

Mar 2004

P 2/42

Rev 1.0

SSD1800 Series

TABLE OF TABLES

Table 1 - Ordering Information ..................................................................................................................5

Table 2 - SSD1800Z Gold Bump Die Pad Coordinates............................................................................8

Table 3 - SSD1800AV Bare Die Pad Coordinates...................................................................................11

Table 4 - Relationship between ICONRAM Address and Display Pattern...........................................18

Table 5 - CGROM Character Code...........................................................................................................19

Table 6 - Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)...........20

Table 7- Contrast Control Register .........................................................................................................22

Table 8 - Command Table.........................................................................................................................26

Table 9 - DD/ CGRAM Address Mapping ................................................................................................31

Table 10 - ICONRAM Address Mapping..................................................................................................32

Table 11 - Maximum Ratings (Voltage Reference to VSS)....................................................................33

Table 12 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4

to 3.6V, TA = -30 to 85°C.).......................................................................................................34

Table 13 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4

to 3.6V, TA = -30 to 85°C.).......................................................................................................35

Table 14 - 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.6V, TA =

-30 to 85°C)...............................................................................................................................35

Table 15 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.6V, TA =

-30 to 85°C)...............................................................................................................................36

Table 16 - Serial Interface Timing Characteristics (VDD - VSS = 2.4 to 3.6V, TA = -30 to 85°C) .......37

SSD1800 Series Rev 1.0

P 3/42

Mar 2004

Solomon Systech

TABLE OF FIGURES

Figure 1 - Block Diagram of SSD1800.......................................................................................................6

Figure 2 - SSD1800Z Pin Arrangement .....................................................................................................7

Figure 3 - SSD1800AV Pin Arrangement ................................................................................................10

Figure 4 - Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800 MPU Mode)...................16

Figure 5 - Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (8080 MPU Mode)...................16

Figure 6 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (6800 MPU Mode)...................17

Figure 7 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (8080 MPU Mode)...................17

Figure 8 - Timing Diagram of Serial Data Transfer................................................................................17

Figure 9 - DDRAM Address ......................................................................................................................18

Figure 10 - Configurations for DC-DC Converter...................................................................................21

Figure 11 - Configurations for Voltage Regulator .................................................................................21

Figure 12 - When Built-in Power Supply is used ...................................................................................24

Figure 13 - When External Power Supply is used .................................................................................24

Figure 14 - Function set command (X1X0 = 00).....................................................................................28

Figure 15 - COM0 ~ COM15 is a Double Height Line in function set command (X1X0 = 01).............28

Figure 16 - Display Attributes ..................................................................................................................30

Figure 17 - 6800-series MCU Parallel Interface Waveform....................................................................35

Figure 18 - 8080-series MCU Parallel Interface Waveform....................................................................36

Figure 19 - Serial Interface Characteristics............................................................................................37

Figure 20- Application Circuit: External Regulator with internal divider mode (8-bit 6800 mode)...38

Figure 21 - Application Circuit: ALL internal power mode with 2x regulated DC-DC converter

(serial mode).......................................................................................................................................39

Figure 22- Application Circuit: ALL internal power mode with 3x regulated DC-DC converter (8-bit

8080 mode) .........................................................................................................................................40

Figure 23- Recommended INITIALIZING of SSD1800............................................................................41

Solomon Systech

Mar 2004

P 4/42

Rev 1.0

SSD1800 Series

1

GENERAL DESCRIPTION

SSD1800 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix character display

system. It consists of 97 high voltage driving output pins for driving 80 Segments, 16 Commons and 1 icon

driving-Common. It can display 2 lines of 16 characters with 5x8 dots format. The double height character mode

and line vertical scroll functions are supported.

SSD1800 displays character directly from its internal 10,240 bits (256 characters x 5 x 8 dots) Character

Generator ROM (CGROM). All the character codes are stored in the 512 bits (16 characters x 4 lines) Data

Display RAM (DDRAM). User defined character can be loaded via 320 bits (8 characters x 5 x 8 dots) Character

Generator RAM (CGRAM). In addition, there is a 80 bits Icon RAM for Icon display. Data/ Commands are sent

from general MCU through software selectable 6800-/8080-series compatible 4/ 8-bit Parallel Interface or Serial

Peripheral Interface.

SSD1800 embeds a DC-DC Converter, Voltage Regulator, Voltage divider and RC oscillator that reduce the

number of external components. With the special design on minimizing power consumption and die size,

SSD1800 is suitable for portable battery-driven applications requiring a long operation period and a compact

size.

2

FEATURES

Single Supply Operation, 2.4V - 3.6V

Maximum 5.8V LCD Driving Output Voltage

Low Current Sleep Mode

On-Chip 2x/3x DC-DC Converter/ External Power Supply

On-Chip RC Oscillator/ External Clock

On-Chip Voltage Regulator

On-Chip Voltage Divider with programmable bias ratio (1/4, 1/5)

32 Level Internal Contrast Control

2 lines x 16 characters with 5x8 dots format display and 80 icons

Double Height Character Mode, Blink Mode, Cursor Display and Line Vertical Scroll Functions

Row remapping and column remapping (4-type LCD application available)

8/4-bit 6800-series Parallel Interface, 8/4-bit 8080-series Parallel Interface and Serial Peripheral Interface

256 Build in characters and 8 user defined characters

On-Chip Memories

Character Generator ROM (CGROM): 10240 bits (256 characters x 5 x 8 dots)

Character Generator RAM (CGRAM): 320 bits (8 characters x 5 x 8 dots)

Display Data RAM (DDRAM): 512 bits (16 characters x 4 lines)

Segment Icon RAM (ICONRAM): 80 bits (80 icons)

Available in Bare Die/Gold bumped Die

3

ORDERING INFORMATION

Table 1 - Ordering Information

Display Size

Ordering Part Number

Package Form

Gold-bump Die

Bare Die

Reference

Remark

SSD1800Z

16x2 Characters

Figure 2 on page 7

Figure 3 on page 10

-

SSD1800AV

SSD1800 Series Rev 1.0

P 5/42

Mar 2004

Solomon Systech

4

BLOCK DIAGRAM

COM0~

COM15

SEG0~SEG79

COMI0, COMI

Level

HV Buffer Cell (Level Shifter)

Display Data Latch

Selector

VL2

VL3

VL4

V_L5

DIRS

VL6

Display

Timing

Generator

V_F

Cursor and

Control

Bli k

Regulated DC/DC

Converter,

Voltage Divider,

Contrast Control

Oscillator

CLK

C_1P

C_1N

C_2P

C_2N

Internal

Character Generator ROM

M

i

Character Generator RAM

(CGROM)

Display Data RAM

(CGRAM)

Icon RAM

(DDRAM)

AV

DV_SS

(ICONRAM)

SS &

AV_{DD &}DV_DD

Command Decoder

RES

Reset

circuit

Command Interface

Parallel/ Serial Interface

DL

P/S

D/C

E

R/W C68/80

RES

D₇

D D₅D₄D₃D D₁

D

0

CS

6

2

(RD) (WR)

(SDA) (SCK)

Figure 1 – Block Diagram of SSD1800

Solomon Systech

Mar 2004

P 6/42

Rev 1.0

SSD1800 Series

5

PIN ARRANGEMENT OF SSD1800Z GOLD BUMP DIE

Alignment Keys

Center (-2101.9, 169.6)

26.3 µm 26.3 µm 26.3 µm

X

61.3µm

Center (2940.9, 480.0)

Center (-2940.9, 480.0)

8.75µm

37.6µm

X

(-2835, -598.5)

(2835, -598.5)

Figure 2 - SSD1800Z Pin Arrangement

Die Size:

6170um x 1480um (include scribe line)

6070um x 1380um (exclude scribe line)

670 +/-25um

Die Thickness:

Bump Size

Minimum Pitch

76.3um

PAD: 1-63

52.15 x 60.2 um

164-178 74.9 x 42 um

42 x 74.9 um

PAD: 65-79,

63.7um

PAD: 81-162

PAD: 64,80,163,179

63.7um

52.15 X 52.15 um

Bump Height: Nominal

18um

Note:

1. PADS: 35-36, 45, 64-65, 75-81, 162-164, 166-169, 178-179 NC pads.

2. The die faces up in the diagram.

3. Coordinates are reference to the center of the chip.

4. Unit of coordinates and size of all alignment keys are in um.

5. All alignment keys do not contain gold bump.

SSD1800 Series Rev 1.0

P 7/42

Mar 2004

Solomon Systech

Table 2 - SSD1800Z Gold Bump Die Pad Coordinates

PAD#

NAME

D/ C

DVSS

X

Y

PAD#

41

42

43

44

NAME

C1N

C1P

NC

X

Y

1

2

3

4

5

-2401.53

-2325.23

-2248.93

-2172.63

-2096.33

-600.78

684.78

761.08

837.38

913.68

989.98

-600.78

R/W ( WR )

DVDD

E(RD )

45

6

-2020.03

-600.78

46

DVSS

1080.63

-600.78

CS

D7

7

-1943.73

-1867.43

-1791.13

-1714.83

-1638.53

-1562.23

-1485.93

-1409.63

-1333.33

-600.78

-600.6

47

48

49

50

51

52

53

54

55

AVSS

DVSS

REF

1156.93

1233.23

1309.53

1385.83

1462.13

1538.43

1614.73

1691.03

1767.33

-600.78

8

D6

9

D5

10

11

12

13

14

15

D4

DIRS

DVDD

AVDD

DVDD

CLK

D3

D2

D1

D0

DVDD

VSS

16

AVDD

-1257.03

-600.6

56

1843.63

-600.78

P / S

DVDD

DL

17

18

19

DVDD

DVSS

AVSS

-1180.73

-1104.43

-1028.13

-600.6

-600.78

-600.6

57

58

59

1919.93

1996.23

2072.53

-600.78

DVSS

20

21

22

DVSS

VL2

-951.83

-861.18

-784.88

-600.6

60

61

62

2148.83

2225.13

2301.43

-600.78

-520.1

-456.4

-392.7

-329

C68/( 80 )

DVDD

RES

TEST

NC

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

VL3

VL4

VL5

VL6

VF

-708.58

-632.28

-555.98

-479.68

-403.38

-327.08

-246.05

-169.75

-93.45

-600.6

-600.78

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

2377.73

2939.3

NC

COMI0

COM 0

COM 1

COM 2

COM 3

COM 4

COM 5

COM 6

COM 7

NC

-265.3

-201.6

-137.9

-74.2

-17.15

64.75

-10.5

VF

141.05

222.25

298.55

379.58

455.88

532.18

608.48

53.2

NC

116.90

180.6

244.3

308.0

371.7

593.43

NC

C2N

C2P

NC

Solomon Systech

Mar 2004

P 8/42

Rev 1.0

SSD1800 Series

PAD#

81

NAME

NC

X

Y

PAD#

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

NAME

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

NC

X

Y

2579.85

2516.15

2452.45

2388.75

2325.05

2261.35

2197.65

2133.95

2070.25

2006.55

1942.85

1879.15

1815.45

1751.75

1688.05

1624.35

1560.65

1496.95

1433.25

1369.55

1305.85

1242.15

1178.45

1114.75

1051.05

987.35

923.65

859.95

796.25

732.55

668.85

605.15

541.45

477.75

414.05

350.35

286.65

222.95

159.25

95.55

593.43

-605.15

-668.85

-732.55

-796.25

-859.95

-923.65

-987.35

-1051.05

-1114.75

-1178.45

-1242.15

-1305.85

-1369.55

-1433.25

-1496.95

-1560.65

-1624.35

-1688.05

-1751.75

-1815.45

-1879.15

-1942.85

-2006.55

-2070.25

-2133.95

-2197.65

-2261.35

-2325.05

-2388.75

-2452.45

-2516.15

-2579.85

-2939.3

593.43

371.7

82

SEG0

83

SEG1

84

SEG2

85

SEG3

86

SEG4

87

SEG5

88

SEG6

89

SEG7

90

SEG8

91

SEG9

92

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

NC

COMI1

NC

308

244.3

NC

180.6

NC

116.9

NC

53.2

COM15

COM14

COM13

COM12

COM11

COM10

COM9

COM8

NC

-10.5

31.85

-74.2

-31.85

-137.9

-201.6

-265.3

-329

-95.55

-159.25

-222.95

-286.65

-350.35

-414.05

-477.75

-541.45

-392.7

-456.4

-520.1

-600.78

NC

SSD1800 Series Rev 1.0

P 9/42

Mar 2004

Solomon Systech

6

PIN ARRANGEMENT OF SSD1800AV BARE DIE

Figure 3 - SSD1800AV Pin Arrangement

Die Size:

6260um x 1810um (include scribe line)

Die Thickness:

Pad Metal Size:

Pad Opening Size:

670 +/-25um

88 x 88um

80 x 80um

Pad number

Pad metal size

PADS: 1-9, 48-56, 72-80, 119-127

PADS: 57, 58, 70, 71, 128, 129, 141, 142

PADS: 10-47, 81-118

103um x111um

111um x103um

90um x111um

111um x90um

PADS: 59-69, 130-140

Note:

1. PADS: 1,2, 29, 34, 56-59, 141, 142 are NC pads.

2. The die faces up in the diagram.

3. Coordinates are reference to the center of the chip.

Solomon Systech

Mar 2004

P 10/42 Rev 1.0

SSD1800 Series

Table 3 - SSD1800AV Bare Die Pad Coordinates

PAD #

NAME

NC

X

Y

PAD # NAME

X

Y

PAD # NAME

X

Y

1

2

-2748.20 -772.71 51 COM3

-2638.13 -772.71 52 COM4

2198.53 -772.71 101 SEG41

2308.60 -772.71 102 SEG42

2418.68 -772.71 103 SEG43

2528.75 -772.71 104 SEG44

2638.83 -772.71 105 SEG45

2748.90 -772.71 106 SEG46

2998.10 -687.75 107 SEG47

2998.10 -577.68 108 SEG48

2998.10 -467.60 109 SEG49

2998.10 -372.75 110 SEG50

-145.08 772.98

-239.93 772.98

-334.78 772.98

-429.63 772.98

-524.48 772.98

-619.33 772.98

-714.18 772.98

-809.03 772.98

-903.88 772.98

-998.73 772.98

NC

3

COM15 -2528.05 -772.71 53 COM5

COM14 -2417.98 -772.71 54 COM6

COM13 -2307.90 -772.71 55 COM7

COM12 -2197.83 -772.71 56 NC

COM11 -2087.75 -772.71 57 NC

COM10 -1977.68 -772.71 58 NC

4

5

6

7

8

9

COM9

COM8

-1867.60 -772.71 59 NC

-1757.53 -772.71 60 SEG0

10

11

12

13

14

D/ C

-1662.68 -772.71 61 SEG1

2998.10 -277.90 111 SEG51 -1093.58 772.98

2998.10 -183.05 112 SEG52 -1188.43 772.98

R/W ( WR ) -1567.83 -772.71 62 SEG2

E(RD )

-1472.98 -772.71 63 SEG3

2998.10

-88.20 113 SEG53 -1283.28 772.98

6.65 114 SEG54 -1378.13 772.98

CS

D7

-1378.13 -772.71 64 SEG4

-1283.28 -772.71 65 SEG5

-1187.73 -772.71 66 SEG6

-1092.18 -772.71 67 SEG7

-996.63 -772.71 68 SEG8

-901.08 -772.71 69 SEG9

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

2998.10 101.50 115 SEG55 -1472.98 772.98

2998.10 196.35 116 SEG56 -1567.83 772.98

2998.10 291.20 117 SEG57 -1662.68 772.98

2998.10 386.05 118 SEG58 -1757.53 772.98

2998.10 480.90 119 SEG59 -1867.60 772.98

D6

D5

D4

D3

D2

-805.53 -772.71 70 SEG10 2998.10 590.98 120 SEG60 -1977.68 772.98

-709.98 -772.71 71 SEG11 2998.10 701.05 121 SEG61 -2087.75 772.98

-614.43 -772.71 72 SEG12 2742.43 772.98 122 SEG62 -2197.83 772.98

-519.58 -772.71 73 SEG13 2632.35 772.98 123 SEG63 -2307.90 772.98

-424.73 -772.71 74 SEG14 2522.28 772.98 124 SEG64 -2417.98 772.98

-329.88 -772.71 75 SEG15 2412.20 772.98 125 SEG65 -2528.05 772.98

-235.03 -772.71 76 SEG16 2302.13 772.98 126 SEG66 -2638.13 772.98

-140.18 -772.71 77 SEG17 2192.05 772.98 127 SEG67 -2748.20 772.98

-45.33 -772.71 78 SEG18 2081.98 772.98 128 SEG68 -2998.10 -687.75

49.53 -772.71 79 SEG19 1971.90 772.98 129 SEG69 -2998.10 -577.68

144.38 -772.71 80 SEG20 1861.83 772.98 130 SEG70 -2998.10 -467.60

239.23 -772.71 81 SEG21 1751.75 772.98 131 SEG71 -2998.10 -372.75

334.08 -772.71 82 SEG22 1657.08 772.98 132 SEG72 -2998.10 -277.90

428.93 -772.71 83 SEG23 1562.23 772.98 133 SEG73 -2998.10 -183.05

D1

D0

VL2

VL3

VL4

VL5

VL6

VF

NC

C2N

C2P

C1N

C1P

NC

523.78 -772.71 84 SEG24 1467.38 772.98 134 SEG74 -2998.10

618.63 -772.71 85 SEG25 1372.53 772.98 135 SEG75 -2998.10

-88.20

6.65

AVSS

DVSS

REF

DIRS

AVDD

DVDD

CLK

P/ S

DL

C68/( 80 )

713.48 -772.71 86 SEG26 1277.68 772.98 136 SEG76 -2998.10 101.50

808.33 -772.71 87 SEG27 1182.83 772.98 137 SEG77 -2998.10 196.35

903.18 -772.71 88 SEG28 1087.98 772.98 138 SEG78 -2998.10 291.20

998.03 -772.71 89 SEG29

1092.88 -772.71 90 SEG30

1187.73 -772.71 91 SEG31

993.13 772.98 139 SEG79 -2998.10 386.05

898.28 772.98 140 ICONS2 -2998.10 480.90

803.43 772.98 141 NC

-2998.10 590.98

-2998.10 701.05

42

43

44

1282.58 -772.71 92 SEG32

1377.43 -772.71 93 SEG33

708.58 772.98 142 NC

613.73 772.98

1472.28 -772.71 94 SEG34

518.88 772.98

45

RES

TEST

ICONS1

COM0

COM1

COM2

1567.13 -772.71 95 SEG35

1661.98 -772.71 96 SEG36

1758.23 -772.71 97 SEG37

1868.30 -772.71 98 SEG38

1978.38 -772.71 99 SEG39

2088.45 -772.71 100 SEG40

424.03 772.98

329.18 772.98

234.33 772.98

139.48 772.98

44.63 772.98

-50.23 772.98

46

47

48

49

50

SSD1800 Series Rev 1.0

P 11/42 Mar 2004

Solomon Systech

7

PIN DESCRIPTIONS

7.1 D/C

This pin is Data/ Command control pin. When the pin is pulled high, the data at D7-D0 is treated as display data.

When the pin is pulled low, the data at D7-D0 will be transferred to the command register.

7.2 R/

W

( WR )

This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used

as R/W signal input. Read mode will be carried out when this pin is pulled high and write mode when low.

When interfacing to a 8080-microprocessor, this pin will be the WR input. Data write operation is initiated when

this pin is pulled low and the chip is selected.

This pin must be fixed to high or low in serial mode.

7.3 DVDD & AVDD

Digital and Analog Power supply pin.

7.4 DVSS & AVSS

Ground.

7.5 E(RD )

This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used

as the enable signal, E. Read/ Write operation is initiated when this pin is pulled high and the chip is selected.

When interfacing to a 8080-microprocessor, this pin receives the RD signal. Data read operation is initiated when

this pin is pulled low and the chip is selected.

This pin must be fixed to high or low in serial mode.

7.6 CS

This pin is the chip select input.

7.7 D7-D0

These pins are the 8-bit bi-directional data bus to be connected to the microprocessor in parallel interface mode.

In 8-bit bus mode, D7 is the MSB while D0 is the LSB. In 4-bit bus mode, it is needed to transfer 4-bit data (through

D7-D4) by two times. The high order bits (for 8-bit mode D7-D4) are written before the low order bits (for 8-bit mode

D3-D0) in write transaction and low order bits (8-bit mode D3-D0) are read before the high order bits (8-bit mode D7-

D4) in read transaction. The D3-D0 pins must be fixed to high or low in 4-bit bus mode. After resets, SSD1800

considers first 4-bit data from MPU as the high order bits.

When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK). D5-D0 must

be fixed to high or low in serial mode

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7.7 VL6, VL5, VL4, VL3, VL2

LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the

following relationship:

VL6 > VL5 > VL4 > VL3 > VL2 > Vss

1:4 bias

1:5 bias (default)

4/5 * VL6

VL5

VL4

VL3

VL2

3/4 * VL6

2/4 * VL6

1/4 * VL6

3/5 * VL6

2/5 * VL6

1/5 * VL6

VL6 is the most positive LCD driving voltage. It can be supplied externally or generated by the internal regulator. It is

recommended to add a capacitor between VL6 and Vss for external regulator.

7.8 VF

This pin is the input of the built-in voltage regulator. When external resistor network is selected to generate the

LCD driving level, VL6, two external resistors, R1 and R2, are connected between AVSS and VF, and VF and VL6,

respectively (see application circuit)

7.9 REF

This pin is to select the input voltage of internal voltage regulator. This pin is need to pulled low for normal

internal voltage regulator operation.

7.10 DIRS

This pin controls the direction of Segment.

When DIRS = Low

SEG0 -> SEG2 -> ..... -> SEG78 -> SEG79

When DIRS = High

SEG79 -> SEG78 -> ..... -> SEG1 -> SEG0

7.11 CLK

External clock input. It must be fixed to high or low when the internal oscillation circuit is used. In case of the

external clock mode, CLK is used as the clock and OSC bit should be OFF.

7.12 P/S

This pin is serial/ parallel interface selection input. When this pin is pulled high, parallel mode is selected. When it

is pulled low, serial interface will be selected. Read back operation is only available in parallel mode.

7.13 DL

This pin is to select the data length for parallel data input.

When P/ S = Low

DL = Low or High: serial interface mode

When P/ S = High

DL = Low: 4-bit bus mode

DL = High: 8-bit bus mode

This pin must be fixed to high or low in serial mode.

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Solomon Systech

7.14 C68/80

This pin is microprocessor interface selection input. When the pin is pulled high, 6800 series interface is selected

and when the pin is pulled low, 8080 series MCU interface is selected. This pin must be fixed to high or low in serial

mode.

7.15 RES

This pin is reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse width for

completing the reset is 10ms.

7.16 TEST

Test pin. This pin is not used for normal operation. Leave this pin open (NC).

7.17 C1P, C1N, C2P and C2N

When internal DC-DC voltage converter is used, external capacitors are connected between these pins. Different

connection will result in different DC-DC converter multiple factor, 2x/3x. Details connections please refer to Figure

12.

7.18 COMI0, COMI1

There are two icons pins (pin47 and 140). Both pins output exactly the same signal. The reason for duplicating the

pin is to enhance the flexibility of the LCD layout.

7.19 COM0 – COM15

These pins provide the common driving signal COM0 – COM15 to the LCD panel. Their output voltage levels are

AVss during sleep mode and standby mode.

7.20 SEG0 - SEG79

These pins provide the LCD segment driving signals. Their output voltage levels are AVSS during sleep mode and

standby mode.

7.21 NC

These are the No Connection pins. Nothing should be connected to these pins, nor they are connected together.

These pins should be left open individually.

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Mar 2004

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8

FUNCTIONAL BLOCK DESCRIPTIONS

8.1 Command Decoder and Command Interface

This module determines whether the input data is interpreted as data or command. Data is directed to this module

based upon the input of the D/ C pin. If D/ C is high, data is written to internal memories (DDRAM, CGRAM,

ICONRAM). If D/ C is low, the input at D7-D0 is interpreted as a Command and it will be decoded and be written to

the corresponding command register.

8.2 MPU Parallel 6800-series Interface in 8 bits bus mode

The parallel interface consists of 8 bi-directional data pins (D7-D0), R/W ( WR ), D/ C , E(RD ), CS . R/W ( WR )

input high indicates a read operation from the internal RAM (DDRAM, CGRAM and ICONRAM). R/W ( WR ) input low

indicates a write operation to internal RAM (DDRAM, CGRAM and ICONRAM) or Internal Command Registers

depending on the status of D/ C input. The E(RD ) input serves as data latch signal (clock) when high provided that

CS are low. Refer to Figure 20 for Parallel Interface Timing Diagram of 6800-series microprocessors.

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline

processings are internally performed which require the insertion of a dummy read before the first actual display data

read. This is shown in Figure 4 below. The dummy read make the address counter (AC) increased by 1. So it is

recommended to set address again before writing. The consecutive read after the dummy read are also the valid

data. The instruction read cycle is not supported and it is regarded as a no operation cycle.

8.3 MPU Parallel 8080-series Interface in 8 bits bus mode

The parallel interface consists of 8 bi-directional data pins (D7-D0), R/W ( WR ), D/ C , E(RD ), CS . E(RD ) input

serves as data read latch signal (clock) when low provided that CS is low whether it is Command write or internal

RAM read/ write is controlled by D/ C . R/W ( WR ) input serves as data write latch signal (clock) when low provided

that CS is low. Refer to Figure 21 for Parallel Interface Timing Diagram of 8080-series microprocessor.

Similar to 6800-series interface, a dummy read is also required before the first actual display data read.

8.4 4-bit MPU Parallel 6800/8080-Series Interface

The control of 4-bit bus mode is exactly the same as 8-bit bus mode except 2 consecutive access (read/ write) is

needed to read/ write 8 bits data. For write operation, upper order bits are written before the low order bits, and low

order bits are always read before the upper order bit in read transaction.

8.5 MPU Serial Interface

The serial interface consists of serial clock SCK (D6), serial data SDA (D7), D/ C , CS . SDA is shifted into a 8-bit

shift register on every rising edge of SCK in the order of D7, D6, ... D0. D/ C is sampled on every eighth clock to

determine whether the data byte in the shift register is written to the internal RAM (DDRAM, CGRAM, ICONRAM) or

command register at the same clock.

8.6 Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry. The oscillator generates the clock for the DC-DC

voltage converter. This clock is also used in the Display Timing Generator.

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Solomon Systech

8.7 ADDRESS COUNTER (AC)

Address Counter (AC) in SSD1800 stores DDRAM/ CGRAM/ ICONRAM address. After writing into or reading

from DDRAM/ CGRAM/ ICONRAM. AC is automatically increased by 1. There is only one address counter and stores

the address among DDRAM / CGRAM / ICONRAM.

DL

C68/80

CS

D/C

R/W (WR)

E(RD)

Valid Data

D7 ~ D0

Instruction

Write

NOP

Dummy

Read

RAM

Read

Data

Write

Figure 4 - Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800 MPU Mode)

DL

C68/80

CS

D/C

R/W (WR)

E(RD)

Valid Data

D7 ~ D0

Instruction

Write

NOP

Dummy

Read

RAM

Read

Data

Write

Figure 5 - Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (8080 MPU Mode)

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DL

C68/80

CS

D/C

R/W (WR)

E(RD)

Lower

4-bits

Upper

4-bits

Lower

4-bits

Upper

4-bits

Upper

4-bits

Lower

4-bits

D7 ~ D0

Write

Instruction

NOP

Dummy Read

RAM Read Data Write

Figure 6 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (6800 MPU Mode)

DL

C68/80

CS

D/C

R/W (WR)

E(RD)

Upper

4-bits

Lower

4-bits

Lower

4-bits

Upper

4-bits

Upper

4-bits

Lower

4-bits

D7 ~ D0

Write

Instruction

NOP

Dummy Read

RAM Read Data Write

Figure 7 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (8080 MPU Mode)

CS

SDA(D7)

D7 D6 D5 D4 D3 D2 D1 D0 D7

SCK(D6)

D/C

1

2

3

4

5

6

7

8

9

Figure 8 – Timing Diagram of Serial Data Transfer

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Solomon Systech

8.8 Display Data RAM (DDRAM)

DDRAM stores display data of maximum 64 x 8 bits (Max 64 characters). DDRAM address is set in the address

counter as a hexadecimal number.

1

^st

Ch

16

^th

Ch

Figure 9 - DDRAM Address

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

20 22 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F

30 33 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F

COM0 – COM7

COM8 – COM15

Hidden Line

(1) DDRAM Address

SEG 0

SEG 79

8.9 SEGMENT ICON RAM (ICONRAM)

ICONRAM has segment control data and segment pattern data. There are 2 ICONS pins (COMI0 & COMI1), which

have the same signal. So the icons on the same SEG are displayed at the same time. The number of icons is 80.

Table 4 - Relationship between ICONRAM Address and Display Pattern

ICONRAM address

ICONRAM bits

D7

D6

D5

D4

S0

D3

S1

D2

S2

D1

S3

D0

S4

00h

-

01h

S5

S6

S7

S8

S9

02h

-

S10

…

S11

…

S12

…

S13

…

S14

…

-

…

-

…

-

0Dh

S65

S70

S75

S66

S71

S76

S67

S72

S77

S68

S73

S78

S69

S74

S79

0Eh

0Fh

-

Note: “-“: Don’t care.

8.10 Character Generator ROM (CGROM)

CGROM has 5 x 8 dot 256 characters. The Function Set instruction selects the 8 characters (00h - 07h) of CGROM

or CGRAM.

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Mar 2004

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Table 5 - CGROM Character Code

Note: The CGROM 0000xxxx are empty.

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Solomon Systech

8.11 Character Generator RAM (CGRAM)

CGRAM has up to 5 x 8 dots 8 characters. By writing font data to CGRAM, user defined character can be used.

CGRAM can be written regardless of Function Set instruction.

Table 6 - Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)

CGRAM address

ICONRAM bits

D7 D6 D5

Character Code

(DDRAM data)

D4

X

D3

X

D2

X

D1

X

D0

X

00h (Pattern 0)

01h (Pattern 1)

02h (Pattern 2)

03h (Pattern 3)

04h (Pattern 4)

05h (Pattern 5)

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

-

X

-

X

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Mar 2004

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SSD1800 Series

Character Code CGRAM address

(DDRAM data)

ICONRAM bits

D7 D6 D5

D4

X

D3

X

D2

X

D1

X

D0

X

06h (Pattern 6)

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

-

X

07h (Pattern 7)

-

X

NOTE: “-” Don’t use

“X” Pattern 0 or 1

8.12 LCD Driving Voltage Generator and Regulator

This module generates the LCD voltage required for display driving output. It takes a single supply input and

generates necessary voltage levels. This block consists of:

1. 2x/3x DC-DC voltage converter

The built-in Regulated DC-DC voltage converter is used to generate

positive LCD driving voltage with internal voltage reference, VREF, relative to AVSS

AVDD

SSD1800

AVDD

SSD1800

AVDD

R2

C1P

C1N

C1P

C1N

C2P

+

C2

C1

V_F

C1

+

V_L6

+

DC-DC

+

C2P

Converter

C2

C2N

VL6

+

-

V_REF

AVss

R1

3x DC-DC Converter 2x DC-DC Converter

Remarks:

C1 = 2.2µF - 4.7µF

C2 = 0.1µF - 1µF

Remarks:

R1 and R2 = 500K-2.5M ohms

Figure 10 – Configurations for DC-DC Converter

Figure 11 - Configurations for Voltage Regulator

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Solomon Systech

2. Voltage Regulator

The feedback gain control for LCD driving contrast can be adjusted by using reference voltage and external

resistor network. The reference voltage is supplied by internal Vref and Ref should be connected to low for normal

operation of internal voltage reference Vref. The external resistors are required to be connected between AVSS and

VF (R1), and between VF and VL6 (R2). The following equations are used to calculate the regulator output voltages.

R2

R1









V_L6= 1+

×V_REF





AND

V_REF= 2V 0.06

3. Contrast Control

Software control of the 32 contrast voltage levels at each voltage regulator feedback gain. The equation of calculating

the LCD driving voltage is given as:

R2

R1

n

150

















V_L6= 1+

×V_REF× 1−





where n is set in contrast control register.

Table 7- Contrast Control Register

X6 X5 X4 X3 X2 X1 X0

No.

1

X7

n

VL6

Contrast

-

0

.

0

.

0

.

0

1

.

0

1

0

1

.

0 (default) Maximum

High

2

1

2

.

3

.

4

3

.

31

32

1

0

1

30

31

.

Minimum

Low

(“ - “: Don’t care)

4. Bias Divider

Divide the regulator output to give the LCD driving voltages (VL5-VL2). A low power consumption circuit design in

this bias divider saves most of the display current comparing to traditional design.

5. Bias Ratio Selection circuitry

Software control of 1/4 and 1/5 bias ratio to match the characteristic of LCD panel.

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Mar 2004

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SSD1800 Series

8.13 Reset Circuit

This block includes Power On Reset circuitry and the Reset pin RES . Both of these having the same reset

function. Once RES receives a negative reset pulse, all internal circuitry will start to initialize. Minimum pulse width

for completing the reset sequence is 10ms.

The status of the chip after reset is given by:

1. Display/ cursor/ blink is turned OFF

2. 2-line display mode

3. Power control register is set to 000b

4. Oscillator is OFF

5. Power save is OFF

6. CGRAM is not used

7. Shift register data clear in serial interface

8. Bias ratio is set to 1/5

9. Address counter is set to 00h

10. Normal scan direction of the COM outputs

11. Contrast control register is set to 00h

12. Test mode is turned OFF

13. In case of 4-bit interface mode selection, SSD1800 considers the 1st 4-bit data from MPU as the

high order bits.

14. The 1st line of display is the address 00h-0Fh.

8.14 Display Data Latch

A series of registers carrying the display signal information. For SSD1800, there are 105 latches (80 + 25) for

holding the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage levels.

8.15 Level Selector

Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and

used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV

Buffer Cell, which in turn outputs the COM or SEG LCD waveform.

8.16 HV Buffer Cell (Level Shifter)

Buffer Cell work as a level shifter, which translates the low voltage output signal to the required, driving voltage.

The output is shifted out with an internal FRM clock that comes from the Display Timing Generator. The voltage

levels are given by the level selector that is synchronized with the internal M signal.

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Solomon Systech

9

VOLTAGE GENERATOR CIRCUIT

VDD

AVDD

C1P

+

C1P

+

C2

C1N

C1

C2

C1N

C2P

+

C2P

C2N

C2

VL6

VF

VL6

VF

R1

R2

GND

VL6

VL5

VL4

VL3

VL2

AVSS

GND

VL6

VL5

VL4

VL3

VL2

AVSS

GND

3x DC-DC Converter

2x DC-DC Converter

Remarks:

(VC,VF = 1,1)

C1 = 2.2µF - 4.7µF

C2 = 0.1µF - 1µF

Note: VC, VF = bit X₂and X₀in the command of Power Control Register;

X₂is the bit of turns on/off of the internal voltage converter and regulator

X₀is the bit of turns on/off of the voltage divider

R1 and R2 = 500K-2.5M ohms

Figure 12 - When Built-in Power Supply is used

VDD

AVDD

C1P

C1N

C1P

C1N

C2P

C2N

C2P

C2N

VF

-

+

E xte rn al

E xte rna l

P owe r

VL6

VL5

VL4

VL3

VL2

VL6

VL5

VL4

VL3

VL2

P owe r

S up ply

C2

S up p ly

AVSS

GND

(VC, V F = 0 ,1)

(VC, VF = 0 ,0 )

All Capacitor is C2.

C2 : 0.1 uF

in

Note: VC, VF = X_{2 ,}X₀

Power Control Register

Figure 13 When External Power Supply is used

Solomon Systech

Mar 2004

P 24/42 Rev 1.0

SSD1800 Series

10 FRAME FREQUENCY

1/17 Duty

SSD1800 Series Rev 1.0

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Solomon Systech

11 COMMAND TABLE

Table 8 - Command Table

D/C

Hex

D7 D6 D5 D4 D3

D2

D1

D0

Command

Return Home

Description

DDRAM address is set to 00h from address counter and

the cursor returns to 00h position

0

02

0

1

0

1

0

The contents of DDRAM are not changed.

Set Double Height

Mode

X1X0 = 00: normal display (POR)

X1X0 = 01: COM0 - COM15 is double height

X1X0 = 10/11: normal display

0

08 – 0B

0C – 0F

0

1

X1

X0

Set Power Save

Mode / Oscillator

Control

X0 = 0: power save OFF (POR)

X0 = 1: power save ON

X1 = 0: oscillator OFF (POR)

X1 = 1: oscillator ON

Function Set

X0 = 0: CGROM is selected (POR)

X0 = 1: CGRAM is selected

X1 = 0: COM0 -> COM15 (POR)

X1 = 1: COM15 -> COM0

0

10 – 13

18 – 1B

0

1

0

1

0

X1

X0

Set Display Start

Line

X1X0 = 00: DDRAM line 1 shows at the first line of LCD

(POR).

X1X0 = 01: DDRAM line 2 shows at the first line of LCD.

X1X0 = 10: DDRAM line 3 shows at the first line of LCD.

X1X0 = 11: DDRAM line 4 shows at the first line of LCD.

Set Bias Control

X0 = 0: 1/5 bias (POR)

0

1C – 1D

20 – 27

0

1

0

1

0

1

*

X0

X0 = 1: 1/4 bias

Set Power Control

Register

X0 = 0: turns off the voltage divider (POR)

X0 = 1: turns on the voltage divider

X1 : Don’t care

X2

X1

X2 = 0: turns off the internal voltage converter and

regulator (POR)

X2 = 1: turns on the internal voltage converter and

regulator

Set Display Control X0 = 0: turns off the display (POR)

X0 = 1: turns on the display

X1 = 0: blink off (POR)

0

28 – 2F

0

1

0

1

X2

X1

X0

X1 = 1: blink on

X2 = 0: cursor off (POR)

X2 = 1: cursor on

Set DD/CGRAM

address

DDRAM/ CGRAM address range:

0

80 – FF

40 – 5F

1

0

X6 X5 X4 X3

X2

X1

X0

DDRAM: 00h - 3Fh

CGRAM: 40h - 7Fh

Set ICONRAM

address / Contrast

Control

ICONRAM address range / Contrast Control Register:

1

0

X4

X3

ICONRAM: 00h - 0Fh

Contrast Control Register: 10h

TE: 11h (test byte)

NOP

Set Test Mode

Command for No Operation

Reserved for IC testing. Do Not use

0

00

30

0

1

0

1

0

*

0

*

0

*

0

*

Note:

1. Patterns other than that given in Command Table are prohibited to enter to the chip as a command. Otherwise, unexpected result

will occur.

2. “*” : Don’t care.

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SSD1800 Series

Data Read/ Write

To read data from the internal memories (DDRAM/ CGRAM/ ICONRAM), input high to R/W ( WR ) pin and D/ C

pin for 6800-series parallel mode, low to E(RD ) pin and high to D/ C pin for 8080-series parallel mode. No data read

is provided for serial mode. In normal mode, address counter will be increased by one automatically after each data

read. A dummy read is required before the first data read. See Figure 4 in Functional Description.

To write data to the internal memories (DDRAM/ CGRAM/ ICONRAM), input low to R/W ( WR ) pin and high to

D/ C pin for 6800-series and 8080-series parallel mode. For serial interface, it will always be in write mode. Address

counter will be increased by one automatically after each data write.

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Solomon Systech

12 COMMAND DESCRIPTIONS

12.1 Return Home

Return Home instruction field makes cursor return home. DDRAM address is set to 00h from address counter

and the cursor returns to 00h position. The contents of DDRAM are not changed.

12.2 Set Double Height Mode

This command increases the height of one character line from 8 to 16 dots. If the number of COM signal needed

exceeds the existing COM signal, the last character line will not be displayed. It will happen at following case:

1. For X1X0 = 01, where COM0-COM15 is double height.

The 2nd line will not be displayed.

Figure 14– Function set command (X₁X₀= 00)

Figure 15 - COM0 ~ COM15 is a Double Height Line in function set command (X₁X₀= 01)

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Mar 2004

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SSD1800 Series

12.3 Set Power Save Mode / Oscillator Control

To enter Standby or Sleep Mode, it should be done by turning off the internal oscillator and turning on the power

save control bit. The corresponding control bits are X1X0 = 01. In order to put the system into low power consumption

mode, internal voltage converter, voltage regulator and voltage divider should also be turned off by using Power

Control Register. After putting the system into power save mode, the following status will be entered:

1. Internal oscillator and LCD power supply circuits are stopped.

2. Segment and Common drivers output AVSS level.

3. The display data and operation mode before sleep are held. All the internal circuit is stopped.

12.4 Function Set

This command sets 2 functions on the system. They are COM shift direction (left or right) and CGROM/ CGRAM

character area select.

12.5 Set Display Start Line

This command is to set Display Start Line register to determine starting address of display data RAM to be

displayed by selecting a value from 0 to 3. With the value equals to 0, the display will start from address (00h-0Fh).

With the value equals to 1, the display will start from address (10h-1Fh). With the value equals to 2, the display will

start from address (20h-2Fh). With the value equals to 3, the display will start from address (30-3Fh).

12.6 Set Bias Control

Bias ratio 1/4 or 1/5 could be set using this command. When changing the number of line display, the bias ratio

also needs to be adjusted to make display contrast consistent.

12.7 Set Power Control Register

This command turns on / off the various power circuits associated with the chip which including regulated DC-DC

converter and voltage divider.

12.8 Set Display Control

This command provides 3 display functions. It turns on/off of the cursor, blink and display. When both cursor and

blink control bit set high, the driver make LCD alternate between inverting display character and normal display

character at the cursor position with about a half second. On the contrary, if cursor control bit is low, only a normal

character is displayed regardless of blink control bit.

SSD1800 Series Rev 1.0

P 29/42 Mar 2004

Solomon Systech

Display State

X2, X1

1, 0 (Cursor Mode)

1, 1 (Blinking Mode)

0, 0

0, 1

Figure 16 - Display Attributes

Solomon Systech

Mar 2004

P 30/42 Rev 1.0

SSD1800 Series

12.9 Set DD/ CGRAM Address

Before writing/ reading data into/ from the RAM, set the address by RAM address set instruction. Next, when

data are written/ read in succession, the address is automatically increased by1. After accessing 7Fh, the address is

00h.

Table 9 - DD/ CGRAM Address Mapping

ADDRESS

00H

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

DDRAM LINE 1 (00H - 0FH)

DDRAM LINE 2 (10H - 1FH)

DDRAM LINE 3 (20H - 2FH)

DDRAM LINE 4 (30H - 3FH)

CGRAM (PATTERN 0)

10H

20H

30H

40H

CGRAM (PATTERN 1)

CGRAM (PATTERN 3)

CGRAM (PATTERN 5)

CGRAM (PATTERN 7)

50H

CGRAM (PATTERN 2)

60H

CGRAM (PATTERN 4)

70H

CGRAM (PATTERN 6)

SSD1800 Series Rev 1.0

P 31/42 Mar 2004

Solomon Systech

12.10 Set ICONRAM Address Set

Before writing/ reading data into/ from the ICONRAM, set the address by ICONRAM Address Set instruction.

Next, when data are written/ read in succession, the address is automatically increased by 1. The 5 icons at a time

can blink if blinking is enabled. The blink attributes of ICON are the same as the cursor blink. For accessing DD/

CGRAM, the DD/ CGRAM Address Set instruction should be set before. After accessing 0Fh, the address of

ICONRAM address is 00h. The ICONRAM address ranges are 00h-0Fh.

Table 10 - ICONRAM Address Mapping

ADDRESS

00H

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

ICONRAM (00h - 0Fh)

C

T

E

C

10H

Reserved

R

12.11 Set Contrast Control Register

Set the Contrast Control Register (CCR) by ICONRAM Address Set Instruction. Next, data are written to the

CCR. The default value of CCR is (00000).

TE: Test Mode Register (Do not Use) (11H)

When the CCR and TE registers are written, the address counter is not increased.

12.12 NOP

A command causing No Operation.

12.13 Set Test Mode

This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user

should NOT use this command.

Solomon Systech

Mar 2004

P 32/42 Rev 1.0

SSD1800 Series

13 MAXIMUM RATINGS

Table 11 - Maximum Ratings (Voltage Reference to VSS)

Symbol

Parameter

Supply Voltage

Value

Unit

AVDD, DVDD

-0.3 to +4.0V

V

VL6

VIN

VLCD Voltage

Input Voltage

-0.3 to +6.5V

V

VSS-0.3 to

VDD+0.3

TA

Operating Temperature

-30 to +85

°C

Tstg

Storage Temperature Range

-65 to +150

* Maximum Ratings are those values beyond which damage to the device may occur. Functional

operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description

section

This device contains circuitry to protect the inputs against damage due to high static voltages or electric

fields; however, it is advised that normal precautions to be taken to avoid application of any voltage

higher than maximum rated voltages to this high impedance circuit. For proper operation it is

recommended that Vin and VL6 be constrained to the range VSS < or = (Vin) < or = VDD.

Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level

(e.g., either Vss or VDD). Unused outputs must be left open. This device may be light sensitive. Caution

should be taken to avoid exposure of this device to any light source during normal operation. This device

is not radiation protected.

SSD1800 Series Rev 1.0

P 33/42 Mar 2004

Solomon Systech

14 DC CHARACTERISTICS

Table 12 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to

3.6V, TA = -30 to 85°C.)

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

DVDD

AVDD

IDD1

Logic and Analog Circuit

Supply Voltage Range

Display Operation Supply

Current Drain

(Absolute value referenced to

DVss and AVss)

2.4

2.7

3.6

V

VDD = 3V, TA = 25°C

VLCD = 5.8V without load

No access from MPU

-

85

500

5

µA

IDD2

ISB

Access operation from MPU

Supply Current Drain

VDD = 3V, TA = 25°C

fcyc = 200kHz

Standby Mode Supply Current

Current No load

Oscillator OFF

Power Save ON

VLCD = VL6 - VSS

TA = 25°C, C = 1uF

V_LCD

VL6

VIH

LCD Driving Voltage Input

Voltage Regulator Output

Logic High Input Voltage

4

-

5.8

DVDD

V

0.8*DVDD

VIL

Logic Low Input Voltage

Logic High Output Voltage

Logic Low Output Voltage

0

-

0.2*DVDD

VOH

VOL

VL6

IOH = -1mA, VDD = 2.4V

IOL = 1mA, VDD = 2.4V

DVDD – 0.4

-

V

0.4

5.8

LCD Driving Voltage Source

(VL6)

Regulator Enable (VL6 voltage

depends on contrast control/

external resistors network)

AVSS - 0.5

VL6

LCD Driving Voltage Source

(VL6)

Regulator Disable

-

Floating

-

V

VL6

VL5

VL4

VL3

VL2

LCD Display Voltage Output

(V L5, VL4, VL3, VL2)

Voltage reference to AVSS,

Bias Divider Enabled, 1:a

bias ratio

VL6

-

V

(a-1)/a * VL6

(a-2)/a * VL6

2/a * VL6

1/a * VL6

VL6

VL5

VL4

VL3

VL2

-

Voltage reference to AVSS,

External Voltage Generator,

Bias Divider Disable

LCD Display Voltage Output

(V L5, VL4, VL3, VL2)

VL5

VL4

VL3

VL2

VSS

5.8

VL6

VL5

VL4

VL3

V

IOH

IOL

IOZ

Logic High Output Current

Source

VOUT = VDD - 0.4V

VOUT = 0.4V

50

-

-50

1

µA

Logic Low Output Current

Drain

-

-1

Logic Output Tri-state Current

Drain Source

IIL/ IIH

CIN

Logic Input Current

-1

-

5

2

1

µA

Logic Pins Input Capacitance

7.5

2.06

PF

Vref

Voltage regulator reference

voltage

1.94

V

Solomon Systech

Mar 2004

P 34/42 Rev 1.0

SSD1800 Series

15 AC CHARACTERISTICS

Table 13 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to

3.6V, TA = -30 to 85°C.)

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

FFRM

Frame Frequency

Internal Oscillator

VDD = 3V, TA = 25°C

67.5

75

90

Hz

Table 14 - 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.6V, TA =

-30 to 85°C)

Symbol

t_cycle

t_AS

Parameter

Min

650

60

30

100

50

-

Typ

Max

-

Unit

ns

Ns

ns

Clock Cycle Time

Address Setup Time

Address Hold Time

Write Data Setup Time

Write Data Hold Time

Read Data Hold Time

Output Disable Time

Access Time

-

t_AH

t_DSW

t_DHW

t_DHR

t_OH

-

70

100

ns

t_ACC

-

150

450

-

ns

E(RD ) Low Pulse Width (read)

E(RD ) Low Pulse Width (write)

E(RD ) High Pulse Width (read)

E(RD ) High Pulse Width (write)

Rise Time

PW_EL

PW_EH

t_R

t_F

-

25

ns

Fall Time

Figure 17– 6800-series MCU Parallel Interface Waveform

SSD1800 Series Rev 1.0

P 35/42 Mar 2004

Solomon Systech

Table 15 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.6V, TA =

-30 to 85°C)

Symbol

t_cycle

t_AS

Parameter

Min

650

60

30

100

50

-

Typ

Max

-

Unit

ns

Clock Cycle Time

Address Setup Time

Address Hold Time

Write Data Setup Time

Write Data Hold Time

Read Data Hold Time

Output Disable Time

Access Time

-

t_AH

t_DSW

t_DHW

t_DHR

t_OH

-

70

100

t_ACC

-

450

150

-

ns

WR Low Pulse Width (read)

WR Low Pulse Width (write)

WR High Pulse Width (read)

WR High Pulse Width (write)

Rise Time

PW_WRL

PW_WRH

t_R

t_F

-

25

ns

Fall Time

Figure 18– 8080-series MCU Parallel Interface Waveform

Solomon Systech

Mar 2004

P 36/42 Rev 1.0

SSD1800 Series

Table 16 - Serial Interface Timing Characteristics (VDD - VSS = 2.4 to 3.6V, TA = -30 to 85°C)

Symbol

t_cycle

t_AS

Parameter

Min

1000

50

300

150

700

50

Typ

Max

-

Unit

ns

Clock Cycle Time

Address Setup Time

Address Hold Time

Chip Select Setup Time

Chip Select Hold Time

Write Data Setup Time

Write Data Hold Time

Clock Low Time

Clock High Time

Rise Time

-

t_AH

t_CSS

t_CSH

t_DSW

t_DHW

t_CLKL

t_CLKH

t_R

50

300

-

25

t_F

Fall Time

-

Figure 19– Serial Interface Characteristics

SSD1800 Series Rev 1.0

P 37/42 Mar 2004

Solomon Systech

16 APPLICATION EXAMPLES

COMI0

COM0

COM1

COM8

:

COM9

..

:

.

:

.

DISPLAY PANEL SIZE

80 X 16 + 1 ICON LINE

COM14

.

:

COM6

COM7

COM15

.

COMI1

SEG0…………………………………………………………SEG79

SEG79……………………………………………………………………………SEG0

COMI1

.

COM7

.

COM6

.

COM5

SSD1800 IC

16 MUX

COM15

COM14

:

.

(DIE FACE IP)

:

.

COM9

COM8

COM0

COMI0

DVDD VL2 VL3 VL4 VL5 VL6

AVDD

0.1uF +

External Power Supply

VDD=3.0V

AVSS

Logic pin connections not specified above:

Pins connected to DVdd: C68/ 80 , P/ S , DL, DIRS

Pins connected to DVss: REF, CLK

Figure 20- Application Circuit: External Regulator with internal divider mode (8-bit 6800 mode)

Solomon Systech

Mar 2004

P 38/42 Rev 1.0

SSD1800 Series

COM8

COMI0

COM9

COM0

:

COM1

:

COM14

:

COM15

.

DISPLAY PANEL SIZE

80 X 16 + 1 ICON LINE

:

.

:

.

COM6

COM7

COMI1

SEG0…………………………………………………………SEG79

SEG79……………………………………………………………………………SEG0

COMI1

.

COM7

COM6

COM5

:

SSD1800 IC

16 MUX

COM15

COM14

:

(DIE FACE IP)

:

COM0

COMI0

COM9

COM8

VL6

C1N C1P C2P

+C1 C2 C2

DVDD VL2 VL3 VL4 VL5 VL6

VF

R2

AVDD

+

R1

C1: 2.2 -4.7 uF

C2: 0.1-1uF

AVDD

VDD = 3.0V

AVSS

Remarks:

R1 and R2 = 500K-2.5M ohms

Note:

It is recommended to use 2x regulated DC-DC

converter to reduce the current consumption

under certain of condition.

Logic pin connections not specified above:

Pins connected to DVdd: DL, DIRS

Pins connected to DVss: REF, CLK, P/ S , R/W ( WR ),

e.g. AVDD /DVDD = 3.0V and VLCD (LCD driving

E(/RD), C68/ 80 , D5-D0

voltage) = 5.0V.

Figure 21 - Application Circuit: ALL internal power mode with 2x regulated DC-DC converter

(serial mode)

SSD1800 Series Rev 1.0

P 39/42 Mar 2004

Solomon Systech

COMI0

COM0

COM8

COM1

COM9

:

DISPLAY PANEL SIZE

80 X 16 + 1 ICON LINE

:

.

COM14

.

COM15

COM6

COM7

:

COMI1

SEG0…………………………………………………………SEG79

SEG79……………………………………………………………………………SEG0

COMI1

.

COM7

COM15

COM14

:

COM6

COM5

:

SSD1800 IC

16 MUX

:

(DIE FACE IP)

COM9

COM8

COM0

COMI0

VL6

C1N C1P C2N C2P

DVDD VL2 VL3 VL4 VL5 VL6

AVDD

VF

R2

+C1 C2

C2

+

R1

C1: 2.2 -4.7 uF

C2: 0.1-1uF

AVDD

VDD = 3.0V

Remarks:

AVSS

R1 and R2 = 500K-2.5M ohms

Logic pin connections not specified above:

Pins connected to DVdd: P/ S , DL, DIRS

Pins connected to DVss: REF, CLK, and C68/(80 )

Figure 22- Application Circuit: ALL internal power mode with 3x regulated DC-DC converter

(8-bit 8080 mode)

Solomon Systech

Mar 2004

P 40/42 Rev 1.0

SSD1800 Series

Recommended INITIALIZING of SSD1800

NOTE:

At instructions 1-6, the minimum clock cycle

time is 650ns for PPI. For details, pls refer

to the SSD1800 datasheet “AC

Characteristics”.

DV_DD/AV_CC-DV_SS/AV_SSPower On

At 5 and 6, the internal RAM should be

cleared.

Send reset pulse to the RES pin.

(Recommended minimum reset pulse width is 10ms)

To clear DDRAM, set address at 00h (first

DDRAM) and then write 20h (space

character code) 64times.

Waiting for 10usec

To clear CGRAM, set address at 40h (first

CGRAM) and then write 00h (null data) 64

times

Command Input

1. Function set (000100X1X0)

To clear ICONRAM, set CONRAM address

at 00h (first ICONRAM) and then write 00h

(null data) 16 times

2. Contrast control register setup

3. Power save (power save off; OSC on)

4. Power control (turns on the internal regulator and turns on the

internal divider)

No delay between each Command/Data

input under ideal timing situation (No time

shift in any signals, refer to page 32 for

details)

Command Input

5. RAM address set

Data Input

6. Data writing (RAM clear)

(DDRAM=20h, CG/ICONRAM=00h)

Command Input

7. Display control (turns on the display) (There is an auto mask

off period ~ 260ms)

End of initialization

Figure 23- Recommended INITIALIZING of SSD1800

SSD1800 Series Rev 1.0

P 41/42 Mar 2004

Solomon Systech

Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising

out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical” must be validated for

each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of

others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the

body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could

create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or

death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or

manufacture of the part.

http://www.solomon-systech.com

Solomon Systech

Mar 2004

P 42/42 Rev 1.0

SSD1800 Series


型号：	SSD1800Z
厂家：	ETC
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下载：	下载PDF数据表文档文件

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