SST32HF162-70-4C-L3K [ETC]
MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|48PIN|PLASTIC ; 混合内存| SRAM + EEPROM | CMOS | BGA | 48PIN |塑料\n
| 型号： | SST32HF162-70-4C-L3K |
| 厂家： | 
ETC |
| 描述： | MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|48PIN|PLASTIC
|
| 文件： | 总30页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
SST32HF802 / 162 / 164MPF (x16) + 1Mb SRAM (x16) ComboMemories
Data Sheet
FEATURES:
•
MPF + SRAM ComboMemory
•
•
Latched Address and Data for Flash
Flash Fast Erase and Word-Program:
– SST32HF802: 512K x16 Flash + 128K x16 SRAM
– SST32HF162: 1M x16 Flash + 128K x16 SRAM
– SST32HF164: 1M x16 Flash + 256K x16 SRAM
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
•
•
Single 2.7-3.3V Read and Write Operations
Concurrent Operation
– Read from or write to SRAM while
Erase/Program Flash
SST32HF802: 8 seconds (typical)
SST32HF162/164: 15 seconds (typical)
Flash Automatic Erase and Program Timing
– Internal VPP Generation
•
•
Superior Reliability
•
•
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Flash End-of-Write Detection
Low Power Consumption:
– Toggle Bit
– Data# Polling
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current: 20 µA (typical)
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Package Available
•
•
Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
– 48-lead TSOP (12mm x 20mm)
– 48-ball TBGA (10mm x 12mm)
– 48-ball LFBGA (6mm x 8mm)
Fast Read Access Times:
– Flash: 70 ns and 90 ns
– SRAM: 70 ns and 90 ns
bank enable signal, BEF# selects the flash memory bank.
The WE# signal has to be used with Software Data Protec-
tion (SDP) command sequence when controlling the Erase
and Program operations in the flash memory bank. The
SDP command sequence protects the data stored in the
flash memory bank from accidental alteration.
PRODUCT DESCRIPTION
The SST32HF802/162/164 ComboMemory devices inte-
grate a 512K x16 or 1M x16 CMOS flash memory bank
with a 128K x16 or 256K x16 CMOS SRAM memory bank
in a Multi-Chip Package (MCP), manufactured with SST’s
proprietary, high performance SuperFlash technology.
The SST32HF802/162/164 provide the added functionality
of being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled erase or pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for read or write.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
14 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 8 seconds for the
SST32HF802 and 15 seconds for the SST32HF162/164,
when using interface features such as Toggle Bit or Data#
Polling to indicate the completion of Program operation. To
protect against inadvertent flash write, the SST32HF802/
162/164 devices contain on-chip hardware and software
data protection schemes.The SST32HF802/162/164
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HF802/162/164 devices are suited for applica-
tions that use both flash memory and SRAM memory to
store code or data. For systems requiring low power and
small form factor, the SST32HF802/162/164 devices signif-
icantly improve performance and reliability, while lowering
power consumption, when compared with multiple chip
solutions. The SST32HF802/162/164 inherently use less
energy during erase and program than alternative flash
The SST32HF802/162/164 devices consist of two inde-
pendent memory banks with respective bank enable sig-
nals. The Flash and SRAM memory banks are
superimposed in the same memory address space. Both
memory banks share common address lines, data lines,
WE# and OE#. The memory bank selection is done by
memory bank enable signals. The SRAM bank enable sig-
nal, BES# selects the SRAM bank. The flash memory
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71171-04-000 7/01
1
520
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
technologies. The total energy consumed is a function of
SRAM Write
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies.
The SRAM Write operation of the SST32HF802/162/164
is controlled by WE# and BES# being low for the system
to write to the SRAM. During the Word-Write operation,
the addresses and data are referenced to the rising edge
of WE# or BES#, which ever occurs first. The write time is
measured from the last falling edge to the rising edge of
WE# or BES#. Refer to the Write cycle timing diagrams,
Figures 5 and 6, for further details.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Flash Operation
With BEF# active, the SST32HF162/164 operate as 1M
x16 flash memory and the SST32HF802 operates as 512K
x16 flash memory. The flash memory bank is read using
the common address lines, data lines, WE# and OE#.
Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and during the
internally timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. When
BES# is low, the SRAM Bank is activated for Read and
Write operation. When BEF# is low the flash bank is acti-
vated for Read, Program or Erase operation. BES# and
BEF# cannot be at low level at the same time. If BES# and
BEF# are both asserted to low level bus contention will
result and the device may suffer permanent damage. All
address, data, and control lines are shared by SRAM Bank
and flash bank which minimizes power consumption and
loading. The device goes into standby when both bank
enables are high.
Flash Read
The Read operation of the SST32HF802/162/164 devices
is controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The data
bus is in high impedance state when OE# is high. Refer to
Figure 7 for further details.
SRAM Operation
With BES# low and BEF# high, the SST32HF802/162
operate as 128K x16 CMOS SRAM, and the SST32HF164
operates as 256K x16 CMOS SRAM, with fully static oper-
ation requiring no external clocks or timing strobes. The
SST32HF802/162 SRAM is mapped into the first 128
KWord address space of the device, and the SST32HF164
SRAM is mapped into the first 256 KWord address space.
When BES# and BEF# are high, both memory banks are
deselected and the device enters standby mode. Read and
Write cycle times are equal. The control signals UBS# and
LBS# provide access to the upper data byte and lower data
byte. See Table 3 for SRAM read and write data byte con-
trol modes of operation.
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory bank
Program and Erase operations of the SST32HF802/162/
164. SDP commands are loaded to the flash memory bank
using standard microprocessor write sequences. A com-
mand is loaded by asserting WE# low while keeping BEF#
low and OE# high. The address is latched on the falling
edge of WE# or BEF#, whichever occurs last. The data is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
Flash Word-Program Operation
SRAM Read
The flash memory bank of the SST32HF802/162/164
devices is programmed on a word-by-word basis. Before
the Program operations, the memory must be erased first.
The Program operation consists of three steps. The first
step is the three-byte-load sequence for Software Data
Protection. The second step is to load word address and
word data. During the Word-Program operation, the
The SRAM Read operation of the SST32HF802/162/164 is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high. See
Figure 4 for the Read cycle timing diagram.
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
2
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
addresses are latched on the falling edge of either BEF# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either BEF# or WE#, whichever occurs first.
The third step is the internal Program operation which is ini-
tiated after the rising edge of the fourth WE# or BEF#,
whichever occurs first. The Program operation, once initi-
ated, will be completed, within 20 µs. See Figures 8 and 9
for WE# and BEF# controlled Program operation timing
diagrams and Figure 19 for flowcharts. During the Program
operation, the only valid flash Read operations are Data#
Polling and Toggle Bit. During the internal Program opera-
tion, the host is free to perform additional tasks. Any SDP
commands loaded during the internal Program operation
will be ignored.
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 11 for timing diagram,
and Figure 22 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF802/162/164 provide two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal program or erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF802/162/164 offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A19-A11, for SST32HF162/164, and A18-A11, for
SST32HF802, are used to determine the sector address.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A19-A15, for SST32HF162/164, and A18-A15,
for SST32HF802, are used to determine the block address.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 13
and 14 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Flash Data# Polling (DQ7)
When the SST32HF802/162/164 flash memory banks are
in the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles. During internal Erase operation,
any attempt to read DQ7 will produce a ‘0’. Once the inter-
nal Erase operation is completed, DQ7 will produce a ‘1’.
The Data# Polling is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operation. For Sector- or
Block-Erase, the Data# Polling is valid after the rising edge
of the sixth WE# (or BEF#) pulse. See Figure 10 for Data#
Polling timing diagram and Figure 20 for a flowchart.
Flash Chip-Erase Operation
The SST32HF802/162/164 provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
3
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
Sector- or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 11 for
Toggle Bit timing diagram and Figure 20 for a flowchart.
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Memory Data Protection
The SST32HF802/162/164 flash memory bank provides
both hardware and software features to protect nonvolatile
data from inadvertent writes.
Product Identification
The product identification mode identifies the devices as
the SST32HFxxx and manufacturer as SST. This mode
may be accessed by software operations only. The
hardware device ID Read operation, which is typically
used by programmers, cannot be used on this device
because of the shared lines between flash and SRAM
in the multi-chip package. Therefore, application of
high voltage to pin A9 may damage this device. Users
may use the software product identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Tables 3 and 4 for software operation, Figure 15 for the
software ID entry and read timing diagram and Figure 21
for the ID entry command sequence flowchart.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST32HF802/162/164 provide the JEDEC approved
software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF802/162/164 devices are shipped with the soft-
ware data protection permanently enabled. See Table 4 for
the specific software command codes. During SDP com-
mand sequence, invalid SDP commands will abort the
device to the read mode, within Read Cycle Time (TRC).
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
00BFH
SST32HF802
SST32HF162/164
0001H
0001H
2781H
2782H
T1.1 520
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software-reset command is ignored during an
internal Program or Erase operation. See Table 4 for soft-
ware command codes, Figure 16 for timing waveform and
Figure 21 for a flowchart.
Concurrent Read and Write Operations
The SST32HF802/162/164 provide the unique benefit of
being able to read from or write to SRAM, while simulta-
neously erasing or programming the Flash. This allows data
alteration code to be executed from SRAM, while altering
the data in Flash. The following table lists all valid states.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
CONCURRENT READ/WRITE STATE TABLE
Flash
SRAM
Read
Write
Program/Erase
Program/Erase
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
4
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
Control Logic
SRAM
UBS#
LBS#
BES#
BEF#
OE#
(1)-A
0
DQ - DQ
15
A
8
MS
I/O Buffers
DQ - DQ
7
0
WE#
Address Buffers
& Latches
SuperFlash
Memory
520 ILL B1.1
SST32HF162/164
SST32HF802
SST32HF802
SST32HF162/164
A15
A14
A13
A12
A11
A10
A9
A15
A14
A13
A12
A11
A10
A9
1
48
A16
NC
A16
NC
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
V
V
SS
DQ15
SS
4
DQ15
5
DQ7
DQ7
6
DQ14
DQ6
DQ14
DQ6
7
A8
A8
8
DQ13
DQ5
DQ13
DQ5
Standard Pinout
Top View
A19
NC
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
DQ12
DQ4
WE#
WE#
V
V
V
V
DDF
DDS
DDS
BES#
DDF
Die Up
BES#
UBS#
LBS#
A18
A17
A7
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
UBS#
LBS#
A18
A17
A7
A6
A6
A5
A5
A4
A4
A3
A3
V
V
SS
SS
A2
A2
BEF#
BEF#
A1
A1
A0
A0
520 ILL F01b.0
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
5
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TOP VIEW (balls facing down)
TOP VIEW (balls facing down)
6
5
4
3
2
1
6
BES#
V
DQ1 A1
A2
A3
A4
A7
NC
NC A14
A15
BES#
V
DQ1 A1
A2
A3
A4
A7
A19
NC A14
A15
SS
A9
SS
A9
5
4
3
2
1
A10 DQ5 DQ2 A0
OE# DQ7 DQ4 DQ0
A10 DQ5 DQ2 A0
OE# DQ7 DQ4 DQ0
A6 A18
A6 A18
NC
NC
A11 A8
A5 DQ8 DQ3 DQ12 A12 LBS#
A11 A8
A5 DQ8 DQ3 DQ12 A12 LBS#
A13 A17 UBS# BEF# DQ10
V
DQ6 DQ15
A13 A17 UBS# BEF# DQ10
V
DQ6 DQ15
DDF
DDF
WE#
V
A16
V
DQ9 DQ11 DQ13 DQ14
WE#
V
A16
V
SS
DQ9 DQ11 DQ13 DQ14
DDS
SS
DDS
A B C D E F G H
SST32HF802
A B C D E F G H
SST32HF162/SST32HF164
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TBGA (10MM X 12MM)
TOP VIEW (balls facing down)
SST32HF802
TOP VIEW (balls facing down)
SST32HF162/164
6
5
4
3
2
1
6
5
4
3
2
1
V
V
SS
A13 A12 A14 A15 A16 USB# DQ15
A13 A12 A14 A15 A16 USB# DQ15
SS
DQ6
DQ4
DQ3
DQ1
DQ6
DQ4
DQ3
DQ1
A9
A8
A10 A11 DQ7 DQ14 DQ13
A9
A8
A10 A11 DQ7 DQ14 DQ13
WE# NC LBS# NC DQ5 DQ12
V
WE# NC LBS# A19 DQ5 DQ12
V
DD
DD
BES# NC
A18
A6
NC DQ2 DQ10 DQ11
BES# NC
A18
A6
NC DQ2 DQ10 DQ11
A7
A3
A17
A4
A5
A1
DQ0 DQ8 DQ9
A0 BEF# OE#
A7
A3
A17
A4
A5
A1
DQ0 DQ8 DQ9
A0 BEF# OE#
V
V
A2
A2
SS
SS
A B C D E F G H
A B C D E F G H
FIGURE 3: PIN ASSIGNMENTS FOR 48-BALL LFBGA (6MM X 8MM)
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
6
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide flash addresses: A19-A0 for 16M, and A18-A0 for 8M
SRAM addresses: A16-A0 for 2M and A17-A0 for 4M
DQ15-DQ0 Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
BEF#
OE#
SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low.
Flash Memory Bank Enable
Output Enable
To activate the Flash memory bank when BEF# is low.
To gate the data output buffers.
WE#
VDDF
VDDS
Write Enable
To control the Write operations.
Power Supply (Flash)
Power Supply (SRAM)
2.7-3.3V Power Supply to Flash only.
2.7-3.3V Power Supply to SRAM only
(For L3K package, VDDF and VDDS share one pin as VDD.)
VSS
UBS#
LBS#
NC
Ground
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
No Connection
To enable DQ15-DQ8
To enable DQ7-DQ0
Unconnected Pins
T2.2 520
1. AMS=Most significant address
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
7
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode
BES#1 BEF#1 OE# WE# UBS# LBS# DQ15 to DQ8 DQ7 to DQ0
Address
Not Allowed
Flash
VIL
VIL
X2
X
X
X
X
X
X
Read
VIH
VIH
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
X
X
X
X
X
X
DOUT
DIN
X
DOUT
DIN
X
AIN
AIN
Program
Erase
Sector or Block address,
XXH for Chip-Erase
SRAM
Read
VIL
VIL
VIL
VIL
VIL
VIL
VIHC
X
VIH
VIH
VIH
VIH
VIH
VIH
VIHC
X
VIL
VIL
VIL
X
VIH
VIH
VIH
VIL
VIL
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
VIL
VIH
VIL
VIL
VIH
VIL
X
DOUT
DOUT
High Z
DIN
DOUT
High Z
DOUT
DIN
AIN
AIN
AIN
AIN
AIN
AIN
X
Write
X
DIN
High Z
DIN
X
High Z
High Z
Standby
X
High Z
Flash Write Inhibit
VIL
X
X
X
X
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
X
X
X
VIH
X
X
X
X
X
VIH
VIL
VIH
VIH
X
X
X
X
Output Disable
VIH
VIL
VIL
VIH
X
VIH
X
X
X
High Z
High Z
High Z
High Z
High Z
High Z
X
VIH
X
VIH
X
X
VIH
VIH
X
Product Identification
Software Mode
VIH
VIL
VIL
VIH
X
X
Manufacturer’s ID (00BFH)
Device ID3
A19-A1=VIL, A0=VIH
(See Table 4)
T3.2 520
1. Do not apply BES#=VIL and BEF#=VIL at the same time
2. X can be VIL or VIH, but no other value.
3. Device ID 2781H for SST32HF802, 2782H for SST32HF162/164
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
8
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
5555H AAH 2AAAH 55H 5555H A0H Data
WA3
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit
Software ID Exit
XXH
F0H
5555H AAH 2AAAH 55H 5555H F0H
T4.2 520
1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence.
3. WA = Program word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses A19-A15 address lines
AMS = Most significant address
AMS = A18 for SST32HF802 and A19 for SST32HF162/164
5. The device does not remain in Software Product ID Mode if powered down.
6. With AMS-A1 =0; SST Manufacturer’s ID= 00BFH, is read with A0=0,
SST32HF802 Device ID = 2781H, is read with A0=1.
SST32HF162/164 Device ID = 2782H, is read with A0=1.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD1 + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1 + 1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
9
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
IDD Power Supply Current
Min
Max Units Test Conditions
Address input = VIL/VIH, at f=1/TRC Min,
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
BEF#=VIL, BES#=VIH
20
20
45
mA
mA
mA
SRAM
BEF#=VIH, BES#=VIL
BEF#=VIH, BES#=VIL
Concurrent Operation
Write
Flash
WE#=VIL
BEF#=VIL, BES#=VIH, OE#=VIH
25
20
mA
mA
µA
SRAM
BEF#=VIH, BES#=VIL
ISB
Standby VDD Current 3.0V
3.3V
40
75
VDD = VDD Max, BEF#=BES#=VIHC
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
VIL
0.8
VIH
Input High Voltage
0.7VDD
V
VDD=VDD Max
VIHC
VOL
VOH
VOLS
VOHS
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
SRAM Output Low Voltage
SRAM Output High Voltage
VDD-0.3
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL=1 mA, VDD=VDD Min
IOH=-500 µA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
T5.5 520
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T6.0 520
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
12 pF
1
CIN
VIN = 0V
T7.0 520
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T8.1 520
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
10
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
AC CHARACTERISTICS
TABLE 9: SRAM READ CYCLE TIMING PARAMETERS
SST32HF802/162/164-70 SST32HF802/162/164-90
Symbol Parameter
Min
Max
Min
Max
Units
ns
TRCS
TAAS
TBES
TOES
TBYES
Read Cycle Time
70
90
Address Access Time
70
70
35
70
90
90
45
90
ns
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
ns
ns
1
TBLZS
TOLZS
0
0
0
0
0
0
ns
1
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
35
35
45
ns
1
TOHZS
TBYHZS
TOHS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
0
0
ns
1
ns
10
10
ns
T9.1 520
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS
SST32HF802/162/164-70 SST32HF802/162/164-90
Symbol Parameter
Min
70
60
60
0
Max
Min
90
80
80
0
Max
Units
ns
TWCS
TBWS
TAWS
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
80
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
80
ns
30
40
ns
0
30
0
0
40
0
ns
ns
TDHS
Data Hold from Write Time
ns
T10.1 520
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
11
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS
SST32HF802/162/164-70 SST32HF802/162/164-90
Symbol Parameter
Min
Max
Min
Max
Units
ns
TRC
TBE
TAA
Read Cycle Time
70
90
Bank Enable Access Time
Address Access Time
70
70
35
90
90
45
ns
ns
TOE
TBLZ
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
0
0
ns
TOLZ
TBHZ
ns
1
1
20
20
30
30
ns
TOHZ
ns
1
TOH
0
0
ns
T11.1 520
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
µs
TBP
Word-Program Time
20
TAS
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
0
30
0
ns
TAH
ns
TBS
ns
TBH
0
ns
TOES
TOEH
TBPW
TWP
TWPH
TBPH
TDS
0
ns
10
40
40
30
30
30
0
ns
ns
ns
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
ns
ns
TDH
TIDA
TSE
Data Hold Time
ns
Software ID Access and Exit Time
Sector-Erase
150
25
ns
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
100
ms
T12.0 520
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
12
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
T
RCS
ADDRESSES A
MSS-0
BES#
T
T
T
T
OHS
AAS
T
BES
T
BLZS
BHZS
T
OE#
OES
T
OLZS
OHZS
T
BYES
UBS#, LBS#
T
T
BYLZS
BYHZS
DQ
DATA VALID
15-0
520 ILL F21.0
Note: WE# remains High (V ) for the Read cycle
IH
A
= Most Significant SRAM Address
MSS
FIGURE 4: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESSES A
MSS-0
WE#
T
ASTS
T
T
WPS
WRS
T
AWS
T
BWS
BES#
T
BYWS
UBS#, LBS#
T
OEWS
T
ODWS
T
T
DHS
DSS
NOTE 2
VALID DATA IN
NOTE 2
DQ
DQ
7-0
15-8,
520 ILL F27.1
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
13
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
T
WCS
ADDRESSES A
MSS-0
T
T
WRS
WPS
WE#
T
BWS
BES#
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
DQ
DQ
7-0
15-8,
NOTE 2
NOTE 2
VALID DATA IN
520 ILL F29.0
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
FIGURE 6: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
14
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
T
T
AA
RC
ADDRESSES A
MSF-0
BEF#
OE#
T
BE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
BHZ
T
OH
T
HIGH-Z
BLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
520 ILL F18.0
A
= Most Significant Flash Address
MSF
FIGURE 7: FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
T
CH
BEF#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
520 ILL F04.1
A
= Most Significant Flash Address
MSF
X can be V or V , but no other value
IL
IH
FIGURE 8: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
15
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
T
AH
T
DH
T
CP
BEF#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
520 ILL F05.1
A
= Most Significant Flash Address
MSF
X can be V or V , but no other value
IL
IH
FIGURE 9: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
ADDRESSES A
MSF-0
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
Data
Data#
Data#
Data
520 ILL F06.0
A
= Most Significant Flash Address
MSF
FIGURE 10: FLASH DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
16
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
ADDRESSES A
MSF-0
T
BE
BEF#
OE#
T
OES
T
T
OE
OEH
WE#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
A
= Most Significant Flash Address
MSF
520 ILL F07.0
FIGURE 11: FLASH TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
MSF-0
CE#
OE#
WE#
T
WP
D
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
520 ILL F25.2
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 12)
A
= Most Significant Flash Address
MSF
X can be V or V , but no other value
IL IH
FIGURE 12: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
17
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
T
SE
SIX-WORD CODE FOR SECTOR-ERASE
2AAA 5555 5555 2AAA
5555
SA
X
ADDRESSES A
MSF-0
BEF#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
520 ILL F08.2
Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
SA = Sector Address
X
MSF
A
= Most Significant Flash Address
X can be V or V , but no other value
IL IH
FIGURE 13: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
T
SBE
SIX-WORD CODE FOR BLOCK-ERASE
5555
2AAA
5555
5555
2AAA
BA
X
ADDRESSES A
MSF-0
BEF#
OE#
T
WP
WE#
D
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
520 ILL F17.2
Note: The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
BA = Block Address
X
MSF
A
= Most Significant Flash Address
X can be V or V , but no other value
IL IH
FIGURE 14: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
18
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
THREE-WORD SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
DEVICE ID
MFG ID
520 ILL F09.1
Note: Device ID = 2781 for SST32HF802
Device ID = 2782 for SST32HF162/164
X can be V or V , but no other value.
IL
IH
FIGURE 15: SOFTWARE ID ENTRY AND READ
THREE-WORD SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
SW0
SW1
SW2
520 ILL F10.2
Note: X can be V or V , but no other value.
IL IH
FIGURE 16: SOFTWARE ID EXIT AND RESET
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
19
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
520 ILL F11.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
520 ILL F12.0
FIGURE 18: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
20
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
Start
Write data: XXAAH
Address: 5555H
Write data: XX55H
Address: 2AAAH
Write data: XXA0H
Address: 5555H
Write Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
520 ILL F13.3
Note: X can be V or V , but no other value
IL
IH
FIGURE 19: WORD-PROGRAM ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
21
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
BP
SCE, or BE
,
T
T
No
Read same
word
Is DQ =
7
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
520 ILL F14.0
FIGURE 20: WAIT OPTIONS
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
22
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: XXAAH
Address: 5555H
Write data: XXAAH
Address: 5555H
Write data: XXF0H
Address: XXXXH
Write data: XX55H
Address: 2AAAH
Write data: XX55H
Address: 2AAAH
Wait T
IDA
Write data: XX90H
Address: 5555H
Write data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
IDA
Wait T
IDA
Return to normal
operation
Read Software ID
520 ILL F15.2
Note: X can be V or V , but no other value.
IL
IH
FIGURE 21: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
23
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
SCE
Wait T
SE
Wait T
BE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
520 ILL F26.2
Note: X can be V or V , but no other value.
IL
IH
FIGURE 22: ERASE COMMAND SEQUENCE
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
24
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase
Initiated
Wait for End of
Write Indication
Read or Write
SRAM
End
Wait
Flash Operation
Completed
End Concurrent
Operation
520 ILL F19.0
FIGURE 23: CONCURRENT OPERATION FLOWCHART
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
25
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST32HFxxx
-
XXX
-
XX
-
XX
Package Modifier
K = 48 leads or balls
Package Type
E = TSOP (12mm x 20mm)
TB = TBGA (10mm x 12mm x 1.2mm)
L3 = LFBGA (6mm x 8mm x 1.4mm)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Density
802 = 8 Mbit Flash + 2 Mbit SRAM
162 = 16 Mbit Flash + 2 Mbit SRAM
164 = 16 Mbit Flash + 4 Mbit SRAM
Function
Voltage
H = 2.7-3.3V
Device Family
32 = MPF + SRAM ComboMemory
Valid combinations for SST32HF802
SST32HF802-70-4C-EK
SST32HF802-70-4E-EK
SST32HF802-70-4C-L3K
SST32HF802-70-4E-L3K
SST32HF802-70-4C-TBK
SST32HF802-70-4E-TBK
Valid combinations for SST32HF162
SST32HF162-70-4C-EK
SST32HF162-70-4E-EK
SST32HF162-70-4C-L3K
SST32HF162-70-4E-L3K
SST32HF162-70-4C-TBK
SST32HF162-70-4E-TBK
Valid combinations for SST32HF164
SST32HF164-70-4C-EK
SST32HF164-90-4C-EK
SST32HF164-70-4C-L3K
SST32HF164-90-4C-L3K
SST32HF164-70-4C-TBK
SST32HF164-90-4C-TBK
SST32HF164-70-4E-EK
SST32HF164-90-4E-EK
SST32HF164-70-4E-L3K
SST32HF164-90-4E-L3K
SST32HF164-70-4E-TBK
SST32HF164-90-4E-TBK
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
26
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
.50
BSC
.270
.170
12.20
11.80
0.15
0.05
18.50
18.30
0.70
0.50
48-TSOP-EK-ILL.6
20.20
19.80
Note:
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max). Scale is 1:5 mm.
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SST PACKAGE CODE: EK
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
27
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
BOTTOM VIEW
12.00 ± 0.20
7.0
TOP VIEW
1.0
8
7
6
5
4
3
2
1
8
7
10.00 ± 0.20
6
5.0
5
4
3
2
1
1.0
0.50 ± 0.05
(48X)
H
G F E D C B A
A
B C D E F G H
A1 CORNER
A1 CORNER
1.10 ± 0.10
SIDE VIEW
48ba-TBGA-TBK-10x12-500mic-ILL.5
1mm
0.15
SEATING PLANE
0.40 ± 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL THIN-PROFILE BALL GRID ARRAY (TBGA) 10MM X 12MM
SST PACKAGE CODE: TBK
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
28
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
BOTTOM VIEW
8.00 ± 0.20
5.60
0.80
TOP VIEW
6
5
4
3
2
1
6
5
4
3
2
1
4.00
6.00 ± 0.20
0.80
0.45 ± 0.05
(48X)
H
G F E D C B A
A
B C D E F G H
A1 CORNER
A1 CORNER
1.30 ± 0.10
SIDE VIEW
0.15
48ba-LFBGA-L3K-6x8-450mic-ILL.1
1mm
SEATING PLANE
0.35 ± 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM
SST PACKAGE CODE: L3K
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
29
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71171-04-000 7/01 520
30
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