STK1744-D35I [ETC]
32K x 8 AutoStore nvSRAM with Real-Time Clock; 32K ×8自动存储的nvSRAM具有实时时钟
| 型号： | STK1744-D35I |
| 厂家： | 
ETC |
| 描述： | 32K x 8 AutoStore nvSRAM with Real-Time Clock |
| 文件： | 总12页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK1744
nvTime™
32K x 8 AutoStore™ nvSRAM
with Real-Time Clock
PRELIMINARY
DESCRIPTION
FEATURES
• Data Integrity of Simtek nvSRAM Combined
The Simtek STK1744 DIP module houses 256Kb of
nonvolatile static RAM, a real-time clock (RTC) with
crystal and a high-value capacitor to support sys-
tems that require high reliability and ease of manu-
facturing. READ and WRITE access to all RTC
functions and the memory is the same as a conven-
tional x 8 SRAM. The highest eight addresses of the
RAM support clock registers for centuries, years,
months, dates, days, hours, minutes and seconds.
with Full-Featured Real-Time Clock
• Stand-Alone Nonvolatile Memory and Time-
Keeping Solution—No Other Parts Required
• No Batteries to Fail
• Fast 25ns, 35ns and 45ns Access Times
• Software- and AutoStore™-Controlled
Nonvolatile Cycles
• Year 2000 Compliant with Leap Year
Independent data resides in the integral Nonvolatile
Elements at all times. Automatic RECALL on power
up transfers the Nonvolatile Elements data to the
SRAM, while an automatic STORE on power down
transfers SRAM data to the Nonvolatile Elements. A
software RECALL and STORE are also possible on
user command. nvTime™ allows unlimited READ
and WRITE accesses to SRAM, unlimited RECALLs
Compensation
• 24-Hour BCD Format
• 100-Year Data Retention over Full Industrial
Temperature Range
• Full 30-Day RTC Operation on Each Power
Loss
• Single 5V ± 10% Power Supply
6
and 10 STOREs.
BLOCK DIAGRAM
PIN CONFIGURATIONS
A14
A12
A7
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
V
CC
QUANTUM TRAP
3
4
5
6
7
8
9
A13
A8
512 x 512
A6
A5
A5
A9
STORE/
POWER
A6
A4
A11
G
A10
E
RECALL
STORE
CONTROL
A3
A7
CONTROL
A2
A8
STATIC RAM
ARRAY
A1
28 - 600 DIP
Module
RECALL
A9
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
SOFTWARE
DETECT
A11
A12
A13
A14
512 x 512
A
- A
13
DQ0
DQ1
DQ2
VSS
0
(See application
note for surface
mount)
RTC
MUX
DQ
DQ
DQ
0
1
2
PIN NAMES
COLUMN I/O
COLUMN DEC
A
- A
Address Inputs
0
14
DQ
3
4
W
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
DQ
A
A
-
0
DQ - DQ
0
DQ
DQ
DQ
7
5
6
7
14
A
0
A A A
A A
1 4
2 3
10
E
G
G
V
V
CC
SS
E
W
January 2003
1
Document Control # ML0020 rev 0.0
STK1744
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V Current
97
80
70
100
85
70
mA
mA
mA
t
t
t
= 25ns
= 35ns
= 45ns
CC
CC
AVAV
AVAV
AVAV
1
I
I
Average V Current during STORE
3
3
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
3
b
W ≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
Average V
Current at t = 200ns
AVAV
CC
10
10
mA
5V, 25°C, Typical
c
I
Average V Current
30
25
22
31
26
23
mA
mA
mA
t
t
t
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
SB
CC
AVAV
AVAV
AVAV
IH
IH
IH
1
(Standby, Cycling TTL Input Levels)
c
I
I
I
V
Standby Current
E ≥ (V
– 0.2V)
IN
SB
CC
CC
All Others V ≤ 0.2V or ≥ (V
2
1.5
±1
±5
1.5
±1
±5
mA
µA
µA
(Standby, Stable CMOS Input Levels)
– 0.2V)
CC
Input Leakage Current
V
V
= max
CC
IN
ILK
= V to V
SS
CC
Off-State Output Leakage Current
V
V
= max
CC
IN
OLK
= V to V , E or G ≥ V
SS CC
IH
V
V
V
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
V
+ .5
V
V
All Inputs
All Inputs
IH
CC
0.8
CC
0.8
V
– .5
V
– .5
SS
IL
SS
2.4
2.4
V
I
I
=– 4mA
= 8mA
OH
OL
OUT
0.4
70
0.4
85
V
OUT
T
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained at minimum cycle with outputs unloaded.
Note c: E ≥1VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
5.0V
CAPACITANCEd
(TA = 25°C, f = 1.0MHz)
480 Ohms
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
OUTPUT
C
Input Capacitance
10
pF
IN
30 pF
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
C
Output Capacitance
12
pF
OUT
Note d: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
January 2003
2
Document Control # ML0020 rev 0.0
STK1744
READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
STK1744-25
STK1744-35
STK1744-45
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
e
Read Cycle Time
25
35
45
AVAV
RC
AA
f
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
f
5
5
5
5
5
5
5
AXQX
6
ELQX
g
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
g
9
GHQZ
d
10
11
ELICCH
EHICCL
,
c
d
PS
Note e: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note f: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note g: Measured + 200mV from steady state output voltage.
READ CYCLE #1: Address Controllede, f
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DATA VALID
DQ (DATA OUT)
READ CYCLE #2: E Controllede
2
t
AVAV
ADDRESS
1
11
t
ELQV
t
6
EHICCL
E
t
ELQX
7
t
EHQZ
G
9
4
t
GHQZ
t
GLQV
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
STANDBY
I
CC
January 2003
3
Document Control # ML0020 rev 0.0
STK1744
WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
STK1744-25
STK1744-35
STK1744-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
AVWH
AVEH
AW
t
t
t
AVWL
AVEL
AS
t
t
t
0
0
0
WHAX
EHAX
WR
g, h
t
t
10
13
15
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note h: If W is low when E goes low, the outputs remain in the high-impedance state.
Note i: E or W must be ≥ VIH during address transitions.
WRITE CYCLE #1: W Controlledi
12
t
AVAV
ADDRESS
19
14
t
WHAX
t
ELWH
E
17
t
AVWH
18
t
AVWL
13
W
t
WLWH
15
16
t
t
DVWH
WHDX
DATA IN
DATA VALID
20
t
WLQZ
21
t
WHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
WRITE CYCLE #2: E Controlledi
12
t
AVAV
ADDRESS
18
14
19
t
t
t
AVEL
ELEH
EHAX
E
17
t
AVEH
13
t
WLEH
W
15
16
t
DVEH
t
EHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
January 2003
4
Document Control # ML0020 rev 0.0
STK1744
AutoStore™/POWER-UP RECALL
(VCC = 5.0V ± 10%)
SYMBOLS
STK1744
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
t
t
Power-up RECALL Duration
STORE Cycle Duration
µs
ms
V
j
RESTORE
STORE
f
V
V
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
4.5
SWITCH
RESET
3.9
V
Note j: tRESTORE starts from the time VCC rises above VSWITCH
.
AutoStore™/POWER-UP RECALL
VCC
5V
24
VSWITCH
25
VRESET
AutoStore™
23
t
STORE
POWER-UP RECALL
22
t
RESTORE
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
BROWN OUT
AutoStore™
BROWN OUT
AutoStore™
NO RECALL
NO RECALL
RECALL WHEN
(VCC DID NOT GO
(VCC DID NOT GO
V
RETURNS
CC
BELOW VRESET
)
BELOW VRESET
)
ABOVE VSWITCH
January 2003
5
Document Control # ML0020 rev 0.0
STK1744
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
NOTES
13
0
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
L
H
k, l
Read SRAM
Read SRAM
Nonvolatile STORE
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
L
H
k, l
Read SRAM
Read SRAM
Nonvolatile RECALL
Note k: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note l: While there are 15 addresses on the STK1744, only the lower 14 are used to control software modes.
SOFTWARE STORE/RECALL CYCLEm, n
(VCC = 5.0V ± 10%)
STK1744-25
MIN MAX
STK1744-35
MIN MAX
STK1744-45
NO.
SYMBOLS
PARAMETER
UNITS
MIN
45
0
MAX
26
27
28
29
30
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
25
0
35
0
ns
ns
ns
ns
µs
AVAV
AVEL
m
m
20
20
25
20
30
20
ELEH
ELAX
f, m
Address Hold Time
RECALL Duration
20
20
20
RECALL
Note m: The software sequence is clocked with E controlled reads.
Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlled
26
AVAV
26
AVAV
t
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
ELEH
t
t
E
29
ELAX
t
23
30
t
STORE / t
RECALL
HIGH IMPEDANCE
DQ (DATA OUT)
DATA VALID
DATA VALID
January 2003
6
Document Control # ML0020 rev 0.0
STK1744
DEVICE OPERATION
The STK1744 is a 32K x 8 nonvolatile static RAM
NOISE CONSIDERATIONS
with a full-function real-time clock (RTC). Nonvolatile
data is preserved in integral QuantumTrap Nonvol-
atile Elements and is not subject to battery failure or
capacitor discharge. The real-time clock registers
reside in the eight uppermost RAM locations, and
contain century, year, month, date, day, hour, minute
and second data in 24-hour BCD format. Corrections
for the day of the month and leap years are made
automatically. This nonvolatile time-keeping RAM is
functionally similar to any JEDEC standard 32K x 8
SRAM.
Note that the STK1744 is a high-speed memory and
so must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCC and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SRAM AND RTC READ
The STK1744 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-14 determines which of the 32,760 data
bytes or 8 RTC registers will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond to
address changes within the tAVQV access time without
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought high or W is brought low.
The RTC registers are double-buffered to avoid
access of incorrect data that could otherwise occur
during clock update cycles. The double-buffered
system prevents time loss by maintaining internal
clock operation while time register data is accessed.
The STK1744 contains integral power-fail circuitry
that deselects the device when VCC drops below
VSWITCH
.
The STK1744 is a pin-compatible replacement for
the ST Microelectronics M48T35 and the Dallas
Semiconductor DS1744, but without the limitations
of an embedded lithium battery. The Simtek module
uses a double-layer high-value capacitor to maintain
RTC operation on every power down for at least 30
days. The part can be soldered directly onto printed
circuit boards and handled without concern for dam-
aging or discharging internal batteries. Unlike some
other RTCs, the STK1744 is Year 2000-compliant.
Note that the eight most significant bytes of the
address space are reserved for accessing the RTC
registers, as shown in the RTC Register Map.
While the double-buffered RTC register structure
reduces the chance of reading incorrect data from the
clock, the user should halt internal updates to the
RTC REGISTER MAP
BCD DATA
ADDRESS
FUNCTION/RANGE
(HEXADECIMAL)
D7
W
X
D6
D5
D4
D3
D2
D1
D0
7FF8
7FF9
7FFA
7FFB
7FFC
7FFD
7FFE
7FFF
R
10 Centuries
Centuries
Seconds
Minutes
Hours
Centuries: 00 - 39, Control
Seconds: 00 - 59
10 Seconds
10 Minutes
X
Minutes: 00 - 59
X
X
FT
X
10 Hours
Hours:
Days:
Dates:
00 - 23
01 - 07
01 - 31
1
X
X
X
X
Days
X
10 Dates
10 Mos.
Dates
X
X
Months
Years
Months: 01 - 12
Years: 00 - 99
10 Years
Key:
R
= Read Bit
W = Write Bit
= Battery Flag high (there is no battery to fail)
FT = Frequency test bit
= Don’t Care
1
X
January 2003
7
Document Control # ML0020 rev 0.0
STK1744
STK1744 clock registers before reading clock data
to prevent reading of data in transition. Stopping the
internal register updates does not affect clock accu-
racy.
CLOCK ACCURACY
The STK1744 is guaranteed to be accurate to
within ± 1 minute per month at 25°C. The part
requires no additional calibration, and temperature
variations will have a negligible effect in most appli-
cations.
The updating process is stopped by writing a “1” to
the read bit (the second most significant bit in the
control register 7FF8), and will not restart until a “0”
is written to the read bit. The RTC registers can
then be read while the internal clock continues to
run.
DATA RETENTION MODE
During normal operation (VCC ≥ 4.5V), the STK1744
can be accessed with standard SRAM READ and
WRITE cycles. However, when VCC falls below the
power-fail voltage, VSWITCH (the voltage at which
write protection occurs), access to the internal clock
register and the SRAM is blocked. At this voltage,
SRAM data is automatically stored to the integral
Nonvolatile Elements, and power for the clock oscil-
lator switches from the VCC pin to the internal capac-
itor. The capacitor maintains clock activity and clock
data until VCC returns to its nominal level.
Within one second after a “0” is written to the read
bit, all STK1744 registers are simultaneously
updated.
SRAM WRITE AND
SETTING THE CLOCK
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of
an E controlled WRITE.
SOFTWARE NONVOLATILE STORE
The STK1744 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal cir-
cuitry will turn off the output buffers tWLQZ after W
goes low.
Setting the write bit (the MSB of the control register
7FF8) to a “1” halts updates to the STK1744 regis-
ters. The correct day, date and time can then be
written into the registers in 24-hour BCD format.
Resetting the write bit to “0” transfers those values
to the actual clock counters, after which the clock
resumes normal operation.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
FREQUENCY TEST BIT
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
As shown in the RTC Register Map, bit 6 of the day
byte is the frequency test (FT) bit. When the FT bit
is set to logic “1”, the LSB of the seconds register
will toggle at 512Hz. When the seconds register is
being read, the DQ0 line will toggle at 512Hz as
long as conditions for access remain valid (i.e., CE
low, OE low, WE high and the address for the sec-
onds register valid and stable). The FT bit must be
reset to “0” in order to resume reading the time
from the seconds register.
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E
controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
SRAM will be disabled. The clock addresses may be
January 2003
8
Document Control # ML0020 rev 0.0
STK1744
accessed during this period. It is important that
READ cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G be
low for the sequence to be valid. After the tSTORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds VSWITCH, a
RECALL cycle will automatically be initiated and will
take tRESTORE to complete.
If the STK1744 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a
sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of READ
operations must be performed:
V
CC or between E and system VCC.
HARDWARE PROTECT
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
The STK1744 offers hardware protection against
inadvertent STORE and SRAM WRITE operation dur-
ing low-voltage conditions. When VCC < VSWITCH, all
software STORE operations and SRAM WRITEs are
inhibited.
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times. Note that
the RTC registers are not affected by nonvolatile
operations.
LOW AVERAGE ACTIVE POWER
The STK1744 draws significantly less current when
it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK1744 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the VCC level; and 7) I/O loading.
AutoStoreTM OPERATION
The STK1744 uses capacitance built into the mod-
ule to perform an automatic STORE on power down.
In order to prevent unnecessary STORE operations,
automatic STOREs will be ignored unless at least
one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software-
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place.
January 2003
9
Document Control # ML0020 rev 0.0
STK1744
aaa
100
80
60
40
20
0
100
80
60
40
20
0
TTL
CMOS
TTL
CMOS
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
January 2003
10
Document Control # ML0020 rev 0.0
STK1744
ORDERING INFORMATION
- D 25 I
STK1744
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns (commercial only)
35 = 35ns
45 = 45ns
Package
D = 600 mil Dual In-Line Module
Note: See Application Note
for surface mount.
January 2003
11
Document Control # ML0020 rev 0.0
STK1744
Document Revision History
Revision
0.0
Date
January 2003
Summary
January 2003
12
Document Control # ML0020 rev 0.0
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