STP2000QFP [ETC]
I/O Controller ; I / O控制器\n
| 型号： | STP2000QFP |
| 厂家： | 
ETC |
| 描述： | I/O Controller
|
| 文件： | 总20页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STP2000QFP
July 1997
Master I/O
32-bit SBus Master I/ O Controller
DATA SHEET
DESCRIPTION
The STP2000 Master I/ O Controller is an integrated SBus master device with built-in standard I/ O capabili-
ties for general purpose computing or embedded applications. The STP2000 directly interfaces the CPU
through the system bus, SBus, to three major I/ O channels for peripherals. The I/ O channels include SCSI-II,
ethernet and a parallel port. Together, with the STP2001 Slave I/ O Controller, it provides a complete I/ O
subsystem.
The STP2000 SBus interface is a 32-bit interface that supports both DMA and slave modes. There is data buff-
ering and flow control on each of the I/ O channels. Each channel has access to the SBus through the controller
which is capable of DMA transfers of up to 32-byte bursts. The SBus slave port is used mostly for status and
control.
The STP2000 incorporates an ethernet controller, a Fast 8-bit SCSI-II controller, and a Centronics parallel port
controller in a single package. The SCSI-II channel directly drives external peripherals. The ethernet channel
can be connected to an external transceiver chip that supports twisted pair ethernet or AUI ethernet. The par-
allel port channel can be routed to external transceivers.
Features
Benefits
• Single-chip solution to standard SPARC DVMA devices
• Saves cost, power, board space, and weight
• Standard low-cost solution
• Compatible with microSPARC, SuperSPARC and any
SBus based system
• Supports concurrent 10 MByte/sec SCSI transfers,
1.25 MByte/sec Ethernet transfers, and 4 MByte/sec
Parallel Port transfers
• Improved system performance
• Direct master/slave SBus interface
• Improved system performance
• Improved chip and board level testability
• Cost effective packaging
• JTAG internal and boundary SCAN logic
• 160-pin PQFP packaging
• IC is also available from NCR Corp. (PN - NCR89C100)
• Second source
1
This Material Copyrighted by Its Respective Manufacturer
Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
BLOCK, APPLICATION, AND LOGIC DIAGRAMS
SBus
Control
14
Data
32
Address
10
6
5
8
JTAG
Slave I/O Clocks
and Interrupts
SBUS DVMA Master
XTAL Osc.
PROM CS
ETHERNET®
Controller
(NCR92C990)
SCSI Controller
(NCR53C9x)
Parallel Port
8
13
5
3
9
9
Data
Control
Data & Control
Data
Control
CENTRONICS® Parallel Port
Ethernet Network Adaptor
SCSI Bus
Figure 1. STP2000 Block Diagram
SCSI Connector
160-Pin I/O Connector
SCSI
Ethernet Parallel
Video
Floppy Key/Mouse Audio
Serial
2
1
0
DRAM Banks
RAMDAC
VRAM
Bank 0
STP2000
Master I/O
MicroSPARC CPU
Frame Buffer
SBUS
Slot 1
Slot 0
STP2001
Slave I/O
SBus Connectors
Floppy Connector
Internal EBus
TOD/NVRA
Boot PROM
Figure 2. STP2000 Typical Application
2
July 1997
This Material Copyrighted by Its Respective Manufacturer
Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
SCSI_D[7:0]
SCSI_DP
SCSI_SEL
SB_A
SCSI_BSY
SCSI_REQ
SCSI_ACK
SCSI_MSG
SCSI_CD
SB_RESET
SB_LERR
SB_CLK
SB_RD
SB_SEL
SCSI_IO
SB_D_IRQ
SB_E_IRQ
SB_P_IRQ
SB_SIZ[2:0]
MACIO_SEL
SB_PA_W
SB_PA_X
SB_PA_Y
SB_PA[5:0]
SB_AS
SCSI_ATN
SCSI_RST
SCSI_XTAL_IN
SCSI_XTAL_OUT
P_DATA[0-7]
P_D_STRB
P_BSY
P_ACK
(ELP_PE) P_PE
P_SLCT
ENET_AUI
P_ERROR
P_INIT
ENET_TX
ENET_TENA
ENET_CLSN
ENET_RX
P_SLCT_IN
P_AFXN
P_DS_DIR
P_BSY_DIR
P_ACK_DIR
P_D_DIR
ENET_RENA
ENET_TCLK
ENET_RCLK
ID_CS
SCC_20_IN
SCC_20_OUT
SCC_CLK20
FPY_24_IN
JTAG_TDO
JTAG_TDI
JTAG_CLK
JTAG_TMS
JTAG_RST
FPY_24_OUT
FPY_CLK24
FPY_32_IN
FPY_32_OUT
FPY_CLK32
VCC
GND
Figure 3. STP2000 Logical Connections
July 1997
3
This Material Copyrighted by Its Respective Manufacturer
Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
SIGNAL DESCRIPTIONS
SBus Interface
Name
SB_D[31:0]
SB_BR
Type
I/O
Description
SBus Data Bus (MSB)
SBus Bus Request
SBus Bus Grant
SBus Acknowledge
SBus Reset
I/O
SB_BG
Input
I/O
SB_ACK[2:0]
SB_RESET
SB_LERR
SB_CLK
Input
Input
Input
I/O
SBus Late Error (INT15)
SBus Clock Input
SBus Read/Write
SBus Select
SB_RD
SB_SEL
Input
SB_D_IRQ
SB_E_IRQ
SB_P_IRQ
SB_SIZ[2:0]
SB_AS
Output SBus Interrupt for SCSI transfers (open-drain)
Output SBus Interrupt for ETHERNET transfers (open-drain)
Output SBus Interrupt for Parallel Port Transfers (open-drain)
I/O
SBus Transfer Size
Input
Input
Input
Input
Input
Input
SBus Address Strobe (address is valid)
High order physical address bit
High order physical address bit
High order physical address bit
High order physical address bit
Low order physical address bits
[1]
CHIP_SEL
SB_PA[W]
SB_PA[X]
SB_PA[Y]
SB_PA[5:0]
1. The CHIP_SEL pin is an additional qualifier (active high) to the SB_SEL line. In some system configurations where the STP2000
(Master I/O Controller) and the STP2001 (Slave I/O Controller) share a single SBus select line, PA[27] can be used to select
between the two.
4
July 1997
This Material Copyrighted by Its Respective Manufacturer
Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
Ethernet Interface
Name
Type
Description
[1]
ENET_AUI
Output
Output
Output
Input
Ethernet TP/AUI select
Ethernet Transmit data
Ethernet Transmit enable
Ethernet Collision detect
Ethernet Receive data
ENET_TX
ENET_TENA
ENET_CLSN
ENET_RX
Input
ENET_RENA
ENET_TCLK
ENET_RCLK
Input
Ethernet Receiver enable (carrier sense)
Ethernet Transmit clock
Input
Input
Ethernet Receive clock
1. Drives MIS input of the AT&T T7213 chip to select between twisted pair and AUI-type Ethernet interfaces, with ENET_AUI = 0 selecting
AUI.
[1]
SCSI Interface
Name
SCSI_D[7:0]
SCSI_DP
Type
I/O
Description
SCSI Data
I/O
SCSI Data Parity
SCSI Select
SCSI_SEL
SCSI_BSY
SCSI_REQ
SCSI_ACK
SCSI_MSG
SCSI_CD
I/O
I/O
SCSI Busy
I/O
SCSI Request
SCSI Acknowledge
SCSI Message
SCSI Command/Data
SCSI Input/Output
SCSI Attention
SCSI Reset
I/O
I/O
I/O
SCSI_IO
I/O
SCSI_ATN
SCSI_RST
SCSI_XTAL_IN
SCSI_XTAL_OUT
I/O
I/O
Input
Output
SCSI Clock Crystal In (can drive with external CMOS clock)
SCSI Clock Crystal Out (must not connect to any external load)
1. All of the SCSI pads (except the crystal oscillator pads) are custom NCR 48 mA bidirectional open-drain pads with hysteresis on inputs.
Parallel Port Interface
Name
P_DATA[7:0]
P_D_STRB
P_BSY
Type
Description
3-State Parallel Port Data Bus
I/O
I/O
Parallel Port Data Strobe (25 µA pull-down)
Parallel Port Busy (25 µA pull-up)
July 1997
5
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Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
Parallel Port Interface
Name
P_ACK
Type
I/O
Description
Parallel Port Acknowledge (25 µA pull-down)
Parallel Port Paper Error
Parallel Port Select
(ELP_PE) P_PE
P_SLCT
I/O
I/O
P_ERROR
P_INIT
Input
Parallel Port Error
Output Parallel Port Initialize
P_SLCT_IN
P_AFXN
Output Parallel Port Select In
Output Parallel Port Auto Feed
[1]
P_DS_DIR
Output Parallel Port Data Strobe Direction
Output Parallel Port Busy Direction
Output Parallel Port Acknowledge Direction
Output Parallel Port Data Direction
[1]
P_BSY_DIR
[1]
P_ACK_DIR
[1]
P_D_DIR
ID_CS
Output Secondary Device Select (boot prom) output; pull low to specify absence of external
PROM
1. The Parallel Port control and data line direction bits, (for example, P_*_DIR), are gang programmed by the DIR bit of the Transfer
Control Register.
DIR=0 sets transfer direction away from the STP2000 (P_D_DIR=P_DS_DIR=1; P_BSY_DIR=P_ACK_DIR=0); DIR=1 sets transfer
direction towards the STP2000 (P_D_DIR=P_DS_DIR=0; P_BSY_DIR=P_ACK_DIR=1).
JTAG Interface
Name
JTAG_TDO
JTAG_TDI
JTAG_CLK
JTAG_TMS
JTAG_RST
Type
Description
Output JTAG Test Data Output
Input
Input
Input
Input
JTAG Test Data Input (100 µA pull-up)
JTAG Clock
JTAG Test Mode Select (100 µA pull-up)
JTAG Reset (100 µA pull-up)
[1]
Clock/Oscillator Interface
Name
Type
Description
SCC_20_IN
SCC_20_OUT
SCC_CLK20
FPY_24_IN
FPY_24_OUT
FPY_CLK24
Input
SCC Clock Crystal In (19.66 MHz) (can drive with external CMOS clock)
Output SCC Clock Crystal Out (19.66 MHz) (must not connect to any external load)
Output SCC Clock Out (19.66 MHz)
Input
Floppy Clock Crystal In (24 MHz) (can drive with external CMOS clock)
Output Floppy Clock Crystal Out (24 MHz) (must not connect to any external load)
Output Floppy Clock Out (24 MHz)
6
July 1997
This Material Copyrighted by Its Respective Manufacturer
Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
[1]
Clock/Oscillator Interface
(Continued)
Name
FPY_32_IN
FPY_32_OUT
FPY_CLK32
Type
Description
Input
Floppy Clock Crystal In (32 MHz) (can drive with external CMOS clock)
Output Floppy Clock Crystal Out (32 MHz) (must not connect to any external load)
Output Floppy Clock Out (32 MHz)
1. In some system configurations, the STP2000 provides these three clocks to the STP2001 (Slave I/O Controller) (which is pin limited).
These are really general-purpose 20-50 MHz crystal oscillator pads that can operate in both fundamental and overtone mode.
July 1997
7
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Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
ELECTRICAL CHARACTERISTICS
[1]
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
V
V
V
Power supply voltage
Input voltage
7.0
CC
V
+ 0.5
CC
V
IN
I
Current Drain V and GND
100
mA
°C
I
CC
T
T
T
Lead temperature (less than 10 second soldering)
Operating temperature
250
L
0 to +70
°C
J
Storage temperature
-55 to +150
°C
S
1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages
are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
Symbol
Parameter
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Units
V
V
Supply voltage
CC
T
Operating Temperature
°C
A
P
Power consumption (@ 25 MHz SBus)
–
750
1400
mW
D
Capacitance
Symbol
Parameter
Input capacitance
Typ
6
Max
–
Units
pF
C
C
C
C
IN
Output capacitance
6
–
pF
OUT
BI
Bidirectional pin capacitance
SCSI pin capacitance
6
–
pF
–
10
pF
SCSI
8
July 1997
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Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
DC Characteristics
Symbol
Parameter
Min
2.0
–
Typ
–
Max
–
Units
V
V
V
V
V
Input high voltage
Input Low voltage
IH
–
0.8
–
V
IL
High level output voltage
Low level output voltage
Input leakage current
4.4
–
4.5
0
V
OH
OL
0.1
10
–
V
I
-10
2
–
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IN
OH
I
High level source
I
I
I
I
I
I
I
I
I
I
I
= 2.0 mA
= 4.0 mA
–
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
current (V = 2.4 V)
OH
4
–
–
= 8.0 mA
8
–
–
= 16.0 mA
= 24.0 mA
= -2.0 mA
= -4.0 mA
= -8.0 mA
= -16.0 mA
= -24.0 mA
= -48.0 mA
16
24
2
–
–
–
–
I
Low level sink
–
–
OL
current (V = 0.4 V)
OL
4
–
–
8
–
–
16
24
48
48
48
–
–
–
–
–
–
SCSIPAD (V = 0.5 V)
–
–
OL
SCSIPADF (V = 0.5 V)
–
–
OL
July 1997
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Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
AC Characteristics: SBus Timing
Signal #
Parameter
Conditions
Min
40.0
17.0
17.0
0.0
Max
60.0
–
Units
ns
1
2
3
4
5
6
7
8
9
Clock Period
Clock High
Clock Low
ns
–
ns
Hold wrt CLK Rising
Setup to CLK Rising
Hold wrt CLK Rising
Hold wrt CLK Rising
–
ns
15.0
1.0
–
ns
[1]
–
ns
0.0
–
ns
CLK Rising to Output Valid
CLK Rising to Output Invalid
160 pF load
160 pF load
2.5
22.5
20.0
ns
2.5
ns
1. This is the only violation of SBus Specification B.0. No known implementation to date provides less than 1.0 ns hold time on these
signals.
AC Characteristics: Parallel Port Timing
Signal #
10
Parameter
CLK to P_D_STRB
Conditions
75 pF
Min
–
Max
Units
35
ns
SB_CLK periods
11
P_D_STRB nominal width
P_DATA valid to P_D_STRB assert
P_DATA valid (nominal)
DSW=0,1,2,3
75 pF
3
–
12
5
–
ns
SB_CLK periods
13
DSS=0, DSN=3
6
–
14
P_ACK, P_BSY setup to CLK
P_ACK, P_BSY input pulse width
P_D_STRB setup to CLK
5
–
ns
SB_CLK periods
15
3
–
16
5
–
ns
SB_CLK periods
17
P_D_STRB input pulse width
P_DATA setup to P_D_STRB
P_DATA input hold from P_D_STRB
P_D_STRB to P_BSY valid
CLK to P_ACK, P_BSY
3
–
18
36
4
–
ns
SB_CLK periods
19
–
SB_CLK periods
20
75 pF
75 pF
75 pF
75 pF
2
3 + 26 ns
21
–
40
–
ns
SB_CLK periods
22
P_ACK, P_BSY nominal pulse width
CLK to output
3
23
–
35
ns
10
July 1997
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Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
AC Characteristics: SCSI TIming
Signal #
24
Parameter
Conditions
Min
Max
Units
ns
Clock period (t
)
25
83.3
CP
25
Synchronization latency
t
t
+ t
CP
ns
CL
CL
With FASTCLK bit reset
[1]
26
27
28
29
Clock frequency, asynchronous
12
20
25
25
MHz
MHz
[1]
Clock frequency, synchronous
Clock high
14.58
14.58
0.65 x t
0.65 x t
ns
ns
CP
CP
Clock low (t
)
CL
With FASTCLK bit set
Asynchronous SCSI
[1]
26
27
28
29
Clock frequency, asynchronous
20
38
40
40
MHz
MHz
ns
[1]
Clock frequency, synchronous
Clock high
0.40 x t
0.40 x t
0.60 x t
0.60 x t
CP
CP
CP
CP
Clock low (t
)
ns
CL
30
31
32
33
Data setup to SCSI_ACK/SCSI_REQ low
60
5
–
–
ns
ns
ns
ns
Data hold from SCSI_REQ high/SCSI_ACK low FIFO is not empty
SCSI_ACK low to SCSI_REQ high
–
50
45
SCSI_ACK high to SCSI_REQ low
(data already setup)
FIFO is not full.
–
34
35
SCSI_REQ high to SCSI_ACK high
–
–
50
50
ns
ns
SCSI_REQ low to SCSI_ACK low
(data already setup)
FIFO is not full.
36
37
Data setup to SCSI_REQ/SCSI_ACK low
Data hold from SCSI_REQ/SCSI_ACK low
0
–
–
ns
ns
18
Synchronous SCSI - Normal SCSI
Data setup to SCSI_REQ/SCSI_ACK low
38
39
40
41
55
100
90
–
–
–
–
ns
ns
ns
ns
Data hold from SCSI_REQ/SCSI_ACK low
SCSI_REQ/SCSI_ACK assertion period
SCSI_REQ/SCSI_ACK negation period
90
Synchronous SCSI - Fast SCSI
38
39
40
41
Data setup to SCSI_REQ/SCSI_ACK low
Data hold from SCSI_REQ/SCSI_ACK low
SCSI_REQ/SCSI_ACK assertion period
SCSI_REQ/SCSI_ACK negation period
25
35
30
30
–
–
–
–
ns
ns
ns
ns
July 1997
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Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
AC Characteristics: SCSI TIming (Continued)
Signal #
Parameter
Conditions
Min
Max
Units
Synchronous SCSI Input Cycle
42
43
44
45
46
47
Data setup to SCSI_REQ/SCSI_ACK low
Data hold from SCSI_REQ/SCSI_ACK low
SCSI_REQ assertion period
5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
15
27
20
20
20
SCSI_REQ negation period
SCSI_ACK assertion period
SCSI_ACK negation period
1. These minimum numbers are required to comply with ANSI SCSI spec. For Synchronous SCSI data transfers and FASTCLK enabled,
the clock inputs must also meet the following requirements: 2tCP + tCL> 97.92 ns and 2tCP + tCH > 97.92 ns.
AC Characteristics: Ethernet Timing
Signal #
48
Parameter
Min
99
45
45
–
Max
101
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENET_TCLK period
49
ENET_TCLK high pulse duration
50
ENET_TCLK low pulse duration
–
51
ENET_TCLK rise time
8
52
ENET_TCLK fall time
–
8
53
ENET_TENA propagation delay after rising edge of ENET_TCLK
ENET_TENA hold time after ENET_TCLK rising
ENET_TX propagation delay after ENET_TCLK rising
ENET_TX hold time after ENET_TCLK rising
ENET_RCLK period
–
25
–
54
7
55
–
32
–
56
7
57
85
38
38
–
118
–
58
ENET_RCLK high pulse duration
59
ENET_RCLK low pulse duration
–
60
ENET_RCLK rise time
8
61
ENET_RCLK fall time
–
8
62
ENET_RX data rise time
–
8
63
ENET_RX data fall time
–
8
64
ENET_RX data hold time from ENET_RCLK rising
ENET_RX data setup time to ENET_RCLK rising
ENET_RENA low duration
5
–
65
40
120
110
1
–
66
–
67
ENET_CLSN high duration
–
68
ENET_RENA hold time after the rising edge of ENET_RCLK
ENET_RENA defer before ENET_TENA
ENET_RENA extended after ENET_RCLK last falling
–
69
356
–
–
70
275
12
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Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
TIMING DIAGRAMS
1
2
3
SB_CLK
4
5
5
5
4
5
SB_BG, SB_SEL
6
7
SB_PA[W, X, Y, 5:0]
CHIP_SEL, SB_RD
SB_AS, SB_D[31:0]
SB_SIZ[2:0]
SB_ACK[2:0]
SB_LERR
Figure 4. SBus Input Timing
1
2
3
SB_CLK
8
8
9
SB_RD, SB_D[31:0]
SB_ACK[2:0]
SB_SIZ[2:0]
8
SB_BR
Figure 5. SBus Output Timing
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Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
SB_CLK
16
17
P_D_STRB(out)
18
19
P_DATA[7:0] (out)
P_ACK (in)
21
20
22
22
P_BSY (in)
Figure 6. Parallel Port Input Timing
SB_CLK
P_D_STRB(out)
P_DATA[7:0] (out)
P_ACK (in)
10
11
12
13
14
15
15
P_BSY (in)
Figure 7. Parallel Port Output Timing
SB_CLK
23
23
P_SLET_IN, P_AFXN, P_INIT,
P_ACK_DIR, P_BSY_DIR
P_DS_DIR, P_D_DIR
Figure 8. Parallel Port Other Timing
14
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Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
24
28
29
SCSI_STAL_IN
Figure 9. SCSI Clock Timing
SCSI_REQ (out)
SCSI_ACK (out)
SCSI_REQ (in)
SCSI_ACK (in)
SCSI_D
32
34
33
35
36
37
Figure 10. SCSI Asynchronous Input Timing
SCSI_REQ (out)
SCSI_ACK (out)
SCSI_REQ (in)
SCSI_ACK (in)
SCSI_D
32
34
33
35
30
31
Figure 11. SCSI Asynchronous Output Timing
July 1997
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Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
SCSI_REQ (in)
44
46
45
47
SCSI_ACK (in)
SCSI_D (in)
42
43
Figure 12. SCSI Synchronous Input Timing
SCSI_REQ (out)
SCSI_ACK (out)
SCSI_D (in)
40
40
41
41
38
39
SCSI_D (out)
Figure 13. SCSI Synchronous Output Timing
16
July 1997
This Material Copyrighted by Its Respective Manufacturer
Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
49
50
48
51
52
ENET_TCLK
ENET_TENA
ENET_TX
53
69
54
55
56
58
59
57
60
61
ENET_RCLK
ENET_RENA
ENET_RX
70
68
66
65
64
62
63
Figure 14. Ethernet Transmit/Receive Timing
67
ENET_CLSN
Figure 15. Ethernet Collision Timing
July 1997
17
This Material Copyrighted by Its Respective Manufacturer
Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
PACKAGE INFORMATION
160-Pin PQFP Pin Assignment
Pin
1
Name
SB_D[22]
Pin
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Name
P_DATA[5]
Pin
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Name
Pin
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Name
SCSI_SEL
Pin
Name
Pin
Name
GND
109 SB_D[1]
110 SB_D[2]
111 SB_D[3]
112 GND
136 SB_AS
2
SB_D[23]
GND
P_DATA[4]
GND
ENET_AUI
ENET_TX
ENET_TENA
ENET_CLSN
ENET_RX
ENET_RENA
ENET_TCLK
ENET_RCLK
JTAG_TDO
JTAG_CLK
JTAG_TDI
JTAG_TMS
JTAG_RST
GND
SCSI_BSY
SCSI_REQ
SCSI_ACK
GND
137 SB_ACK[0]
138 SB_SIZ[2]
139 SB_SIZ[1]
140 SB_SIZ[0]
141 VCC
3
4
SB_D[24]
SB_D[25]
SB_D[26]
VCC
P_DATA[3]
P_DATA[2]
VCC
5
113 SB_D[4]
114 VCC
6
SCSI_MSG
SCSI_CD
SCSI_IO
SCSI_ATN
SCSI_RST
GND
7
P_DATA[1]
P_DATA[0]
GND
115 SB_D[5]
116 SB_D[6]
117 GND
142 SB_CLK
143 GND
8
SB_D[27]
SB_D[28]
SB_D[29]
SB_D[30]
SB_D[31]
GND
9
144 SB_PA_W
145 SB_PA_X
146 SB_P_Y
147 SB_PA[4]
148 SB_PA[3]
149 SB_PA[2]
150 SB_PA[1]
151 SB_PA[0]
152 SB_PA[5]
153 SB_D[16]
154 SB_D[17]
155 SB_D[18]
156 VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
P_ERROR
P_SLCT
118 SB_D[7]
119 SB_D[8]
120 SB_D[9]
121 SB_D[10]
122 SB_D[11]
123 SB_D[12]
124 VCC
P_PE
GND
P_SLCT_IN
P_AFXN
GND
ID_CS
SCSI_XTAL_OUT
SCSI_XTAL_IN
VCC
GND
P_INIT
SB_RESET
VCC
P_ACK_DIR
P_BSY_DIR
P_DS_DIR
P_D_DIR
GND
GND
SCSI_D[0]
SCSI_D[1]
SCSI_D[2]
SCSI_D[3]
GND
VCC
125 SB_D[13]
126 SB_D[14]
127 GND
SB_P_IRQ
SB_E_IRQ
GND
SCC_20_IN
100 SCC_20_OUT
101 SCC_CLK20
102 GND
128 SB_D[15]
129 SB_ACK[2]
130 SB_ACK[1]
131 SB_BR
132 SB_BG
133 SB_LERR
134 CHIP_SEL
135 SB_SEL
P_ACK
FPY_CLK24
FPY_24_OUT
FPY_24_IN
VCC
P_BSY
SCSI_D[4]
SCSI_D[5]
SCSI_D[6]
SCSI_D[7]
SCSI_DP
GND
103 GND
157 SB_D[19]
158 GND
P_D_STRB
VCC
104 SB_D_IRQ
105 VCC
159 SB_D[20]
160 SB_D[21]
P_DATA[7]
P_DATA[6]
VCC
FPY_32_IN
FPY_32_OUT
FPY_CLK32
106 SB_RD
107 GND
108 SB_D[0]
18
July 1997
This Material Copyrighted by Its Respective Manufacturer
Master I/O
32-bit SBus Master I/O Controller
STP2000QFP
19
This Material Copyrighted by Its Respective Manufacturer
Master I/O
STP2000QFP
32-bit SBus Master I/O Controller
ORDERING INFORMATION
Part Number
Description
STP2000QFP
160-Pin Plastic Quad Flat Package (PQFP)
Document Part Number: STP2000
20
July 1997
This Material Copyrighted by Its Respective Manufacturer
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