TMP96C031F_技术文档

TOSHIBA

TLCS-900 Series

TMP96C031N/F

(3) External memory expansion

• Can be expanded up to 16M-bytes (for both programs and

data).

CMOS 16-bit Microcontrollers

TMP96C031N/TMP96C031F

• External data bus width selection pin (AM8/16)

• Can mix 8- and 16-bit external data buses.

Dynamic data bus sizing

(4) 8-bit timer: 2 channels

(5) 16-bit timer: 2 channels

(6) Pattern generator: 4 bits, 2 channels

(7) Serial interface: 2 channels

(8) 8-bit A/D converter: 4 channels

(9) DRAM controller

(10) Watchdog timer

(11) Chip select/wait controller: 4 blocks

1. Outline and Device Characteristics

…

The TMP96C031 are high-speed advanced 16-bit microcon-

trollers developed for controlling medium to large-scale equip-

ment. TMP96C031N comes in a 64-pin shrink DIP; the

TMP96C031F, in a 64-pin ﬂat package.

(1) Original 16-bit CPU

• TLCS-90 instruction mnemonic upward compatible.

• 16M-byte linear address space

• General-purpose registers and register bank system

• 16-bit multiplication/division and bit transfer/arithmetic

instructions

• High-speed micro DMA

- 4 channels (1.6µs/2 bytes @ 20MHz)

(2) Minimum instruction execution time

- 200ns @ 20MHz

(12) Interrupt functions

… …

• 3 CPU interrupts

SWI instruction, privileged violation,

and Illegal instruction

• 12 internal interrupts

• 9 external interrupts

(13) I/O ports: 37 pins

7-level priority can be set.

(14) Standby function : 3 HALT modes (RUN, IDLE, STOP)

The information contained here is subject to change without notice.

The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties

which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic

equipments (ofﬁce equipment, communication equipment, measuring equipment, domestic electriﬁcation, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-

ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, trafﬁc signal, combustion control, all types

of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.

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TMP96C031N/F

Figure 1. TMP96C031F Block Diagram

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2.1 Pin Assignment

Figure 2.1 shows pin assignment of TMP96C031N.

2. Pin Assignment and Functions

Figure 2.1 (1). Pin Assignment (64-SDIP)

Figure 2.1 (2) shows pin assignment of TMP96C031F.

Figure 2.1 (2). Pin Assignment (64QFP)

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2.2 Pin Names and Functions

The names of input/output pins and their functions are described below.

Table 2.2. Pin Names and Functions

Functions

Number

of Pins

Pin Name

AD0 ~ AD7

I/O

8

Tri-state

Address/data (lower): 0 - 7 for address/data bus

AD8 ~ AD15

A8 ~ A15

Tri-state

Output

Address data (upper): 8 - 15 for address/data bus

Address: 8 to 15 for address bus

P20 ~ P27

A0 ~ A7

A16 ~ A23

I/O

Output

Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)

Address: 0 - 7 for address bus

Address: 16 - 23 for address bus

8

1

P30

TO5

HWR

I/O

Output

Port 30: Output port (with pull-up register)

Timer output 5: Timer 4 output pin

High write: Strobe signal for writing data on pins AD8 - 15

P31

TI0

WAIT

I/O

Output

Port 31: Output port (with pull-up register)

Timer output 0: Timer 0 input

Write: Pin used to request CPU bus wait

Port 32: I/O port (with pull-up register)

Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0,

CS1, and CS2 pins. (For external DMAC)

P32

BUSRQ

I/O

Input

Port 33: I/O port (with pull-up register)

Bus acknowledge: Strobe indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2

pins are at high impedance after receiving BUSRQ.

P33

BUSAK

I/O

Input

P34

R/W

NMI

I/O

Output

Input

Port 34: I/O (with pull-up register)

Read/write: 1 represents read or dummy cycle 0, write cycle.

Non-maskable interrupt request pin; Interrupt request pin with falling edge. Can also be operated at rising

edge by program.

1

P35

RAS

INT7

I/O

Output

Input

Port 35: I/O (with pull-up register)

Row address strobe: Outputs RAS strobe for DRAM.

Interrupt request pin 7: Interrupt request pin with rising edge.

P40

CS0

Output

Port 40: I/O port

1

Chip select 0: Outputs 0 when address is within speciﬁed address area.

P41

CS1

Port 41: Output port

Chip select 1: Outputs 0 if address is within speciﬁed address area.

Output

P42

CS2

Output

Port 42: Output port

Chip select 2: Outputs 0 if address is within speciﬁed address area.

P43

CS3

CAS

Output

Port 43: Output port

1

4

Chip select 3: Outputs 0 if address is within speciﬁed address area.

Column address strobe 2: Outputs CAS strobe for DRAM if address is within speciﬁed address area.

P50 ~ P53

AN0 ~ AN3

INT1 ~ INT3

Input

Port 50 ~ 53: Input port

Analog input: Input to A/D converter

Interrupt request pin 0: Interrupt request pin with programmable level/rising edge.

Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge.

Interrupt request pin 2 ~ 3: Interrupt request pin with rising edge.

P60

TxD0

PG00

I/O

Output

Port 60: I/O port

Serial send data 0

Pattern generator port 00

1

P61

RxD0

PG01

I/O

Output

Port 61: I/O port

Serial receive data 0

Pattern generator port 01

Note: The internal I/O of this device cannot be accessed using the external DMA controller.

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Number

of Pins

Pin Name

P62

I/O

Functions

I/O

Port 62: I/O port

CTS0

PG02

1

Output

Serial data send enable 0 (Clear to Send)

Pattern generator port 02

P63

RFSH

PG03

I/O

Output

Port 63: I/O port

Refresh out: This is a state signal output pin which indicates that the DRAM controller is in refresh cycle.

Pattern generator port 03

P64

PG10

I/O

Output

Port 64: I/O port

Pattern generator port 10

1

P65

PG11

I/O

Output

Port 65: I/O port

Pattern generator port 11

P66

INT6

PG12

I/O

Input

Output

Port 66: I/O port

Interrupt request pin 6: Interrupt request pin with rising edge.

Pattern generator port 12

1

P67

WDTOUT

PG13

I/O

Output

Port 71: I/O port

Watchdog timer output pin

Pattern generator port 13

P70

TO1

TO4

I/O

Output

Port 70: I/O port

Timer output 1: Timer 0 or 1 output pin

Timer output 4: Timer 4 output pin

P71

T03

DMUX

I/O

Output

Port 71: I/O port

Timer output 3: Timer 2 or Timer 3 output pin

DRAM address multiplexor: This pin outputs row address, column address, and selector select signal.

P72

INT4

TI4

I/O

Input

Port 72: I/O port

Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge.

Timer input 4: Timer 4 count/capture trigger signal input

P73

INT5

TI5

I/O

Input

Port 73: I/O port

Interrupt request pin 5: Interrupt request pin with programmable rising edge.

Timer input 5: Timer 4 count/capture trigger signal input

P74

TxD1

I/O

Output

Port 74: I/O port

Serial send data 1

1

P75

RxD1

I/O

Input

Port 75: I/O port

Serial receive data 1

P76

SCLK1

I/O

Port 76: I/O port

Serial clock I/O 1

CLK

1

Output

Clock output: Outputs X1÷ 4 clock. Pulled-up during reset.

Read: Strobe signal for reading external memory.

RD

WR

Write: Strobe signal for writing data on pins AD0 - 7.

AM8/16

Address mode: External data bus width selection pin. Set to “0” for ﬁxed external 16-bit bus or for mixed

external 8/16 bit bus and to “1” for ﬁxed external 8-bit bus.

1

Input

RESET

ALE

1

Input

Output

I/O

Reset: Initializes LSI. (With pull-up resistor)

Address latch enable

X1/X2

VCC

Oscillator connecting pin

Power supply pin (-5V)

GND pin (0V)

VSS

Note: Pull-up/pull-down resistor can be released from the pin by software.

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• Initializes built-in I/O registers as per specifications.

3. Operation

• Sets port pins (including pins also used as built-in I/Os) to

general-purpose input/output port mode (sets I/O ports to

input ports).

• Sets the WDTOUT pin to 0. (Watchdog timer is set to enable

after reset.)

• Pulls up the CLK pin to 1.

• Sets the ALE pin to 0.

This section describes in blocks the functions and basic opera-

tions of the TMP96C031F device.

Check the chapter Guidelines and Restrictions for proper

care of the device.

3.1 CPU

The TMP96C031F device has a built-in high-performance 16-

bit CPU. (For CPU operation, see TLCS-900 CPU in the book

Core Manual Architecture User Manual.)

This section describes CPU functions unique to

TMP96C031F that are not described in the previous section.

3.1.2 External Data Bus Width Selection Pin (AM8/16)

The TMP96C031F automatically operates in 8-bit bus/16-bit

bus mode after reset depending on how the AM8/16 pin is set.

The TMP96C031F have altogether the following 23 inter-

rupt sources:

3.1.1 Reset

To reset the TMP96C031F, the RESET input must be kept at 0

for at least 10 system clocks (10 states: 1µs with a 20MHz

system clock) within an operating voltage range and with a sta-

ble oscillation.

• For mixed external 8/16-bit data bus or fixed 16-bit data bus

When reset is accepted, the CPU sets as follows:

• Program counter (PC) to 8000H.

• Stack pointer (XSP) for system mode to 100H.

• SYSM bit of status register (SR) to 1. (Sets to system mode.)

• IFF2 to 0 bits of status register to 111. (Sets mask register to

interrupt level 7.)

Set this pin to “0”. Then the AD8 to 15/A8 to 15 pins are

fixed to functions AD8 to 15.

The external data bus width is set by the chip select/wait

control register described in section 3.6.1.

• For fixed external 8-bit data bus

• MAX bit of status register to 0. (Sets to minimum mode.)

• Bits RFP2 to 0 of status register to 000. (Sets register banks

to 0.)

Set this pin to “1”. Then the AD8 to 15/A8 to 15 pins are

fixed to functions A8 to 15.

The value of chip select/wait control register bit 4

(<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS>) described in

Section 3.6.1 is ignored and the bus is fixed external 8-bit data

bus.

When reset is released, instruction execution starts from

address 8000H. CPU internal registers other than the above

are not changed.

When reset is accepted, processing for built-in I/Os,

ports, and other pins is as follows:

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3.2 Memory Map

Figure 3.2 is a memory map of the TMP96C031F.

Note: The start address after reset is 8000H. Resetting sets the stack pointer (XSP) on the system mode side to 100H.

Figure 3.2. Memory Map

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3.3 Interrupts

TMP96C031F have altogether the following 24 interrupt

sources:

TLCS-900 interrupts are controlled by the CPU interrupt mask

ﬂip-ﬂop (IFF2 to 0) and the built-in interrupt controller.

…

• Interrupts from the CPU 3

(Software interrupts, privileged violations, and Illegal (undeﬁned) instruction execution)

…

• Interrupts from external pins (NMI, INT0, and INT0 to 7) 9

…

• Interrupts from built-in I/Os 12

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A ﬁxed individual interrupt vector number is assigned to

each interrupt source; six levels of priority (variable) can also be

assigned to each maskable interrupt. Non-maskable interrupts

have a ﬁxed priority of 7.

When an interrupt is generated, the interrupt controller

sends the value of the priority of the interrupt source to the

CPU. When more than one interrupt is generated simulta-

neously, the interrupt controller sends the value of the highest

priority (7 for non-maskable interrupts is the highest) to the

CPU.

The CPU compares the value of the priority sent with the

value in the CPU interrupt mask register (IFF2 to 0). If the value

is greater than that of the CPU interrupt mask register, the

interrupt is accepted. The value in the CPU interrupt mask reg-

ister (IFF2 to 0) can be changed using the EI instruction (con-

tents of the EI num/IFF <2:0> = num). For example,

programming EI 3 enables acceptance of maskable interrupts

with a priority of 3 or greater, and non-maskable interrupts

which are set in the interrupt controller. The DI instruction (IFF

<2:0> = 7) operates in the same way as the EI 7 instruction.

Since the priority values for maskable interrupts are 0 to 6, the

DI instruction is used to disable maskable interrupts to be

accepted. The EI instruction becomes effective immediately

after execution. (With the TLCS-90, the EI instruction becomes

effective after execution of the subsequent instruction.)

In addition to the general-purpose interrupt processing

mode described above, there is also a high-speed µDMA pro-

cessing mode. High-speed µDMA is a mode used by the CPU

to automatically transfer byte or word data. It enables the CPU

to process interrupts such as data saves to built-in I/Os at high

speed.

Figure 3.3 (1) is a ﬂowchart showing overall interrupt

processing.

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TMP96C031N/F

Figure 3.3 (1). Interrupt Processing Flowchart

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3.3.1 General-Purpose Interrupt Processing

When accepting an interrupt, the CPU operates as follows:

The table below shows the number of execution states

for the above processing times.

(1) The CPU reads the interrupt vector from the interrupt

controller. When more than one interrupt with the same

level is generated simultaneously, the interrupt controller

generates interrupt vectors in accordance with the

default priority (which is ﬁxed as follows: the smaller the

vector value, the higher the priority), then clears the inter-

rupt request.

Interrupt Processing State Number

Bus Width of Stack Area

MAX mode

Min mode

8-bit

23

17

19

15

16-bit

To return to the main routine after completion of the inter-

rupt processing, the RETI instruction is usually used. Executing

this instruction restores the contents of the program counter

and the status registers.

(2) The CPU pushes the program counter and the status

register to the system stack area (area indicated by the

system mode stack pointer).

(3) The CPU sets a value in the CPU interrupt mask register

<IFF2 to 0> that is higher by 1 than the value of the

accepted interrupt level. However, if the value is 7, 7 is

set without an increment.

Though acceptance of non-maskable interrupts cannot

be disabled by program, acceptance of maskable interrupts

can. A priority can be set for each source of maskable inter-

rupts. The CPU accepts an interrupt request with a priority

higher than the value in the CPU mask register <IFF2 to 0>.

The CPU mask register <IFF2 to 0> is set to a value higher by

1 than the priority of the accepted interrupt. Thus, if an inter-

rupt with a level higher than the interrupt being processed is

generated, the CPU accepts the interrupt with the higher level,

causing interrupt processing to nest. The CPU does not

accept an interrupt request of the same level as that of the

interrupt being processed.

(4) The CPU sets the <SYSM> ﬂag of the status register to 1

and enters the system mode.

(5) The CPU jumps to address 8000H + interrupt vector,

then starts the interrupt processing routine.

Resetting initializes the CPU mask registers <IFF2 to 0>

to 7; therefore, maskable interrupts are disabled.

The addresses 008000H to 0081FFH (512 bytes) of the

TLCS-900 are assigned for interrupt processing entry area.

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Table 3.3 (1) TMP96C031F Interrupt Table

High-Speed

Micro DMA

Start to Vector

Vector Value

Default Priority

Type

Interrupt Source

Start Address

“V”

1

Reset

, or SWI0 instruction

0 0 0 0 H

0 0 1 0 H

0 0 2 0 H

0 0 3 0 H

0 0 4 0 H

0 0 5 0 H

0 0 6 0 H

0 0 7 0 H

0 0 8 0 H

0 0 9 0 H

0 0 A 0 H

0 0 B 0 H

0 0 C 0 H

0 0 D 0 H

0 0 E 0 H

0 0 F 0 H

0 1 0 0 H

0 1 1 0 H

0 1 2 0 H

0 1 3 0 H

0 1 4 0 H

0 1 5 0 H

0 1 6 0 H

0 1 7 0 H

0 1 8 0 H

0 1 9 0 H

0 1 A 0 H

0 1 B 0 H

0 1 C 0 H

0 1 D 0 H

0 1 E 0 H

0 1 F 0 H

8 0 0 0 H

8 0 1 0 H

8 0 2 0 H

8 0 3 0 H

8 0 4 0 H

8 0 5 0 H

8 0 6 0 H

8 0 7 0 H

8 0 8 0 H

8 0 9 0 H

8 0 A 0 H

8 0 B 0 H

8 0 C 0 H

8 0 D 0 H

8 0 E 0 H

8 0 F 0 H

8 1 0 0 H

8 1 1 0 H

8 1 2 0 H

8 1 3 0 H

8 1 4 0 H

8 1 5 0 H

8 1 6 0 H

8 1 7 0 H

8 1 8 0 H

8 1 9 0 H

8 1 A 0 H

8 1 B 0 H

8 1 C 0 H

8 1 D 0 H

8 1 E 0 H

8 1 F 0 H

–

2

INTPREV:

INTUNDEF:

SWI 3 Instruction

SWI 4 Instruction

SWI 5 Instruction

SWI 6 Instruction

SWI 7 Instruction

NMI Pin

Privileged violation, or SWI1

Illegal instruction, or SWI2

–

3

–

4

–

Non-

Maskable

5

–

6

–

7

–

8

–

9

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

10

11

12

13

14

15

-

INTWD:

Watchdog timer

INTO pin

INT4 pin

INT5 pin

INT6 pin

INT7 pin

(Reserved)

INTT0:

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

8-bit timer 0

INTT1:

8-bit timer 1

INTT2:

8-bit timer 2/PWM0

8-bit timer 3/PWM1

16-bit timer 4 (TREG4)

16-bit timer 4 (TREG5)

INTT3:

INTTR4:

Maskable

INTTR5:

(Reserved)

INTRX0:

Serial receive (Channel.0)

Serial send (Channel.0)

Serial receive (Channel.1)

Serial send (Channel.1)

A/D conversion completion

INTTX0:

INTRX1:

INTTX1:

INTAD:

INT1 pin

INT2 pin

INT3 pin

3.3.2 High-Speed µDMA

The TLCS-900 can process at very high speed com-

pared with the TLCS-90 µDMA because it has transfer param-

eters in dedicated registers in the CPU. Since those dedicated

registers are assigned as CPU control registers, they can only

be accessed by the LDC (privileged) instruction.

In addition to the conventional interrupt processing, the TLCS-

900 also has a high-speed µDMA function. When an interrupt

is accepted, in addition to an interrupt vector, the CPU receives

data indicating whether processing is high-speed µDMA mode

or general-purpose interrupt. If high-speed µDMA mode is

requested, the CPU performs high-speed µDMA processing.

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(1) High-Speed µDMA Operation

There are two data transfer modes: one-byte mode and

one-word mode. Incrementing, decrementing, and ﬁxing the

transfer source/destination address after transfer can be done

in both modes. Therefore data can easily be transferred

between I/O and memory and between I/Os. For details of

transfer modes, see the description of transfer mode registers.

The transfer counter has 16-bit, so up to 65536 transfers

(the maximum when the initial value of the transfer counter is

0000H) can be performed for one interrupt source by high-

speed µDMA processing.

After transferring data using the high-speed µDMA and

the transfer counter has been decremented to 0, the program

goes to a general-purpose interrupt processing. Note that after

interrupt processing, when an interrupt for the same channel is

generated, if the system requires resetting the transfer counter

starts from 65536.

High-speed µDMA operation starts when the accepted inter-

rupt vector value matches the µDMA start vector value set in

the interrupt controller. The high-speed µDMA has four chan-

nels so that it can be set for up to four types of interrupt

source.

When a high-speed µDMA interrupt is accepted, data is

automatically transferred from the transfer source address to

the transfer destination address set in the control register, and

the transfer counter is decremented. If the value in the counter

after decrementing is other than 0, high-speed µDMA process-

ing is completed. If the value in the counter after decrementing

is 0, general-purpose interrupt processing is performed. In

read-only mode, which is provided for DRAM refresh, the value

in the counter is ignored and dummy read is repeated.

The 32-bit control registers are used for setting transfer

source/destination addresses. However, the TLCS-900 has

only 24 address pins for output. A 16M-byte space is available

for the high-speed µDMA. Also in normal mode operation, the

all address space (in other words, the space for system mode

which is set by the CS/WAIT controller) can be accessed by

high-speed µDMA processing.

The following section illustrates the high-speed µDMA

cycle when the transfer destination address is in INC mode.

(MIN mode, 16-bit bus for all address areas, 0 wait).

Interrupt sources processed by high-speed µDMA pro-

cessing are those with the high-speed µDMA start vectors

listed in Table 3.3 (1).

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(2) Register Conﬁguration (CPU Control Register)

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(3) Transfer Mode Register Details

Execution time: When 16-bit bus width and 0 wait are set for the transfer destination/source address.

Note: n: corresponds to high-speed µDMA channels 0 - 3.

DMADn +/DMASn + : Post-increment (Increments register value after transfer.)

DMADn -/DMASn - :

Post-decrement (Decrement register value after transfer.)

All address space (the space for system mode) can be

for transfer mode control.

accessed by high-speed µDMA. Do not use undeﬁned codes

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3.3.3 Interrupt Controller

ables the corresponding interrupt request. The priority of the

non-maskable interrupt (NMI pin, watchdog timer, etc.) is ﬁxed

to 7. If interrupt requests with the same interrupt level are gen-

erated simultaneously, interrupts are accepted in accordance

with the default priority (the smaller the vector value, the higher

the priority).

The interrupt controller sends the interrupt request with

the highest priority among the simultaneous interrupts and its

vector address to the CPU. The CPU compares the priority

value <IFF2 to 0> set in the Status Register by the interrupt

request signal with the priority value sent; if the latter is higher,

the interrupt is accepted. Then the CPU sets a value higher

than the priority value by 1 in the CPU SR <IFF2 to 0>. Inter-

rupt requests where the priority value equals or is higher than

the set value are accepted simultaneously during the previous

interrupt routine. When interrupt processing is completed (after

execution of the RETI instruction), the CPU restores the priority

value saved in the stack before the interrupt was generated to

the CPU SR <IFF2 to 0>.

The interrupt controller also has four registers used to

store the high-speed other µDMA start vector. These are I/O

registers; unlike other DMA registers (DMAS, DMAD, DMAM,

and DMAC), they can be accessed in either normal or system

mode. Writing the start vector of the interrupt source for the

µDMA processing (see Table 3.3 (1)), enables the correspond-

ing interrupt to be processed by µDMA processing. The values

must be set in the µDMA parameter registers (e.g., DMAS and

DMAD) prior to the µDMA processing.

Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The

left half of the diagram shows the interrupt controller; the right

half includes the CPU interrupt request signal circuit and the

HALT release signal circuit.

Each interrupt channel (total of 20 channels) in the inter-

rupt controller has an interrupt request ﬂip-ﬂop, interrupt prior-

ity setting register, and a register for storing the high-speed

micro DMA start vector. The interrupt request ﬂip-ﬂop is used

to latch interrupt requests from peripheral devices. The ﬂip-ﬂop

is cleared to 0 at reset, when the CPU reads the interrupt

channel vector after the acceptance of interrupt, or when the

CPU executes an instruction that clears the interrupt of that

channel (writes 0 in the clear bit of the interrupt priority setting

register).

For example, to clear the INT0 interrupt request, set the

register after the DI instruction as follows.

INTE0AD←---- 0 ---

Zero-clears the INT0 Flip Flop.

The status of the interrupt request ﬂip-ﬂop is detected by

reading the clear bit. Detects whether there is an interrupt

request for an interrupt channel.

The interrupt priority can be set by writing the priority in

the interrupt priority setting register (e.g., INTE0AD, INTE45,

etc.) provided for each interrupt source. Interrupt levels to be

set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis-

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Figure 3.3.3 (1). Block Diagram of Interrupt Controller

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(1) Interrupt Priority Setting Register

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(2) External Interrupt Control

Setting of External Interrupt Pin Functions

Interrupt

Pin Name

Mode

Setting Method

NMI

P34

Falling edge

Rising and falling edge

Rising edge

Level

IIMC <NMIREE> = 0

IIMC <NMIREE> = 1

IIMC <I0LE> = 0, <I0IE> = 1

IIMC <I0LE> = 1, <I0IE> = 1

IIMC <I1EM> = 0

INT0

INT1

P50

P51

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

IIMC <I1EM> = 1

INT2

INT3

P52

P53

IIMC <I2EM> = 1

IIMC <I3EM> = 1

T4MOD <CAP12M1, 0> = 0, 0 or 0, 1 or 1, 1

INT4

P72

T4MOD <CAP12M1, 0> = 1, 0

–

INT5

INT6

INT7

P73

P66

P35

IIMC <I6IIE> = 1

IIMC <I7IIE> = 1

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TMP96C031N/F

(3) High-Speed µDMA Start Vector

mode for the channel whose value matched.

If the interrupt vector matches more than one channel,

the channel with the lower channel number has a higher prior-

ity.

When the CPU reads the interrupt vector after accepting an

interrupt, it simultaneously compares the interrupt vector with

each channel’s µDMA start vector (bits 4 to 8 of the interrupt

vector). When both match, the interrupt is processed in µDMA

(4) Notes

while reading the interrupt vector after accepting the inter-

rupt. If so, the CPU would read the default vector 00A0H

and start the interrupt processing from the address

80A0H.

To avoid this, make sure that the instruction used to

clear the interrupt request ﬂag comes after the DI instruction.

The instruction execution unit and the bus interface unit of this

CPU operate independently of each other. Therefore, if the instruc-

tion used to clear an interrupt request ﬂag of an interrupt is fetched

before the interrupt is generated, it is possible that the CPU might

execute the fetched instruction to clear the interrupt request ﬂag

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reduced to 1/10 or less than that during normal

operation.

3.4 Standby Function

When the HALT instruction is executed, the TMP96C031

enters RUN, IDLE, or STOP mode depending on the contents

of the HALT mode setting register.

(3) STOP: All internal circuits including the built-in oscillator

halt. This greatly reduces power consumption.

(1) RUN:

Only the CPU halts; power consumption remains

unchanged.

The states of the port pins in STOP mode can be set as

listed in Table 3.4 (1) using the I/O register WDMOD <DRVE>

bit.

(2) IDLE:

Only the built-in oscillator operates, while all other

built-in circuits halt. Power consumption is

7

6

5

4

3

2

1

0

Bit Symbol

Read/Write

After reset

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

WDMOD

(005CH)

R/W

1

0

16

1 : WDT

Enable

00 : 2 / fc

Warming up Standby mode

1: Connects

watchdog

timer

output to

RESET pin

internally.

1: Drive pin

even in

STOP

18

01 : 2 / fc

time

00 : RUN

01 : STOP

10 : IDLE

mode

20

16

10 : 2 / fc

0 : 2 /fc

Function

22

18

11 : 2 / fc

1 : 2 /fc

mode.

Detection time

11 : Don’t care

When STOP mode is released by other than a reset, the

system clock output starts after allowing some time for warm-

ing up set by the warming-up counter fro stabilizing the built-in

oscillator. To release STOP mode by reset, it is necessary to

allow the oscillator to stabilize.

To release standby mode, a reset or an interrupt is used.

To release IDLE or STOP mode, only an interrupt by the NMI or

INT0 pin, or a reset can be used. The details are described

below:

Standby Release by Interrupt

Interrupt Level

Interrupt Mask (IFF2 to 0)

≤ Interrupt Request Level

Interrupt Mask (IFF2 to 0)

> Interrupt Request Level

Standby Mode

Can be released by any interrupt.

After standby mode is released, interrupt processing starts.

Can only be released by INT0 pin.

Processing resumes from address next to HALT instruction.

RUN

IDLE

Can only be released by NMI or INT0 pin. After standby mode

is released, interrupt processing starts.

↑

STOP

↑

Note 1: When releasing standby setting INT0 to high level input mode, keep it high until interrupt processing starts. If the level drops to low, interrupt process-

ing cannot be started correctly.

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TMP96C031N/F

Table 3.4 (1) Pin States in STOP Mode

Pin Name

I/O

DRVE = 0

DRVE = 1

AD0 ~ AD7

AD0 ~ 7

–

AD8 ~ 15

A8 ~ 15

–

AD8 ~ AD15

P20 ~ P27

P30 ~ P33

Input mode

Output mode/A16 ~ 23

PD*

PD

Output

Input mode

Output mode

PD*

PD

Output

Input mode

Output mode

PU*

PU

Output

P34 (R/W/NMI)

P35 (RAS/INT7)

NMI

Input

Input mode

Output mode

RAS

PU*

Output

PU

Output

P40 ~ P42 (CS0 ~ CS2)

P43 (CS3/CAS)

Output

PU*

Output

CAS

PU*

Output

Input

INT0

–

Input

P50 (AN0/INT0)

P51 ~ P53

Input

–

Input

Input mode

Output mode

–

Input

Output

P60 ~ P66

Input mode

Output mode

WDTOUT

–

Input

Output

P67 (P13/WDTOUT)

P70 ~ P76

Output

Input mode

Output mode

–

Input

Output

ALE

Output

Input

“0”

–

“0”

“1”

CLK

RESET

WR

Input

–

Input

Output

Input

“1” Output

Input

RD

–

AM8/16

X1

Input

–

Input

–

X2

Output

“1”

–:

Input for input mode/input pin is invalid; output mode/output pin is at high impedance.

Input: Input enable state

Input: Input gate in operation. Fix input voltage to 0 or 1 so that input pin stays constant.

Output: Output state

PU:

PD:

*:

Programmable pull-up pin. Fix the pin to avoid through current since the input gate operates when a pull-up resistor is not set.

Programmable pull-down pin. Fix the pin like a pull-up pin when a pull-down resistor is not set.

Input gate disable state. No through current even if the pin is set to high impedance.

Note: Port registers are used for controlling programmable pull-up/pull-down. If a pin is also used for an output function (e.g., TO1) and the output function

is speciﬁed, whether pull-up or pull-down is selected depends on the output function data. If a pin is also used for an input function, whether pull-up or

pull-down is selected depends on the port register setting value only.

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3.5 Port Functions

The input/output ports of the TMP96C031F consist of a total

of 37 bits.

tions, these port pins also function as input/outputs for internal

CPU and built-in I/O. Table 3.5 (1) shows the function of each

port pin.

In addition to general purpose input/output port func-

(R:

↑ = With programmable pull-up resistor

↓ = WIth programmable pull-down resistor)

Table 3.5 (1) Port Function

Number of

Pins

Port Name

Pin Name

Direction

R

Direction Setting Unit

Pin Name for Built-in Function

Port2

Port3

P20 to P27

8

Input/Output

↓

Bit

A0 to A7/ A16 to A23

P30

P31

P32

P33

P34

P35

1

Input/Output

↑

Bit

TO5/HWR

TI0/WAIT

BUSRQ

BUSAK

R/W/RAS

RAS/INT7

Port4

P40

P41

P42

P43

1

Output

↑

(Fixed)

CS0

CS1

CS2

CS3/CAS

Port5

Port6

P50 to P53

4

Input

–

(Fixed)

AN0 ~ AN3

P60

P61

P62

P63

P64

P65

P66

P67

1

Input/Output

–

Bit

PG00/TxD0

PG01/RxD0

PG02/CTS0

PG03/RSFH

PG10

PG11

PG12/INT6

PG13/WDTOUT

Port7

P70

P71

P72

P73

P74

P75

P76

1

Input/Output

–

Bit

TO1/TO4

TO2/DMUX

INT4/TI4

INT5/TI5

TxD1

RxD1

SCLK1

3.5.1 Programmable Pull-up/Pull-down

They can also be set in stand-by (STOP) mode and the load

can be turned on or off when the immediately preceding set-

ting is the value of output latch in input mode or is the value of

output data in output mode.

PORT2 has a built-in pull-down resistor and PORT3 and

PORT4 have a built-in pull-up resistor. Normally, their load can

be turned on or off from software by setting the value of the

output latch (registers P2, P3, and P4) during input mode.

Table 3.5 (2) Pull-up/down Function Setting

Programmable

Setting

Standby (STOP) mode

Pull-up/down

Output latch

ON/OFF

Normal

Output data

0

1

0

1

0

1

ON

OFF

ON

Setting enabled only in

input mode

Setting enabled in input/

output mode

PORT2 (I/O)

PORT3 (I/O)

Pull-down

Pull-up

↑

OFF

ON

Setting enabled only in

output mode

PORT4 (Output)

Pull-up

Setting disabled

OFF

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TMP96C031N/F

3.5.2 Bus Release Function

The pull-up/down function explained in section 3.5.1 is also

used to stabilize bus control signal at bus release.

Table 3.5 (2) shows pin states at bus release (BUSAK = 0).

Pin state at bus release

Function mode

Pin Name

Port mode

AD0 - AD15

AD0 - AD7

(A8 ~ A15)

–

Becomes high impedance.

First sets all bits to low, then sets output buffer to off.

Internal pull-down is added regardless to output latch

value.

P20 - P27

(A16 ~ 23)

No status change.

(Does not become high impedance.)

RD

WR

–

First sets all bits to high, then sets them to high impedance.

First sets all bits to high, then sets output buffer to off.

Internal pull-down is added regardless to output latch

value.

P30 (HWR)

P34 (R/W)

No status change.

(Does not become high impedance.)

P40 (CS0)

P41 (CS1)

P42 (CS2)

P43 (CS3)

First sets all bits to high, then sets output buffer to off.

Internal pull-down is added regardless to output latch

value.

No status change.

(Does not become high impedance.)

P71 (DMUX)

P63 (RFSH)

No status change.

(Does not become high impedance.)

First sets all bits to high, then sets them to high impedance.

P35 (RAS)

P43 (CAS)

No status change.

(Does not become high impedance.)

No status change.

(Does not become high impedance.)

Figure 3.5 (2) shows the external bus interface when the

bus release function is in use. The internal I/O of this device

cannot be accessed when the bus is released.

Figure 3.5 (1). External bus interface example when bus release function is in use

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input mode and connects a pull-down resistor.

3.5.3 Port 2 (P20 - P27)

In addition to functioning as a general-purpose I/O port,

Port 2 also functions as an address bus (A16 to 23).

Port 2 is an 8-bit general-purpose I/O port. I/O can be set on

bit basis using the control register P2CR and function register

P2FC. Resetting resets all bits of output latch P2, control regis-

ter P2CR and function register P2FC to 0. It also sets Port 2 to

Figure 3.5 (2). Port 2

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TMP96C031N/F

Figure 3.5 (3). Registers for Port 2

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3.5.4 Port 3 (P30 - P35)

pull-up resistor. In addition to functioning as a general-pur-

pose I/O port, port 3 is also used for CPU control/status signal

interrupt input, and timer I/O.

Port 3 is a 6-bit general-purpose I/O port. I/O can be set bit by

bit using control registers P3CRL and P3CRH. Resetting sets

all bits of P3 to 0; P30 to P35 to input mode and connects a

Figure 3.5 (4). Port 3 (P30)

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TMP96C031N/F

Figure 3.5 (5). Port 3 (P31, P32)

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Figure 3.5 (6). Port 3 (P33, P35)

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TMP96C031N/F

(1) P34/NMI/R/W

the NMI pin is speciﬁed only once, the NMI pin cannot be

switched to the general-purpose port. The <P34C1,P34C0>

should be initialized to “0” by resetting in order to switch to the

general-purpose I/O port mode. Port3 register (P34) is set to

be “1” when the pull-up resistor is attached.

Port 34 is a general-purpose I/O port, shared with non-

maskable interrupt input pin (NMI). The NMI pin is selected by

the control register P3CRH <P34C1,P34C0>. By setting

<P34C1,P34C0> = <0,0>, it turns to the NMI input pin. Since

Figure 3.5 (6). Port 3 (P33, P34)

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Figure 3.5 (8). Port 3 Registers

Note: There is no port/function switch register for pin P31 (TIO/WAIT). For example, if pin P31 is used as an input port, data are input to 8-bit timer 0. If pin

P31 is used as the WAIT pin, set P3CRL <P31C1,0) > to 00, and bits 3 and 2 <BXW1,0> in the chip select/wait control register to 10.

If pin P35 (RAS/INT7) is used as the INT7 pin, set P3CRH <P35C1,0) to 00 and <171E> to 1.

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TMP96C031N/F

3.5.5 Port 4 (P40 - P43)

function register P4FC. Resetting sets the output register for

P40, P41, and P42 to 1; the output register for P42 to 0; all bits

in the function register to 0. P40, P41, and P43 are set to out-

put ports for outputting 1; P42 to output port for outputting 0.

Port 4 is a 4-bit output dedicated port. Port 4 is also used for

chip select CS0 - CS3 outputs and column address strobe

CAS (CS3 only) output. To select the function to be used, use

Figure 3.5 (9). Port 4 (P40, P41, P43)

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Figure 3.5 (10). Port 4 (P42)

Figure 3.5 (11). Registers for Port 4

P4FC is disabled for read-modify-write.

Note: To select the function to be used for P43, use the B3CS register for the chip select/wait controller.

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TMP96C031N/F

3.5.6 Port 5 (P50 - P53)

analog inputs or external interrupts.

Port 5 is a 4-bit input dedicated port which is also used for

Figure 3.5 (11). Port 5 (P50, P51, P52, P53)

Port 5 Register

Figure 3.5 (12). Register for Port 5

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3.5.7 Port 6 (P60 - P67)

P63: DRAM controller refresh signal pin

P66: external interrupt request input INT6 pin

P67: watchdog timer WDT output pin. Set using port 6 con-

trol registers. P6CRL and P6CRH.

Port 6 is an 8-bit port. I/O can be set bit by bit. In addition to

functioning as an I/O port, pins P60 to P67 function as follows:

P60 - P63/P64 - P67: pattern generate PG0/PG1 output

P60: serial channel TxD0 output pin and programmable

open drain function.

Resetting sets control registers P6CRL and P6CRH to 0; all

bits to input mode.

P61: serial channel RxD0 output pin

P62: serial channel CTS0 output pin

Figure 3.5 (13) Port 6 (P60, P67)

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TMP96C031N/F

Figure 3.5 (14). Registers for Port 6 (P61, P62, P66)

Figure 3.5 (15). Port 6 (P63, P64, P65)

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Figure 3.5 (16). Registers for Port 6

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TMP96C031N/F

3.5.8 Port 7 (P70 - P76)

P70 - P76 to input mode. In addition to functioning as a gen-

eral-purpose I/O port, port 7 as follows: interrupt input, timer

I/O, DRAM address multiplex, serial channel send/receive

(TXD1 and RXD1), and transfer clock input (SCLK1) pin.

Port 7 is a 7-bit general-purpose I/O port. I/O can be set bit by

bit using control registers P7CRL and P7CRH. Resetting sets

all bits in P7 to 1; control registers P7CRL and P7CRH to 0;

Figure 3.5 (17). Port 7 (P70, P71)

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Figure 3.5 (18). Port 7 (P72, P73, P75)

Figure 3.5 (19). Port 7 (P74)

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TMP96C031N/F

Figure 3.5 (20). Port 7 (P76)

40

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TMP96C031N/F

Figure 3.5 (21). Registers for Port 7

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TMP96C031N/F

3.6 Chip Select/Wait Control

3.6.1 Control Registers

The TMP96C031F has a built-in chip select/wait controller

used to control chip select (CS0 - CS3 pins), wait (WAIT pin),

and data bus size (8 or 16 bits) for any of the three block

address areas.

The select pin (AM8/16) is used to select the width of the

external data bus. (See section 3.1.2, External data width

select pin.)

Table 3.6 (1) shows control registers

The block address areas is controlled by corresponding

CS/wait control register (B0CS, B1CS, B2CS, B3CS) and start

address register/address mask register (explained in section

3.6.2, Address area).

Registers can be written to only when the CPU is in sys-

tem mode. (There are two CPU modes: system and normal.)

The reason is that the settings of these registers have an

important effect on the system.

Table 3.6 (1) Chip Select/Wait Control Register

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(1)

(2)

Enable

(3)

Address area speciﬁcation

Control register bit 7 (B0E, B1E, B2E, and B3E) is a

master bit used to specify enable “1”)/disable “0” of

the setting.

Resetting sets B0E, B1E, and B3E to disable “0” and

B2E to enable “1”.

Control register bit 5 (B0ARE, B1ARE, B2ARE, and

B3ARE) is used to specify the target address space.

When this bit is set to “0” after reset, CS0 is set to

addresses 7F00H to 7FFFF, CS1 is set to address 80H

to 7FFFH, and CS2 is set to addresses 8000H to

3FFFFF. CS3 is undeﬁned. (See 3.6.3 Default Address

Space Speciﬁcation.) When this bit is set to “1”, the

target address is the address space is the address

space speciﬁed by the memory start address register

MSAR and memory start address mask register

MAMR. (See 3.6.2 Address Space Speciﬁcation.)

System only speciﬁcation

Control register bit 6 (B0SYS, B1SYS, B2SYS, and

B3SYS) is used to specify enable/disable of the setting

depending on the CPU operating mode (system or nor-

mal). Setting this bit to 0 enables setting (Address

space for CS, Wait state, Bus size, etc.) regardless of

the CPU operating mode; setting it to 1 enables setting

in system mode but disables setting in normal mode.

(4)

Data bus width select

Control register bit 4 (B0BUS, B1BUS, B2BUS,

B3BUS) is used to specify the data bus width. When

this bit is set to “0”, memory is accessed in 16-bit data

bus mode. When this bit is set to “1”, memory is

accessed in 16-bit data bus mode. However, this bit is

valid only in 16-bit bus mode (AM8/16 pin = “0”). In 8-

bit bus mode (AM8/16 pin = “1”), all address space is

accessed in 8-bit data bus mode regardless of the

value of this bit. (See 3.1.2 External Data Bus Width

Selection Pin.)

Resetting clears bit 6 to 0.

Bit 6 is mainly used when external memory data

should not be accessed in normal mode (i.e., for sys-

tem mode only memory data for the operating system).

The changing data bus width according to the address

to be address to be accessed is referred to dynamic

bus sizing. Table 3.6 (2) shows the details of the bus

operation.

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TMP96C031N/F

Table 3.6 (2) Dynamic Bus Sizing

CPU Data

Operand

Data Size

Operand

Start Address

Memory

CPU Address

Data Size

D15 - D8

D7 - D0

2n + 0

(even number)

8-bit

16-bit

8-bit

2n + 0

2n + 1

xxxxx

b7 - b0

xxxxx

8-bit

2n + 1

(odd number)

xxxxx

16-bit

b7 - b0

2n + 0

2n + 1

xxxxx

b7 - b0

b15 - b8

8-bit

16-bit

8-bit

2n + 0

(even number)

2n + 0

b15 - b8

b7 - b0

16-bit

2n + 1

2n + 2

xxxxx

b7 - b0

b15 - b8

2n + 1

(odd number)

2n + 1

2n + 2

b7 - b0

xxxxx

b15 - b8

16-bit

2n + 0

2n + 1

2n + 2

2n + 3

xxxxx

b7 - b0

b15 - b8

b23 - b16

b31 - b24

8-bit

2n + 0

(even number)

2n + 0

2n + 2

b15 - b8

b31 - b24

b7 - b0

b23 - b16

16-bit

32-bit

2n + 1

2n + 2

2n + 3

2n + 4

xxxxx

b7 - b0

b15 - b8

b23 - b16

b31 - b24

8-bit

2n + 1

(odd number)

2n + 1

2n + 2

2n + 4

b7 - b0

b23 - b16

xxxxx

b15 - b8

b31 - b24

16-bit

xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active.

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(5)

Wait control

(6)

CS/CAS waveform select

Control register bits 3 and 2 (B0W1, 0; B1W1, 0; B2W1,

0; B3W1, 0) are used to specify the number of waits.

Setting these bits to 00 inserts a 2-state wait regard-

less of the WAIT pin status. Setting them to 01 inserts

a 1-state wait regardless of the WAIT status. Setting

them to 10 inserts a 1-state wait and samples the

WAIT pin status. If the pin is low, inserting the wait

maintains the bus cycle until the pin goes high. Setting

them to 11 completes the bus cycle without a wait

regardless of the WAIT pin status.

The B3CS register bit 1 <B3CAS> is used to specify

the mode of the waveform output from the chip select

pin (CS3/CAS) pin. When this bit is set to “0”, CS3

waveform is output. When it is set to “1”, CAS wave-

form is output. This bit is cleared to zero after reset.

(7)

(8)

Self refresh control

(described in section 3.13.1 Refresh Controller.)

Resetting sets these bits to 00 (2-state wait mode).

Wait control outside space CS0 to CS3

Note: If there ia a contention between DRAM access

and refresh when using DRAM, the refresh

cycle is added to the speciﬁed wait.

This bit is used to specify the number of waits when

B0CS register bits 1 and 0 <BEXW1, 0> or space out-

side CS0 to CS3 is accessed.

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TMP96C031N/F

3.6.2 Address Space Speciﬁcation (B0CS to B3CS

< B0ARE to B3ARE> = “1”)

The address space is speciﬁed with the start address register

(MSAR0, MSAR1, MSAR2, and MSAR3) and address mask

register (MAMR0, MAMR1, MAMR2, and MAMR3). For each

bus cycle, the chip select controller compares the address on

the bus and value of this start address register. The value of

the address mask register is used to ignore result of this

address comparison. When there is a match, the speciﬁed

space is assumed to be accessed and a low strobe signal is

output from the corresponding chip select pin (CS0 to CS3) if

it is enabled (B0E to B3E = “1”).

Figure 3.6 (1). Chip Select (CS0 to CS3) Operation Timing

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Figure 3.6 (2). CS0 Address Decode Block Diagram

Figure 3.6 (3). CS1 Address Decode Block Diagram

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TMP96C031N/F

Figure 3.6 (4). CS2, CS3 Address Decode Block Diagram

(1) Memory start address register

Memory start address register

Table 3.6 (3) Memory Start Address Register

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Table 3.6 (4) Memory Start Address Mask Registers

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MSAR0 to 3 < S23> to <S16> correspond to addresses

(2) How to the Start Address

A23 to A16 and S15, S14 to 9, and S8 corresponding to

addresses A15, A14, to 9, and A8 are “0” by default. MAMR0

<V20> to <V8> enable/disable comparison of value set with

MSAR0 and address and <V20> to <V8> correspond to

<S20> to <S16>, S15, S14 to 9, and S8. In addition, V21,

V22, and V23 corresponding to <S21>, <S22>, and <S23>

are “0” by default and comparison is always enabled.

The address decoder is output by specifying the start address

for CS output and the space size.

The start address is set every 64K-byte because it is

decoded by A16 to A23 as shown in the block diagram.

In other words, the DRAM start address is set to one of

the 64K-byte intervals after “000000H”.

However, note that the start address may be changed

due to the value of the MAMR.

Example of enabling/disabling comparison

(CS0 registers MSAR0 and MSAMR0)

When comparison is disabled by setting <V16> = 1, the

comparison of the value of <S16> and address A16 is dis-

abled and the value of <S16> becomes invalid.

When comparison is enabled by setting <V16> = 0, the

comparison of the value of <S16> and address A16 is

enabled and CS0 is enabled only when they match.

CS1, CS2, and CS3 can be used in the same manner.

Figure 3.6 (5). Where to Set Start Address

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(3) How to Set the Address Space

As shown in the address decoder block diagram (Figures

3.6 (2) to (4)), CS0, CS1, or CS2/CS3 can specify the address

area for which the chip select signal can be output depending

on whether to compare the address A8 to A20, A8 to A21, or

A15 to A22 respectively.

The address space is speciﬁed by setting the memory start

address mask register (MAMR0 to 3).

Figure 3.6 (6). Chip Select and Space Size

(4) Start Address/Address Space Setting Procedure

➅Reset MSAR and re-verify (return to step 3).

(Setting Example)

➀ Set memory start address mask register (MAMR)

(Set address space)

When address space is 128K-byte and start address is

30000H (area 30000H to4FFFFH).

➁ Set memory start address register (MSAR)

(Set area start address)

Set

➂Check the identical address bit of MAMR and MSAR

MAMR = 0FH address space 128K-byte

MSAR = 03H start address 30000H

Example: Check the value of (CS0) MAMR0 <V16>

and MSAR0 <S16>

MAMR <V16> and MSAR <S16> are “1” and “1” and the

start address changes to 2000H. (space 20000H to

3FFFFH).

If this is not desired, change the start address.

Change the start address to 4000H. (space 40000H to

5FFFFH).

➃If the bits at identical address are “1” and “1”, MSAR bit

is treated as “0”. <-The start address changes.

Example: If (CS0) MAMR <V16> = 1 and MSAR

<S16> = 1, comparison of address A16

and <S16> is disabled and address A16 is

selected regardless of whether the value is

“1” or “0” and the start address is replaced

by the value in MSAR.

MAMR = 0FH

MSAR = 04H

The bits at identical address of MAMR and MSAR are not

“1” and “1” and the start address remains unchanged.

Therefore, a 128K-byte space starting at address

40000H can be decoded.

➄ If it is OK for the start address to change, end the set-

ting procedure. If not, change the value to MSAR.

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(Setting example 1) (CS0)

chip select output is as shown in the following memory map.

When MSAR is set to 02H and MAMR is set to 0FH, the

S23 to S17 are valid because V23 to V17 = “0” and S16

are invalid because V16 to V8 = “1”.

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(Setting example 2) (CS0)

chip select output is as shown in the following memory map.

When MSAR is set to 01H and MSAR is set to 04H, the

The values of S23 - S16, and S14-S8 become valid

becomes invalid because V15 = 1.

because V23 to V16 = 0 and V14 - V8 = 0.The value of S15

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(Setting example 3) (CS0)

Space where chip select is output by values set in MSAR and

MAMR (excerpt).

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3.6.3 Default Address Space Speciﬁcation (B0CS to

B2CS < B0ARE to B2ARE> = “0”)

The following ﬁgures show the actual chip select image. CS0

can specify 7F00H to 7FFFH, CS1 can specify 80H to 7FFFH,

and CS2 can specify 8000H to 3FFFFFH. This is because

external connection of devices (such as RAM or I/O) other than

ROM is considered.

mapped in this space mainly due to external I/O expansion

consideration.

The area 80H to 7FFFH (approximately 32K-byte space)

for CS1 is mapped in this space mainly due to external RAM

expansion consideration.

The area 8000H to 3FFFFFH (approximately 4M-byte

space) for CS2 is mapped in this space mainly due to external

ROM expansion consideration.

The area 7F00 to 7FFFH (256-byte space) for CS0 is

CS0

CS1

CS2

7F00H

80H

8000H

3FFFFFH

FFFFFFH

(Mainly for I/O)

(Mainly for RAM)

(Mainly for ROM)

Supplement 1: The access priority is in the order of built-in I/O and chip select/wait controller.

Supplement 2: Wait for spaces other than CS0 to CS3 is set with B0CS register <BEXW1,0> and the data bus width is ﬁxed to 16-bit if the AM8/16 pin is “0”

and to 8 bits if it is “1”.

Note:

When using the chip select/wait controller, do not assign multiple deﬁnitions to the same address area. (However, if CS0 is set to 7F000H to

7FFFH and CS1 is set to 80H to 7FFFH, only the CS0 setting/pin is active in the overlapped address space 7F00H to 7FFFH.)

When the bus is opened (BUSAK = “0”), CS0 to CS3 pins are also opened (output buffer OFF). Refer to the note on bus open in section “3.5

Port Functions” for the pin status at this point.

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3.6.4 Example of Usage

Figure 3.6 (6) is an example (1) in which an external

memory is connected to the TMP96C031F. In this

example, a ROM is connected using 16-bit Bus; a

RAM is connected using 8-bit Bus.

(1)

Connection example 1

Figure 3.6 (7). Example of External Memory Connection (ROM = 16-bit, RAM and I/O = 8-bit)

After a reset, the CS0 - CS3 pins are set to output port

The program used to set these pins is as follows:

mode; 1 is output from CS0, CS1, and CS3; 0 from CS2.

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P4FC EQU

B0CS EQU

B1CS EQU

B2CS EQU

B3CS EQU

MSAR3 EQU

MAMR3 EQU

10H

68H

69H

6AH

6BH

46H

47H

LD

(BOCS),

10010000B ; CS0 = 8-bit, 2WAIT, 7F00H ~ 7FFFH, 2WAIT other than in CS0 ~ CS3 areas

100111XXB ; CS1 = 8-bit, 0WAIT, 80H ~ 7FFFH

100001XXB ; CS2 = 16-bit, 1WAIT, 8000H ~ 3FFFFFH

10111100B ; CS3 = 8-bit, 0WAIT, address area speciﬁcation (400000H ~ 407FFFH)

01000000B ; CS3 start address: 400000H

(B1CS),

(B2CS),

(B3CS),

(MSAR3),

(MAMR3), 00000000B ; CS3 area = 32K-byte

(P4FC), XXXX1111B ; CS0 ~ CS3 output mode

Note: X: don’t care

(2)

Connection example 2

Figure 3.6 (7) is an example (2) in which an external

memory is connected to the TMP96C031. In this

example, the ROM, RAM, and I/O are connected with

8-bit width.

Figure 3.6 (8). Example of External Memory Connection (ROM = 16-bit, RAM and I/O = 8-bit)

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After a reset, the CS0 - CS3 pins are set to output port

mode; 1 is output from CS0, CS1, and CS3; 0 from CS2.

The program used to set these pins is as follows:

P4FC EQU

B0CS EQU

B1CS EQU

B2CS EQU

B3CS EQU

MSAR3 EQU

MAMR3 EQU

10H

68H

69H

6AH

6BH

46H

47H

LD

(BOCS),

10010000B ; CS0 = 8-bit, 2WAIT, 7F00H ~ 7FFFH, 2WAIT other than in CS0 ~ CS3 areas

100111XXB ; CS1 = 8-bit, 0WAIT, 80H ~ 7FFFH

(B1CS),

(B2CS),

(B3CS),

(MSAR3),

100001XXB ; CS2 = 16-bit, 1WAIT, 8000H ~ 3FFFFFH

10111100B ; CS3 = 8-bit, 0WAIT, address area speciﬁcation (400000H ~ 407FFFH)

01000000B ; CS3 start address: 400000H

(MAMR3), 00000000B ; CS3 area = 32K-byte

(P4FC), XXXX1111B ; CS0 ~ CS3 output mode

Note: X: don’t care

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3.6.5 How to Start with an 8-Bit Data Bus

(with AM8/16 = “0”)

Resetting sets the CS2 pin low due to an internal pull-down

resistor; memory access starts in 16-bit data bus (2-wait)

mode. To start in 8-bit data bus mode, a special operation is

required. Operation is as described in the example below:

B2CS EQU

ORG

6AH

; CS2 register address

; RESET address

8000H

LDX

(B2CS), 9CH ; CS2 8-bit, 0WAIT, 8000H ~

After reset, the program reads the LDX (B2CS), 9CH

instruction in 16-bit data bus mode. LDX is a 6-byte instruc-

tion: the 2nd, 4th and 6th bytes are handled as dummies (i.e.,

only codes in the 1st, 3rd and 5th bytes are actually used).

Even if starting in 8-bit data bus mode, it is possible to pro-

gram so that the LDX instruction is executed and the block 2

area (8000H - 3FFFFFH) is accessed in 8-bit data bus mode

without any problem.

The above program does not include setting the P42/

CS2 pin to output; add a program to set the P4CR and P4FC

registers as required.

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3.7 8-bit Timers

Figure 3.7 (1) shows the block diagram of 8-bit timer

(timer 0 and timer 1).

Timers 2 and 3 have the same circuit conﬁguration as

timers 0 and 1. However, timer 0 has an external clock, pin TI0,

whereas timer 2 does not.

Each interval timer consists of an 8-bit up counter, 8-bit

comparator, and 8-bit timer register. Timer ﬂip-ﬂop (TFE1) is

provided for timers 0 and 1; TFE3 timer 2 and 3.

Among the input clock sources for the interval timers, the

internal clocks of φ T1, φ T4, φT16, and φT256 are obtained

from the 9-bit prescaler shown in Figure 3.7 (2).

The operation modes and timer ﬂip-ﬂops of the 8-bit

timer are controlled by three control registers T01MOD,

T23MOD, TFFCR, TRUN, and TRDC.

TMP96C031F contains four 8-bit timers (timers 0, 1 2, and 3),

each of which can be operated independently. The cascade

connection allows these timers to be used as two 16-bit tim-

ers. The following four operating modes are provided for the 8-

bit timers.

• 8-bit interval timer mode (4 timers)

• 16-bit interval timer mode (2 timers)

• 8-bit programmable square wave pulse generation (PPG:

variable duty with variable cycle) output mode (2 timers)

• 8-bit pulse width modulation (PWM: variable duty with con-

stant cycle) output mode (1 timer)

Either two 8-bit buses or

one 16-bit bus can be used.

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Figure 3.7 (1). Block Diagram of 8-Bit Timers (Timers 0 and 1)

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➀ Prescaler

Among them, 8-bit timer uses 4 types of clock:

φT1, φ T4, φT16, and φT256.

This prescaler can be run or stopped by the timer

operation control register TRUN <PRRUN>. Counting

starts when <PRRUN> is set to “1”, while the prescaler is

cleared to zero, and stops operation when <PRRUN> is

set to “0”. Resetting clears <PRRUN> to “0”, which

clears and stops the prescaler.

This 9-bit prescaler generates the clock input to the

8-bit timers, 16-bit timer/event counters, and baud rate

generators by further dividing the fundamental clock (fc)

after it has been divided by 4 (fc/4).

Figure 3.7 (2). Prescaler

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➁ Up-counter

This is an 8-bit binary counter counted by an input

clock speciﬁed by mode register T01MOD for timers 0

and 1, or mode register T23MOD for timers 2 and 3.

Input clocks for timer 0 or 2 can be selected from internal

clocks φ T1, φ T4, and φT16 depending to the value set in

the TI0 pin can also be selected.

The counting and stop and clear of up-counter can

be controlled for each interval timer by the timer opera-

tion control register TRUN. When reset, all up-counters

will be cleared to stop the timers.

➂ Timer register

This is an 8-bit register for setting an interval time.

When the set value of timer registers TREG0, TREG1,

TREG2, TREG3 matches the value of up-counter, the

comparator match detect signal becomes active. If the

set value is 00H, this signal becomes active when the up-

counter overﬂows.

Timer register TREG0/TREG2 is of double buffer

structure, each of which makes a pair with register buffer.

TREG0/TREG2 is used to control enable/disable of

the double buffers according to the timer register double

buffer control register, TRDC <TR0DE, TR2DE>. It is dis-

abled when <TR0DE>/<TR2DE> = 0 and enabled when

they are set to 1.

The input clock of timer 1 or 3 depends on the oper-

ation mode; in 16-bit timer mode, timer 0/2 overﬂow out-

put is used as the output clock. When set to any other

mode than 16-bit timer mode, the input clock is selected

from the internal clocks φ T1, φ T16, and φT256 as well

as the comparator output (match detection signal) of

timer 0 according to the set value of T01MOD register or

T23MOD.

Example: When T01MOD <T01M1,0> = 01, the over

ﬂow output of timer 0 becomes the input

clock of timer 1 (16-bit timer).

When T01MOD7, 6 = 00, T01MOD3, 2 =

01, φ T1 (8/fc) becomes the input of timer

1 (8-bit timer).

In the condition of double buffer enable state, the

data is transferred from the register buffer to the timer

n

register when the 2 - 1 overﬂow occurs in PWM mode,

or at the PPG cycle in PPG mode.

Operation mode is also set by T01MOD register and

T23MOD register. When reset, it is initialized to T01MOD

<T01M1, 0> = 00, T23MOD <T23M1, 0> = 00 whereby

the up-counter is placed in the 8-bit timer mode.

When reset, it will be initialized to <TR0DE>/

<TR2DE> = 0 to disable the double buffer. To use the

double buffer, write data in the timer register, set

<TR0DE>/<TR2DE> to 1, and write the following data in

the register buffer.

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Figure 3.7 (3). Conﬁguration of Timer Register 0/2

Note: Timer register and the register buffer are allocated to the same memory address. When <TR0DE>/<TR2DE> = 0, the same value is written in the reg-

ister buffer as well as the timer register, while when <TR0DE>/<TR2DE> = 1 only the register buffer is written.

The memory address of each timer register is as fol-

lows.

TREG2: 000026H

TREG3: 000027H

All registers are write-only and cannot be read.

TREG0: 000022H

TREG1: 000023H

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Figure 3.7 (4). Timer 0, 1 Mode Register (T01MOD)

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Figure 3.7 (5). Timer 2,3 Mode Register (T23MOD)

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Figure 3.7 (6). 8-Bit Timer Flip-Flop Control Register (TFFCR)

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Figure 3.7 (7). Timer Operation Control Register (TRUN)

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Figure 3.7 (8). Timer Register Double Buffer Control Register (TRDC)

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➃Comparator

The operation of 8-bit timers will be described below:

8-bit timer mode

(1)

A comparator compares the value in the up-counter

with the values to which the timer register is set. When

they match, the up-counter is cleared to zero and an

interrupt signal (INTT0, INTT1, INTT2, INTT3) is gener-

ated. If the timer ﬂip-ﬂop inversion is enabled, the timer

ﬂip-ﬂop is inverted at the same time.

Four interval timers 0, 1, 2, 3, can be used indepen-

dently as 8-bit interval timer. All interval timers operate

in the same manner, and thus only the operation of

timer 1 will be explained below.

➄ Timer flip-flops (timer F/F)

➀ Generating interrupts in a fixed cycle

The timer ﬂip-ﬂops are inverted according to the

interval timer match detect signal (comparator output).

The signal can output a value to the timer output pins

TO1 (also used as P70) and TO3 (also used as P71).

There are two timer ﬂip-ﬂops: TFF1 for timers 0 and

1; TFF3 for timers 2 and 3. TFF1 is output to the TO1 pin;

TFF3 to the TO3 pin.

TO3 (also used as P71) is multiplexed using the

DMUX pin; setting must be done using the port 7 control

registers (P7CRL and P7CRH).

To generate timer 1 interrupt at constant intervals using

timer 1 (INTT1), ﬁrst stop timer 1 then set the operation

mode, input clock, and a cycle to T01MOD and

TREG1 register, respectively. Then, enable interrupt

INTT1 and start the counting of timer 1.

Example: To generate timer 1 interrupt every 40

microseconds at fc = 16MHz, set each

register in the following manner.

MSB

LSB

7

–

0

6

–

0

5

–

x

4

–

x

3

–

0

2

–

1

0

–

0

–

TRUN

←

Stop timer 1, and clear it to “0”.

T01MOD

Set the 8-bit timer mode, and select φT1

(0.5µs @ fc = 16MHz) as the input clock.

Set the timer register at 40µs φT1 = 50H.

Enable INTT1, and set it to “Level 5”.

Start timer 1 counting.

TREG1

INTET10

TRUN

←

0

1

x

1

x

1

0

1

0

1

–

1

–

0

–

0

–

1

0

–

Note: x; don’t care

–; no change

Use the following table for selecting the input clock.

Table 3.7 (1) 8-Bit Timer Interrupt Cycle and Input Clock

Interrupt Cycle

(at fc = 20MHz)

Input Clock

Resolution

φT1 (8/fc)

0.4µs ~ 102.4µs

1.6µs ~ 409.6µs

0.4µs

1.6µs

φT4 (32/fc)

φT16 (128/fc)

φT256 (2048/fc)

6.4µs ~ 1.638ms

102.4µs ~ 2.621ms

6.4µs

102.4µs

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➁ Generating a 50% duty square wave pulse

Example: To output a 2.4µs square wave pulse from

TO1 pin at fc = 20MHz, set each register in

the following procedures. Either timer 0 or

timer 1 may be used, but this example uses

timer 1.

The timer ﬂip-ﬂop is inverted at constant intervals, and

its status is output to timer output pin (TO1).

MSB

LSB

7

–

0

6

–

0

5

–

x

4

–

x

3

–

0

2

–

1

0

–

0

–

TRUN

←

Stop timer 1, and clear it to “0”.

T01MOD

Set the 8-bit timer mode, and select φT1 as the input clock.

TREG1

TFFCR

←

0

1

0

1

Set the timer register at 2.4µs ÷φT1 ÷2 = 3.

–

Clear TFF1 to “0”, and set to invert by the match detect signal from timer 1.

P7CRL

TRUN

←

–

x

–

x

–

1

–

1

0

Select P71 as TO1 pin.

Start timer 1 counting.

–

Note: x; don’t care

–; no change

Figure 3.7 (9). Square Wave (50% Duty) Output Timing Chart

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➂ Making timer 1 count up by match signal from timer

Set the 8-bit timer mode, and set the comparator out-

put of timer 0 as the input clock to timer 1.

0 comparator

Figure 3.7 (10). Timer 1 Count Up by Timer 0

➃ Output inversion with software

(2)

16-bit timer mode

The value of timer ﬂip-ﬂop (Timer F/F) can be inverted,

independent of timer operation.

A 16-bit interval timer is conﬁgured by combining tim-

ers 0 and 1, or timers 2 and 3.

Writing “00” into TFFCR <TFF1C1, 0> inverts the value

of TFF1, writing “00” into TFFCR <FF3C1, 0> inverts

the value of TFF3.

Timers 0 and 1 combined function the same as timers

2 and 3. A combination of timers 0 and 1 is used for

explanation here.

To conﬁgure a 16-bit timer by cascade-connecting tim-

ers 0 and 1, set the mode register, T01MOD

<T10M1,0>, to 00.

➄ Initial setting of timer flip-flop (Timer F/F)

Setting 16-bit timer mode the input clock for timer 1 to

timer 0 overﬂow output regardless of the value set in

the clock control register, TCLK.

The value of TFF1 can be initialized to “0” or “1”, inde-

pendent of timer operation.

For example, write “10” in TFFCR <TFF1C1, 0> to

clear TFF1 to “0”, while write “01” in TFFCR <TFF1C1,

0> to set TFF1 to “1”.

Note: The value of timer register and timer ﬂip-ﬂop cannot be read.

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Table 3.7 (2) 16-Bit Timer (Interrupt) and Input Clock

Interrupt Cycle

(at fc = 20MHz)

Input Clock

Resolution

φT1 (8/fc)

φT4 (32/fc)

φT16 (128/fc)

0.4µs ~ 26.214ms

1.6µs ~ 104.857ms

6.4µs ~ 419.430ms

0.4µs

1.6µs

6.4µs

The lower 8-bit of the timer (interrupt) cycle are set by the

timer register TREG0, and the upper 8 bits are set by TREG1.

Note that TREG0 always must be set ﬁrst. (Writing data into

TREG0 disables the comparator temporarily, and the compar-

ator is restarted by writing data into TREG1.)

The comparator match signal is output from timer 0

each time the up-counter UC0 matches TREG0, where the

up-counter UC0 is not to be cleared.

INT0 is not to be generated at this time, either.

With the timer 1 comparator, the match detect signal is

output at each comparator timing when up-counter UC1 and

TREG1 values match. When the match detect signal is output

simultaneously from both comparators of timer 0 and timer 1,

the up-counters UC0 and UC1 are cleared to “0”, and the

interrupt INTT1 is generated. If inversion is enabled, the value

of the timer ﬂip-ﬂop TFF1 is inverted.

Setting example:

To generate an interrupt INTT1 every

0.4 seconds at fc = 20MHz, set the

following values for timer registers

TREG0 and TREG1:

When counting with input clock of

φT16 (8µs @ 16MHz) 0.4 sec ÷ 4µs

= 62500 = F424H

Therefore, set TREG1 = F4H and

TREG0 = 24H, respectively.

Figure 3.7 (11). Output Timer by 16-Bit Timer Mode

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(3)

8-bit PPG (Programmable Pulse Generation) Output

mode

mode, timer 1 cannot be used.

With timer 0, data are output to the TO1 pin (also used

as P70); with timer 2, to the TO3 pin (also used as

P71).

Square wave pulse can be generated at any frequency

and duty by timer 0 or timer 1 and timer 0. The output

pulse may be either low-active or high-active. In this

Figure 3.7 (12). Block Diagram of 8-Bit PPG Output Mode

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When the double buffer of TREG0 is enabled in this

mode, the value of register buffer will be shifted in TREG0 each

time TREG1 matches UC0.

Use of the double buffer makes easy handling of low duty

waves (when duty is varied).

Example: Generating 1/4 duty 62.5kHz pulse @ fc = 20MHz)

• Calculate the value to be set for timer register.

To obtain the frequency 62.5kHz, the pulse cycle t

should be: t = 1/62.5kHz = 16µs.

Consequently, to set the timer register 1 (TREG1) to

TREG1 = 40 = 28H and then duty to 1/4, t x 1/4 =

16µs x 1/4 = 4µs

4µs ÷ 0.4µs = 10

Therefore, set timer register 0 (TREG0) to TREG0 = 10

= 0AH.

Given φ T1 = 0.4µs @ 20MHz),

16µs ÷ 0.4µs = 40

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MSB

LSB

7

6

x

5

–

x

4

–

x

3

–

x

2

–

x

1

0

1

x

TRUN

←

x

0

1

Stop timer 0, and clear it to “0”.

Set the 8-bit PPG mode, and select φT1 as input clock.

Sets TFF1 and enables the inversion and double buffer enable.

Writing “10” provides negative logic pulse.

Write “0AH”.

T01MOD

TFFCR

1

–

0

–

0

1

TREG0

TREG1

P7CRL

TRUN

←

0

–

x

0

–

x

0

1

–

1

0

–

1

–

0

–

1

0

1

0

1

Write “28H”.

Set P70 as the TO1 pin.

Start timer 0 and timer 1 counting.

Note: x; don’t care

–; no change

(4)

8-bit PWM Output mode (Pulse Width Modulation)

matches the set value of timer register TREG or when

2n - 1 (n = 6, 7, or 8; speciﬁed by T01MOD) counter

overﬂow occurs. Up-counter UC1 is cleared when 2n -

1 counter overﬂow occurs. For example, when n = 6,

6-bit PWM will be output, while when n = 7, 7-bit PWM

will be output.

Mode used for timers 1 and 3. Up to 2 PWMs with a

resolution of 8-bit (PWM1 and PWM3) pulse can be

output.

With timer 1, PWM is output to the TO1 pin (also used

as P70); with timer 3, to the TO3 pin (also used as

P71).

To use this PWM mode, the following conditions must

be satisﬁed.

Timer 0 or 2 is used as an 8-bit timer.

Timer 1 (PWM1) is explained here because the opera-

tion is the same as timer 3.

n

(Set value of timer register) < (Set value of 2 - 1

counter overﬂow)

(Set value of timer register ≠ 0)

Timer output is inverted when up-counter (UC1)

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Figure 3.7 (13). Block Diagram of 8-Bit PWM Waveforms

In this mode, the value of register buffer will be shifted in

TREG0 if 2 - 1 overﬂow is detected when the double buffer of

Use of the double buffer makes the handling of small

duty waves easy.

n

TREG0 is enabled.

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Example: To output the following PWM waves to TO1

To realize 50.8µs of PWM cycle by φT1 = 0.4µs (@ fc =

20MHz),

pin at fc = 20MHz.

n

50.8µs ÷ 0.4µs = 127 = 2 - 1

Consequently, n should be set to 7.

As the period of low level is 36µs, for φT1 = 0.4µs, set the

following value for TREG0:

36µs ÷ 0.4µs = 90 = 5AH

MSB

7

LSB

0

6

x

1

5

–

1

4

–

0

3

–

2

–

1

–

0

TRUN

←

x

0

1

Stop timer 0, and clear it to “0”.

7

T01MOD

1

Set 8-bit PWM mode (cycle : 2 - 1)

and select φT1 as the input clock.

Clears TFF1, enables the inversion and double buffer.

Write “5AH”.

TFFCR

TREG0

P7CRL

TRUN

←

–

0

–

x

–

1

–

x

–

0

–

1

–

1

–

1

–

0

–

1

–

x

0

1

Set P70 as the TO1 pin.

Start timer 0 counting.

Note : x; don’t care

–; no change

n

Table 3.7 (3) PWM Cycle and the Setting of 2 - 1 Counter

PWM Cycle (@ fc = 20 MHz)

φT1

φT4

100µsec (10.0kHz)

φT16

4.03msec (2.4kHz)

6

2 - 1

25.2µsec (39.0kHz)

50.8µsec (19.7kHz)

102µsec (9.80kHz)

7

2 - 1

203µsec (4.9kHz)

408µsec (2.4kHz)

812msec (1.2kHz)

8

2 - 1

1.63msec (0.61kHz)

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(5)

Table 3.7 (4) shows the list of 8-bit timer modes.

Table 3.7 (4) Timer Mode Setting Registers

Mode

T01M

(T23M)

Upper Input

T1CLK

(T3CLK)

Lower Input

T0CLK

(T2CLK)

Invert Select

FF1IS

(FF3IS)

Timer Mode

(8-bit timer x 2channel)

PWM0

(PWM2)

16-bit timer

(Full 16-bit) x 1channel

(External clock,

φT1, 4, 16)

–

01

00

–

8-bit timer

(External clock,

φT1, 4, 16)

0 : Lower timer

1 : Upper timer

(8-bit x 8-bit mode x 1channel)

(Comparator output from the lower timer is

input to the upper timer.)

00

(External clock,

φT1, 4, 16)

0 : Lower timer

1 : Upper timer

8-bit timer x 2channel

8-bit PPG x 1channel

00

10

11

–

(φT1, T16, T256)

–

(External clock,

φT1, 4, 16)

–

8-bit PWM x 1channel (Lower)

8-bit timer x 1channel (Upper)

(External clock,

φT1, 4, 16)

PWM cycle

(φT1, T16, T256)

Note: –: don’t care

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3.8 16-Bit PWM Timer

The TMP96C031F contains one (timer 4) multifunctional 16-bit

timer/event counter with the following operation modes.

Timer/event counter consists of 16-bit up-counter, two

16-bit timer registers, two 16-bit capture registers (One of

them applies double-buffer), two comparators, capture input

controller, and timer ﬂip-ﬂop and the control circuit.

• 16-bit interval timer mode

• 16-bit event counter mode

Timer/event counter is controlled by 4 control registers:

T4MOD, T4FFCR, TRUN and T45CR.

• 16-bit programmable pulse generation mode

• Frequency measurement mode

• Pulse width measurement mode

• Time differential measurement mode

Figure 3.8 (1) shows the block diagram of 16-bit timer/

event counter (timer 4).

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Figure 3.8 (1). Block Diagram of 16-Bit Timer (Timer 4)

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Figure 3.8 (2). 16-Bit Timer Mode Controller Register (T4MOD) (1/2)

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Figure 3.8 (3). 16-Bit Timer Mode Controller Register (T4MOD) (2/2)

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Figure 3.8 (4). 16-Bit Timer 4 F/F Control (T4FFCR)

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Figure 3.8 (5). 16-Bit Timer (Timer 4) Control Register (T45CR)

Figure 3.8 (6). Timer Operation Control Register (TRUN)

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➀ Up-counter

timer register TREG5. The “clear enable/disable” is set

by T4MOD <CLE>.

UC4 is a 16-bit binary counter which counts up

according to the input clock speciﬁed by T4MOD

<T4CLK1,0> register.

If clearing is disabled, the counter operates as a free-

running counter.

As the input clock, one of the internal clocks φT1(8/

fc), φT4 (32/fc), and φT16 (128/fc) from 9-bit prescaler

(also used for 8-bit timer), and external clock from TI4

pin (also used as P72/INT4 pin) can be selected.

When reset, it will be initialized to <T4CLK1,0> = 00

to select TI4 input pin mode. Counting or stop and

clear of the counter is controlled by timer operation

control register TRUN <T4RUN> .

➁ Timer registers

These two 16-bit registers are used to set the interval

time. When the value of up-counter UC4 matches the

set value of this timer register, the comparator match

detect signal will be active.

Setting data for timer register (TREG4 and TREG5) is

executed using 2-byte data transfer instruction or

using 1-byte data transfer instruction twice for lower

8-bit and upper 1-bit in order.

When clearing is enabled, up-counter UC4 will be

cleared to zero each time it coincides matches the

TREG4 timer register is of double buffer structure,

which is paired with register buffer. The timer control

register T45CR <DB4EN> controls whether the dou-

ble buffer should be enabled or disabled. : disabled

when <DB4EN> = 0, while enabled when <DB4EN>

= 1.

When the double buffer is enabled, the timing to

transfer data from the register buffer to the timer regis-

ter is at the match between the up-counter (UC4) and

timer register TREG5.

register buffer.

TREG4 and register buffer are allocated to the same

memory addresses 000030H/000031H. When

<DB4EN> = 0, same value will be written into only the

register buffer.

➂Capture Register

These 16-bit registers are used to hold the values of

the up-counter.

When reset, it will be initialized to <DB4EN> = 0,

whereby the double buffer is disabled. To use the

double buffer, write data in the timer register, set

<DB4EN> = 1, and then write the following data in the

Data in the capture registers should be read by a 2-

byte data load instruction or two 1-byte data load

instruction, from the lower 8-bit followed by the upper

8-bit.

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➃ Capture Input Control

➄ Comparator

This circuit controls the timing to latch the value of up-

counter UC4 into (CAP1, CAP2). The latch timing of

capture register is controlled by register T4MOD

<CAP12M 1, 0>/T5MOD <CAP34M1,0>.

These are 16-bit comparators which compare the up-

counter UC4 value with the set value of (TREG4,

TREG5) to detect the match. When a match is

detected, the comparators generate and interrupt

(INTT4, INTT5) respectively. The up-counter UC4 is

cleared only when UC4 matches TREG5. (The clear-

ing of up-counter UC4 can be disabled by setting

T4MOD <CLE> = 0.)

• When T4MOD <CAP12M 1, 0> = 00

Capture function is disabled. Disable is the default on

reset.

➅ Timer flip-flop (TFF4)

• When T4MOD <CAP12M1, 0> = 01

Data is loaded to CAP1 at the rise edge of TI4 pin

(also used P80/INT4) input, while data is loaded to

CAP2 at the rise edge of TI5 pin (also used as P81/

INT5) and input. (Time difference measurement)

This ﬂip-ﬂop is inverted by the match detect signal

from the comparators and the latch signals to the

capture registers. Disable/enable of inversion can be

set for each element by T4FFCR <CAP2T4, CAP1T4,

EQ5T4, EQ4T4>. TFF4 will be inverted when “00” is

written in T4FFCR <TFF4C1,0>. Also it is set to “1”

when “10” is written, and cleared to “0” when “10” is

written. The value of TFF4 can be output to the timer

output pin TO4 (also used as P70).

• When T4MOD <CAP12M1, 0> = 10

Data is loaded to CAP1 at the rise edge of TI4 pin

input, while to CAP2 at the fall edge. Only in this set-

ting, interrupt INT4 occurs at fall edge. (Pulse width

measurement)

➆ Timer flip-flop (TFF5)

• When T4MOD <CAP12M1, 0> = 11

Data is loaded to CAP1 at the rise edge of timer ﬂip-

ﬂop TFF1, while to CAP2 at the fall edge.

This ﬂip-ﬂop is inverted by the match detect signal

from the comparator and the latch signal to the cap-

ture register CAP2. TFF5 will be inverted when “00” is

written in T4FFCR <TFF5C1,0>/T6FFCR

<TFF6C1,0>. Also it is set to “1” when “10” is written,

and cleared to “0” when “10” is written. The value of

TFF5 can be output to the timer output pin TO5 (also

used as P82).

Besides, the value of up-counter can be loaded to

capture registers by software. Whenever “0” is written

in T4MOD <CAP1IN> the current value of up-counter

will be loaded to capture register CAP1. It is neces-

sary to keep the prescaler in RUN mode (TRUN

<PRRUN> to be “1”).

TO5 (also used as P30) is multiplexed using the HWR

pin; setting must be done using the port 3 control reg-

ister, P3CRL.

Note: TO5 (also used as P30) is multiplexed with HWR; setting

must be done using the P3SR.

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(1) 16-Bit Timer Mode

Generating interrupts at ﬁxed intervals

In this example, the interval time is set in the timer reg-

ister TREG5 to generate the interrupt INTTR5.

7

x

6

x

5

–

0

1

4

0

3

–

1

0

2

–

0

1

–

0

1

*

0

–

0

1

*

TRUN

←

Stop timer 4.

INTET54

T4FFCR

T4MOD

1

0

1

0

Enable INTTR5 and sets interrupt level 4. Disable INTTR4.

Disable trigger.

Select internal clock for input and disable the capture function.

(** = 01, 10, 11)

TREG5

TRUN

←

0

*

1

0

*

x

1

*

1

0

*

1

*

0

*

0

*

0

*

Set the interval time (16-bit).

Start timer 4.

–

Note : x; don’t care

–; no change

(2)

16-Bit Event Counter Mode

external clock (TI4 pin input) as the input clock. To read

the value of the counter, ﬁrst perform the “software

capture” once and read the captured value.

The counter counts at the rise edge of TI4 pin input.

TI4 can also be used as P72/INT4.

In 16-bit timer mode as described in above, the timer

can be used as an event counter be selecting the

7

x

6

x

5

–

0

4

0

3

–

1

2

–

0

1

–

0

–

0

TRUN

←

Stop timer 4.

P7CR

–

1

–

1

Set P72 to input mode.

INTET54

Enable INTTR5 and sets interrupt level 4, while disable INTTR4.

T4FFCR

T4MOD

TREG5

TRUN

←

1

0

*

x

1

0

*

x

0

1

*

0

*

0

*

0

1

*

1

0

*

1

0

*

Disable trigger.

Select TI4 as the input clock.

Set the number of counts (16-bit).

Start timer 4.

1

–

Note: When used as an event counter, set the prescaler in RUN mode.

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(3)

16-Bit Programmable Pulse Generation (PPG) Mode

up-counter UC4 with the timer register TREG4 or 5

and to be output to TO4 (also used as P70). In this

mode, the following conditions must be satisﬁed.

The PPG mode is obtained by inversion of the timer

ﬂip-ﬂop TFF4 that is to be enabled by the match of the

(Set value of TREG4) < (Set value of TREG5)

7

x

*

6

x

*

5

–

*

4

0

*

3

–

*

2

–

*

1

–

*

0

–

*

TRUN

←

Stop timer 4.

TREG4

TREG5

T45CR

Set the duty. (16-bit).

Set the cycle. (16-bit).

Double Buffer of TREG4 enable

(Change the duty and cycle at the interrupt INTTR5).

Set the mode to invert TFF4 at the match with

TREG4/TREG5, and also set the TFF4 to “0”.

Select the internal clock for the input, and disable the

capture function.

T4FFCR

T4MOD

←

1

0

1

0

1

0

1

0

1

0

(** = 01, 10, 11)

P7CR

TRUN

←

–

x

–

x

–

1

–

1

–

1

Assign P70 as TO4.

–

Start timer 4.

Note : x; don’t care

–; no change

Figure 3.8 (7). Programmable Pulse Generation (PPG) Output Waveforms

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When the double buffer of TREG4 is enabled in this

mode, the value of register buffer 4 will be shifted in TREG4 at

match with TREG5. This feature makes easy the handling of

low duty waves.

Figure 3.8 (8). Operation of Register Buffer

Shows the block diagram of this mode.

Figure 3.8 (9). Block Diagram of 16-Bit PPG Mode

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(4)

Application Examples of Capture Function

➀ One-Shot Pulse Output from the External Trigger

Pulse

The loading of up-counter (UC4) values into the cap-

ture registers CAP1 and CAP2, the timer ﬂip-ﬂop TFF4

inversion due to the match detection by comparators

CP4 and CP5, and the output of the TFF4 status to

TO4 pin can be enabled or disabled. Combined with

interrupt function, they can be applied in many ways,

for example;

Set the up-counter UC4 in free-running mode with the

internal input clock, input the external trigger pulse

from TI4 pin, and load the value of up-counter into

capture register CAP1 at the rise edge of the TI4 pin.

Then set T4MOD <CAP12M1, 0> = 01.

When the interrupt INT4 is generated at the rise edge

of the TI4 pin, set the CAP1 value (c) plus a delay time

(d) to TREG5 (= c + d), and set the above set value (c +

d) plus a one-shot pulse width (p) to TREG5 (= c + d +

p). When interrupt INT4 occurs the T4FFCR <EQ5T4,

EQ4T4> register sgould be set that the TFF4 inversion

is enabled only when the up-counter value matches

TREG4 or TREG5. When interrupt INTTR5 occurs, this

inversion will be disabled.

➀ One-shot pulse output from the external trigger

pulse

➁ Frequency measurement

➂Pulse width measurement

➃Time difference measurement

Figure 3.8 (10). One-Shot Pulse Output (with Delay)

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Setting example: To output 2ms one-shot with 3ms delay

to the external trigger pulse to TI4 pin.

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When delay is unnecessary, invert timer ﬂip-ﬂop TFF4

when the up-counter value is loaded into capture register 1

(CAP1), and set the CAP1 value (c) plus the one-shot pulse

width (p) to TREG5 when the interrupt INT4 occurs. The TFF4

inversion should be enabled when the up-counter (UC4) value matches TREG5, and disabled when generating the interrupt

INTTR5.

Figure 3.8 (11). One-Shot Pulse Output (without Delay)

and Timer 1) and the 16-bit timer/event counter (Timer 4).

The TI4 pin input should be selected for the input

clock of Timer 4. The value of the up-counter is loaded

➁ Frequency Measurement

into the capture register CAP1 at the rise edge of the timer

ﬂip-ﬂop TFF1 of 8-bit timers (Timer 0 and Timer 1), and

into CAP2 at its fall edge.

The frequency is calculated by the difference between

the loaded values in CAP1 and CAP2 when the interrupt

(INTT0 or INTT1) is generated by either 8-bit timer.

The frequency of the external clock can be measured

in this mode. The clock is input through the TI4 pin, and

its frequency is measured by the 8-bit timers (Timer 0

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Figure 3.8 (12). Frequency Measurement

For example, if the value for the level “1” width of

TFF1 of the 8-bit timer is set to 0.5 s. and the difference

between CAP1 and CAP2 is 100, the frequency will be

100/0.5[s] = 200[Hz].

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➂ Pulse Width Measurement

external trigger pulse respectively. The interrupt INT4

occurs at the falling edge of TI4.

The pulse width is obtained from the difference

between the values of CAP1 and CAP2 and the internal

clock cycle.

For example, if the internal clock is 0.8 microseconds

and the difference between CAP1 and CAP2 is 100, the

pulse width will be 100 x 0.8 = 80 microseconds.

This mode allows measuring the “H” level width of an

external pulse. While keeping the 16-bit timer/event

counter counting (free-running) with the internal clock

input, the external pulse is input through the TI4 pin. Then

the capture function is used to load the UC4 values into

CAP1 and CAP2 at the rising edge and falling edge of the

Figure 3.8 (13). Pulse Width Measurement

Note: Only in this pulse width measuring mode (T4MOD <CAP12M1, 0> = 10), external interrupt INT4 occurs at the falling edge of TI4 pin input. In other

modes, it occurs at the rising edge.

The width of “L” level can be measured from the dif-

ference between the ﬁrst C2 and the second C1 at the

second INT4 interrupt.

Keep the 16-bit timer/event counter (Timer 4) count-

ing (free-running) with the internal clock, and load the

UC4 value into CAP1 at the rising edge of the input pulse

to TI4. Then the interrupt INT4 is generated.

Similarly, the UC4 value is loaded into CAP2 at the

rising edge of the input pulse to TI5, generating the inter-

rupt INT5.

➃ Time Difference Measurement

The time difference between these pulses can be

obtained from the difference between the time counts at

which loading the up-counter value into CAP1 and CAP2

has been done.

This mode is used to measure the difference in time

between the rising edges of external pulses input through

TI4 and TI5.

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Figure 3.8 (14). Time Difference Measurement

(5)

Different Phased Pulses Output Mode

When the value in up-counter UC4 and the value in

TREG4 (TREG5) match, the value in TFF4 (TFF5) is

inverted and output to TO4 (TO5).

In this output mode, signals with any different phase

can be outputted by free-running up-counter UC4.

This mode can only be used by 16-bit timer 4.

Figure 3.8 (15). Phase Output

Cycles (counter overﬂow time) of the above output

waves are listed below.

16MHz

20MHz

φT1

φT4

32.768ms

131.072ms

524.288ms

26.214ms

104.856ms

419.424ms

φT16

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bit timer2 or timer3, 16-bit timer4, to update the output.

The PG ports are controlled by control registers

(PG01CR) and can select either stepping motor control mode

or pattern generation mode. Each bit of the P6 can be used as

the PG port.

Channel 0 (PG0) and channel 1 (PG1) operate indepen-

dently.

Except in the following case, both channels operate the

same. Thus, channel 0 (PG0) is explained here.

3.9 Stepping Motor Control/Pattern Generation Port

The TMP96C031F contains 2 channels (PG0 and PG1) of 4-bit

hardware stepping motor control/pattern generation (herein

after called PG) which actuate in synchronization with the

(8-bit/16-bit) timers. The PG (PG0 and PG1) are shared in 8-bit

I/O ports P6.

Channel 0 (PG0) is synchronous with 8-bit timer 0 or

timer 1, 16-bit timer 4, channel 1 (PG1) is synchronous with 8-

Difference between PG0 and PG1

Figure 3.9 (1). Pattern Generator/Stepping Motor Control Block Diagram

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Figure 3.9 (2a). Pattern Generation Control Register (PG01CR)

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Figure 3.9 (2b). Pattern Generation Control Register (PG01CR)

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7

6

5

4

3

2

1

0

PG0REG

(004CH)

bit Symbol

Read/Write

After reset

Function

PG03

PG02

PG01

PG00

SA03

SA02

SA01

SA00

W

R/W

0

Undeﬁned

Pattern Generation 0 (PG0) output latch register

(Reading the P6 that is set to the PG port allows to read-out.)

Shift alternate register 0

For the PG mode (4-bit write) register

Prohibit Read

modify write

Figure 3.9 (3). Pattern Generation 0 Register (PG0REG)

7

6

5

4

3

2

1

0

PG1REG

(004DH)

bit Symbol

Read/Write

After reset

Function

PG13

PG12

PG11

PG10

SA13

SA12

SA11

SA10

W

R/W

0

Undeﬁned

Pattern Generation 1 (PG1) output latch register

(Reading the P6 that is set to the PG port allows to read-out.)

Shift alternate register 1

For the PG mode (4-bit write) register

Prohibit Read

modify write

Figure 3.9 (4). Pattern Generation 1 Register (PG1REG)

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Figure 3.9 (5). 16-bit Timer Trigger Control Register (T45CR)

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Figure 3.9 (6). Connection of Timer and Pattern Generator

(1)

Pattern Generation Mode

In this mode, set PG01CR <PG0M> and <PG1M> to

1, and PG01CR <CCW0> and <CCW1> to 0.

The output of this pattern generator is output to port 6;

since port and functions can be switched on a bit basis

using port function control register P6CRL/P6CRH, any

port pin can be assigned to pattern generator output.

PG functions as a pattern generation according to the

setting of PG01CR <PAT1>/<PAT0>. In this mode,

writing from CPU is executed only on the shifter alter-

nate register. Writing a new data should be done during

the interrupt operation of the timer for shift trigger, and

a pattern can be output synchronous with the timer.

Figure 3.9 (7) shows the block diagram of this mode.

Figure 3.9 (7). Pattern Generation Mode Timing Example

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Figure 3.9 (7). Pattern Generation Mode Block Diagram (PG0)

In this pattern generation mode, only writing the output

latch is disabled by hardware, but other functions do the same

operation as 1-2 excitation in stepping motor control port

mode. Accordingly, the data shifted by trigger signal from a

timer must be written before the next trigger signal is output.

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(2)

Stepping Motor Control Mode

➀ 4-phase 1-Step/2-Step Excitation

Figure 3.9 (8) and Figure 3.9 (9) show the output wave-

forms of 4-phase 1 excitation and 4-phase 2 excita-

tion, respectively when channel 0 (PG0) is selected.

Figure 3.9 (8). Output Waveforms of 4-Phase 1-Step Excitation

(Normal Rotation and Reverse Rotation)

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Figure 3.9 (9). Output Waveforms of 4-Phase 2-Step Excitation (Normal Rotation)

The operation when channel 0 is selected is

explained below.

The output latch of PG0 (also used as P6) is shifted

at the rising edge of the trigger signal from the timer to be

output to the port.

The direction of shift is speciﬁed by PG01CR

<CCW0>: Normal rotation (PG00 → PG01 → PG02 →

PG03) when <CCW0> is set to “0”; reverse rotation

(PG00 ← PG01 ← PG02 ← PG03) when “1”. Four-phase

1-step excitation will be selected when only one bit is set

to “1” during the initialization of PG, while 4-phase 2-step

excitation will be selected when two consecutive bits are

set to “1”.

The value in the shift alternate registers are ignored

when the 4-phase 1-step/2-step excitation mode is

selected.

Figure 3.9 (10) shows the block diagram.

Figure 3.9 (10). Block Diagram of 4-Phase 1-Step Excitation/2-Step Excitation

(Normal Rotation)

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➁ 4-Phase 1-2 Step Excitation

Figure 3.9 (11) shows the output waveforms of 4-

phase 1 -2 step excitation when channel 0 is selected.

Figure 3.9 (11). Output Waveforms of 4-Phase 1-2 Step Excitation

(Normal Rotation and Reverse Rotation)

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The initialization for 4-phase 1-2 step excitation is as

follows:

By rearranging the initial value “b7 b6 b5 b4 b3 b2

b1 b0” to “b7 b3 b6 b2 b5 b1 b4 b0”, the consecutive 3

bits are set to “1” and other bits are set to “0” (positive

logic).

For example, if b7, b3, and b6 are set to “1", the ini-

tial value becomes “11001000”, obtaining the output

waveforms as shown in Figure 3.10 (11).

example, to change the output waveform shown in Fig-

ure 3.10 (11) into negative logic, change the initial value

to “00110111”.

The operation will be explained below for channel 0.

The output latch of PG0 (shared by P6) and the

shifter alternate register (SA0) for Pattern Generation are

shifted at the rising edge of trigger signal from the timer

to be output to the port. The direction of shift is set by

PG01CR <CCW0>.

To get an output waveform of negative logic, set val-

ues 1s and 0’s of the initial value should be inverted. For

Figure 3.9 (12) shows the block diagram.

Figure 3.9 (12). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation)

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Setting example: To drive channel 0 (PG0) by 4-phase 1-2

step excitation (normal rotation) when

timer 0 is selected, set each register as follows:

7

–

0

x

6

x

0

x

*

0

–

1

x

5

–

x

4

–

x

3

–

1

*

2

–

0

*

1

–

0

1

*

0

1

0

*

TRUN

←

Stop timer 0, and clears it to zero.

TMOD

TFFCR

TREG0

P6CRL

PG01CR

PG0REG

TRUN

Set 8-bit timer mode and selects φT1 as the input clock of timer 0.

Clear TFF1 to zero and enables the inversion trigger by timer 0.

Set the cycle in timer register.

x

0

*

1

–

1

–

0

–

0

–

0

–

1

0

1

–

0

–

1

0

–

0

1

0

1

Set P60 ~ P63 bits to PG output.

Select PG0 4-phase 1 - 2 step excitation mode and normal rotation.

Set an initial value.

Start timer 0.

Note: x; don’t care

–; no change

(3)

Trigger Signal From Timer

not equal to the trigger signal of timer ﬂip-ﬂop (TFF1,

TFF4, TFF5, and TFF6) and differs as shown in Table

3.9 (1) depending on the operation mode of the timer.

The trigger signal from the timer which is used by PG is

Table 3.9 (1) Select of Trigger Signal

TFF1 Inversion

PG Shift

8-bit timer mode

16-bit timer mode

Selected by TFFCR <TFF1IS> when the up-counter value matches

TREG0 or TREG1 value.

When the up-counter value matches with both TREG0 and TREG1

8

values. (The value of up-counter = TREG1*2 + TREG0)

PPG output mode

PWM output mode

When the up-counter value matches with both TREG0 and TREG1.

When the up-counter value matches TREG1 value (PPG cycle).

When the up-counter value matches TREG0 value and PWM cycle. Trigger signal for PG is not generated.

Note: To shift PG, TFFCR <TFF1IE> must be set to “1” to enable TFF1 inversion.

Channel 1 of PG can be synchronized with the 16-bit

timer Timer 4. In this case, the PG shift trigger signal

from the 16-bit timer is output only when the up-

counter UC4 value matches TREG5.

When using a trigger signal from Timer 4, set either

T4FFCR <EQ5T4> or T4MOD <EQ5T5> to “1” and a

trigger is generated when the value in UC4 and the

value in TREG5 match.

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(4)

Application of PG and Timer Output

To drive a stepping motor, in addition to the value of

each phase (PG output), synchronizing signal is often

required at the timing when excitation is changed over.

In this application, port 6 is used as a stepping motor

control port to output a synchronizing signal to the

TO1 pin (shared by P70).

As explained in “Trigger signal from timer”, the timing

to shift PG and invert TFF differs depending on the

mode of timer. An application to operate PG while

operating an 8-bit timer in PPG mode will be explained

below.

Figure 3.9 (13). Output Waveforms of 4-Phase 1-Step Excitation

Setting example:

7

6

x

0

x

*

–

0

–

*

x

5

–

x

4

–

x

3

–

x

2

–

x

1

0

1

*

0

1

x

*

0

1

*

1

TRUN

←

–

1

x

Stop timer 0, and clears it to zero.

TMOD

TFFCR

TREG0

TREG1

P7CR

Set timer 0 and timer 1 in PPG output mode and selectsφT1 as the input clock.

Enable TFF1 inversion and sets TFF1 to “1”.

Set the duty of TO1 to TREG0.

x

0

*

0

*

1

*

Set the cycle of TO1 to TREG1.

–

1

–

*

–

1

–

*

–

0

–

*

–

1

0

*

–

0

*

1

0

*

Assign P70 as TO1.

P6CRL

PG01CR

PG0REG

TRUN

Assign P60 ~ 63 as PG0.

Set PG0 in 4-phase 1-step excitation mode.

Set an initial value.

1

–

1

Start timer 0 and timer 1.

Note: x; don’t care

–; no change

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3.10 Serial Channel

The TMP96C031F contains 2 serial I/O channels for full duplex

asynchronous transmission (UART) as well as for I/O exten-

sion.

The serial channel has the following operation modes.

● I/O interface mode

Mode 0: To transmit and receive I/O data as well as

the synchronizing signal SCLK for extending I/O.

(channel 1 only)

Mode 1: 7-bit data

Mode 2: 8-bit data

Mode 3: 9-bit data

● Asynchronous transmission

(UART) mode (channel 0 and 1)

In mode 1 and mode 2, a parity bit can be added. Mode

3 has wake-up function for making the master controller start

slave controllers in serial link (multi-controller system).

Figure 3.10 (1) shows the data format (for one frame) in

each mode.

Figure 3.10 (1). Data Formats

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detected to be normal at least twice in three samplings.

When the transmission buffer becomes empty and

requests the CPU to send the next transmission data, or when

data is stored in the receiving data register and the CPU is

requested to read the data, INTTX or INTRX interrupt occurs.

Besides, if an overrun error, parity error, or framing error occurs

during receiving operation, ﬂag SC0CR/SC1CR <OERR,

PERR, FERR> will be set.

The serial channel 0/1 includes a special baud rate gen-

erator, which can set any baud rate by dividing the frequency

of four clocks (φT0, φT2, φT8, and φT32) from the internal pres-

caler (shared by 8-bit/16-bit timer) by the value 2 to 16.

In I/O interface mode, it is possible to input synchronous

signals as well as to transmit or receive data by external clock.

The serial channel has a buffer register for transmitting

and receiving operations, in order to temporarily store trans-

mitted or received data, so that transmitting and receiving

operations can be done independently (full duplex).

However, in I/O interface mode, SCLK (serial clock) pin is

used for both transmission and receiving, the channel

becomes half-duplex.

The receiving data register is of a double buffer structure

to prevent the occurrence of overrun error and provides one

frame of margin before CPU reads the received data. The

receiving data register stores the already received data while

the buffer register receives the next frame data.

By using CTS and RTS (there is no RTS pin, so any one

port must be controlled by software), it is possible to halt data

send until CPU ﬁnishes reading receive data every time a frame

is received (Handshake function).

3.10.1 Control Registers

In the UART mode, a check function is added not to start

the receiving operation by error start bits due to noise. The

channel starts receiving data only when the start bit is

The serial channel is controlled by three control registers

SC0CR, SC0MOD, and BR0CR. Transmitted and received

data is stored in register SC0BUF.

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Figure 3.10 (2). Serial Mode Control Register (Channel 0, SC0MOD)

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Figure 3.10 (3). Serial Control Register (Channel, SC0CR)

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Note:

Figure 3.10 (4). Serial Channel Control (Channel 0, BR0CR)

7

6

5

4

3

2

1

0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0

(Transmission)

(Receiving)

SC0BUF

(50H)

7

6

5

4

3

2

1

0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

Figure 3.10 (5). Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF)

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Figure 3.10 (6). Serial Mode Control Register (Channel 1, SC1MOD)

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Figure 3.10 (7). Serial Control Register (Channel 1, SC1CR)

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Figure 3.10 (8). Baud Rate Generator Control Register (Channel 0, BR0CR)

7

6

5

4

3

2

1

0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0 (Transmission)

SC1BUF

(0054H)

7

6

5

4

3

2

1

0

(Receiving)

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

Figure 3.10 (9). Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)

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Figure 3.10 (10). Port 6, 7 Control Registers

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Port 3.10 (11). Serial Open Drain Enable Register (ODE)

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3.10.2 Conﬁguration

Figure 3.10 (12) shows the block diagram of the serial channel 0.

Figure 3.10 (12). Block Diagram of the Serial Channel 0

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Figure 3.10 (13) shows the block diagram of the serial

channel 1.

÷ 16

Figure 3.10 (13). Block Diagram of the Serial Channel 1

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➀ Baud Rate Generator

One of these input clocks is selected by the baud rate

generator control register BR0CR/BR1CR <BR0CK1,

0/BR1CK1, 0>.

The baud rate generator includes a 4-bit frequency

divider, which divides frequency by 2 to 16 values to

determine the transfer rate.

Baud rate generator comprises a circuit that generates

transmission and receiving clocks to determine the

transfer rate of the serial channel.

The input clock to the baud rate generator, φT0 (fc/4),

φT2 (fc/16), φT8 (fc/64), or φT32 (fc/256) is generated

by the 9-bit prescaler which is shared by the timers.

How to calculate a transfer rate when the baud rate

generator is used is explained below.

● UART mode

Transfer rate =

Input clock of baud rate generator

Frequency divisor of baud rate generator

● I/O interface mode

Transfer rate =

Input clock of baud rate generator

Frequency divisor of baud rate generator

The relation between the input clock and the source clock (fc) is as follows:

φT0 = fc/4

φT2 = fc/16

φT8 = fc/64

φT32 = fc/256

Accordingly, when source clock fc is 12.288MHz, input clock is φT2 (fc/16), and frequency divisor is 5, the transfer rate in

UART mode becomes as follows:

Transfer rate =

fc/16

5

6

= 12.288 x 10 /16/5/16 = 9600 (bps)

Table 3.10 (1) shows an example of the transfer rate in UART mode.

Also with 8-bit timer 0, the serial channel can get a transfer rate. Table 3.10 (2) shows an example of baud rate using

timer 0.

Table 3.10 (1) Selection of Transfer Rate (1) (When Baud Rate Generator is Used)

Unit (Kbps)

Input Clock

φT0

φT2

φT8

φT32

fc [MHz]

Frequency

Divisor

(fc/4)

(fc/16)

(fc/64)

(fc/256)

9.830400

2

4

8

0

5

A

3

6

C

76.800

38.400

19.200

9.600

19.200

9.600

4.800

2.400

9.600

4.800

19.200

9.600

4.800

2.400

1.200

0.600

2.400

1.200

4.800

2.400

1.200

0.600

0.300

0.150

0.600

0.300

1.200

0.600

0.300

↑

12.288000

38.400

19.200

76.800

38.400

19.200

↑

14.745600

↑

Note: Transfer rate in I/O interface mode is 8 times as fast as the values given in the above table.

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Table 3.10 (2) Selection of Transfer Rate (1) (When Timer 0 (Input Clock φT1) is Used)

Unit (Kbps)

fc

12.288MHz

12MHz

9.8304MHz

8MHz

6.144MHz

TREG0

1H

2H

96

48

32

24

19.2

12

9.6

6

76.8

38.4

62.5

48

24

16

12

9.6

6

31.25

3H

31.25

4H

19.2

9.6

5H

8H

AH

10H

14H

4.8

3

4.8

2.4

How to calculate the transfer rate (when timer 0 is used):

Transfer rate =

fc

TREG0 x 8 x 16

↑

(When timer 0 (input clock φT1) is used)

Input clock of timer 0

fc

φT1 =

/8

fc

φT4 = /32

φT16 = /128

fc

Note: Timer 0 match detect signal cannot be used as the transfer clock in I/O interface mode.

➁ Serial Clock Generation Circuit

According to the setting of SC0CR and SC1CR

<SC1, 0>, the above baud rate generator clock, internal

clock φ1 (500Kbps @ fc = 16 MHz), or the match detect

signal from timer 0 will be selected to generate the basic

clock SIOCLK.

This circuit generates the basic clock for transmitting

and receiving data.

• I/O interface mode (channel 1 only)

➂ Receiving Counter

When in SCLK output mode with the setting of

SC1CR <IOC> = “0", the basic clock will be generated

by dividing by 2 the output of the baud rate generator as

described before. When in SCLK input mode with the

setting of SC1CR <IOC> = “1", the rising edge or falling

edge will be detected according to the setting of SC1CR

<SCLKC> register to generate the basic clock.

The receiving counter is a 4-bit binary counter used

in asynchronous communication (UART) mode and

counts up by SIOCLK clock. 16 pulses of SIOCLK are

used for receiving one bit of data, and the data bit is

sampled three times at 7th, 8th and 9th clock.

With the three samples, the received data is evalu-

ated by the rule of majority.

• Asynchronous Communication (UART) mode

For example, if the sampled data bit is “1", “0” and

“1” at 7th, 8th and 9th clock respectively, the received

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data is evaluated as “1”. The sampled data “0", “0” and

Received data is stored one bit by one bit in the

receiving buffer 1 (shift register type). When 7 bits or 8

bits of data are stored in the receiving buffer 1, the stored

data is transferred to another receiving buffer 2

(SC0BUF/SC1BUF), generating an interrupt INTRX0/

INTRX1. The CPU reads only receiving buffer 2

(SC0BUF/SC1BUF). Even before the CPU reads the

receiving buffer 2 (SC0BUF/SC1BUF), the received data

can be stored in the receiving buffer 1. However, unless

the receiving buffer 2 (SC0BUF/SC1BUF) is read before

all bits of the next data are received by the receiving

buffer 1, an overrun error occurs. If an overrun error

occurs, the contents of the receiving buffer 1 will be lost,

although the contents of the receiving buffer 2 and

SC0CR <RB8> SC1CR <RB8> are still preserved.

The parity bit added in 8-bit UART mode and the

most signiﬁcant bit (MSB) in 9-bit UART mode are stored

in SC0CR <RB8>/SC1CR <RB8>.

“1” is evaluated that the received data is “0”.

➃ Receiving Control

• I/O interface mode (channel 1 only)

When in SCLK1 output mode with the setting of

SC1CR <IOC> = “0", RxD1 signal will be sampled at the

rising edge of shift clock which is output to SCLK pin.

When in SCLK input mode with the setting SC1CR

<IOC> = “1", RxD1 signal will be sampled at the rising

edge or falling edge of SCLK input according to the set-

ting of SC1CR <SCLKS> register.

• Asynchronous Communication (UART) mode

When in 9-bit UART mode, the wake-up function of

the slave controllers is enabled by setting SC0MOD

<WU>/SC1MOD <WU> to “1", and interrupt INTRX0/

INTRX1 occurs only when SC0CR <RB8>/SC1CR

<RB8> is set to “1”.

The receiving control has a circuit for detecting the

start bit by the rule of majority. When two or more “0” are

detected during 3 samples, it is recognized as start bit

and the receiving operation is started.

Data being received is also evaluated by the rule of

majority.

➅ Transmission Counter

➄ Receiving Buffer

Transmission counter is a 4-bit binary counter which

is used in asynchronous communication (UART) mode

and, like a receiving counter, counts by SIOCLK clock,

generating TxDCLK every 16 clock pulses.

To prevent overrun error, the receiving buffer has a

double buffer structure.

Figure 3.10 (14). Generation of Transmission Clock

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➆ Transmission Controller

edge of the next TxDCLK, generating a transmission shift

clock TxDSFT.

• I/O interface mode (channel 1 only)

Handshake function

In SCLK output mode with the setting of SC1CR

<IOC> = “0", the data in the transmission buffer are out-

put bit by bit to TxD1 pin at the rising edge of shift clock

which is output from SCLK1 pin.

Serial channel 0 has a CTS0 pin. Using this pin, data

can be sent in units of one frame; thus, overrun errors

can be avoided. The handshake function is enabled/dis-

abled by SC0MOD <CTSE>.

In SCLK input mode with the setting SC1CR <IOC>

= “1", the data in the transmission buffer are output bit by

bit to TxD1 pin at the rising edge or falling edge of SCLK

input according to the setting of SC1CR <SCLKC> regis-

ter.

When the CTS0 pin goes high, after completion of

the current data send, data send is halted until the CTS0

pin goes low again. The INTTX0 Interrupts are generated,

requests the next send data to the CPU.

Though there is no RTS pin, a handshake function

can be easily conﬁgured by setting any port assigned to

the RTS function. The RTS should be output “High” to

request data send halt after data receive is completed by

a software in the RXD interrupt routine.

• Asynchronous Communication (UART) mode

When transmission data is written in the transmission

buffer sent from the CPU, transmission starts at the rising

Figure 3.10 (15). Handshake Function

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Figure 3.10 (16). Timing of CTS (Clear to Send)

➇ Transmission Buffer

pared with SC0BUF <RB7>/SC1BUF <RB7> when in 7-

bit UART mode and with SC0MOD <RB8>/SC1MOD

<RB8> when in 8-bit UART mode. If they are not equal, a

parity error occurs, and SC0CR <PERR>/SC1CR

<PERR> ﬂag is set

Transmission buffer (SC0BUF/SC1BUF) shifts to and

sends the transmission data written from the CPU from

the least signiﬁcant bit (LSB) in order, using transmission

shift clock TxDSFT which is generated by the transmis-

sion control. When all bits are shifted out, the transmis-

sion buffer becomes empty and generates INTTX0/

INTTX1 interrupt.

➉ Error Flag

Three error ﬂags are provided to increase the reliabil-

ity of receiving data.

➈ Parity Control Circuit

1. Overrun error <OERR>

When serial channel control register SC0CR <PE>/

SC1CR <PE> is set to “1", it is possible to transmit and

receive data with parity. However, parity can be added

only in 7-bit UART or 8-bit UART mode. With SC0CR

<EVEN>/SC1CR <EVEN> register, even (odd) parity can

be selected.

If all bits of the next data are received in receiving

buffer 1 while valid data is stored in receiving buffer 2

(SCBUF), an overrun error will occur.

2. Parity error <PERR>

For transmission, parity is automatically generated

according to the data written in the transmission buffer

SCBUF, and data are transmitted after being stored in

SC0BUF <TB7>/SC1BUF <TB7> when in 7-bit UART

mode while in SCMOD <TB8>/SCMOD <TB8> when in

8-bit UART mode. <PE> and <EVEN> must be set

before transmission data are written in the transmission

buffer.

The parity generated for the data shifted in receiving

buffer 2 (SCBUF) is compared with the parity bit received

from RxD pin. If they are not equal, a parity error occurs.

3. Framing error <FERR>

The stop bit of received data is sampled three times

around the center. If the majority is “0", a framing error

occurs.

For receiving, data is shifted in the receiving buffer 1,

and parity is added after the data is transferred in the

receiving buffer 2 (SC0BUF/SC1BUF), and then com-

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11

Generating Timing

1) UART mode

Receiving

Mode

9-Bit

8-Bit + Parity

8-Bit, 7-Bit + Parity, 7-Bit

Interrupt timing

Center of last bit (Bit 8)

Center of stop bit

Center of last bit (parity bit)

Center of stop bit

Framing error timing

Parity error timing

Overrun error timing

Center of last bit (Bit 8)

Center of last bit (parity bit)

Transmitting

Mode

9-Bit

8-Bit + Parity

8-Bit, 7-Bit + Parity, 7-Bit

Interrupt timing

Just before last bit is transmitted.

←

2) I/O Interface mode

SCLK output mode

Immediately after rise of last SCLK signal. (See ﬁgure 3.10 (19) .)

Transmission interrupt tim-

ing

Immediately after rise of last SCLK signal (rising mode), or immediately after fall in

falling mode. (See ﬁgure 3.10 (20))

SCLK input mode

SCLK output mode

SCLK input mode

Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is,

immediately after last SCLK. (See ﬁgure 3.10 (21))

Receiving interrupt timing

Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is,

immediately after SCLK. (See ﬁgure 3.10 (22))

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3.10.3 Operational Description

for transmitting or receiving data to or from the external

shifter register.

(1)

Mode 0 (I/O interface mode)

This mode includes SCLK output mode to output syn-

chronous clock SCLK and SCLK input mode to input

external synchronous clock SCLK.

This mode is used to increase the number of I/O pins

Figure 3.10 (17). Example of SCLK Output Mode Connection

FIgure 3.10 (18). Example of SCLK Input Mode Connection

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➀ Transmission

time the CPU writes data in the transmission buffer. When

all data is output, INTES1 <ITX1C> will be set to generate

INTTX1 interrupt.

In SCLK output mode, 8-bit data and synchronous clock

are output from TxD pin and SCLK pin, respectively, each

Figure 3.10 (19). Transmitting Operation in I/O Interface Mode (SCLK Output Mode)

In SCLK output mode, 8-bit data are output from TxD1

pin when SCLK input becomes active while data are

written in the transmission buffer by CPU.

When all data are output, INTES1 <ITXIC> will be set

to generate INTTX1 interrupt.

Figure 3.10 (20). Transmitting Operation in I/O Interface Mode (SCLK Input Mode)

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➁ Receiving

<IRX1C> is cleared by reading the received data.

When 8-bit data are received, the data will be trans-

ferred in the receiving buffer 2 (SC1BUF) at the timing

shown below, and INTES1 <IRX1C> will be set again

to generate INTRX1 interrupt.

In SCLK output mode, synchronous clock is output

from SCLK pin and the data is shifted in the receiving

buffer 1 whenever the receive interrupt ﬂag INTES1

Figure 3.10 (21). Receiving Operation in I/O Interface Mode (SCLK Output Mode)

In SCLK input mode, the data is shifted in the receiving

buffer 1 when SCLK input becomes active, while the

receive interrupt ﬂag INTES1 <IRX1C> is cleared by read-

ing the received data. When 8-bit data is received, the

data will be shifted in the receiving buffer 2 (SC1BUF) at

the timing shown below, and INTES1 <IRX1C> will be set

again to generate INTRX interrupt.

Figure 3.10 (22). Receiving Operation in I/O Interface Mode (SCLK Input Mode)

Note: For data receiving, the system must be placed in the receive enable state (SCMOD <RXE> = “1”)

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(2)

Mode 1 (7-bit UART Mode)

and even parity or odd parity is selected by SC0CR

<EVEN>/SC1CR <EVEN> when <PE> is set to “1”

(enable).

The 7-bit mode can be set by setting serial channel

mode register SC0MOD <SM1, 0> /SC1MOD <SM1,

0> to “01”.

In this mode, a parity bit can be added, and the addi-

tion of a parity bit can be enabled or disabled by serial

channel control register SC0CR <PE>/SC1CR <PE>,

Setting example: When transmitting data with the fol-

lowing format, the control registers

should be set as described below.

Channel 0 is explained here.

7

–

x

0

x

1

*

6

–

0

1

x

5

–

1

0

*

4

–

x

3

–

0

x

2

–

1

x

1

0

–

*

0

1

0

1

–

*

P9CRL

SC0MOD

SC0CR

BR0CR

TRUN

←

Select P60 as the TxD pin.

Set 7-bit UART mode.

x

Add an even parity.

0

–

0

*

0

–

*

1

–

*

Set transfer rate at 2400 bps.

Start the prescaler for the baud rate generator.

Enable INTTX0 interrupt and sets interrupt level 4.

Set data for transmission.

x

INTES0

SC0BUF

1

*

Note: x; don’t care –; no change

SC1CR <PE>, and even parity or odd parity is selected

by SC0CR <EVEN>/SC1CR <EVEN> when <PE> is

set to “1” (enable).

(3)

Mode 2 (8-bit UART Mode)

The 8-bit UART mode can be speciﬁed by setting

SC0MOD <SM1, 0> / SC1MOD <SM1, 0> to “10”. In

this mode, parity bit can be added, the addition of a

parity bit is enabled or disabled by SC0CR <PE>/

Setting example: When receiving data with the follow-

ing format, the control register

should be set as described below.

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Main setting

7

–

x

6

–

0

x

5

–

1

0

1

–

4

–

x

3

0

1

x

2

0

x

1

–

0

–

0

–

1

0

1

–

0

P9CRL

SC0MOD

SC0CR

BR0CR

TRUN

←

Select P61 (RxD) as the input pin.

Enable receiving in 8-bit UART mode.

Add an odd parity.

x

0

x

1

–

0

–

1

–

1

Set transfer rate at 9600 bps.

x

Start the prescaler for the baud rate generator.

Enable INTTX0 interrupt and sets interrupt level 4.

INTES0

–

Interrupt processing

Acc ← SC0CR and 00011100

if Acc ≠ 0 then ERROR

Acc ← SC0BUF

Check for error.

)

Read the received data.

Note:

x; don’t care

–; no change

(4)

Mode 3 (9-bit UART Mode)

Wake-up function

In 9-bit UART mode, the wake-up function of slave

controllers is enabled by setting SC0MOD <WU> /

SC1MOD <WU> to “1”. The interrupt INTRX1/INTRX0

occurs only when <RB8> = 1

9-bit UART mode can be speciﬁed by setting

SC0MOD <SM1, 0> /SC1MOD <SM1, 0> to “11”. In

this mode, parity bit cannot be added

For transmission, the MSB (9th bit) is written in SCM0D

<TB8>, while in receiving it is stored in SCCR <RB8>.

For writing and reading the buffer, the MSB is read or

written ﬁrst, then SC0BUF/SC1BUF.

.

Figure 3.10 (23). Serial Link Using Wake-Up Function

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➂ The master controller transmits one-frame data

Protocol

➀ Select the 9-bit UART mode for master and slave

including the 8-bit select code for the slave control-

lers. The MSB (bit 8) <TB8> is set to “1”.

controllers.

➁ Set SC0MOD <WU>/SC1MOD <WU> bit of each

slave controller to “1” to enable data receiving.

➃ Each slave controller receives the above frame, and

clears WU bit to “0” if the above select code matches

its own select code.

➄ The master controller transmits data to the specified

slave controller whose SC0MOD <WU> / SC1MOD

<WU> bit is cleared to “0.” The MSB (bit 8) <TB8> is

cleared to “0”.

➅ The other slave controllers (with the <WU> bit remain-

ing at “1”) ignore the receiving data because their

MSBs (bit 8 or <RB8>) are set to “0” to disable the

interrupt INTRX0/INTRX1.

The slave controllers (WU = 0) can transmit data

to the master controller, and it is possible to indicate

the end of data receiving to the master controller by

this transmission.

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the internal clock φ1 (fc/2) as the transfer clock.

Setting Example:

To link two slave controllers serially

with the master controller, and use

Since serial channels 0 and 1 operate in exactly the

same

way, channel 0 is used for the purposes of explanation.

• Setting the master controller

Main setting

P6CRL

INTES0

←

–

1

–

1

–

0

–

0

1

0

1

0

1

Select P60 as TxD pin and P61 as RxD pin.

Enable INTTX0 and sets the interrupt level 4.

Enable INTRX0 and sets the interrupt level 5.

Set φ1 (fc/2) as the transmission clock in 9-bit UART mode.

Set the select code for slave controller 1.

SC0MOD

SC0BUF

←

1

0

1

0

1

0

1

0

1

0

1

INTTX0 interrupt

SC0MOD

SC0BUF

←

–

*

0

*

–

*

–

*

–

*

–

*

–

*

–

*

Set TB8 to “0”.

Set data for transmission.

• Setting the slave controller 2

Main setting

P6CRL

ODE

←

x

1

0

x

1

0

–

x

–

x

–

x

–

x

0

–

1

0

Select P61 as RxD pin and P60 as TxD pin.

Enable INTRX0 and INTTX0.

INTES0

SC0MOD

0

1

Set <WU> to “1” in the 9-bit UART transmission mode with transfer

clock φ1 (fc/2).

INTRX0 interrupt

Acc ← SC0BUF

If Acc = Select Code

Then SC0MOD4

←

–

0

–

Clear <WU> to “0”.

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Figure 3.11 (1) shows the block diagram of the A/D con-

verter. The 4-channel analog input pins (AN3 to AN0) are

shared by input-only P5 and so can be used as input port.

3.11 Analog/Digital Converter

The TMP96C031F contains a high-speed analog/digital con-

verter (A/D converter) with 4-channel analog input that features

10-bit successive approximation.

Figure 3.11 (1). Block Diagram of A/D Converter

Note1: This A/D converter does not have a built-in sample and hold circuit. Therefore, when A/D converting high-frequency signals, connect a sample and

hold circuit externally.

Note2: The lower the power supply current in IDLE or STOP mode, depending on the timing, standby mode can be entered with the internal comparator in

enable state. Thus, stop A/D conversion before executing the HALT instruction.

The ladder resistor between VREF- GND cannot be disconnected internally. Therefore, IREF will ﬂow regardless of the mode.

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3.11.1 Control Register

Figure 3.11 (2). A/D Converter Mode Register (ADMOD)

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Figure 3.11 (3). Register for Saving an A/D Switch Value (ADREG0 ~ 3)

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3.11.1 Operation

(5)

(6)

A/D Conversion Speed Selection

(1)

Analog Reference Voltage

There are two A/D conversion speed modes: high

speed mode and low speed mode. The selection is

executed by ADMOD <ADCS> register.

When reset, ADMOD <ADCS> will be initialized to “0,”

so that high speed conversion mode will be selected.

High analog reference voltage is applied to the VREF

pin.

The reference voltage between VREG and AGND is

divided by 256 using ladder resistance, and compared

with the analog input voltage for A/D conversion.

A/D Conversion End and Interrupt

• A/D conversion single mode

(2)

Analog Input Channels

Analog input channel is selected by ADMOD <ADCH1,

0>. However, in ﬁxed analog input mode, one channel

is selected by ADMOD <ADCH1, 0> among four pins:

AN0 to AN3.

In analog input channel scan mode, the number of

channels to be scanned from AN0 is speciﬁed by

ADMOD <ADCH1, 0>, such as AN0 → AN1, AN0 →

AN1 → AN2, and AN0 → AN1 → AN2 → AN3.

When reset, A/D conversion channel register will be ini-

tialized to ADMOD <ADCH1, 0> = 00, so that AN0 pin

will be selected.

The pins which are not used as analog input channel

can be used as ordinary input port P5.

ADMOD <EOCF> for A/D conversion end will be set to

“1,” ADMOD <ADBF> ﬂag will be reset to “0,” and

INTAD interrupt will be enabled when A/D conversion

of speciﬁed channel ends in ﬁxed conversion channel

mode or when A/D conversion of the last channel ends

in channel scan mode.

(7)

(8)

Storing the A/D Conversion Result

The results of A/D conversion are stored in ADREG0 to

ADREG3 registers for each channel. In repeat mode,

the registers are updated whenever conversion ends.

ADREG0 to ADREG3 are read-only registers.

(3)

(4)

Starting A/D Conversion

Reading the A/D Conversion Result

A/D conversion starts when A/D conversion register

ADMOD <ADS> is written “1". When A/D conversion

starts, A/D conversion busy ﬂag ADMOD <ADBF>

which indicates “A/D conversion is in progress” will be

set to “1".

The results of A/D conversion are stored in ADREG0 to

ADREG3 registers. When the contents of one of

ADREG0 to ADREG3 registers are read, ADMOD

<EOCF> will be cleared to “0".

Setting example: ➀ When the analog input volt-

age of the AN3 pin is A/D

A/D Conversion Mode

converted and the result is

stored in the memory

address FF10H by A/D

Both ﬁxed A/D conversion channel mode and A/D con-

version channel scan mode have two conversion

modes, i.e., single and repeat conversion modes.

interrupt INTAD routine.

In ﬁxed channel repeat mode, conversion of speciﬁed

one channel is executed repeatedly.

…

In scan repeat mode, scanning from AN0, → AN3 is

executed repeatedly.

A/D conversion mode is selected by ADMOD <REPET,

SCAN>.

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Main setting

INTE0AD

ADMOD

←

1

x

1

x

0

x

Enable INTAD and sets interrupt level 4.

Specify AN3 pin as an analog input channel and starts

A/D conversion in high speed mode.

0

1

INTAD routine

A

←

ADREG3

A

The value of ADREG3 is read into the accumulator. Then the accumulator

value is stored into memory at FF10H.

(FF10H)

Setting example: ➁ When the analog pin voltage of

AN0 ~ AN2 pin is A/D converted in

high speed conversion channel scan repeat

mode.

INTE0AD

ADMOD

←

1

x

0

x

0

1

x

Disable INTAD.

1

0

1

0

Start the A/D conversion of analog input channels AN0 ~ AN2

in the high-speed scan repeat mode.

Note:

x; don’t care –; no change

3.12 Watchdog Timer (Runaway Detecting Timer)

The TMP96C031F is containing watchdog timer of Runaway

detecting.

The watchdog timer (WDT) is used to return the CPU to

the normal state when it detects that the CPU has started to

malfunction (runaway) due to causes such as noise. When the

watchdog timer detects a malfunction, it generates a non-

maskable interrupt to notify the CPU of the malfunction, and

outputs 0 externally from watchdog timer out pin WDTOUT to

notify the peripheral devices of the malfunction.

Connecting the watchdog timer output to the reset pin

internally forces a reset.

A built-in function is used to stop the WDT count at bus

release request (BUSRQ).

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3.12.1 Conﬁguration

Figure 3.12 (1) shows the block diagram of the watchdog timer (WDT).

Figure 3.12 (1). Block Diagram of Watchdog Timer

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The watchdog timer is a 22-stage binary counter which

LD

(WDCR), 4EH

; writes clear code

; enables watchdog

timer again.

uses φ (fc/2) as the input clock. There are four outputs from the

SET 7, (WDMOD)

16

18

20

22

binary counter: 2 /fc, 2 /fc, 2 /fc, and 2 /fc. Selecting one

of the outputs with the WDMOD register generates a watch-

dog interrupt, and outputs watchdog timer out when an over-

ﬂow occurs.

In other words, the WDTOUT keeps outputting “0” until

the clear code is written.

Since the watchdog timer out pin (WDTOUT) outputs “0”

due to a watchdog timer overﬂow, the peripheral devices can

be reset.

Clearing the watchdog timer (by writing the clear code

(4EH) to the WDCR) after disabling it sets 0 to output to 1 (Pro-

gram example).

The watchdog timer out pin can also be connected to the

reset pin internally. In this case, the watchdog timer out pin

(WDTOUT) outputs 0 at 8 to 20 states (800ns to 2.0µs @

20MHz) and resets itself.

The WDTOUT (also used as P67) is multiplexed with pin

PG13; setting must be done using the port 6 control register,

P6CRH (WDTOUT pin is set after reset).

LDW (WDMOD), 0B100H

; disables

watchdog timer

Figure 3.12 (2). Normal Mode

Figure 3.12 (3). Reset Mode

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3.12.2 Control Registers

Watchdog timer WDT is controlled by two control registers

WDMOD and WDCR.

To disable, it is necessary to clear this bit to “0” and

write the disable code (B1H) in the watchdog timer

control register WDCR. This makes it difﬁcult for the

watchdog timer to be disabled by runaway.

However, it is possible to return from the disable state

to enable state by merely setting <WDTE> to “1".

(1)

Watchdog Timer Mode Register (WDMOD)

➀ Setting the detecting time of watchdog timer

➂ Watchdog timer out reset connection <RESCR>

<WDTP>

This register is used to connect the output of the

watchdog timer with RESET terminal, internally. Since

WDMOD <RESCR> is initialized to 0 at reset, a reset

by the watchdog timer will not be performed.

This 2-bit register is used to set the watchdog timer

interrupt time for detecting the runaway. This register is

initialized to WDMOD <WDTP1, 0> = 00 when reset,

16

and therefore 2 /fc is set. (The number of states is

approximately 32,768.)

(2)

Watchdog Timer Control Register (WDCR)

➁ Watchdog timer enable/disable control register

<WDTE>

This register is used to disable and clear the binary

counter of the watchdog timer function.

When reset, WDMOD <WDTE> is initialized to “1”

enable the watchdog timer.

• Disable control

WDMOD

WDCR

←

0

1

–

0

–

1

–

1

–

0

–

0

x

Clear WDMOD <WDTE> to “0".

Write the disable code (B1H).

0

1

• Enable control

• Watchdog timer clear control

Set WDMOD <WDTE> to “1".

The binary counter can be cleared and resume count-

ing by writing clear code (4EH) into the WDCR register.

WDCR ← 0

1

0

1

0

Write the clear code (4EH).

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Figure 3.12 (4). Watchdog Timer Mode Register

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Figure 3.12 (5). Watchdog Timer Control Register

Figure 3.12 (6)

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ation by an anti-malfunction program. By connecting the

3.12.3 Operation

watchdog timer out pin to peripheral devices’ resets, a CPU

malfunction can also be acknowledged to other devices.

The watchdog timer restarts operation immediately after

resetting is released.

The watchdog timer stops its operation in the IDLE and

STOP modes. In the RUN mode, the watchdog timer is

enabled.

The watchdog timer generates interrupt INTWD after the

detecting time set in the WDMOD <WDTP1, 0> register and

outputs a low level signal. The watchdog timer must be zero-

cleared by software before an INTWD interrupt is generated. If

the CPU malfunctions (runaway) due to causes such as noise,

but does not execute the instruction used to clear the binary

counter, the binary counter overﬂows and an INTWD interrupt

is generated. The CPU detects malfunction (runaway) due to

the INTWD Interrupt and it is possible to return to normal oper-

However, the function can be disabled when entering the

RUN mode.

Example:

➀ Clear the binary counter

WDCR

←

0

1

0

1

0

Write clear code (4EH).

18

➁ Set the watchdog timer detecting time to 2 /fc

WDMOD

←

1

0

1

–

x

➂ Disable the watchdog timer

WDMOD

WDCR

←

0

1

–

0

–

1

–

1

–

0

–

0

x

Clear WDTE to “0".

0

1

Write disable code (B1H).

➃ Set IDLE mode

WDMOD

WDCR

←

0

1

–

0

–

1

–

1

0

x

Disables WDT and sets IDLE mode.

Set the standby mode

0

1

Executes HALT command

16

➄ Set the STOP mode (warming up time: 2 /fc)

WDMOD

Executes HALT command

←

–

1

0

1

x

Set the STOP mode.

Execute HALT instruction. Set the standby mode.

2) Writing 1 to the P4FC <BUSWDT> register halts count by

the WDT binary counter at bus release due to the bus

request signal, BUSRQ.

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3.13 Dynamic RAM (DRAM Controller

The TMP96C031F consists of a control circuit to refresh

DRAM, an access circuit to perform read/write, and an

address decoder.

Figure 3.13 (1) shows a block diagram of the DRAM controller.

Figure 3.13 (1). DRAM Controller

3.13.1 Control Register

Figure 3.13 (2). Chip Select Wait Control Register (B3CS)

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Figure 3.13 (3). Port 4 Function Register

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Figure 3.13 (4). Refresh Control Register

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3.13.2 Operation Description

accessed.

In addition, a DMUX signal is output for row address/

column address switching.

(1)

Read/Write Control

Figure 3.13 (6) shows the RAS, CAS, and DMUX out-

put timing diagram during memory access cycle.

The read/write controller outputs valid signals RAS and

CAS to DRAM when address space speciﬁed by the

internal address decoder (chip select 2 CS3/CAS) is

Figure 3.13 (5). Memory Access Cycle Timing

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How to set the registers is described next.

Figure 3.13 (2) shoes the structure of the chip select

wait control register B3CS. B3CS <B3E> can be used to

control the output of CS3/CAS and B3CS <B3CAS> can

be used to control CAS selection.

➀ Setting the RAS, CAS, DMUX, and RFSH output

Figure 3.13 (6). Relationship Between Address Decoder and DRAM Controller

The RAS, CAS, DMUX, and RFSH signals must be

set with the corresponding port control register because

they are multiplexed with P35, P43, P71, and P63

respectively.

➁ Inserting WAIT

WAIT insertion during read/write control can be set

with the register B3CS <B3W1, 0>.

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(2)

Refresh Controller

• Refresh cycle is asynchronous with CPU operation

cycle.

The TMP96C031F can output RAS/CAS used to

refresh in DRAM. At the same time the state signal

RFSH which indicates a refresh cycle is output.

i) CAS before RAS interval refresh mode

DRAM can be refreshed easily because RAS/CAS out-

put frequency and pulse width are programmable.

The refresh controller has the following features.

The refresh interval and refresh width for CAS before

RAS interval refresh mode depends on the DRAM

being used.

Therefore, TMP96C031F enables the CAS before RAS

output to be set with the refresh controller register

value according to the system clock and DRAM that

are being used.

Figure 3.13 (2) shows a timing example for CAS before

RAS refresh cycle.

• Refresh mode: CAS before RAS interval refresh

mode

CAS before RAS self refresh mode

• Refresh interval: 15 to 154 states (programmable)

• Refresh cycle width: 2 to 9 states (programmable)

• Dummy cycle can be generated

Figure 3.13 (7). Refresh Cycle Timing Example

How to set the register is described next.

Figure 3.13 (4) shows the bit structure of the refresh con-

The insertion interval is set with the three bits DREFCR

<RS2 to 0> according to the system clock being used.

trol register DREFCR.

➀ Refresh cycle insertion interval

Example: When the system clock is 20MHz and the

DRAM refresh cycle is to be 16µs, set these

bits to “111”.

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Table 3.13 Refresh Cycle Insertion Interval

➁ The three bits DREFCR <RW2 to 0> can used to

change the refresh cycle width (RAS, CAS output). (2

to 9 states)

This mode is used when CPU or DRAM control is

halted with a HALT (IDEL, STOP) instruction while

refreshing with CAS before RAS interval refresh mode

(hereafter referred to as interval mode).

➂Refresh cycle control

However, RFSH is not output. (“1” is output.).

The refresh cycle can be disabled/enable with the bit

DREFCR <RC>.

Figure 3.13 (8) shows the self refresh mode timing dia-

gram.

ii) CAS before RAS self refresh mode

Figure 3.13 (8). Self Refresh Cycle Timing

This mode is executed as follows. First, the settings are

made for normal interval mode Then, B3CS <SRFC> is

set to “0” just before a HALT instruction to perform one

normal refresh. Then, the CAS pin and RAS pin are

kept at low level and self refresh mode is entered. Set

B3CS <SRFC> to “1” to cancel this mode and return

to normal CAS before RAS refresh mode. (The ﬁrst

CAS before RAS refresh is performed immediately after

cancellation because the refresh counter is cleared.)

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(3)

DRAM initialize

to “1” and cancelled by setting it to “0”. (The <RC> bit

need not be changed.)

The dummy cycle width is ﬁxed to 4 states.

Figure 3.13 (9) shows the CAS before RAS dummy

cycle timing.

The DRAM controller can generate consecutive CAS

before RAS dummy cycles necessary when using

DRAM. This is executed by setting DREFCR <DMI> bit

Figure 3.13 (9). CAS before RAS Dummy Cycle Timing (Fixed to 4 states)

3.13.4 Priority

the cycle that starts operation ﬁrst. If the priority is given to the

refresh cycle, a wait is automatically inserted in the memory

access cycle. Figure 3.13 (8) shows the timing in this case.

The DRAM refresh cycle may overlap with the DRAM read/

write cycle because it is not synchronized with the CPU oper-

ating cycle. In this case, the DRAM controller gives priority to

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Figure 3.13 (101). Timing Diagram when Refresh Cycle is Inserted in Memory Access Cycle

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3.13.4 Connection Example

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4. Electrical Characteristics

4.1 Absolute Maximum (TMP96C031F)

Symbol

Parameter

Power Supply Voltage

Rating

Unit

V

-0.5 ~ 6.5

V

cc

V IN

Σ IOL

Input Voltage

-0.5 ~ V + 0.5

V

cc

Output Current (total)

100

-100

mA

mW

°C

Σ IOH

PD

°

Power Dissipation (Ta = 70 C)

Soldering Temperature (10s)

Storage Temperature

600

T SOLDER

T STG

T OPR

260

°

-65 ~ 150

-20 ~ 70

C

°

Operating Temperature

C

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4.2 DC Characteristics (TMP96C031F)

= 5V ± 10%, Ta = -20 ~ 70 C (Typical values are for Ta = 25 C and V = 5V)

°

V

cc

Symbol

V IL

Parameter

Min

Max

Unit

Test Condition

Input Low Voltage (AD0-15)

P2, P3, P4, P5, P6, P7, P8, P9

RESET, NMI, INTO (P87)

AM8/EA

-0.3

2.2

0.8

V

V IL1

V IL2

V IL3

V IL4

V IH

0.3V

cc

0.25V

cc

0.3

0.2V

X1

cc

Input High Voltage (AD0-15)

P2, P3, P4, P5, P6, P7, P8, P9

RESET, NMI, INTO (P87)

EA

V + 0.3

cc

V IH1

V IH2

V IH3

V IH4

V OL

0.7V

V

+ 0.3

cc

0.75V

cc

V

- 0.3

cc

X1

0.8V

cc

Output Low Voltage

Output High Voltage

0.45

I OL = 1.6mA

I OH = -400µA

I OH = -100µA

I OH = - 20µA

V OH

V OH1

V OH2

2.4

0.75V

cc

0.9V

cc

Darlington Drive Current

(8 Output Pins max.)

V EXT - 1.5V

R EXT = 1.1KΩ

I DAR

-1.0

-3.5

mA

I LI

Input Leakage Current

Output Leakage Current

0.02 (Typ)

0.05 (Typ)

±5

µA 0.0 ≤ V ≤ V

in cc

I LO

±10

µA 0.2 ≤ V ≤ V - 0.2

in cc

Operating Current (RUN)

IDLE

STOP (Ta = -20 ~ 70°C)

STOP (Ta = 0 ~ 50°C)

60

10

50

10

mA tosc = 20MHz

mA

30 (Typ)

2.0 (Typ)

0.2 (Typ)

I

cc

µA 0.2 ≤ V ≤ V - 0.2

in cc

µA 0.2 ≤ V ≤ V - 0.2

in

cc

Power Down Voltage

(@STOP, RAM Back up)

V IL2 = 0.2V ,

cc

V STOP

2.0

50

6.0

V

V IH2 = 0.8V

cc

R RST

C IO

RESET Pull Up Register

Pin Capacitance

150

10

KΩ

pF tosc = 1MHz

Schmitt Width

RESET, NMI, INTO (P50)

V TH

R K

0.4

50

1.0 (Typ)

150

V

Pull Down/Up Register

KΩ

Note: I-DAR is guaranteed for a total of up to 8 ports.

TOSHIBA CORPORATION

157

TMP96C031N/F

°

4.3 AC Electrical Characteristics (TMP96C031F) V = 5V±10%, Ta = -20 ~ 70 C (4MHz ~ 20MHz)

cc

Variable

16MHz

20MHz

No.

Symbol

Parameter

Unit

Min

Max

250

Min

Max

Min

Max

1

t

Osc. Period (= x)

CLK width

50

62.5

85

50

60.0

50

ns

OSC

2

3

t

2x - 40

CLK

t

A0 - 23 Valid→CLK Hold

CLK Valid→A0 - 23 Hold

A0-15 Valid→ALE fall

0.5x - 20

1.5x - 70

0.5x - 15

x - 40

11.0

240

160

23.0

1.0

AK

4

50

KA

5

t

100

-5

AL

6

ALE fall→A0 - 15 Hold

LA

7

t

ALE High width

LL

LC

CL

8

t

ALE fall→RD/WR fall

0.5x - 30

0.5x - 20

x - 25

9

RD/WR rise→ALE rise

11.0

38.0

44.0

11.0

50

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

t

A0 - 15 Valid→RD/WR fall

A0 - 23 Valid→RD/WR fall

RD/WR rise→A0 - 23 Hold

A0 - 15 Valid→D0 - 15 input

A0 - 23 Valid→D0 - 15 input

RD fall→D0 - 15 input

250

25.0

5

ACL

ACH

t

1.5x - 50

0.5x - 20

t

CA

t

3.0x - 45

3.5x - 65

2.0x - 50

143

154

75

105

110

50

ADL

ADH

t

RD

t

RD Low width

2.0x - 40

0

85.0

0.0

60.0

0.0

RR

HR

t

RD rise→D0 - 15 Hold

t

RD rise→A0 - 15 output

WR Low width

x - 15

48.0

85.0

75.0

21.0

35.0

60.0

50.0

15.0

RAE

WW

t

2.0x - 40

2.0x - 50

0.5x - 10

t

D0 - 15 Valid→WR rise

WR rise→D0 - 15 Hold

DW

WD

t

A0 - 23 Valid→WAIT input (1WAIT + n mode)

A0 - 15 Valid→WAIT input (1WAIT + n mode)

RD/WR fall→WAIT Hold (1WAIT + n mode)

A0 - 23 Valid→PORT input

A0 - 23 Valid→PORT Hold

WR rise→PORT Valid

3.5x - 90

3.0x - 80

129

108

85

70

AEH

AWL

t

2.0x + 0

125.0

206.0

100.0

175.0

CW

t

2.5x - 120

200

36

5

APH

t

2.5x + 50

APH2

t

200

CP

AC Measuring Conditions

• Output Level:

High 2.2V

/Low 0.8V, CL50pF

(However CL = 100pF for AD0 ~ AD15, AD0 ~ AD23, ALE, RD, WR, HWR, CLK, CS0 ~ CS3)

• Input Level: High 2.4V /Low 0.45V (AD0 ~ AD15)

High 0.8Vcc /Low 0.2Vcc (Except for AD0 ~ AD15)

158

TOSHIBA CORPORATION

TMP96C031N/F

(1) Read Cycle

TOSHIBA CORPORATION

159

TMP96C031N/F

(2) Write Cycle

160

TOSHIBA CORPORATION

TMP96C031N/F

4.4 DRAM Control AC Characteristics (TMP96C031F)

= 5V±10% TA = -20 ~ 70°C (4MHz ~ 20MHz)

V

cc

Variable

16MHz

20MHz

No.

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

1

t

RAS cycle time

4x - 10

240

190

ns

RC

2

3

t

RAS fall → data input

CAS fall → data input

RAS high pulse width

RAS low pulse width

CAS fall → RAS rise

RAS fall → CAS rise

CAS low pulse width

RAS fall → CAS fall

CAS rise → RAS rise

RAS fall → A0 - 15 hold

2x - 20

105

38

80

25

RAC

CAC

t

1x - 25

4

t

2x - 30

95

115

38

105

84

48

44

0

70

90

25

80

65

35

25

0

RP

5

t

2x - 10

1x - 25

2x - 20

1.5x - 10

1x - 15

1.5x - 50

0

RAS

RSH

CSH

6

t

7

t

8

t

CAS

RCD

9

t

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

t

CRP

RAH

t

A

valid → RAS fall

1x - 10

1.5x - 10

2x - 50

1x - 30

1.5x - 50

2.5x - 50

1x - 30

53

84

75

33

44

106

33

21

75

64

21

125

230

0

40

65

50

20

25

75

20

15

50

45

15

100

180

0

ASRL

ASRH

0 - 15

0 - 23

t

WR fall → RAS rise

RWL

t

WR fall → CAS rise

CWL

t

Data output → CAS fall setup

CAS fall → data output hold

RAS fall → data output hold

WR fall → CAS fall setup

CAS fall → WR hold

RAS fall → DMUX fall

DMUX fall → CAS fall

RAS fall → CAS rise

RAS rise → CAS fall

CAS high pulse width

CAS fall → RAS fall

DS

t

DH

t

DHR

t

WCS

WCH

t

0.5x - 10

RDM

CDM

t

0.5x - 10

2x - 50

1.5x + 0

0.5x - 10

2000x

t

CHR*1

t

RPC*

t

CP*

t

CSR*

t

RAS low pulse width

RAS precharge time

RASS*2

t

4x - 20

0

RPS*2

CHS*2

t

CAS hold time

t

RFSH fall → CAS fall

CAS rise → RFSH rise

1x - 10

0.5x - 10

53

21

40

15

CFL*

CFH*

t

*1 CAS before RAS interval refresh mode

*2 CAS before RAS self-refresh mode

* Both refresh modes

AC Measuring Conditions

• Output Level:

(However CL = 100pF for AD0 ~ AD15, AD0 ~ AD23, RD, WR, HWR, R/W RAS)

• Input Level: High 2.4V /Low 0.45V (AD0 ~ AD15)

High 2.2V

/Low 0.8V, CL50pF

High 0.8Vcc/Low 0.2Vcc (Except for AD0 ~ AD15)

TOSHIBA CORPORATION

161

TMP96C031N/F

(1) Read/Write Access Cycle

(2) CAS before RAS Interval Refresh Cycle

(3) CAS before RAS Self-Refresh Cycle

162

TOSHIBA CORPORATION

TMP96C031N/F

4.5 A/D Conversion Characteristics (TMP96C031F)

V

= 5V±10% TA = -20 ~ 70°C

cc

Symbol

Parameter

Min

Typ

Max

Unit

V

Analog reference voltage

V - 1.5

V

REF

cc

ss

cc

A

V

GND

ss

V

Analog input voltage range

V

ss

AIN

REF

I

Analog current for analog reference voltage

Total error

0.5

1.0

1.5

mA

LSB

Error

(Quantize error of

±0.5 LSB not included)

(TA = 25°C, V = VREF = 5.0V)

CC

Total error

2.5

4.6 Serial Channel Timing - I/O Interface Mode

V

= 5V±10% TA = -20 ~ 70°C

cc

(1) SCLK Input Mode

Variable

16MHz

20MHz

Unit

Symbol

Parameter

Min

Max

Min

Max

Min

Max

t

SCLK cycle

16x

1

0.8

µs

ns

SCY

OSS

OHS

Output Data→rising edge of SCLK

SCLK rising edge→output data hold

SCLK rising edge→input data hold

SCLK rising edge→effective data input

t

/2 - 5x - 50

137

212

0

100

150

0

SCY

t

5x - 100

0

t

HSR

SRD

t

- 5x - 100

587

450

SCY

(2) SCLK Output Mode

Variable

16MHz

20MHz

Symbol

Parameter

SCLK cycle (programmable)

Unit

Min

Max

Min

Max

Min

Max

t

16x

8192x

1

725

45

0

512

0.8

550

20

409.6

µs

ns

SCY

OSS

OHS

Output Data→rising edge of SCLK

SCLK rising edge→output data hold

SCLK rising edge→input data hold

SCLK rising edge→effective data input

t

- 2x - 150

SCY

t

2x - 80

0

t

0

HSR

SRD

t

- 2x - 150

725

550

SCY

4.7 Timer/Counter Input Clock (TI0, TI4, TI5)

V

= 5V±10% TA = -20 ~ 70°C

cc

Variable

16MHz

20MHz

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

t

Clock cycle

8x + 100

4x + 40

600

290

500

240

ns

VCK

t

Low level clock pulse width

High level clock pulse width

VCKL

VCKH

t

TOSHIBA CORPORATION

163

TMP96C031N/F

4.8 Interrupt Operation

V

= 5V±10% Ta = -20 ~ 70°C

cc

Variable

16MHz

Min Max

20MHz

Min Max

Symbol

Parameter

Unit

Min

Max

t

NMI, INT0 Low level pulse width

NMI, INT0 High level pulse width

INT1 ~ INT7 Low level pulse width

INT1 ~ INT7 High level pulse width

4x

250

600

200

500

ns

INTAL

t

4x

INTAH

t

8x + 100

INTBL

INTBH

t

164

TOSHIBA CORPORATION

TMP96C031N/F

4.9 Timing Chart for I/O Interface Mode

TOSHIBA CORPORATION

165

TMP96C031N/F

4.10 Timing Chart for Bus Request/BUS Acknowledge

Variable

16MHz

20MHz

Symbol

Parameter

BUSRQ setup time for CLK

Unit

Min

Max

Min

Max

Min

Max

t

120

ns

BRC

t

CLK→BUSAK falling edge

CLK→BUSAK rising edge

Output buffer is off to BUSAK

1.5x + 120

0.5x + 40

80

214

71

220

65

CBAL

CBAH

t

0

80

0

80

ABA

BAA

BUSAK

output buffer is on.

80

Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “Wait” cycle.

Note 2: An internal programmable pull-down resistor must be connected.

Note 3: An internal programmable pull-up resistor must be connected.

166

TOSHIBA CORPORATION

TMP96C031N/F

(1) I/O port

(2) I/O port control

(3) Timer control

(4) Pattern Generator control

(5) Watch Dog Timer control

(6) Serial Channel control

(7) A/D converter control

(8) Interrupt control

5. Table of Special Function Registers

(SFR; Special Function Register)

The special function registers (SFRs) include the I/O ports and

peripheral control registers allocated to the 128-byte

addresses from 000000H to 00007FH.

(9) Chip Select/Wait Control

(10) DRAM Control

Conﬁguration of the table

TOSHIBA CORPORATION

167

TMP96C031N/F

Table 5 I/O Register Address Map

Name Address Name

40H MSAR0

Address

Name

Address

20H TRUN

Address

60H ADREG0

Name

000000H

1H

21H

41H MAMR0

42H MSAR1

43H MAMR1

44H MSAR2

45H MAMR2

46H MSAR3

47H MAMR3

48H

61H ADREG1

62H ADREG2

63H ADREG3

64H

2H

22H TREG0

23H TREG1

3H

4H

24H T01TMOD

25H TFFCR

26H TREG2

27H TREG3

28H T23MOD

29H TRDC

2AH

5H

65H

6H P2

7H P3

8H P2CR

9H P2FC

AH P3CRL

BH P3CRH

CH P4

DH P5

EH

66H

67H

68H

49H

69H B0CS

6AH B1CS

6BH B2CS

6CH B3CS

6DH

4AH

2BH

4BH DREFCR

4CH PG0REG

4DH PG1REG

4EH PG01CR

4FH

2CH

2DH

2EH

6EH

FH

2FH

6FH

10H P4FC

11H

30H TREG4L

31H TREG4H

32H TREG5L

33H TREG5H

34H CAP1L

35H CAP1H

36H CAP2L

37H CAP2H

38H T4MOD

39H TFF4CR

3AH T45CR

3BH

50H SC0BUF

51H SC0CR

52H SC0MOD

53H BR0CR

54H SC1BUF

55H SC1CR

56H SC1MOD

57H BR1CR

58H ODE

70H INTE01

71H INTE23

72H INTE45

73H INTE67

74H INTET10

75H INTET32

76H INTET54

77H INTES0

78H INTES1

79H INTEAD

7AH IIMC0

7BH IIMC1

7CH DMA0V

7DH DMA1V

7EH DMA2V

7FH DMA3V

12H P6

13H P7

14H P6CRL

15H P7CRL

16H P6CRH

17H P7CRH

18H

19H

59H

1AH

5AH

1BH

5BH

1CH

3CH

5CH WDMOD

5DH WDCR

5EH ADMOD

5FH

1DH

3DH

1EH

3EH

1FH

3FH

168

TOSHIBA CORPORATION

TMP96C031N/F

(1) I/O Port

Symbol

Name

Address

7

6

5

4

3

2

1

0

P27

P26

P25

P24

P23

P22

P21

P20

R/W

P2

P3

P4

PORT2

06H

Input mode

0

P35

P34

P33

P32

P31

P30

R/W

PORT3

PORT4

07H

0CH

1

P42

0

1

P41

1

Input mode (Pulled-up)

P43

P40

1

R/W

1

Output mode

P52 P51

P53

P50

R

P5

P6

PORT5

PORT6

0DH

12H

Input mode

P67

1

P66

1

P65

1

P64

1

P63

1

P62

1

P61

1

P60

1

R/W

Input mode

P76

1

P75

1

P74

1

P73

R/W

1

P72

1

P71

1

P70

1

P7

PORT7

13H

Input mode

Read/Write

R/W

R

W

;

Either read or write is possible

Only read is possible

Only write is possible

Prohibit RWM ;

Prohibit Read Modify Write. (Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF Instruction)

TOSHIBA CORPORATION

169

TMP96C031N/F

(2) I/O Port Control (1/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

P27C

P26C

P25C

P24C

P23C

P22C

P21C

P20C

08H

W

PORT2

Control

P2CR

0

P27F

0

P26F

0

P25F

0

P22F

0

P20F

0

(Prohibit

RMW)

<<Refer to the “P2FC”>>

P24F

0

P23F

0

P21F

0

09H

W

PORT2

Function

P2FC

(Prohibit

RMW)

P2FC/ P2CR = 00 : IN, 01 : OUT, 10 : –, 11 : A23 - 16

P33C1

P33C0

0

P32C1

P32C0

P31C1

P31C0

0

P30C1

P30C0

0

0AH

W

PORT3

Control

Low

P3CRL

0

(Prohibit

RMW)

00 : PORT input

01 : PORT output

10 : BUSRQ

11 : –

00 : PORT input

01 : PORT output

10 : –

00 : PORT input

01 : PORT output

10 : TO5

01 : PORT output

10 : BUSAK

11 : –

11 : HWR

RDEN

P35C1

P35C0

0

P34C1

P34C0

0BH

W

0

W

PORT3

Control

High

P3CRH

0

(Prohibit

RMW)

1 : pseudo

SRAM

EN

00 : PORT input

01 : PORT output

10 : RAS

00 : PORT input

01 : PORT output

10 : NMI

11 : –

11 : R/W

BUSWDT

BUDRM

P43F

P42F

0

P41F

P40F

10H

W

0

W

0

PORT4

P4FC

Function

0

(Prohibit

RMW)

00 : BUSSRQ 0 : ON

00 : PORT

01 : CS3/CAS 01 : CS2

00 : PORT

01 : CS1

00 : PORT

01 : CS0

DIS

01 : BUSRQ

EN

1 : OFF

170

TOSHIBA CORPORATION

TMP96C031N/F

I/O Port Control (2/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

P63C1

P63C0

P62C1

P62C0

P61C1

P61C0

P60C1

P60C0

14H

W

PORT6

Control

Low

P6CRL

0

(Prohibit

RMW)

00 : PORT input

01 : PORT output

10 : PG03

11 : RFSH

01 : PORT output

10 : PG02

11 : –

01 : PORT output

10 : PG01

11 : –

01 : PORT output

10 : PG00

11 : TxD0

P67C1

P67C0

P66C1

P66C0

P65C1

P65C0

P64C1

P64C0

15H

W

PORT6

Control

High

P6CRH

P7CRL

P7CRH

0

(Prohibit

RMW)

00 : PORT input

01 : PORT output

10 : PG13

00 : PORT input

01 : PORT output

10 : PG12

00 : PORT input

01 : PORT output

10 :PG11

00 : PORT input

01 : PORT output

10 : PG10

11 : WDTOUT

11 : –

P73C1

P73C0

0

P72C1

P72C0

0

P71C1

P71C0

0

P70C1

P70C0

0

16H

W

PORT7

Control

Low

0

(Prohibit

RMW)

00 : PORT input

01 : PORT output

10 : –

00 : PORT input

01 : PORT output

10 : –

00 : PORT input

01 : PORT output

10 : TO3

00 : PORT input

01 : PORT output

10 : TO1

11 : –

11 : DMUX

11 : TO4

P76C1

P76C0

P75C1

P75C0

P74C1

P74C0

17H

W

PORT7

Control

High

0

(Prohibit

RMW)

00 : PORT input

01 : PORT output

10 : SCLK1

11 : –

00 : PORT input

01 : PORT output

10 : –

00 : PORT input

01 : PORT output

10 : TxD1

11 : –

TOSHIBA CORPORATION

171

TMP96C031N/F

(3) Timer Control (1/3)

Symbol

Name

Address

7

6

5

4

3

2

1

0

T5RUN

T4RUN

P1RUN

P0RUN

T1RUN

T0RUN

R/W

Timer RUN

Control

Reg.

0

TRUN

20H

Prescaler and Timer Run/Stop CONTROL

0 : Stop and Clear

1 : Run (Count up)

22H

(Prohibit

RMW)

–

8bit Timer

Register 0

TREG0

TREG1

W

Undeﬁned

–

23H

8bit Timer

Register 1

(Prohibit

RMW)

W

Undeﬁned

T10M1

0

T10M0

0

PWMM1

0

PWMM0

T1CLK1

T1CLK0

0

T0CLK1

0

T0CLK0

0

W

8bit Timer

Source CLK

and MODE

24H

0

T01TMOD

00 : 8-bit Timer

00 : –

01 : 2 - 1

10 : 2 - 1

11 : 2 - 1

00 : TO0TRG

00 : TI0 Input

6

01 : 16-bit Timer

10 : 8-bit PPG

11 : 8-bit PWM

PWM

Cycle

01 : φT1

10 : φT16

11 : φT256

01 : φT1

10 : φT4

11: φT16

(Prohibit

RMW)

7

8

TFF3C1

TFF3C0

TFF3IE

TFF3IS

TFF1C1

TFF1C0

TFF1IE

TFF1IS

0

W

–

R/W

W

–

R/W

8bit Timer

Flip-ﬂop

Control

0

TFFCR

25H

00 : Invert TFF3

01 : Set TFF3

1 : TFF3

Invert

0 : Timer 2

1 : Timer 3

00 : Invert TFF1

01 : Set TFF1

1 : TFF1

Invert

0 : Timer 0

1 : Timer 1

10 : Clear TFF3

11 : Don’t care

Enable

10 : Clear TFF1

11 : Don’t care

Enable

–

PWM Timer

Register 2

TREG2

TREG3

26H

27H

W

Undeﬁned

–

W

PWM Timer

Register 3

Undeﬁned

T23M1

T23M0

PWM21

0

PWM20

T3CLK1

T3CLK0

T2CLK0

0

T2CLK0

0

R/W

28H

0

Timer 2, 3

Hode Reg.

T23MOD

00 : 8-bit Timer

01 : 16-bit Timer

10 : 8-bit PPG

11 : 8-bit PWM

00 : –

00 : TO2TRG

01 : φT1

10 : φT16

11 : φT256

00 : TI0 Input

6

01 : 2 - 1

PWM

Cycle

01 : φT1

10 : φT4

11: φT16

7

(Prohibit

RMW)

10 : 2 - 1

8

11 : 2 - 1

TR2DE

TR0DE

0

R/W

0

Timer Reg.

Double Buffer

Control Reg.

TRDC

Tmer Reg.

29H

Double Buffer Control

0 : Double Buffer Disable

1 : Double Buffer Enable

172

TOSHIBA CORPORATION

TMP96C031N/F

(3) Timer Control (2/3)

Symbol

Name

Address

7

6

5

4

3

2

1

0

30H

(Prohibit

RMW)

–

16bit Timer

Register 4L

TREG4L

W

Undeﬁned

31H

(Prohibit

RMW)

–

16bit Timer

Register 4H

TREG4H

TREG5L

TREG5H

CAP1L

CAP1H

CAP2L

CAP2H

W

Undeﬁned

32H

(Prohibit

RMW)

–

16bit Timer

Register 5L

W

Undeﬁned

33H

(Prohibit

RMW)

–

16bit Timer

Register 5H

W

Undeﬁned

–

Capture

Register 1L

34H

35H

36H

37H

R

Undeﬁned

–

Capture

Register 1H

R

Undeﬁned

–

Capture

Register 2L

R

Undeﬁned

–

R

Capture

Register 2H

Undeﬁned

CAP2T5

0

EQ5T5

0

CAP1IN

CAP12M1

CAP12M0

CLE

0

T4CLK1

0

T4CLK0

0

R/W

W

0

R/W

16bit Timer 4

Source

CLK and

MODE

0

T4MOD

38H

TFF5 INV TRG

O : TRG Disable

1: TRG Enable

0 : Soft-

Capture

1 : Don’t care

Capture Timing

00 : Disable

01 : T14 ↑ TI5

10 : T14 ↑ T14

1 : UC4

Clear

Enable

Source Clock

00 : TI4

01 : φT1

10 : φT4

11 : φT16

↑

11 : TFF1 ↑ TFF1 ↓

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173

TMP96C031N/F

(3) Timer Control (3/3)

Symbol

Name

Address

7

6

5

4

3

2

1

0

TFF5C1

TFF5C0

CAP2T4

CAP1T4

EQ5T4

EQ4T4

TFF4C1

TFF4C0

W

R/W

W

16bit Timer 4

Flip-ﬂop

Control

0

T4FFCR

39H

00 : Invert TFF5

01 : Set TFF5

10 : Clear TFF5

11 : Don’t care

TFF4 Invert Trigger

0 : Trigger Disable

1 : Trigger Enable

Source Clock

00 : Invert TFF4

01 : Set TFF4

10 : Clear TFF4

11 : Don’t care

–

PG1T

PG0T

0

DB4EN

R/W

0

T45CR T4, T5 Control

3AH

PG1 shift

trigger

0 : Timer 0, 1 O : Timer 2,3

PG0 shift

trigger

1 : Double

Buffer

Fix at “0”

Enable

1 : Timer 4

(4) Pattern Generator

Symbol

Name

Address

7

6

5

4

3

2

1

0

PG03

PG02

PG01

PG00

SA03

SA02

SA01

SA00

4CH

(Prohibit

RMW)

PG0REG PGO Register

PG1REG PG1 Register

W

R/W

0

Undeﬁned

PG13

PG12

PG11

PG10

SA13

PAT0

SA12

SA11

SA10

4DH

(Prohibit

RMW)

R/W

0

Undeﬁned

PAT1

CCW1

PG1M

PG1TE

CCW0

PG0M

PG0TE

R/W

0

4EH

PG01CR PG0, 1 Control

0 : Normal

Rotation

PG1 trigger

0 : Normal

Rotation

PG0 trigger

0 : 8-bit write

1 : 4-bit write 1 : Reverse

Rotation

0 : 4-bit Step input

1 : 8-bit Step enable

0 : 8-bit write

1 : 4-bit write 1 : Reverse

Rotation

0 : 4-bit Step input

1 : 8-bit Step enable

1 : Enable

(5) Watch Dog Timer

Symbol

Name

Address

7

6

5

4

3

2

1

0

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

R/W

1

0

WD-

MOD

Watch Dog

Timer Mode

5CH

Standby Mode

1 : Connect

internally

WDT out

pin to

16

00 : 2 /fc

Warming up

Time

1 : Drive

the pin

in STOP

Mode

00 : RUN Mode

01 : STOP Mode

10 : IDLE Mode

11 : Don’t care

18

1 : WDT

Enable

01 : 2 /fc

20

14

10 : 2 /fc

0 : 2 /fc

22

16

11 : 2 /fc

1 : 2 /fc

Reset Pin

–

Watch Dog

Timer

Control

Register

W

WDCR

5DH

Undeﬁned

B1H : WDT Disable Code

4EH : WDT Clear Code

174

TOSHIBA CORPORATION

TMP96C031N/F

(6) Serial Channel (1/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

RB7

TB7

RB6

TB6

RB5

TB5

RB4

TB4

RB3

TB3

RB2

TB2

RB1

TB1

RB0

TB0

Serial

Channel 0

Buffer

SC0BUF

50H

R (Receiving)/W (Transmission)

Undeﬁned

RB8

R

EVEN

0

PE

0

OERR

PERR

FERR

–

0

R/W

R (Cleared to 0 by reading)

R/W

Serial

Channel 0

Control

0

Fix at “0”

SC1

SC0CR

51H

52H

Parity

0 : Odd

1 : Even

1 : Error

Receiving

data bit 8

1 : Parity

Enable

Fix at “0”

SC0

Overrun

WU

Parity

SM1

Framing

SM0

TB8

CTSE

RXE

R/W

Serial

Channel 0

Mode

0

SC0-

MOD

00 : Unused

00 : TO0 Trigger

Transmission 1 : CTS

data bit 8

1 : Receive

Enable

1 : Wake up

Enable

01 : UART 7-bit

10 : UART 8-bit

11 : UART 9-bit

01 : Baud rate generator

10 : Internal clock φ1

11 : Don’t care

Enable

–

R/W

0

BR0CK1

0

BR0CK0

BR053

BR052

BR051

BR050

R/W

0

Baud Rate

Control

BR0CR

53H

54H

00 : φt0 (fc/4)

01 : φt2 (fc/16)

10 : φt8 (fc/64)

Set frequency divisor

0 ~ F

(“1” prohibited)

Fix at “0”

11 : φt32 (fc/256)

RB7

TB7

RB6

TB6

RB5

TB5

RB4

TB4

RB3

TB3

RB2

TB2

RB1

TB1

RB0

TB0

Serial

Channel 1

Buffer

SC1BUF

R (Receiving)/W (Transmission)

Undeﬁned

RB8

R

EVEN

0

PE

OERR

PERR

FERR

SCLKS

0

IOC

0

R/W

R (Cleared to 0 by reading)

R/W

0

Serial

Channel 1

Control

1 : Error

SC1CR

55H

Parity

0 : Odd

1 : Even

Receiving

data bit 8

1 : Parity

Enable

1 : Input

SCLK1 pin

Overrun

Parity

Framing

TB8

0

–

0

RXE

0

WU

0

SM1

0

SM0

0

SC1

0

SC0

0

R/W

Serial

Channel 1

Mode

SC1-

MOD

56H

00 : I/O Interface

01 : UART 7-bit

10 : UART 8-bit

11 : UART 9-bit

00 : TO0 Trigger

Transmission

data bit 8

1 : Receive

Enable

1 : Wake up

Enable

01 : Baud rate generator

10 : Internal clock φ1

11 : Don’t care

Fix at “0”

TOSHIBA CORPORATION

175

TMP96C031N/F

(6) Serial Channel (2/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

–

R/W

0

BR1CK1

BR1CK0

BR153

R/W

0

BR152

BR151

BR150

0

Baud Rate

Control

BR1CR

57H

00 : φt0 (fc/4)

Set frequency divisor

0 ~ F

(“1” prohibited)

01 : φt2 (fc/16)

10 : φt8 (fc/64)

11 :φt32 (fc/256)

Fix at “0”

ODE1

ODE0

0

R/W

Special

Open Drain

Enable

ODE

58H

0

1 : P74

1 : P60

Open-drain

(7) A/D Converter Control

Symbol

Name

Address

7

6

5

4

3

2

1

0

EOCF

ADBF

REPET

R/W

0

SCAN

R/W

0

ADCS

ADS

ADCH1

ADCH0

R

R/W

A/D Converter

Mode Reg.

ADMOD

5EH

0

1 : Repeat

mode set

1 : Scan

mode

1 : Slow

mode

1 : END

1 : BUSY

1 : START

Analog Input Channel Select

–

R

AD Result

Reg. 0

ADREG0

60H

61H

62H

63H

Undeﬁned

–

AD Result

Reg. 1

R

ADREG1

ADREG2

Undeﬁned

–

AD Result

Reg. 2

R

Undeﬁned

–

R

AD Result

Reg. 3

ADREG3

Undeﬁned

176

TOSHIBA CORPORATION

TMP96C031N/F

(8) Interrupt Control (1/2)

TOSHIBA CORPORATION

177

TMP96C031N/F

(8) Interrupt Control (2/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

µDMA0 start vector

DMA 0

request

Vector

7CH

(Prohibit

RMW)

DMA0V8

DMA0V7

DMA0V6

DAM0V5

DMA0V4

DMA0V

W

0

DMA01V8

0

µDMA1 start vector

DMA 1

request

Vector

7DH

(Prohibit

RMW)

DMA1V7

0

DMA1V6

DAM1V5

0

DMA1V4

0

DMA1V

DMA2V

DMA3V

W

0

µDMA2 start vector

DMA 2

request

Vector

7EH

(Prohibit

RMW)

DMA2V8

0

DMA2V7

0

DMA2V6

DAM2V5

0

DMA2V4

0

W

0

µDMA3 start vector

DMA 3

request

Vector

7FH

(Prohibit

RMW)

DMA3V8

DMA3V7

DMA3V6

DAM3V5

DMA3V4

W

0

I4IE

0

I3IE

0

I2IE

0

I1IE

I1EM

I0IE

I0LE

NMIREE

W

7AH

0

Interrupt Input

Mode

Control 0

0 : INTO

rising

edge

1 : INT1

falling

edge

0 : INTO

edge

mode

1 : INTO

level

IIMC0

IIMC1

1 : Operate

even at

NMI rise

edge

(Prohibit

RMW)

1 : INT4

input

enable

1 : INT3

input

enable

1 : INT2

input

enable

1 : INT1

input

enable

1 : INT0

input

enable

mode

I7IE

0

I6LE

W

I5IE

7BH

Interrupt Input

Mode

Control 1

0

(Prohibit

RMW)

1 : INT7

input

1 : INT6

input

1 : INT5

input

enable

178

TOSHIBA CORPORATION

TMP96C031N/F

(9) Chip Select/Wait Controller (1/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

B0E

B0SYS

B0ARE

B0BUS

B0W1

B0W0

B0C1

B0C0

W

68H

Block 0

CS/WAIT

control

0

B0CS

0 : 7F00 ~

7FFF

1 : Address

area

00 : 2WAIT

01 : 1WAIT

00 : 2WAIT

01 : 1WAIT

(Prohibit

RMW)

register

0 : CS0 DIS 1 : SYSTEM

1 : CS0 EN

0 : 16-bit Bus

1 : 8-bit Bus

only

10 : 1WAIT + n

11 : 0WAIT

10 : 1WAIT + n

11 : 0WAIT

speciﬁcation

B1E

0

B1SYS

0

B1ARE

B1BUS

0

B1W1

B1W0

69H

Block 1

CS/WAIT

control

0

B1CS

0 : 80 ~

7FFF

1 : Address

area

(Prohibit

RMW)

register

0 : CS1 DIS

1 : CS1 EN

↑

–

speciﬁcation

B2E

1

B2SYS

0

B2ARE

B2BUS

B2W1

0

B2W0

0

6AH

Block 2

CS/WAIT

control

0

Undeﬁned

B2CS

B3CS

0 : 8000 ~

3FFFFF

1 : Address

area

(Prohibit

RMW)

register

0 : CS0 DIS

1 : CS0 EN

↑

–

speciﬁcation

B3E

0

B3SYS

0

B3ARE

B3BUS

0

B3W1

0

B3W0

0

B3CAS

0

SRFC

0

68H

Block 3

CS/WAIT

control

0

0 : CS3/CAS

DIS

1 : CS3/CAS

EN

0 : Undeﬁned

1 : Address

area

0 : CS3/CAS 0 : Self

DIS refresh

1 : CS3/CAS execution

(Prohibit

RMW)

register

↑

speciﬁcation

EN

1 : Release

S23

S22

1

S21

S20

S19

1

S18

1

S17

S16

Memory

Start

Adrress

Reg. 0

R/W

40H

MSAR0

MAMR0

MSAR1

1

A23 ~ A16

Memory start address setting

V20

1

V19

1

V18

1

V17

V16

V15

1

V14 ~ 9

1

V8

1

Memory

Start

Adrress

Mask

R/W

41H

42H

1

0: Address A8 ~ A20 comparison is valid.

1: Address A8 ~ A20 comparison is invalid. (Speciﬁcation bit by bit).

Reg. 0

S23

1

S22

1

S21

S20

S19

S18

S17

S16

1

Memory

Start

Adrress

Reg. 1

R/W

1

A23 ~ A16

Memory start address setting

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179

TMP96C031N/F

(9) Chip Select/Wait Controller (2/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

V21

V20

V19

V18

V17

V16

V15 ~ 9

V8

Memory

Start

R/W

MAMR1

Adrress

Mask

Reg. 1

43H

1

0: Address A8 ~ A21 comparison is valid.

1: Address A8 ~ A21 comparison is invalid. (Speciﬁcation bit by bit).

S23

1

S22

1

S21

S20

S19

S18

S17

S16

1

Memory

Start

Adrress

Reg. 2

R/W

MSAR2

MAMR2

MSAR3

MAMR3

44H

45H

46H

1

A23 ~ A16

Memory start address setting

V22

1

V21

1

V20

1

V19

V18

V17

1

V16

1

V15

1

Memory

Start

Adrress

Mask

R/W

1

0: Address A15 ~ A22 comparison is valid

1: Address A15 ~ A22 comparison is invalid. (Speciﬁcation bit by bit).

Reg. 2

S23

1

S22

1

S21

S20

S19

S18

S17

S16

1

Memory

Start

Adrress

Reg. 3

R/W

1

A23 ~ A16

Memory start address setting

V22

1

V21

1

V20

1

V19

V18

V17

1

V16

1

V15

1

Memory

Start

Mask

Adrress

Reg. 3

R/W

1

0: Address A15 ~ A22 comparison is valid

1: Address A15 ~ A22 comparison is invalid. (Speciﬁcation bit by bit).

180

TOSHIBA CORPORATION

TMP96C031N/F

(10) DRAM Control

Symbol

Name

Address

7

6

5

4

3

2

1

0

DMI

RS2

RS1

RS0

RW2

RW1

RW0

RC

R/W

0

Refresh cycle insertion interval

000 : 15 states

Refresh cycle insertion interval

000 : 2 states

Refresh

Control

Reg.

DREFCR

48H

001 : 31 states

010 : 62 states

011 : 78 states

100 : 97 states

001 : 3 states

010 : 4 states

011 : 5 states

100 : 6 states

Dummy cycle

0 : Prohibit

1 : Execute

Refresh cycle

0 : Prohibit

1 : Execute

101 : 109 states

110 : 124 states

111 : 154 states

101 : 7 states

110 : 8 states

111 : 9 states

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181

TMP96C031N/F

STOP: This signal becomes active “1” when the hold mode

setting register is set to the STOP mode and the CPU

executes the HALT instruction. When the drive enable

bit [DRIVE] is set to “1”, however, STP remains at “0”.

• The input protection resistans ranges from several tens of

ohms to several hundreds of ohms.

6. Port Section Equivalent Circuit Diagram

• Reading The Circuit Diagram

Basically, the gate singles written are the same as

those used for the standard CMOS logic IC [74HCXX]

series.

The dedicated signal is described below.

• PO (AD0 ~ AD7), P1 (AD8 ~ 15, A8 ~ 15), P2 (A16 ~ 23)

• RD, WR

• P30 ~ 33, P35

182

TOSHIBA CORPORATION

TMP96C031N/F

• P61 ~ P67, P70 ~ P73, P75 ~ P76

VCC

• P50 (AN0/INT0)

• P51 ~ P53 (AN1 ~ 3/INT1 ~ 3)

TOSHIBA CORPORATION

183

TMP96C031N/F

• P60 (TXD0), P74 (TXD1)

• P34 (NMI/R/W)

• P40~ P43 (CS0 ~ CS3/CAS)

184

TOSHIBA CORPORATION

TMP96C031N/F

• CLK

• AM8/16

• RESET

• X1, X2

• VREF

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185

TMP96C031N/F

(2)

Guidelines

7. Guidelines and Restrictions

(1)

Special Expression

➀ AM8/16 pin

➀ Explanation of a built-in I/O register: Register

Fix these pins VCC or GND unless changing voltage.

➁ Warming-up Counter

Symbol

. . .

ex) TRUN <TRUN>

Bit T0RUN of Register TRUN

The warming-up counter operates when the STOP

mode. is released even the system which is used an

external oscillator. As a result, it takes warming up time

from inputting the releasing request to outputting the

system clock.

➁ Read, Modify and Write Instruction

An instruction which CPU executes following by one

instruction.

➂ Programmable Pull Up/Down Resistance

1. CPU reads data of the memory.

2. CPU modiﬁes the data.

The programmable pull up/down resistors can be

selected ON/OFF by program when they are used as

the input ports. The case of they are used as the out-

put ports, they cannot be selected ON/OFF by pro-

gram.

3. CPU writes the data to the same memory.

. . .

ex1) SET 3, (TRUN)

set bit3 of TRUN

ex2) INC1, (100H) increment the data of 100H

➃ Bus Releasing Function

• The representative Read, Modify and Write

Instruction in the TLCS-900

Refer to the “Note about the Bus Release” in 3.5 Func-

tions of Ports because the pin state when the bus is

released is written.

SET imm, mem,

CHG imm, mem,

INC imm, mem,

RLD A, mem,

RES

TSET

DEC

ADD

imm, mem

imm, reg

➄ Watch Dog Timer

The watch dog timer starts operation immediately after

the reset is released. When the watch dog timer is not

used, set watch dog timer to disable.

➂ 1 state

One cycle clock divided by 2 oscillation frequency is

called 1 state

➅ CPU (High Speed µDMA)

Only the “LDC cr, r”, “LDC r, cr” instruction can be

used to access the control register like transfer source

address register (DMASn) in the CPU.

ex) Oscillation frequency is 20MHz

2/20MHz = 100ns = 1 state

186

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型号：	TMP96C031F
厂家：	ETC
描述：	16-Bit Microcontroller 16位微控制器\n 微控制器
文件：	总186页 (文件大小：5195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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