TMP96C141AF_技术文档

TOSHIBA

TLCS-900 Series

TMP96C141AF

Internal ROM: None

(4) External memory expansion

• Can be expanded up to 16M bytes (for both programs and

data).

CMOS 16-bit Microcontroller

TMP96C141AF

1. Outline and Device Characteristics

• Can mix 8- and 16-bit external data buses.

…

Dynamic data bus sizing

The TMP96C141AF is high-speed advanced 16-bit microcon-

troller developed for controlling medium to large-scale equip-

ment.

The TMP96C141AF is housed in an 80-pin ﬂat package.

Device characteristics are as follows:

(5) 8-bit timers: 2 channels

(6) 8-bit PWM timers: 2 channels

(7) 16-bit timers: 2 channels

(8) Pattern generators: 4 bits, 2 channels

(9) Serial interface: 2 channels

(10) 10-bit A/D converter: 4 channels

(11) Watchdog timer

(1) Original 16-bit CPU

• TLCS-90 instruction mnemonic upward compatible.

• 16M-byte linear address space

• General-purpose registers and register bank system

• 16-bit multiplication/division and bit transfer/arithmetic

instructions

• High-speed micro DMA

- 4 channels (1.6µs/2 bytes @ 20MHz)

(2) Minimum instruction execution time

- 200ns @ 20MHz

(12) Chip select/wait controller: 3 blocks

(13) Interrupt functions

… …

• 3 CPU interrupts

SWI instruction, privileged violation,

and Illegal instruction

• 14 internal interrupts

• 6 external interrupts

(14) I/O ports

7-level priority can be set.

(15) Standby function : 3 halt modes (RUN, IDLE, STOP)

(3) Internal RAM: 1K byte

The information contained here is subject to change without notice.

The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties

which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic

equipments (ofﬁce equipment, communication equipment, measuring equipment, domestic electriﬁcation, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-

ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, trafﬁc signal, combustion control, all types

of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.

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TMP96C141AF

Figure 1. TMP96C141AF Block Diagram

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TMP96C141AF

2.1 Pin Assignment

Figure 2.1 shows pin assignment of TMP96C141AF.

2. Pin Assignment and Functions

The assignment of input/output pins for TMP96C141AF, their

name and outline functions are described below.

Figure 2.1 Pin Assignment (80-pin QFP)

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TMP96C141AF

2.2 Pin Names and Functions

The names of input/output pins and their functions are described below.

Table 2.2. Pin Names and Functions

Number

of Pins

Pin Name

P00 ~ P07

I/O

Functions

I/O

Tri-state

Port 0: I/O port that allows I/O to be selected on a bit basis

Address / data (lower): 0 - 7 for address / data bus

8

AD0 ~ AD7

P10 ~ P17

AD8 ~ AD15

A8 ~ A15

I/O

Tri-state

Output

Port 1: I/O port that allows I/O to be selected on a bit basis

Address data (upper): 8 - 15 for address / data bus

Address: 8 to 15 for address bus

P20 ~ P27

A0 ~ A7

A16 ~ A23

I/O

Output

Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)

Address: 0 - 7 for address bus

Address: 16 - 23 for address bus

8

P30

RD

Output

Port 30: Output port

Read: Strobe signal for reading external memory

1

P31

WR

Output

Port 31: Output port

Write: Strobe signal for writing data on pins AD0 -7

P32

HWR

I/O

Output

Port 32: I/O port (with pull-up resistor)

High write: Strobe signal for writing data on pins AD8 - 15

P33

WAIT

I/O

Input

Port 33: I/O port (with pull-up resistor)

Wait: Pin used to request CPU bus wait

P34

BUSRQ

Port 34: I/O port (with pull-up resistor)

Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0,

CS1, and CS2 pins. (For external DMAC)

I/O

Input

1

P35

BUSAK

Port 35: I/O (with pull-up resistor)

Bus acknowledge: Signal indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2

pins are at high impedance after receiving BUSRQ. (For external DMAC)

I/O

Output

P36

R/W

I/O

Output

Port 36: I/O port (with pull-up resistor)

Read/write: 1 represents read or dummy cycle; 0, write cycle.

1

P37

RAS

I/O

Output

Port 37: I/O port (with pull-up resistor)

Row address strobe: Outputs RAS strobe for DRAM.

P40

CS0

CAS0

I/O

Output

Port 40: I/O port (with pull-up resistor)

Chip select 0: Outputs 0 when address is within speciﬁed address area.

Column address strobe 0: Outputs CAS strobe for DRAM when address is within speciﬁed address area.

1

Note: With the external DMA controller, this device’s built-in memory or built-in I/O cannot be accessed using the BUSRQ and BUSAK pins.

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TMP96C141AF

Number

of Pins

Pin Name

P41

CS1

CAS1

I/O

Functions

I/O

Output

Port 41: I/O port (with pull-up resistor)

Chip select 1: Outputs 0 if address is within speciﬁed address area.

Column address strobe 1: Outputs CAS strobe for DRAM if address is within speciﬁed address area.

1

P42

CS2

CAS2

I/O

Output

Port 42: I/O port (with pull-up resistor)

Chip select 2: Outputs 0 if address is within speciﬁed address area.

Column address strobe 2: Outputs CAS strobe for DRAM if address is within speciﬁed address area.

1

4

P50 ~ P53

AN0 ~ AN3

Input

Port 5: Input port

Analog input: Input to A/D converter

VREF

1

Input

Pin for reference voltage input to A/D converter

Ground pin for A/D converter

AGND

P60 ~ P63

PG00 ~ PG03

I/O

Output

Ports 60 - 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)

Pattern generator ports: 00 - 03

4

1

P64 ~ P67

PG10 ~ PG13

I/O

Output

Ports 64 - 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)

Pattern generator ports: 10 - 13

P70

T10

I/O

Input

Port 70: I/O port (with pull-up resistor)

Timer input 0: Timer 0 input

P71

T01

I/O

Output

Port 71: I/O port (with pull-up resistor)

Timer output 1: Timer 0 or 1 output

P72

T02

I/O

Output

Port 72: I/O port (with pull-up resistor)

PWM output 2: 8-bit PWM timer 2 output

P73

T03

I/O

Output

Port 73: I/O port (with pull-up resistor)

PWM output 3: 8-bit PWM timer 3 output

P80

TI4

INT4

I/O

Input

Port 80: I/O port (with pull-up resistor)

Timer input 4: Timer 4 count/capture trigger signal input

Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge

1

P81

TI5

INT5

I/O

Input

Port 81: I/O port (with pull-up resistor)

Timer input 5: Timer 4 count/capture trigger signal input

Interrupt request pin 5: Interrupt request pin with rising edge

P82

TO4

I/O

Output

Port 82: I/O port (with pull-up resistor)

Timer output 4: Timer 4 output pin

1

P83

TO5

I/O

Output

Port 83: I/O port (with pull-up resistor)

Timer output 5: Timer 4 output pin

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TMP96C141AF

Number

of Pins

Pin Name

P84

I/O

Functions

I/O

Port 84: I/O port (with pull-up resistor)

TI6

INT6

1

Input

Timer input 6: Timer 5 count/capture trigger signal input

Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge

P85

TI7

INT7

I/O

Input

Port 85: I/O port (with pull-up resistor)

Timer input 7: Timer 5 count/capture trigger signal input

Interrupt request pin 7: Interrupt request pin with rising edge

1

P86

TO6

I/O

Output

Port 86: I/O port (with pull-up resistor)

Timer output 6: Timer 5 output pin

1

P87

INT0

I/O

Input

Port 87: I/O port (with pull-up resistor)

Interrupt request pin 0: Interrupt request pin with programmable level/rising edge

P90

TXD0

I/O

Output

Port 90: I/O port (with pull-up resistor)

Serial send data 0

P91

RXD0

I/O

Input

Port 91: I/O port (with pull-up resistor)

Serial receive data 0

P92

CTS0

I/O

Input

Port 92: I/O port (with pull-up resistor)

Serial data send enable 0 (Clear to Send)

P93

TXD1

I/O

Output

Port 93: I/O port (with pull-up resistor)

Serial send data 1

P94

RXD1

I/O

Input

Port 94: I/O port (with pull-up resistor)

Serial receive data 1

P95

SCLK1

I/O

Port 95: I/O port (with pull-up resistor)

Serial clock I/O 1

1

WDTOUT

NMI

Output

Watchdog timer output pin

Non-maskable interrupt request pin: Interrupt request pin with falling edge.

Can also be operated at rising edge by program.

Input

CLK

EA

Output

Input

Clock output: Outputs X1 ÷ 4 clock. Pulled-up during reset.

External access: 0 should be inputted with TMP96C141AF

1, with TMP96CM40F/TMP96PM40F.

ALE

1

2

3

Output

Input

I/O

Address latch enable

RESET

X1/X2

VCC

Reset: Initializes LSI. (With pull-up resistor)

Oscillator connecting pin

Power supply pin (+ 5V)

GND pin (0V)

VSS

Note: Pull-up/pull-down resistor can be released from the pin by software.

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TMP96C141AF

• Stack pointer (XSP) for system mode to 100H.

• SYSM bit of status register (SR) to 1. (Sets to system mode.)

• IFF2 to 0 bits of status register to 111. (Sets mask register to

interrupt level 7.)

3. Operation

This section describes in blocks the functions and basic oper-

ations of the TMP96C141AF device.

Check the chapter Guidelines and Restrictions for proper

care of the device.

• MAX bit of status register to 0. (Sets to minimum mode.)

• Bits RFP2 to 0 of status register to 000. (Sets register banks

to 0.)

When reset is released, instruction execution starts from

address 8000H. CPU internal registers other than the above

are not changed.

3.1 CPU

The TMP96C141AF device has a built-in high-performance

16-bit CPU. (For CPU operation, see TLCS-900 CPU in the

book Core Manual Architecture User Manual.)

This section describes CPU functions unique to

TMP96C141AF that are not described in that manual.

When reset is accepted, processing for built-in I/Os,

ports, and other pins is as follows:

• Initializes built-in I/O registers as per specifications.

3.1.1 Reset

• Sets port pins (including pins also used as built-in I/Os) to

general-purpose input/output port mode (sets I/O ports to

input ports).

• Sets the WDTOUT pin to 0. (Watchdog timer is set to enable

after reset.)

• Pulls up the CLK pin to 1.

• Sets the ALE pin to 0.

To reset the TMP96C141AF, the RESET input must be kept at

0 for at least 10 system clocks (10 states: 1µs with a 20MHz

system clock) within an operating voltage range and with a

stable oscillation.

When reset is accepted, the CPU sets as follows:

• Program counter (PC) to 8000H.

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TMP96C141AF

3.2 Memory Map

Figure 3.2 is a memory map of the TMP96C141AF.

Figure 3.2 Memory Map

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TMP96C141AF

3.3 Interrupts

A ﬁxed individual interrupt vector number is assigned to

each interrupt source; six levels of priority (variable) can also

be assigned to each maskable interrupt. Non-maskable inter-

rupts have a ﬁxed priority of 7.

The TLCS-900 interrupts are controlled by the CPU interrupt

mask ﬂip-ﬂop (IFF2 to 0) and the built-in interrupt controller.

The TMP96C141AF have altogether the following 23

interrupt sources:

When an interrupt is generated, the interrupt controller

…

• Interrupts from the CPU 3

(Software interrupts, privileged violations, and Illegal (undeﬁned) instruction execution)

…

• Interrupts from external pins (NMI, INT0, and INT4 to 7) 6

…

• Interrupts from built-in I/Os 14

sends the value of the priority of the interrupt source to the

CPU. When more than one interrupt is generated simulta-

neously, the interrupt controller sends the value of the highest

priority (7 for non-maskable interrupts is the highest) to the

CPU.

The CPU compares the value of the priority sent with the

value in the CPU interrupt mask register (IFF2 to 0). If the value

is greater than that of the CPU interrupt mask register, the

interrupt is accepted. The value in the CPU interrupt mask reg-

ister (IFF2 to 0) can be changed using the EI instruction (con-

tents of the EI num/IFF<2:0> = num). For example,

programming EI 3 enables acceptance of maskable interrupts

with a priority of 3 or greater, and non-maskable interrupts

which are set in the interrupt controller. The DI instruction

(IFF<2:0> = 7) operates in the same way as the EI 7 instruc-

tion. Since the priority values for maskable interrupts are 0 to 6,

the DI instruction is used to disable maskable interrupts to be

accepted. The EI instruction becomes effective immediately

after execution. (With the TLCS-90, the EI instruction becomes

effective after execution of the subsequent instruction.)

In addition to the general-purpose interrupt processing

mode described above, there is also a high-speed micro DMA

processing mode. High-speed micro DMA is a mode used by

the CPU to automatically transfer byte or word data. It enables

the CPU to process interrupts such as data saves to built-in I/Os

at high speed.

Figure 3.3 (1) is a ﬂowchart showing overall interrupt

processing.

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TMP96C141AF

Figure 3.3 (1) Interrupt Processing Flowchart

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TMP96C141AF

3.3.1 General-Purpose Interrupt Processing

Bus Width of Stack

Area

Interrupt Processing State Number

When accepting an interrupt, the CPU operates as follows:

MAX mode

Min mode

(1) The CPU reads the interrupt vector from the interrupt

controller. When more than one interrupt with the same

level is generated simultaneously, the interrupt controller

generates interrupt vectors in accordance with the

default priority (which is ﬁxed as follows: the smaller the

vector value, the higher the priority), then clears the inter-

rupt request.

8 bit

23

17

19

15

16 bit

To return to the main routine after completion of the inter-

rupt processing, the RETI instruction is usually used. Executing

this instruction restores the contents of the program counter

and the status registers.

Though acceptance of non-maskable interrupts cannot

be disabled by program, acceptance of maskable interrupts

can. A priority can be set for each source of maskable inter-

rupts. The CPU accepts an interrupt request with a priority

higher than the value in the CPU mask register <IFF2 to 0>.

The CPU mask register <IFF2 to 0> is set to a value higher by

1 than the priority of the accepted interrupt. Thus, if an inter-

rupt with a level higher than the interrupt being processed is

generated, the CPU accepts the interrupt with the higher level,

causing interrupt processing to nest. The CPU does not

accept an interrupt request of the same level as that of the

interrupt being processed.

(2) The CPU pushes the program counter and the status

register to the system stack area (area indicated by the

system mode stack pointer).

(3) The CPU sets a value in the CPU interrupt mask register

<IFF2 to 0> that is higher by 1 than the value of the

accepted interrupt level. However, if the value is 7, 7 is

set without an increment.

(4) The CPU sets the <SYSM> ﬂag of the status register to 1

and enters the system mode.

Resetting initializes the CPU mask registers <IFF2 to 0>

to 7; therefore, maskable interrupts are disabled.

The addresses 008000H to 0081FFH (512 bytes) of the

TLCS-900 are assigned for interrupt processing entry area.

(5) The CPU jumps to address 8000H + interrupt vector,

then starts the interrupt processing routine.

In minimum mode, all the above processing is completed

15 states

in

(1.5µs @ 20MHz). In maximum mode, it is com-

pleted in 17 states.

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TMP96C141AF

Table 3.3 (1) TMP96C141AF Interrupt Table

High-Speed

Micro DMA

Start Vector

Vector Value

Default Priority

Type

Interrupt Source

Start Address

“V”

1

2

Reset

, or SW10 instruction

0 0 0 0 H

0 0 1 0 H

0 0 2 0 H

0 0 3 0 H

0 0 4 0 H

0 0 5 0 H

0 0 6 0 H

0 0 7 0 H

0 0 8 0 H

0 0 9 0 H

0 0 A 0 H

0 0 B 0 H

0 0 C 0 H

0 0 D 0 H

0 0 E 0 H

0 0 F 0 H

0 1 0 0 H

0 1 1 0 H

0 1 2 0 H

0 1 3 0 H

0 1 4 0 H

0 1 5 0 H

0 1 6 0 H

0 1 7 0 H

0 1 8 0 H

0 1 9 0 H

0 1 A 0 H

0 1 B 0 H

0 1 C 0 H

0 1 D 0 H

0 1 E 0 H

0 1 F 0 H

8 0 0 0 H

8 0 1 0 H

8 0 2 0 H

8 0 3 0 H

8 0 4 0 H

8 0 5 0 H

8 0 6 0 H

8 0 7 0 H

8 0 8 0 H

8 0 9 0 H

8 0 A 0 H

8 0 B 0 H

8 0 C 0 H

8 0 D 0 H

8 0 E 0 H

8 0 F 0 H

8 1 0 0 H

8 1 1 0 H

8 1 2 0 H

8 1 3 0 H

8 1 4 0 H

8 1 5 0 H

8 1 6 0 H

8 1 7 0 H

8 1 8 0 H

8 1 9 0 H

8 1 A 0 H

8 1 B 0 H

8 1 C 0 H

8 1 D 0 H

8 1 E 0 H

8 1 F 0 H

–

INTPREV:

INTUNDEF:

SWI 3 Instruction

SWI 4 Instruction

SWI 5 Instruction

SWI 6 Instruction

SWI 7 Instruction

NMI Pin

Privileged violation, or SWI1

Illegal instruction, or SWI2

–

3

–

4

–

Non-

Maskable

5

–

6

–

7

–

8

–

9

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

10

11

12

13

14

15

-

INTWD:

Watchdog timer

INTO pin

INT4 pin

INT5 pin

INT6 pin

INT7 pin

(Reserved)

INTT0:

16

17

18

19

20

21

22

23

24

25

26

27

28

–

8-bit timer 0

INTT1:

8-bit timer 1

INTT2:

8-bit timer 2/PWM0

8-bit timer 3/PWM1

16-bit timer 4 (TREG4)

16-bit timer 4 (TREG5)

16-bit timer 5 (TREG6)

16-bit timer 5 (TREG7)

Serial receive (Channel.0)

Serial send (Channel.0)

Serial receive (Channel.1)

Serial send (Channel.1)

A / D conversion completion

INTT3:

INTTR4:

Maskable

INTTR5:

INTTR6:

INTTR7:

INTRX0:

INTTX0:

INTRX1:

INTTX1:

INTAD:

(Reserved)

–

3.3.2 High-Speed Micro DMA

The TLCS-900 can process at very high speed com-

pared with the TLCS-90 micro DMA because it has transfer

parameters in dedicated registers in the CPU. Since those

dedicated registers are assigned as CPU control registers, they

can only be accessed by the LDC (privileged) instruction.

In addition to the conventional interrupt processing, the TLCS-

900 also has a high-speed micro DMA function. When an

interrupt is accepted, in addition to an interrupt vector, the CPU

receives data indicating whether processing is high-speed micro

DMA mode or general-purpose interrupt. If high-speed micro

DMA mode is requested, the CPU performs high-speed micro

DMA processing.

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TMP96C141AF

mode which is set by the CS/WAIT controller) can be

(1) High-Speed Micro DMA Operation

accessed by high-speed micro DMA processing.

There are two data transfer modes: one-byte mode and

one-word mode. Incrementing, decrementing, and ﬁxing the

transfer source/destination address after transfer can be done

in both modes. Therefore data can easily be transferred

betweenI/O and memory and between I/Os. For details of

transfer modes, see the description of transfer mode registers.

The transfer counter has 16 bits, so up to 65536 trans-

fers (the maximum when the initial value of the transfer counter

is 0000H) can be performed for one interrupt source by high-

speed micro DMA processing.

A the data transferred by the µDMA function, the transfer

nter was decreased.

When this counter is “0”H, the processor operates gen-

eral interrupt processing. At this time if the same channel of

interrupt is required next interrupt, the transfer counter starts

from 65536.

High-speed micro DMA operation starts when the accepted

interrupt vector value matches the micro DMA start vector

value set in the interrupt controller. The high-speed micro DMA

has four channels so that it can be set for up to four types of

interrupt source.

When a high-speed micro DMA interrupt is accepted,

data is automatically transferred from the transfer source

address to the transfer destination address set in the control

register, and the transfer counter is decremented. If the value in

the counter after decrementing is other than 0, high-speed

micro DMA processing is completed. If the value in the counter

after decrementing is 0, general-purpose interrupt processing

is performed. In read-only mode, which is provided for DRAM

refresh, the value in the counter is ignored and dummy read is

repeated.

The 32-bit control registers are used for setting transfer

source/destination addresses. However, the TLCS-900 has

only 24 address pins for output. A 16M-byte space is available

for the high-speed micro DMA. Also in normal mode operation,

the all address space (in other words, the space for system

Interrupt sources processed by high-speed micro DMA

processing are those with the high-speed micro DMA start

vectors listed in Table 3.3 (1).

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TMP96C141AF

The following timing chart is a high-speed µDMA cycle of

cept the Read-only mode is same as this)

the Transfer Address Increment mode (the other mode exe-

(Condition: MIN mode, 16bit Bus width for 16M Byte, 0 wait)

(2) Register Conﬁguration (CPU Control Register)

These Control Registers cannot be set only “LCD cr, r” instruction.

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TMP96C141AF

(3) Transfer Mode Register Details

This condition is 16-bit bus width and 0 wait of source/destination address space.

Note: n: corresponds to high-speed µDMA channels 0 - 3.

DMADn +/DMASn + : Post-increment (Increments register value after transfer.)

DMADn -/DMASn - :

Post-decrement (Decrement register value after transfer.)

All address space (the space for system mode) can be

for transfer mode control.

accessed by high-speed µDMA. Do not use undeﬁned codes

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TMP96C141AF

When the hardware conﬁguration is as follows:

ity setting register, and a register for storing the high-speed

micro DMA start vector. The interrupt request ﬂip-ﬂop is used

to latch interrupt requests from peripheral devices. The ﬂip-ﬂop

is cleared to 0 at reset, when the CPU reads the interrupt

channel vector after the acceptance of interrupt, or when the

CPU executes an instruction that clears the interrupt of that

channel (writes 0 in the clear bit of the interrupt priority setting

register).

DRAM mapping size:

DRAM data bus size:

= 1MB

= 8 bits

DRAM mapping address range: = 100000H to

1FFFFFH

Set the following registers ﬁrst; refresh is performed

automatically.

For example, to clear the INT0 interrupt request, set the

register after the

as follows.

DI instruction

➀ Register initial value setting

INTE0AD←---- 0 ---

Zero-clears the INT0 Flip-Flop.

LD

LDC

LD

XIX, 100000H

DMAS0,XIX

A, 00001010B

DMAM0,

…

mapping start address

The status of the interrupt request ﬂip-ﬂop is detected by

reading the clear bit. Detects whether there is an interrupt

request for an interrupt channel.

…

LDC

A read only mode (for

DRAM refresh)

The interrupt priority can be set by writing the priority in

the interrupt priority setting register (e.g., INTE0AD, INTE45,

etc.) provided for each interrupt source. Interrupt levels to be

set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis-

ables the corresponding interrupt request. The priority of the

non-maskable interrupt (NMI pin, watchdog timer, etc.) is ﬁxed

to 7. If interrupt requests with the same interrupt level are gen-

erated simultaneously, interrupts are accepted in accordance

with the default priority (the smaller the vector value, the higher

the priority).

The interrupt controller sends the interrupt request with

the highest priority among the simultaneous interrupts and its

vector address to the CPU. The CPU compares the priority

value <IFF2 to 0> set in the Status Register by the interrupt

request signal with the priority value sent; if the latter is higher,

the interrupt is accepted. Then the CPU sets a value higher

than the priority value by 1 in the CPU SR<IFF2 to 0>. Interrupt

requests where the priority value equals or is higher than the

set value are accepted simultaneously during the previous

interrupt routine. When interrupt processing is completed (after

execution of the RETI instruction), the CPU restores the priority

value saved in the stack before the interrupt was generated to

the CPU SR<IFF2 to 0>.

➁ Timer Setting

Set the timers so that interrupts are generated at

intervals of 62.5µs or less.

➂ Interrupt controller setting

Set the timer interrupt mask h other interrupt mask.

Write the above timer interrupt vector value in the

High-Speed µDMA start vector register, DMA0V.

(Operation description)

The DRAM data bus is an 8-bit bus and the micro

DMA is in read-only mode (4 bytes), so refresh is per-

formed four times per interrupt.

When a 512 refresh/8ms DRAM is connected, DRAM

refresh is performed sufﬁciently if the micro DMA is

started every 15.625µs x 4 = 62.4µs or less, since the

timing is 15.625µs/refresh.

(Overhead)

Each processing time by the micro DMA is 1.8µs (18

states) @ 20MHz with an 8-bit data bus.

In the above example, the micro DMA is started every

62.5µs, 1.8µs/62.5µs = 0.029; thus, the overhead is

2.9%.

The interrupt controller also has four registers used to

store the high-speed micro other DMA start vector. These are I/

O registers; unlike other DMA registers (DMAS, DMAD, DMAM,

and DMAC), they can be accessed in either normal or system

mode. Writing the start vector of the interrupt source for the

micro DMA processing (see Table 3.3 (1)), enables the corre-

sponding interrupt to be processed by micro DMA processing.

The values must be set in the micro DMA parameter registers

(e.g., DMAS and DMAD) prior to the micro DMA processing.

3.3.3 Interrupt Controller

Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The

left half of the diagram shows the interrupt controller; the right

half includes the CPU interrupt request signal circuit and the

HALT release signal circuit.

Each interrupt channel (total of 20 channels) in the inter-

rupt controller has an interrupt request ﬂip-ﬂop, interrupt prior-

16

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TMP96C141AF

Figure 3.3.3 (1) Block Diagram of Interrupt Controller

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TMP96C141AF

(1) Interrupt Priority Setting Register

18

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(2) External Interrupt Control

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TMP96C141AF

(3) High-Speed Micro DMA Start Vector

tor). When both match, the interrupt is processed in micro

DMA mode for the channel whose value matched.

If the interrupt vector matches more than one chan-

nel, the channel with the lower channel number has a

higher priority.

When the CPU reads the interrupt vector after accepting an inter-

rupt, it simultaneously compares the interrupt vector with each

channel’s micro DMA start vector (bits 4 to 8 of the interrupt vec-

Micro DMA0 Start Vector

(read-modify-write is not possible.)

7

6

5

4

3

2

1

0

bit Symbol

Read / Write

After reset

DMA0V8

DMA0V7

DMA0V6

DMA0V5

DMA0V4

DMA0V

(007CH)

W

0

(read-modify-write is not possible.)

Micro DMA1 Start Vector

7

4

3

2

1

0

bit Symbol

DMA1V8

DMA1V7

DMA1V6

DMA1V5

DMA1V4

DMA1V

(007DH)

Read / Write

W

0

After reset

0

(read-modify-write is not possible.)

Micro DMA2 Start Vector

7

4

3

2

1

0

bit Symbol

DMA2V8

DMA2V7

DMA2V6

DMA2V5

DMA2V4

DMA2V

(007EH)

Read / Write

W

0

After reset

0

(read-modify-write is not possible.)

Micro DMA3 Start Vector

7

4

3

2

1

0

bit Symbol

Read / Write

After reset

DMA3V8

DMA3V7

DMA3V6

DMA3V5

DMA3V4

DMA3V

(007FH)

W

0

(4) Notes

while reading the interrupt vector after accepting the inter-

rupt. If so, the CPU would read the default vector 00A0H

and start the interrupt processing from the address

80A0H.

To avoid this, make sure that the instruction used to

clear the interrupt request ﬂag comes after the DI instruction.

The instruction execution unit and the bus interface unit of this

CPU operate independently of each other. Therefore, if the instruc-

tion used to clear an interrupt request ﬂag of an interrupt is fetched

before the interrupt is generated, it is possible that the CPU might

execute the fetched instruction to clear the interrupt request ﬂag

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3.4 Standby Function

other built-in circuits halt. Power consump-

tion is reduced to 1/10 or less than that dur-

ing normal operation.

When the HALT instruction is executed, the TMP96C141AF

enters RUN, IDLE, or STOP mode depending on the contents

of the HALT mode setting register.

(3) STOP

: All internal circuits including the built-in oscil-

lator halt. This greatly reduces power con-

sumption. The states of the port pins in

STOP mode can be set as listed in Table 3.4

(1) using the I/O register

(1)

RUN : Only the CPU halts; power consumption

remains unchanged.

(2)

IDLE : Only the built-in oscillator operates, while all

WDMOD<DRVE>bit.

7

6

5

4

3

2

1

0

Bit Symbol

Read/Write

After reset

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

WDMOD

(005CH)

R/W

1

0

16

1 : WDT

Enable

00 : 2 / fc

Warming up Standby mode

1: Connects

watchdog

timer

output to

RESET pin

internally.

1: Drive pin

even in

STOP

18

01 : 2 / fc

time

00 : RUN

01 : STOP

10 : IDLE

mode

20

16

10 : 2 / fc

0 : 2 /fc

Function

22

18

11 : 2 / fc

1 : 2 /fc

mode.

Detection time

11 : Don’t care

When STOP mode is released by other than a reset, the

allow the oscillator to stabilize.

system clock output starts after allowing some time for warm-

ing up set by the warming-up counter fro stabilizing the bulit-in

oscillator. To release STOP mode by reset, it is necessary to

To release standby mode, a reset or an interrupt is used.

To release IDLE or STOP mode, only an interrupt by the NMI or

INT0 pin, or a reset can be used. The details are described

below:

Standby Release by Interrupt

Interrupt Level

Interrupt Mask (IFF2 to 0)

≤ Interrupt Request Level

Interrupt Mask (IFF2 to 0)

> Interrupt Request Level

Standby Mode

Can be released by any interrupt.

After standby mode is released, interrupt processing starts.

Can only be released by INT0 pin.

Processing resumes from address next to HALT instruction.

RUN

IDLE

Can only be released by NMI or INT0 pin. After standby mode

is released, interrupt processing starts.

↑

STOP

↑ (Note)

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Table 3. 4 (1) Pin States in STOP Mode

96C141AF

96CM40/96PM40

Pin Name

I/O

DRVE = 0

DRVE = 1

DRVE = 0

DRVE = 1

Input mode/AD0 ~ 7

Output mode

–

x

–

x

–

P0

P1

Output

Input mode/AD8 ~ 15

Output mode/A8 ~ 15

–

x

–

x

–

Output

Input mode

Output mode/A0 ~ 7, A16 ~ 23

PD*

Output

PD*

Output

P2

P30 (RD), P31 (WR)

P32 ~ P37

Output

–

“1” Output

–

Output

Input mode

Output mode

PU

Output

Input mode

Output mode

PU*

PU

Output

P40, P41

Input mode

Output mode

PD*

PD

Output

P42 (CS2/CAS2)

P5

P6

Input

–

Input mode

Output mode

PU*

PU

Output

Input mode

Output mode

PU*

PU

Output

P7

Input mode

Output mode

PU*

PU

Output

P80 ~ P86

P87 (INT0)

P9

←

Input mode

Output mode

PU

Output

Input mode

Output mode

PU*

PU

Output

NMI

WDTOUT

ALE

Input

Output

“0”

Input

Output

“0”

Output

Input

CLK

RESET

EA

–

“1”

Input

–

Input

–

Input

X1

Input

X2

Output

“1”

–:

Input for input mode/input pin is invalid; output mode/output pin is at high impedance.

Input: Input enable state

Input: Input gate in operation. Fix input voltage to 0 or 1 so that input pin stays constant.

Output: Output state

PU:

PD:

*:

Programmable pull-up pin. Fix the pin to avoid through current since the input gate operates when a pull-up resistor is not set.

Programmable pull-down pin. Fix the pin like a pull-up pin when a pull-down resistor is not set.

Input gate disable state. No through current even if the pin is set to high impedance.

Cannot set.

x:

Note: Port registers are used for controlling programmable pull-up/pull-down. If a pin is also used for an output function (e.g., TO1) and the output function

is speciﬁed, whether pull-up or pull-down is selected depends on the output function data. If a pin is also used for an input function, whether pull-up or

pull-down is selected depends on the port register setting value only.

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15, RD, and WR.

3.5 Functions of Ports

These port pins have I/O functions for the built-in CPU

and internal I/Os as well as general-purpose I/O port func-

tions. Table 3.5 lists the function of each port pin.

The TMP96CM40F/TMP96PM40F has 65 bits for I/O ports.

The TMP96C141AF, TMP96C041AF has 47 bits for I/O ports

because Port0, Port1, P30, and P31 are dedicated pins for

AD0 to 7, AD8 to

(R:

↑ = With programmable pull-up resistor

↓ = WIth programmable pull-down

Table 3.5 Functions of Ports

Number of

Pins

Port Name

Pin Name

Direction

R

Direction Setting Unit

Pin Name for Built-in Function

Port0

Port1

Port2

Port 3

P00 ~ P07

P10 ~ P17

P20 ~ P27

8

I/O

–

↓

Bit

AD0 ~ AD7

AD8 ~ AD15/ A8 ~ A15

A0 ~ A7/ A16 ~ A23

P30

P31

P32

P33

P34

P35

P36

P37

1

Output

I/O

–

↑

(Fixed)

Bit

RD

WR

HWR

WAIT

BUSRQ

BUSAK

R/W

RAS

Port4

P40

P41

P42

1

I/O

↑

↓

Bit

CS0 / CAS0

CS1 / CAS1

CS2 / CAS2

Port5

Port6

Port7

P50 ~ P53

P60 ~ P67

4

8

Input

I/O

–

(Fixed)

Bit

AN0 ~ AN3

↑

PG00 ~ PG03, PG10 ~ PG13

P70

P71

P72

P73

1

I/O

↑

Bit

T10

TO1

TO2

TO3

Port8

P80

P81

P82

P83

P84

P85

P86

P87

1

I/O

↑

Bit

T14/INT4

T15/INT5

TO4

TO5

T16 / INT6

T17 / INT7

TO6

INT0

Port9

P90

P91

P92

P93

P94

P95

1

I/O

↑

Bit

TXD0

RXD0

CTS0

TXD1

RXD1

SCLK1

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TMP96C141AF

Resetting makes the port pins listed below function as

general-purpose I/O ports.

I/O pins programmable for input or output function as

input ports.

• P00 ~ P07

• P10 ~ P17

• P30

→AD0 ~ AD7

→AD8 ~ AD15

→RD

• P31

→WR

To set port pins for built-in functions, a program is

required.

Bus release function

The TMP96C141AF has the internal pull-up and pull-

down resistors to ﬁx the bus control signals at bus release.

Table 3.5 (1) shows the pin condition at bus release

(BUSAK) = “L”).

Since the TMP96C141AF has an external ROM, some

ports are permanently assigned to the CPU.

Pin state at bus release

Function mode

Pin Name

Port mode

P00 - P07

(AD0 - AD7)

P10 - P17

No status change (these pins are not “Hz”)

These pins are “Hz”.

(AD8 - AD15)

P30 (RD)

P31 (WR)

These pins are “Hz”.

(“Hz” status after these pins are driven to high level.)

↑

P32 (HWR)

P37 (RAS)

The output buffer is “OFF” after these pins are drinen high.

These pins are added in the internal resistor of pull-up. It’s

no relation for the value of output latch.

P36 (R/W)

P40 (CS0/CAS0)

P41 (CS1/CAS1)

↑

P42 (CS2/CAS2)

(*) ↑

P20 - P27

(A16 - A23)

P42 (CS2/CAS2)

The output buffer is “OFF” after these pins are drinen high.

These pins are added in the internal resistor of pull-down.

It’s no relation for the value of output latch.

(*) P42 has the resistor of programmable pull-down, but

when the bus are released, P42 pin is added a resistor of pull-

P10 - P17 (AD8 - AD15)

P30 (RD)

up.

P31 (WR)

That is, when it is used for bus release (BUSAK = “0”), the

When the bus is released, both internal memory and

internal I/O cannot be accessed. But the internal I/O continues

to run. Therefore, be careful about releasing time and set the

setection time WDT.

pins of below need pull-up or pull-down resistor for an external

circuit.

P00 - P07 (AD07)

Figure 3.5. Example of external bus interface using bus release function.

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3.5.1 Port 0 (P00 - P07)

3.5.2 Port 1 (P10 - P17)

Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a

bit basis using control register P0CR to 0 and sets Port 0 to

input mode.

In addition to functioning as a general purpose I/O port,

Port 0 also functions as an address data bus (AD0 to 7). To

access external memory, Port 0 functions as an address data

bus (AD 0 to 7) and all bits of the control register P0CR are

cleared to 0.

Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a

bit basis using control register P1CR and function register

P1FC. Resetting resets all bits of output latch P1, control reg-

ister P1CR, and function register P1FC to 0 and sets Port 1 to

input mode.

In addition to functioning as a general purpose I/O port,

Port 1 also functions as an address data bus (AD8 to 15) or an

address bus (A8 to 15).

With the TMP96C141AF/TMP96C041AF, which comes

with an external ROM, Port 0 always functions as an address

data bus (AD0 to 7) regardless of the value set in control regis-

ter P0CR.

With the TMP96C141AF/TMP96C041AF, which comes

with an external ROM, Port 1 always functions as an address

data bus (AD8 to 15) regardless of the value set in control reg-

ister P1CR.

Figure 3.5 (1). Port 0

Figure 3.5 (2). Port 1

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TMP96C141AF

Port 0 Register

Figure 3.5 (3). Registers for Ports 0 and 1

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TMP96C141AF

3.5.3 Port 2 (P20 - P27)

input mode and connects a pull-down resistor. To disconnect

the pull-down resistor, write 1 in the output latch.

In addition to functioning as a general-purpose I/O port,

Port 2 also functions as an address data bus (A0 to 7) and an

address bus (A16 to 23).

Port 2 is an 8-bit general-purpose I/O port. I/O can be set on

bit basis using the control register P2CR and function register

P2FC. Resetting resets all bits of output latch P2, control regis-

ter P2CR and function register P2FC to 0. It also sets Port 2 to

Figure 3.5 (4). Port 2

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TMP96C141AF

Figure 3.5 (5). Registers for Port 2

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3.5.4 Port 3 (P30 - P37)

Port 3 is an 8-bit general-purpose I/O port.

With the TMP96C141AF, when P30 pin is deﬁned as RD

signal output mode (<P30F> = 1), clearing the output latch

register <P30> to 0 outputs the RD strobe (used for the

pseudo static RAM) from the P30 pin even when the internal

address area is accessed.

If the output latch register <P30> remains 1, the RD

strobe signal is output only when the external address area is

accessed.

I/O can be set on a bit basis, but note that P30 and P31

are used for output only. I/O is set using control register P3CR

and function register P3FC. Resetting resets all bits of output

latch P3, control register P3CR (bits 0 and 1 are unused), and

function register P3FC to 0. Resetting also outputs 1 from P30

and P31, sets P32 to P37 to input mode, and connects a pull-

up resistor.

In addition to functioning as a general-purpose I/O port,

Port 3 also functions as an I/O for the CPU’s control/status sig-

nal.

With the TMP96C141AF/TMP96C041AF, which comes

with an external ROM, Port 30 outputs the RD signal; P31, the

WR signal, regardless of the values set in function registers

P30F and P31F.

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TMP96C141AF

Figure 3.5 (6). Port 3 (P30, P31, P32, P35, P36, P37)

30

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TMP96C141AF

Figure 3.5 (7). Port 3 (P33, P34)

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TMP96C141AF

Port 3 Register

Note: When P33/WAIT pin is used as a WAIT pin, set P#CR <P33C> to “0” and Chip Select/Wait control register.

Figure 3.5 (8). Registers for Port 3

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3.5.5 Port 4 (P40 - P42)

In addition to functioning as a general-purpose I/O port,

Port 4 also functions as a chip select output signal (CS0 to

CS2 or CAS0 to CAS2).

Port 4 is a 3-bit general-purpose I/O port. I/O can be set on a

bit basis using control register P4CR and function register

P4FC. Resetting does the following:

- Sets the P40 and P42 output latch registers to 1.

- Resets all bits of the P42 output latch register, the control

register P4CR, and the function register P4FC to 0.

- Sets P40 and P41 to input mode and connects a pull-up

resistor.

- Sets P42 to input mode and connects a pull-down resistor.

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TMP96C141AF

Figure 3.5 (9). Port 4

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Port 4 Register

Note: To output chip select signal (CS0/CAS0 to CS2/CAS2), set the corresponding

bits of the control register P4CR and the function register to P4FC.

The BOCS, B1CS, and B2CS registers of the chip select/wait controller are used

to select the CS/CAS function.

Figure 3.5 (10). Registers for Port 4

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TMP96C141AF

3.5.6 Port 5 (P50 - P53)

Port 5 is a 4-bit input port, also used as an analog input pin.

Figure 3.5 (11). Port 5

Port 5 Register

7

6

5

4

3

2

1

0

P5

(000DH)

bit Symbol

Read/Write

After reset

P53

P52

P51

P50

R

Input mode

Note: The input channel selection of A/D Converter is set by A/D Converter mode register ADMOD2.

Figure 3.5 (12). Registers for Port 5

36

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3.5.7 Port 6 (P60 - P67)

assigned to P60 to P63; PG1, to P64 to P67. Writing 1 in the

corresponding bit of the port 6 function register (P6FC)

enables PG output. Resetting resets the function register

P6FC value to 0, and sets all bits to ports.

Port 6 is an 8-bit general-purpose I/O port. I/O can be set on

bit basis. Resetting sets Port 6 as an input port and connects

a pull-up resistor. It also sets all bits of the output latch to 1. In

addition to functioning as a general-purpose I/O port, Port 6

also functions as a pattern generator PG0/PG1 output. PG0 is

Figure 3.5 (13). Port 6

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TMP96C141AF

Port 6 Register

Figure 3.5 (14). Registers for Port 6

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3.5.8 Port 7 (P70 - P73)

71 as an 8-bit timer output (TO1), Port 72 as a PWM0 output

(TO2), and Port 73 as a PWM1 output (TO3) pin. Writing 1 in

the corresponding bit of the Port 7 function register (P7FC)

enables output of the timer. Resetting resets the function regis-

ter P7FC value to 0, and sets all bits to ports.

Port 7 is a 4-bit general-purpose I/O port. I/O can be set on bit

basis. Resetting sets Port 7 as an input port and connects a

pull-up resistor. In addition to functioning as a general-purpose

I/O port, Port 70 also functions as an input clock pin TI0; Port

Figure 3.5 (15). Port 7

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TMP96C141AF

Figure 3.5 (16). Registers for Port 7

40

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3.5.9 Port 8 (P80 - P83)

clocks, an output for 16-bit timer F/F 4, 5 and 6 output, and an

input for INT0. Writing 1 in the corresponding bit of the Port 8

function register (P8FC) enables those functions. Resetting

resets the function register P8FC value to 0, and sets all bits to

ports.

Port 8 is an 8-bit general-purpose I/O port. I/O can be set on a

bit basis. Resetting sets Port 8 as an input port and connects

a pull-up resistor. It also sets all bits of the output latch register

P8 to 1. In addition to functioning as a general-purpose I/O

port, Port 8 also functions as an input for 16-bit timer 4 and 5

(1) P80 ~ P86

Figure 3.5 (17). Port 8 (P80 - P86)

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TMP96C141AF

an INT0 pin for external interrupt request input.

(2)

P87 (INT0)

Port 87 is a general-purpose I/O port, and also used as

Figure 3.5 (18). Port 87

42

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TMP96C141AF

Figure 3.5 (19). Registers for Port 8

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TMP96C141AF

3.5.10 Port 9 (P90 - P95)

Resetting resets the function register value to 0 and sets

all bits to ports.

Port 9 is a 6-bit general-purpose I/O port. I/Os can be set on a

bit basis. Resetting sets Port 9 to an input port and connects a

pull-up resistor. It also sets all bits of the output latch register to

1.

(1)

Port 90 and 93 (TXD0/TXD1)

In addition to functioning as a general-purpose I/O port, Port 9

can also function as an I/O for serial channels 0 and 1. Writing

1 in the corresponding bit of the port 9 function register (P9FC)

enables this function.

Ports 90 and 93 also function as serial channel TXD

output pins in addition to I/O ports.

They have a programmable open drain function.

Figure 3.5 (20). Ports 90 and 93

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TMP96C141AF

(2)

Ports 91 and 94 (RXD0, 1)

input pins for serial channels.

Ports 91 and 94 are I/O ports, and also used as RXD

Figure 3.5 (21). Ports 91 and 94

(3)

Port 92 (CTS/SCKL0)

for serial channel0; additionally, the CTS0 pin, and also

as a SCKL0 I/O pin.

Port 92 is an I/O port. It is also used as a CTS input pin

Figure 3.5 (22). Port 92

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TMP96C141AF

(4)

Port 95 (SCLK)

Port 95 is a general-purpose I/O port. It is also used as

an SCLK I/O pin for serial channel 1.

Figure 3.5 (23). Port 95

46

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TMP96C141AF

Figure 3.5 (24). Registers for Port 9

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TMP96C141AF

3.6 Chip Select/Wait Control

ister is used to specify data bus size. Setting this bit to

0 accesses the memory in 16-bit data bus mode; set-

ting it to 1 accesses the memory in 8-bit data bus

mode.

Changing data bus size depending on the access

address is called dynamic bus sizing. Table 3.6 (2)

shows the details of the bus operation.

TMP96C141AF has a built-in chip select/wait controller used

to control chip select (CS0 - CS2 pins), wait (WAIT pin), and

data bus size (8 or 16 bits) for any of the three block address

areas.

3.6.1 Control Registers

Table 3.6 (1) shows control registers

One block address areas are controlled by 1-byte CS/

WAIT control registers (B0CS, B1CS, and B2CS). Registers

can be written to only when the CPU is in system mode. (There

are two CPU modes: system and normal.) The reason is that

the settings of these registers have an important effect on the

system.

(5)

Wait control

Control register bits 3 and 2 (B0W1, 0; B1W1, 0; B2W1,

0) are used to specify the number of waits. Setting these

bits to 00 inserts a 2-state wait regardless of the WAIT

pin status. Setting them to 01 inserts a 1-state wait

regardless of the WAIT status. Setting them to 10

inserts a 1-state wait and samples the WAIT pin status.

If the pin is low, inserting the wait maintains the bus

cycle until the pin goes high. Setting them to 11 com-

pletes the bus cycle without a wait regardless of the

WAIT pin status.

(1)

Enable

Control register bit 7 (B0E, B1E, and B2E) is a master

bit used to specify enable (1)/disable (0) of the setting.

Resetting B0E and B1E to disable (0) and B2E to

enable (1).

Resetting sets these bits to 00 (2-state wait mode).

(2) System only speciﬁcation

(6)

Address area speciﬁcation

Control register bit 6 (B0SYS, B1SYS, and B2SYS) is

used to specify enable/disable of the setting depend-

ing on the CPU operating mode (system or normal).

Setting this bit to 0 enables setting (Address space for

CS, Wait state, Bus size, etc.) regardless of the CPU

operating mode; setting it to 1 enables setting in sys-

tem mode but disables setting in normal mode.

Control register bits 1 and 0 (B0C1, 0; B1C1, 0; B2C1,

0) are used to specify the target address area. Setting

these bits to 00 enables settings (CS output, Wait

state, Bus size, etc.) as follows:

* CS0 setting enabled when 7F00H to 7FFFH is

accessed.

* CS1 setting enabled when 480H to 7FFFH is

accessed.

* CS2 setting enabled when 8000H to 3FFFFFFH is

accessed, for the TMP96C141, which does not have a

built-in ROM.

Resetting clears bit 6 to 0.

Bit 6 is mainly used when external memory data should

not be accessed in normal mode (i.e., for system mode

only memory data for the operating system).

(3)

CS/CAS Waveform select

CS2 setting enabled when 10000H to 3FFFFFH is

accessed for the TMP96CM40/TMP96PM40, which

has built-in

Control register bit 5 (B0CAS, B1CAS, and B2CAS) is

used to specify waveform mode output from the chip

select pin (CS0/CAS0 - CS2/CAS2). Setting this bit to

0 speciﬁes CS0 to CS2 waveforms; setting it to 1

speciﬁes CAS0 to CAS2 waveforms.

ROM/PROM

Setting bits to 01 enables setting for all CS’s blocks

and outputs a low strobe signal (CS0/CAS0 ~ CS2/

CAS2) from chip select pins when 400000H to

7FFFFFH is accessed. Setting bits to 10 enables them

800000H to BFFFFFH is accessed. Setting bits to 11

enables them when C00000H to FFFFFFH is

accessed.

Resetting clears bit 5 to 0.

(4)

Data bus size select

Bit 4 (B0BUS, B1BUS, and B2BUS) of the control reg-

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Table 3.6 (1) Chip Select/Wait Control Register

Code

Name

Address

7

6

5

4

3

2

1

0

B0E

W

B0SYS

B0CAS

B0BUS

B0W1

B0W0

B0C1

W

B0C0

W

0

W

0

W

0

W

0

W

0

Block0

CS/WAIT

control

0

B0CS

0068H

1 : CS/CAS 1 : SYSTEM

Enable

0 : CSO

1 : CAS0

0 : 16-bit

Bus

1 : 8-bit

Bus

00 : 2WAIT

01 : 1WAIT

10 : 1WAIT + n

11 : 0WAIT

00 : 7F00H ~ 7FFFH

01 : 400000H ~

10 : 800000H ~

11 : C00000H ~

register

only

B1E

W

B1SYS

B1CAS

B1BUS

B1W1

B1W0

B1C1

B1C0

W

0

W

0

W

0

W

0

W

0

W

0

Block1

0

CS/WAIT

control

register

B1CS

B2CS

0069H

006AH

1 : CS/CAS 1 : SYSTEM

Enable

0 : CS1

1 : CAS1

0 : 16-bit

Bus

1 : 8-bit

Bus

00 : 2WAIT

01 : 1WAIT

10 : 1WAIT + n

11 : 0WAIT

00 : 480H ~ 7FFFH

01 : 400000H ~

10 : 800000H ~

11 : C00000H ~

only

B2E

W

B2SYS

B2CAS

B2BUS

B2W1

B2W0

B2C1

B2C0

W

0

W

0

W

0

W

0

W

0

W

0

Block2

1

0

CS/WAIT

control

register

1 : CS/CAS 1 : SYSTEM

Enable only

0 : CS2

1 : CAS2

0 : 16-bit

Bus

1 : 8-bit

Bus

00 : 2WAIT

01 : 1WAIT

10 : 1WAIT +n

11 : 0WAIT

00 : 8000H ~

01 : 400000H ~

10 : 800000H ~

11 : C00000H ~

Note: With only block 2, enable (16-bit data bus, 2-wait mode) after reset.

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Table 3.6 (2) Dynamic Bus Sizing

CPU Data

Operand

Data Size

Operand

Start Address

Memory

CPU Address

Data Size

D15 - D8

D7 - D0

2n + 0

(even number)

8 bits

16 bits

8 bits

2n + 0

2n + 1

xxxxx

b7 - b0

xxxxx

8 bits

2n + 1

(odd number)

xxxxx

16 bits

b7 - b0

2n + 0

2n + 1

xxxxx

b7 - b0

b15 - b8

8 bits

16 bits

8 bits

2n + 0

(even number)

2n + 0

b15 - b8

b7 - b0

16 bits

2n + 1

2n + 2

xxxxx

b7 - b0

b15 - b8

2n + 1

(odd number)

2n + 1

2n + 2

b7 - b0

xxxxx

b15 - b8

16 bits

2n + 0

2n + 1

2n + 2

2n + 3

xxxxx

b7 - b0

b15 - b8

b23 - b16

b31 - b24

8 bits

2n + 0

(even number)

2n + 0

2n + 2

b15 - b8

b31 - b24

b7 - b0

b23 - b16

16 bits

32 bits

2n + 1

2n + 2

2n + 3

2n + 4

xxxxx

b7 - b0

b15 - b8

b23 - b16

b31 - b24

8 bits

2n + 1

(odd number)

2n + 1

2n + 2

2n + 4

b7 - b0

b23 - b16

xxxxx

b15 - b8

b31 - b24

16 bits

xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active.

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3.6.2 Chip Select Image

bytes) for CS1 are mapped there mainly for possible exten-

sions to external RAM.

An image of the actual chip select is shown below. Out of the

whole memory area, address areas that can be speciﬁed are

divided into four parts. Addresses from 000000H to 3FFFFFH

are divided differently: 7F00H to 7FFFH is speciﬁed for CS0;

480H to 7FFFH, for CS1; and 8000H to 3FFFFFH, for CS2.

The reason is that a device other than ROM (i.e., RAM or I/O)

might be connected externally.

The addresses 7F00 to 7FFFH (256 bytes) for CS0 are

mapped mainly for possible expansions to external I/O.

The addresses 480H to 7FFFH (approximately 31K

The addresses 8000H to 3FFFFFFH (approximately

4Mbytes) for CS2 are mapped mainly for possible extensions

to external ROM. After reset, CS2 is enabled in 16-bit bus and

2-wait. With the TMP96C141AF, which does not have a built-

in ROM, the program is externally read at address 8000H in

this setting (16-bit bus, 2-wait). With the TMP96CM40F/

TMP96PM40F, which has a built-in ROM, addresses from

8000H to FFFFFH are used as the internal ROM area; CS2 is

disabled in this area. After reset, the CPU reads the program

from the built-in ROM in 16-bit bus, 0-wait mode.

CS0

000000H

CS1

CS2

7F00H

B1C1, 0 = “00”

8000H

400000H

800000H

C00000H

FFFFFFH

B0C1, 0 = “00”

B2C1, 0 = “00”

B2C1, 0 = “01”

B2C1, 0 = “10”

B2C1, 0 = “11”

(Mainly for ROM)

B0C1, 0 = “01”

B0C1, 0 = “10”

B0C1, 0 = “11”

(Mainly for I/O)

B1C1, 0 = “01”

B1C1, 0 = “10”

B1C1, 0 = “11”

(Mainly for RAM)

Supplement 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip select/wait controller.

Supplement 2: External areas other than CS0 to CS2 are accessed in 16-bit data bus (0 wait) mode.

When using the chip select/wait controller, do not specify the same address area more than once. (However, when addresses 7F00H - 7FFFH

for CS0 and 480H - 7FFFH for CS1 are speciﬁed, in other words, speciﬁcations overlap, only the CS0 setting/pin is active.)

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3.6.3 Example of Usage

Figure 3.6 (1) is an example in which an external memory is con-

nected to the TMP96C141AF. In this example, a ROM is con-

nected using 16-bit Bus; a RAM is connected using 8-bit Bus.

Figure 3.6 (1). Example of External Memory Connection (ROM = 16 bits, RAM and I/O = 8 bits)

Resetting sets pins CS0 to CS2 to input port mode. CS0

and CS1 are set high due to an internal pull-up resistor; CS2,

low due to an internal pull-down resistor. The program used to

set these pins is as follows:

P4CR EQU

P4FC EQU

B0CS EQU

B1CS EQU

B2CS EQU

0EH

10H

68H

69H

6AH

LD

(BOCS), 90H

(B1CS), 9CH

(B2CS), 84H

(P4CR), 07H

(P4FC), 07H

; CS0 = 8 bits, 2WAIT, 7F00H ~ 7FFFH

; CS1 = 8 bits, 0WAIT, 480H ~ 7EFFH

; CS2 = 16 bits, 1WAIT, 8000H ~ 3FFFFFH

CSO, CS1, CS2 output mode setting

)

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3.6.4 How to Start with an 8-Bit Data Bus

Resetting sets the CS2 pin low due to an internal pull-down

resistor; memory access starts in 16-bit data bus (2-wait)

mode. To start in 8-bit data bus mode, a special operation is

required. Operation is as described in the example below:

B2CS EQU

ORG

6AH

; CS2 register address

; RESET address

8000H

LDX

(B2CS), 9CH ; CS2 8-bit, 0WAIT, 8000H ~

After reset, the program reads the LDX (B2CS), 9CH

instruction in 16-bit data bus mode. LDX is a 6-byte instruc-

tion: the 2nd, 4th and 6th bytes are handled as dummies (i.e.,

only codes in the 1st, 3rd and 5th bytes are actually used).

Even if starting in 8-bit data bus mode, it is possible to pro-

gram so that the LDX instruction is executed and the block 2

area (8000H - 3FFFFFH) is accessed in 8-bit data bus mode

without any problem.

The above program does not include setting the P42/

CS2 pin to output; add a program to set the P4CR and P4FC

registers as required.

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3.7 8-bit Timers

stant cycle) output mode (1 timer)

Figure 3.7 (1) shows the block diagram of 8-bit timer

(timer 0 and timer 1).

The TMP96C141AF contains two 8-bit timers (timers 0 and 1),

each of which can be operated independently. The cascade

connection allows these timers to be used as 16-bit timer. The

following four operating modes are provided for the 8-bit tim-

ers.

Each interval timer consists of an 8-bit up-counter, 8-bit

comparator, and 8-bit timer register. Besides, one timer ﬂip-

ﬂop (TFF1) is provided for pair of timer 0 and timer 1.

Among the input clock sources for the interval timers, the

internal clocks of φ T1, φ T4, φT16, and φT256 are obtained

from the 9-bit prescaler shown in Figure 3.7 (2).

The operation modes and timer ﬂip-ﬂops of the 8-bit

timer are controlled by three control registers TMOD, TFFCR,

and TRUN.

• 8-bit interval timer mode (2 timers)

• 16-bit interval timer mode (1 timer)

• 8-bit programmable square wave pulse generation (PPG :

variable duty with variable cycle) output mode (1 timer)

• 8-bit pulse width modulation (PWM: variable duty with con-

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Figure 3.7 (1). Block Diagram of 8-Bit Timers (Timers 0 and 1)

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➀ Prescaler

φT1, φ T4, φT16, and φT256.

This prescaler can be run or stopped by the timer

operation control register TRUN <PRRUN>. Counting

starts when <PRRUN> is set to “1”, while the prescaler

is cleared to zero, and stops operation when

<PRRUN> is set to “0”. Resetting clears <PRRUN> to

“0”, which clears and stops the prescaler.

This 9-bit prescaler generates the clock input to the 8-

bit timers, 16-bit timer/event counters, and baud rate

generators by further dividing the fundamental clock

(fc) after it has been divided by 4 (fc/4).

Among them, 8-bit timer uses four types of clock:

Figure 3.7 (2). Prescaler

➁ Up-counter

Example : When TMOD <T10M1, 0> = 01, the over

ﬂow output of timer 0 becomes the input

clock of timer 1 (16 bit timer mode).

This is an 8-bit binary counter which counts up by the

input clock pulse speciﬁed by TMOD.

The input clock of timer 0 is selected from the external

clock from T10 pin and the three internal clocks φ T1

(8/fc), φ T4 (32/fc), and φT16 (128/fc), according to the

set value of TMOD register.

The input clock of timer 1 differs depending on the

operation mode. When set to 16-bit timer mode, the

overﬂow output of timer 0 is used as the input clock.

When set to any other mode than 16-bit timer mode,

the input clock is selected from the internal clocks φ T1

(8/fc), φ T16 (128/fc), and φT256 (2048/fc) as well as

the comparator output (match detection signal) of

timer 0 according to the set value of TMOD register.

When TMOD <T10M1, 0> = 00 and TMOD

<T1CLK1, 0> = 01, φ T1 (8/fc) becomes

the input of timer 1 (8 bit timer mode).

Operation mode is also set by TMOD register. When

reset, it is initialized to TMOD <T01M1, 0> = 00

whereby the up-counter is placed in the 8-bit timer

mode.

The counting and stop and clear of up-counter can be

controlled for each interval timer by the timer operation

control register TRUN. When reset, all up-counters will

be cleared to stop the timers.

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➂ Timer register

TREG0 should be enabled or disabled. It is disabled

when <DBEN> = 0 and enabled when they are set to

1.

This is an 8-bit register for setting an interval time.

When the set value of timer registers TREG0, TREG1,

matches the value of up-counter, the comparator

match detect signal becomes active. If the set value is

00H, this signal becomes active when the up-counter

overﬂows.

In the condition of double buffer enable state, the data

is transferred from the register buffer to the timer regis-

n

ter when the 2 -1 overﬂow occurs in PWM mode, or at

the PPG cycle in PPG mode. Therefore, during timer

mode, the double buffer cannot be used.

When reset, it will be initialized to <DBEN> = 0 to dis-

able the double buffer. To use the double buffer, write

data in the timer register, set <DBEN> to 1, and write

the following data in the register buffer.

Timer register TREG0 is of double buffer structure,

each of which makes a pair with register buffer.

The timer ﬂip-ﬂop control register TFFCR <DBEN> bit

controls whether the double buffer structure in the

Figure 3.7 (3). Conﬁguration of Timer Register 0

Note : Timer register and the register buffer are allocated to the same

memory address. When <DBEN> = 0, the same value is written in

the register buffer as well as the timer register, while when <DBEN>

= 1 only the register buffer is written.

The memory address of each timer register is as fol-

lows.

ﬂip-ﬂop inversion is enabled, the timer ﬂip-ﬂop is

inverted at the same time.

TREG0: 000022H

TREG1: 000023H

All registers are write-only and cannot be read.

⑤ Timer flip-flop (timer F/F: TFF1)

The status of the timer ﬂip-ﬂop is inverted by the match

detect signal (comparator output) of each interval timer

and the value can be output to the timer output pins

TO1 (also used as P71).

A timer F/F is provided for a pair of timer 0 and timer 1

and is called TFF1. TFF1 is output to TO1 pin.

➃Comparator

A comparator compares the value in the up-counter

with the values to which the timer register is set. When

they match, the up-counter is cleared to zero and an

interrupt signal (INTT0, INTT1) is generated. If the timer

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Figure 3.7 (4). Timer Operation Control Register (TRUN)

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Figure 3.7 (5). Timer Mode Control Register (TMOD)

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Figure 3.7 (6). Timer Flip-Flop Control Register (TFFCR)

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➀ Generating interrupts in a fixed cycle

The operation of 8-bit timers will be described below:

(1) 8-bit timer mode

To generate timer 1 interrupt at constant intervals using

timer 1 (INTT1), ﬁrst stop timer 1 then set the operation

mode, input clock, and a cycle to TMOD and TREG1

register, respectively. Then, enable interrupt INTT1 and

start the counting of timer 1.

Two interval timers 0, 1, can be used independently as

8-bit interval timer. All interval timers operate in the

same manner, and thus only the operation of timer 1

will be explained below.

Example: To generate timer 1 interrupt every 40

microseconds at fc = 16 MHz, set each

register in the following manner.

MSB

LSB

0

7

–

0

6

x

0

5

–

x

4

–

x

3

–

0

2

–

1

0

–

TRUN

←

–

Stop timer 1, and clear it to “0”.

TMOD

–

Set the 8-bit timer mode, and select φT1 (0.5µs @ fc = 16MHz) as the input clock.

TREG1

INTET10

TRUN

←

0

1

x

0

–

1

–

0

–

0

–

0

–

1

0

–

Set the timer register at 40µs φT1 = 50H.

Enable INTT1, and set it to “Level 5”.

Start timer 1 counting.

Note: x; don’t care

–; no change

Use the following table for selecting the input clock.

Table 3.7 (1) 8-Bit Timer Interrupt Cycle and Input Clock

Interrupt Cycle

(at fc = 16MHz)

Interrupt Cycle

(at fc = 20MHz)

Input Clock

Resolution

φT1 (8/fc)

φT4 (32/fc)

0.5µs ~ 128µs

2µs ~ 512µs

0.5µs

2µs

0.4µs ~ 102.4µs

1.6µs ~ 409.6µs

0.4µs

1.6µs

6.4µs

128µs

φT16 (128/fc)

φT256 (2048/fc)

8µs ~ 2.048ms

128µs ~ 32.708ms

8µs

6.4µs ~ 1.638ms

102.4µs ~ 2.621ms

128µs

Note: The input clock of timer 0 and timer 1 are different from as follows:

Timer 0: T10 input, φT1, φT4, φT16

Timer 1: Match Output of Timer 0, φT1, φT16, φT256

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➁ Generating a 50% duty square wave pulse

TO1 pin at fc = 16MHz, set each register in

the following procedures. Either timer 0 or

timer 1 may be used, but this example uses

timer 1.

The timer ﬂip-ﬂop (TFF1) is inverted at constant inter-

vals, and its status is output to timer output pin (TO1).

Example: To output a 3.0µs square wave pulse from

7

–

0

6

x

0

5

–

x

4

–

x

3

–

0

2

–

1

0

–

0

–

TRUN

←

Stop timer 1, and clear it to “0”.

TMOD

Set the 8-bit timer mode, and select φT1 (0.5µs @ fc = 16MHz) as the input clock.

TREG1

TFFCR

←

0

1

0

1

Set the timer register at 3.0µs ÷φT1 ÷2 = 3.

–

Clear TFF1 to “0”, and set to invert by the match detect signal from timer 1.

P7CR

P7FC

TRUN

←

x

1

x

–

x

–

1

–

x

Select P71 as TO1 pin.

)

–

Start timer 1 counting.

Note: x; don’t care

–; no change

Figure 3.7 (7). Square Wave (50% Duty) Output Timing Chart

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➂ Making timer 1 count up by match signal from timer

Set the 8-bit timer mode, and set the comparator out-

put of timer 0 as the input clock to timer 1.

0 comparator

Figure 3.7 (8). Timer 1 Count Up by Timer 0

➃ Output inversion with software

Note: The value of timer register cannot be read.

16-bit timer mode

The value of timer ﬂip-ﬂop (TFF1) can be inverted, inde-

pendent of timer operation.

(2)

Writing “00” into TFFCR <TFF1C1, 0> (memory

address: 000025h of bit 3 and bit 2) inverts the value of

TFF1.

A 16-bit interval timer is conﬁgured by using the pair of

timer 0 and timer 1.

To make a 16-bit interval timer by cascade connecting

timer 0 and timer 1, set timer 0/timer 1 mode register

TMOD <T10M1, 0> to “0, 1”.

➄ Initial setting of timer flip-flop (TFF1)

When set in 16-bit timer mode, the overﬂow output of

timer 0 will become the input clock of timer 1, regard-

less of the set value of TMOD <T1CLK1, 0>. Table 3.7

(2) shows the relation between the cycle of timer (inter-

rupt) and the selection of input clock.

The value of TFF1 can be initialized to “0” or “1”, inde-

pendent of timer operation.

For example, write “10” in TFFCR <TFF1C1, 0> to

clear TFF1 to “0”, while write “01” in TFFCR <TFF1C1,

0> to set TFF1 to “1”.

Table 3.7 (2) 16-Bit Timer (Interrupt) and Input Clock

Interrupt Cycle

(at fc = 16MHz)

Interrupt Cycle

(at fc = 20MHz)

Input Clock

Resolution

φT1 (8/fc)

φT4 (32/fc)

φT16 (128/fc)

0.5µs ~ 32.786ms

2µs ~ 131.072ms

8µs ~ 524.288ms

0.5µs

2µs

0.4µs ~ 26.214ms

1.6µs ~ 104.857ms

6.4µs ~ 419.430ms

0.4µs

1.6µs

6.4µs

8µs

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The lower 8 bits of the timer (interrupt) cycle are set by

The comparator match signal is output from timer 0

each time the up-counter UC0 matches TREG0, where

the up-counter UC0 is not to be cleared.

the timer register TREG0, and the upper 8 bits are set

by TREG1. Note that TREG0 always must be set ﬁrst.

(Writing data into TREG0 disables the comparator tem-

porarily, and the comparator is restarted by writing

data into TREG1.)

With the timer 1 comparator, the match detect signal is

output at each comparator timing when up-counter

UC1 and TREG1 values match. When the match

detect signal is output simultaneously from both com-

parators of timer 0 and timer 1, the up-counters UC0

and UC1 are cleared to “0”, and the interrupt INTT1 is

generated. If inversion is enabled, the value of the timer

ﬂip-ﬂop TFF1 is inverted.

Setting example:

To generate an interrupt INTT1 every

0.5 seconds at fc = 16MHz, set the

following values for timer registers

TREG0 and TREG:

When counting with input clock of

φT16 (8µs @ 16MHz)

Example:

When TREG1 = 04H and TREG0 = 80H

0.5 sec ÷ 8µs = 62500 = F424H

Therefore, set TREG1 = F4H and

TREG0 = 24H, respectively.

Figure 3.7 (9). Output Timer by 16-Bit Timer Mode

(3)

8-bit PPG (Programmable Pulse Generation) Output

mode

counter (UC0) matches the timer registers TREG0 and

TREG1.

However, it is required that the set value of TREG0 is

smaller than that of TREG1.

Though the up-counter (UC1) of timer 1 is not used in

this mode, UC1 should be set for counting by setting

TRUN <T1RUN> to 1.

Square wave pulse can be generated at any frequency

and duty by timer 0 and timer 1. The output pulse may

be either low-active or high-active. In this mode, timer

1 cannot be used.

Timer 0 outputs pulse to TO1 pin (also used as P70).

Figure 3.7 (11) shows the block diagram for this mode.

In this mode, a programmable square wave is gener-

ated by inverting timer output each time the 8-bit up-

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Figure 3.7 (10). 8-Bit PPG Output Waveforms

Figure 3.7 (11). Block Diagram of 8-Bit PPG Output Mode

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When the double buffer of TREG0 is enabled in this

mode, the value of register buffer will be shifted in TREG0 each

time TREG1 matches UC0.

Use of the double buffer makes easy handling of low duty

waves (when duty is varied).

Figure 3.7 (12). Operation of Register Buffer

Example: Generating 1/4 duty 50KHz pulse @ fc = 16MHz)

• Calculate the value to be set for timer register.

To obtain the frequency 50KHz, the pulse cycle t

should be: t = 1/50KHz = 20µs.

TREG1 = 40 = 28H and then duty to 1/4, t x 1/4 =

20µs x 1/4 = 5µs

5µs ÷ 0.5µs = 10

Therefore, set timer register 0 (TREG0) to TREG0 = 10

= 0AH.

Given φ T1 = 0.5µs @ 16MHz),

20µs ÷ 0.5µs = 40

Consequently, to set the timer register 1 (TREG1) to

7

–

1

0

–

6

x

5

–

x

4

–

x

3

–

x

2

–

x

1

0

1

0

1

0

1

0

x

TRUN

←

Stop timer 0, and clear it to “0”.

TMOD

TREG0

TREG1

TFFCR

0

–

Set the 8-bit PPG mode, and select φT1 as input clock.

Write “0AH”.

0

1

–

0

1

0

1

Write “28H”.

Sets TFF1 and enables the inversion and double buffer enable.

Writing “10” provides negative logic pulse.

P7CR

P7FC

TRUN

←

x

1

x

–

x

–

1

–

x

Set P71 as TO1 pin.

)

1

Start timer 0 and timer 1 counting.

Note : x; don’t care

–; no change

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0>) counter overﬂow occurs. Up-counter UC0 is

(4)

8-bit PWM Output mode

cleared when 2n - 1 counter overﬂow occurs. For

example, when n = 6, 6-bit PWM will be output, while

when n = 7, 7-bit PWM will be output.

To use this PWM mode, the following conditions must

be satisﬁed.

This mode is valid only for timer 0. In this mode, maxi-

mum 8-bit resolution of PWM pulse can be output.

PWM pulse is output to TO1 pin (also used as P71)

when using timer 0. Timer 1 can also be used as 8-bit

timer.

n

(Set value of timer register) <(Set value of 2 - 1

Timer output is inverted when up-counter (UC0)

matches the set value of timer register TREG0 or when

2n - 1 (n = 6, 7, or 8; speciﬁed by T01MOD <PWM01,

counter overﬂow)

(Set value of timer register ≠ 0)

Figure 3.7 (13). 8-Bit PWM Waveforms

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Figure 3.7 (14) shows the block diagram of this mode.

Figure 3.7 (14). Block Diagram of 8-Bit PWM Mode

In this mode, the value of register buffer will be shifted in

TREG0 if 2 - 1 overﬂow is detected when the double buffer of

Use of the double buffer makes the handling of small duty

waves easy.

n

TREG0 is enabled.

Figure 3.7 (15). Operation of Register Buffer

Example: To output the following PWM waves to TO1 pin at fc = 16MHz.

To realize 63.5µs of PWM cycle by φT1 = 0.5µs (@ fc =

16MHz),

7

63.5µs ÷ 0.5µs = 127 = 2 - 1

Consequently, n should be set to 7.

As the period of low level is 36µs, for φT1 = 0.5µs, set the

following value for TREG0:

36µs ÷ 0.5µs = 72 = 48H

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MSB

LSB

0

7

-

6

x

1

5

–

1

4

–

0

3

–

2

–

1

–

0

TRUN

←

0

Stop timer 0, and clear it to “0”.

7

TMOD

1

Set 8-bit PWM mode (cycle: 2 - 1) and select φT1 as the input clock.

TREG0

TFFCR

←

0

x

1

x

0

x

0

x

1

0

1

0

x

Write “48H”.

Clears TFF1, enables the inversion and double buffer.

P7CR

P7FC

TRUN

←

x

1

x

–

x

–

1

–

x

Set P71 as the TO1 pin.

Start timer 0 counting.

)

1

Note: x; don’t care

–; no change

n

Table 3.7 (3) PWM Cycle and the Setting of 2 -1 Counter

PWM Cycle (@ fc =16MHz)

PWM Cycle (@ fc = 20 MHz)

φT1

φT4

φT16

φT1

φT4

φT16

6

2 -1

31.5µsec (31.7kHz)

63.5µsec (15.7kHz)

126msec (7.9kHz)

254msec (3.9kHz)

510msec (1.9kHz)

0.50µsec (1.9kHz)

1.01µsec (0.98kHz)

2.04µsec (0.49kHz)

25.2µsec (39.0kHz)

50.8µsec (19.7kHz)

100µsec (10.0kHz)

203µsec (4.9kHz)

0.40msec (2.4kHz)

0.81msec (1.2kHz)

1.63msec (0.61kHz)

7

2 -1

8

2 -1

127µsec (7.8kHz)

102µsec (9.80kHz) 408µsec (2.4kHz)

(5)

Table 3.7 (4) shows the list of 8-bit timer modes.

Table 3.7 (4) Timer Mode Setting Registers

TMOD

Register Name

TFFCR

TFF1IS

Name of Function in

T10M

PWMM

T1CLK

T0CLK

Upper Timer

Input Clock

Lower Timer

Input Clock

Timer F/F Invert

Signal Select

Function

Timer Mode

PWM0 Cycle

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

16-bit timer mode

01

–

Lower timer match :

φT1, φT16, φT256

(00, 01, 10, 11)

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

0 : Lower timer output

1 : Upper timer output

8-bit timer x 2 channels

8-bit PPG x 1 channel

00

10

–

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

–

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

6

7

8

2 - 1, 2 - 1, 2 - 1

(01, 10, 11)

8-bit PWM x 1 channel

8-bit timer x 1 channel

11

–

φT1, φT16, φT256

–

Output disabled

(01, 10, 11)

Note: –: don’t care

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3.8 8-Bit PWM Timer

Figure 3.8 (1) is a block diagram of 8-bit PWM timer (tim-

ers 2 and 3).

PWM timers consist of an 8-bit up-counter, 8-bit com-

parator, and 8-bit timer register. Two timer ﬂip-ﬂops (TFF2 for

timer 2 and TFF3 for timer 3) are provided.

The TMP96C141AF/TMP96CM40F/TMP96PM40F has two

built-in 8-bit PWM timers (timers 2 and 3).

They have two operating modes.

Input clocks φP1, φP4, and φP16 for the PWM timers can

be obtained using the built-in prescaler.

PWM timer operating mode and timer ﬂip-ﬂops are con-

trolled by four control registers (P0MOD, P1MOD, PFFCR, and

TRUN).

• 8-bit PWM (pulse width modulation: variable duty at fixed

interval) output mode

• 8-bit interval timer mode

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Figure 3.8 (1). Block Diagram of 8-Bit PWM Timer 0 (Timer 2)

Note: Block diagram for 8-bit PWM timer 1 (timer 3) is the same as the above diagram.

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➀ Prescaler

The PWM timer uses three input clocks: φ/P1, φ/P4,

and φ/P16.

Like the 9-bit prescaler described in the 8-bit timer

section, this prescaler can be counted/stopped using

bit 7 <PRRUN> of the timer operation control register

TRUN. Setting <PRRUN> to 1 starts counting; setting

it to 0 zero-clears and stops counting. Resetting clears

<PRRUN> to 0, which clears and stops the prescaler.

Generates input clocks dedicated to PWM timers by

further dividing the fundamental clock (fc) after it has

been divided by 2 (fc/2). Since the register used to

control the prescaler is the same as the one for other

timers, the prescaler cannot be operated indepen-

dently.

Dedicated Prescaler Cycle

16MHz

20MHz

φP1 (4/fc)

φP4 (16/fc)

φP16 (64/fc)

250ns

1µs

200ns

800ns

3.2µsc

4µs

Figure 3.8 (2). Prescaler

➁ Up-counter

match.

Count/stop and clear of the up-counter can be con-

trolled for each PWM timer using the timer operation

control register TRUN. Resetting clears all up-counters

and stops timers.

An 8-bit binary counter which counts up using the

input clock speciﬁed by PWM mode register (P0MOD

or P1MOD).

The input clock for the PWM0/PWM1 is selected from

the internal clocks φP1, φP4, and φP16 (PWM dedi-

cated prescaler output) depending on the value set in

the P0MOD/P1MOD register.

➂ Timer registers

Two 8-bit registers used for setting an interval time.

When the value set in the timer registers (TREG 2 and

3) matches the value in the up-counter, the match

detect signal of the comparator becomes active.

Timer registers TREG2 and TREG3 are each paired

with register buffer to make a double buffer structure.

Operating mode is also set by P0MOD and P1MOD

registers. At reset, they are initialized to P0MOD

<PWM0M> = 0 and P1MOD <PWM1M> = 0, thus, the

up-counter is in PWM mode. In PWM mode, the up-

n

counter is cleared when a 2 - 1 overﬂow occurs; in

timer mode, the up-counter is cleared at compare and

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TREG2 and TREG3 are controlled double buffer

enable/disable by P0MOD <DB2EN> and P1MOD

<DB3EN> : disabled when <DB2EN>/<DB3EN> = 0,

enabled when <DB2EN>/<DB3EN> = 1.

in double buffer enable state, unlike timer mode for

timers 0 and 1.

At reset, <DB2EN>/<DB3EN> is initialized to 0 to dis-

able double buffer. To use double buffer, write the data

in the timer register at ﬁrst, then set <DB2EN>/

<DB3EN> to 1, and write the following data in the reg-

ister buffer.

Data is transferred from register buffer to timer when a

n

2 - 1 overﬂow occurs in the PWM mode, or when

compare and match occurs in 8-bit timer mode. That

is, with a PWM timer, the timer mode can be operated

Figure 3.8 (3). Structure of Timer Registers 2 and 3

Note: The timer register and register buffer are allocated to the same

memory address. When <DB2EN>/<DB3EN> = 0, the same value

is written to both register buffer and timer register. When <DB2EN>/

<DB3EN> = 1, the value is written to the register buffer only.

the comparator outputs the match detect signal. A

timer interrupt (INTT2/INTT3) is generated at compare

and match if the interrupt select bit <PWM01NT>/

<PWM1NT> of the mode register (P0MOD/P1MOD) is

set to 1. In timer mode, the comparator clears the up-

counter to 0 at compare and match. It also inverts the

value of the timer ﬂip-ﬂop if timer ﬂip-ﬂop invert is

enabled.

Memory addresses of the timer registers are as follows:

TREG2 : 000026H

TREG3 : 000027H

➄ Timer flip-flop

Both timer registers are write only; however, register

buffer values can be read when reading the above

addresses.

The value of the timer ﬂip-ﬂop is inverted by the match

detect signal (comparator output) of each interval timer

or 2 - 1 overﬂow. The value can be output to the timer

n

output pin TO2/TO3 (also used as P72/P73).

➃ Comparator

Compares the value in the up-counter with the value in

the timer register (TREG2/TREG3). When they match,

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Figure 3.8 (4). 8-Bit PWM0 Mode Control Register

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Figure 3.8 (5). 8-Bit PWM1 Mode Control Register

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Figure 3.8 (6). 8-Bit PWM F/F Control Register

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Figure 3.8 (7). Timer Operation Control Register (TRUN)

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The following explains PWM timer operations.

Condition 2:

• TFF2 is set to 1 when the value in the up-counter

(UC2) and the value set in TREG2 match.

• TFF2 is cleared to 0 when a 2 - 1 counter over

(1)

PWM timer mode

n

ﬂow (n = 6, 7, or 8) occurs.

Both PWM timers can output 8-bit resolution PWM

independently. Since both timers operate in exactly the

same way, PWM0 is used for purposes of explanation.

PWM output changes under the following two condi-

tions.

n

The up-counter (UC2) is cleared by a 2 - 1 counter

overﬂow.

The PWM timer can output 0% - 100% duty pulses

n

because a 2 - 1 counter overﬂow has a higher priority.

That is, to obtain 0% output (always low), the mode

used to set TFF2 to 0 due to overﬂow (PFFCR

<FF2TRG1, 0> = 1, 0) must be set and 2 - 1 (value for

overﬂow) must be set in TREG2. To obtain 100% out-

put (always high), the mode must be changed: PFFCR

<FF2TRG1, 0> = 1,1 then the same operation is

required.

Condition 1:

n

• TFF2 is cleared to 0 when the value in the up-

counter (UC2) and the value set in the TREG2

match.

• TFF2 is set to 1 when a 2 - 1 counter overﬂow (n

= 6, 7, or 8) occurs.

n

PWM timing

Figure 3.8 (8). Output Waves in PWM Timer Mode

Note: The above waves are obtained in a mode where the F/F is set by a match with the timer register (TREG) and reset by an overﬂow.

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Figure 3.8 (9) is a block diagram of this mode.

Figure 3.8 (9). Block Diagram of PWM Timer Mode (PWM0)

In this mode, enabling double buffer is very useful. The

register buffer value shifts into TREG2 when a 2 -1 overﬂow

Using double buffer makes handling small duty waves

n

easy.

is detected, when double buffer is enabled.

Figure 3.8 (10). Register Buffer Operation

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Example: To output the following PWM waves to TO2 pin

using PWM0 at fc = 16MHz.

To implement 31.75µs PWM cycle by φ P1 = 0.25µs (@ fc

= 16MHz)

7

31.75µs ÷ 0.25µs = 127 = 2 -1.

Consequently, set n to 7.

Since the low level cycle = 15µs; for φ P1 = 0.25µs

15µs ÷ 0.25 = 60 = 3CH

set the 3CH in TREG2.

7

–

-

6

x

0

5

–

0

4

–

0

3

–

0

2

0

1

–

0

–

1

TRUN

←

Stops PWM0 and clears it to 0.

7

P0MOD

Sets PWM (2 - 1) mode, input clock φP1, overﬂow interrupt, and disables double buffer.

TREG2

P0MOD

PFFCR

←

0

–

0

1

–

1

0

–

1

0

–

1

0

1

0

1

0

1

0

1

Writes 3CH.

Enables double buffer.

Sets TFF2 and a mode where TFF2 is set by compare and match, and cleared by overﬂow.

P7CR

P7FC

TRUN

←

x

1

x

–

x

–

1

–

x

Sets P72 as the TO2 pin.

)

–

Starts PWM0 counting.

Note: x; don’t care

–; no change

n

Table 3.8 (1) PWM Cycle and 2 -1 Counter Setting

16MHz

20MHz

Formula

φP1

φP4

φP16

φP1

φP4

φP16

6

2 -1

2 -1 - φPn

15.8µsec

63.0µsec

252µsec

12.6µsec

50.4µsec

201µsec

(63kHz)

(16kHz)

(3.9kHz)

(79kHz)

(20kHz)

(4.9kHz)

7

2 -1

2 -1 - φPn

31.8µsec

127.0µsec

508µsec

25.4µsec

101.6µsec

406µsec

(31kHz)

(7.9kHz)

(1.9kHz)

(39kHz)

(9.8kHz)

(2.5kHz)

8

2 -1

2 -1 - φPn

63.8µsec

255.0µsec

1020µsec

51.0µsec

204.0µsec

816µsec

(16kHz)

(3.9kHz)

(0.98kHz)

(20kHz)

(4.9kHz)

(1.2kHz)

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➀ Generating interrupts at a fixed interval

(2)

8-bit timer mode

Both PWM timers can be used independently as 8-bit

interval timers. Since both timers operate in exactly the

same way, PWM0 (timer 2) is used for the purposes of

explanation.

To generate timer 2 interrupt (INTT2) at a ﬁxed interval

using PWM0 timer, ﬁrst stop PWM0, then set the oper-

ating mode, input clock, and interval in the P0MOD

and TREG2 registers. Next, enable INTT2 and start

counting PWM0.

Example: To generate a timer 2 interrupt every 40µs

at fc = 16MHz, set registers as follows:

7

–

x

6

x

0

5

–

1

4

–

1

3

–

0

2

0

1

–

x

0

–

x

TRUN

←

Stops PWM0 and clears it to 0.

P0MOD

Sets 8-bit timer mode and selects φP1 (0.25µs) and compare interrupt.

TREG2

←

1

–

1

0

–

x

1

–

0

–

0

1

–

0

1

0

–

0

–

Sets 40µs/0.25µs = A0H in timer register.

Enables INTT2 and sets interrupt level 4.

Starts PWM0 counting.

INTEPW10

TRUN

Note: x; don’t care –; no change

Select an input clock using the table below.

Table 3.8 (2) Interrupt Cycle and Input Clock Selection using 8-Bit Timer Mode

Interrupt Cycle

(at fc = 16MHz)

Interrupt Cycle

(at fc = 20MHz)

Input Clock

Resolution

φP1 (4/fc)

φP4 (16/fc)

φP16 (64/fc)

0.25µs ~ 64µs

1µs ~ 256µs

4µs ~ 1024µs

0.25µs

1µs

0.2µs ~ 51.2µs

0.8µs ~ 204.8µs

3.2µs ~ 819.2µs

0.2µs

0.8µs

3.2µs

4µs

Note: To generate interrupts in 8-bit timer mode, bit 5 (interrupt control bit <PWM01NT>/<PWM1NT> of P0MOD/P1MOD) must be set to 1.

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➁ Generating a 50% square wave

value to the timer output pin (TO2).

To generate a 50% square wave, invert the timer ﬂip-

ﬂop at a ﬁxed interval and output the timer ﬂip-ﬂop

Example: To output a 3.0µs square wave at fc =

16MHz from TO2 pin, set register as fol-

lows:

7

–

x

6

x

0

5

–

1

4

–

1

3

–

0

2

0

1

–

x

0

–

x

TRUN

←

Stops PWM0 and clears it to 0.

P0MOD

Sets 8-bit timer mode and selects φP1 (0.25µs) as the input clock.

TREG2

PFFCR

P7CR

P7FC

←

0

–

x

0

–

x

0

–

x

0

–

x

0

1

–

1

0

1

0

–

0

1

–

x

Sets 3.0µs/0.25µs/2 = 6 in the timer register.

Clears TFF2 to 0 and inverts using comparator output.

Sets P72 as the TO2 pin.

)

x

TRUN

1

–

Note: x; don’t care

–; no change

Figure 3.8 (11). Square Wave (50% Duty) Output Timing Chart

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This mode is as shown in Figure 3.8 (12) below.

Figure 3.8 (12). Block Diagram of 8-Bit Timer Mode

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3.9 16-Bit Timer

Timer/event counter consists of 16-bit up-counter, two

16-bit timer registers, two 16-bit capture registers (one of them

applies double-buffer), two comparators, capture input con-

troller, and timer ﬂip-ﬂop and the control circuit.

Timer/event counter is controlled by four control regis-

ters: T4MOD/T5MOD, T4FFCR/T5FFCR, TRUN and T45CR.

The TMP96C141AF has two (timer 4 and timer 5) multifunc-

tional 16-bit timer/event counter with the following operation

modes.

• 16-bit interval timer mode

• 16-bit event counter mode

• 16-bit programmable pulse generation (PPG) mode

• Frequency measurement mode

• Pulse width measurement mode

• Time differential measurement mode

Figure 3.9 (1) and (2) show the block diagram of 16-bit

timer/event counter (timer 4 and timer 5).

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Figure 3.9 (1). Block Diagram of 16-Bit Timer (Timer 4)

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Figure 3.9 (2). Block Diagram of 16-Bit Timer (Timer 5)

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Figure 3.9 (3). 16-Bit Timer Mode Controller Register (T4MOD) (1/2)

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Figure 3.9 (4). 16-Bit Controller Register (T4MOD) (2/2)

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Figure 3.9 (5). 16-Bit Timer 4 F/F Control (T4FFCR)

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Figure 3.9 (6). 16-Bit Timer Mode Control Register (T5MOD) (1/2)

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Figure 3.9 (7). 16-Bit Timer Control Register (T5MOD) (2/2)

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CAP4T6 : Invert when the up-counter value is loaded to CAP4

CAP3T6 : Invert when the up-counter value is loaded to CAP3

EQ7T6

EQ6T6

: Invert when up-counter matches TREG7

: Invert when up-counter matches TREG6

Figure 3.9 (8). 16-Bit Timer 5 F/F Control (T5FFCR)

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DB6EN : Double buffer of TREG6

DB4EN : Double buffer of TREG4

Figure 3.9 (9). 16-Bit Timer (Timer 4, 5) Control Register (T45CR)

Figure 3.9 (10). Timer Operation Control Register (TRUN)

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➀ Up-counter (UC4/UC5)

timer register TREG5, TREG7. The “clear enable/disable”

is set by T4MOD <CLE> and T5MOD <CLE>.

If clearing is disabled, the counter operates as a free-

running counter.

UC4/UC5 is a 16-bit binary counter which counts up

according to the input clock speciﬁed by T4MOD

<T4CLK1, 0> or T5MOD <T5CLK1, 0> register.

As the input clock, one of the internal clocks φ T1 (8/

fc), φ T4 (32/fc), and φ T16 (128/fc) from 9-bit prescaler

(also used for 8-bit timer), and external clock from TI4 pin

(also used as P80/INT4 pin) or TI6 (also used as P84/

INT6 pin) can be selected. When reset, it will be initialized

to <T4CLK1, 0>/<T5CLK1, 0> = 00 to select TI4/TI6

input mode. Counting or stop and clear of the counter is

controlled by timer operation control register TRUN

<T4RUN, T5RUN>.

➁ Timer Registers

These two 16-bit registers are used to set the interval

time. When the value of up-counter UC4/UC5 matches

the set value of this timer register, the comparator match

detect signal will be active.

Setting data for timer register (TREG4, TREG5,

TREG6 and TREG7) is executed using 2 byte date trans-

fer instruction or using 1 byte date transfer instruction

twice for lower 8 bits and upper 1 bits in order.

When clearing is enabled, up-counter UC4/UC5 will

be cleared to zero each time it coincides matches the

TREG4

TREG5

Upper 8 bits

000031H

Lower 8 bits

000030H

Upper 8 bits

000033H

Lower 8 bits

000032H

TREG6

TREG7

Upper 8 bits

000041H

Lower 8 bits

000040H

Upper 8 bits

000043H

Lower 8 bits

000042H

TREG4 and TREG6 timer register is of double buffer

structure, which is paired with register buffer. The timer

control register T45CR <DB4EN, DB6EN> controls

whether the double buffer structure should be enabled or

disabled. : disabled when <DB4EN, DB6EN> = 0, while

enabled when <DB4EN, DB6EN> = 1.

the same memory addresses 000030H/000031H/

0000400H/000041H. When <DB4EN, DB6EN> = 0,

same value will be written in both the timer register and

register buffer. When <DB4EN, DB6EN> = 1, the value is

written into only the register buffer.

When the double buffer is enabled, the timing to

transfer data from the register buffer to the timer register

is at the match between the up-counter (UC4/UC5) and

timer register TREG5/TREG7.

When reset, it will be initialized to <DB4EN, DB6EN>

= 0, whereby the double buffer is disabled. To use the

double buffer, write data in the timer register, set

<DB4EN, DB6EN> = 1, and then write the following data

in the register buffer.

➂ Capture Register

These 16-bit registers are used to hold the values of

the up-counter.

Data in the capture registers should be read by a 2-

byte data load instruction or two 1-byte data load instruc-

tion, from the lower 8 bits followed by the upper 8 bits.

TREG4, TREG6 and register buffer are allocated to

CAP 1

CAP 2

Upper 8 bits

000035H

Lower 8 bits

000034H

Upper 8 bits

000037H

Lower 8 bits

000036H

CAP 3

CAP 4

Upper 8 bits

000045H

Lower 8 bits

000044H

Upper 8 bits

000047H

Lower 8 bits

000046H

➃ Capture Input Control

The latch timing of capture register is controlled by regis-

ter T4MOD <CAP12M1, 0>/T5MOD <CAP34M1, 0>.

• When T4MOD <CAP12M1, 0>/T5MOD

<CAP34M1, 0> = 00

This circuit controls the timing to latch the value of

Capture function is disabled. Disable is the

default on reset.

up-counter UC4/UC5 into (CAP1, CAP2)/(CAP3, CAP4).

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• When T4MOD <CAP12M1, 0>/T5MOD

<CAP34M1, 0> = 01

matches TREG5/TREG7. (The clearing of up-counter

UC4/UC5 can be disabled by setting T4MOD <CLE>/

T5MOD <CLE> = 0.)

Data is loaded to CAP1, CAP3 at the rise edge

of TI4 pin (also used as P80/INT4) and TI6 pin (also

used as P84/INT6) input, while data is loaded to

CAP2, CAP4 at the rise edge of TI5 pin (also used as

P81/INT5 and TI7 pin (also used as P85/INT7) input.

(Time difference measurement)

➅ Timer Flip-Flop (TFF4/TFF6)

This ﬂip-ﬂop is inverted by the match detect signal

from the comparators and the latch signals to the cap-

ture registers. Disable/enable of inversion can be set for

each element by T4FFCR <CAP2T4, CAP1T4, EQ5T4,

EQ4T4>/T6FFCR <CAP4T6, CAP3T6, EQ7T6, EQ6T6>.

TFF4/TFF6 will be inverted when “00” is written in

T4FFCR <TFF4C1, 0>/T6FFCR <TFF6C1, 0>. Also it is

set to “1” when “10” is written, and cleared to “0” when

“10” is written. The value of TFF4/TFF6 can be output to

the timer output pin TO4 (also used as P82) and TO6

(also used as P86).

• When T4MOD <CAP12M1, 0>/T5MOD

<CAP34M1, 0> = 10

Data is loaded to CAP1 at the rise edge of TI4

pin input and to CAP3 at the rise edge of TI6, while

to CAP2, CAP4 at the fall edge. Only in this setting,

interrupt INT4/INT6 occurs at fall edge. (Pulse width

measurement)

• When T4MOD <CAP12M1, 0>/T5MOD

<CAP34M1, 0> = 11

Data is loaded to CAP1, CAP3 at the rise edge

of timer ﬂip-ﬂop TFF1, while to CAP2, CAP4 at the

fall edge.

Besides, the value of up-counter can be loaded

to capture registers by software. Whenever “0” is

written in T4MOD <CAPIN>, T5MOD <CAP31N> the

current value of up-counter will be loaded to capture

register CAP1/CAP3. It is necessary to keep the

prescaler in RUN mode (TRUN <PRRUN> to be “1”).

➆ Timer Flip-Flop (TFF5)

This ﬂip-ﬂop is inverted by the match detect signal

from the comparator and the latch signal to the capture

register CAP2. TFF5 will be inverted when “00” is written

in T4FFCR <TFF5C1, 0>/T6FFCR <TFF6C1, 0>. Also it is

set to “1” when “10” is written, and cleared to “0” when

“10” is written. The value of TFF5 can be output to the

timer output pin TO5 (also used as P82).

Note: This ﬂip-ﬂop (TFF5) is contained only in the 16-bit timer 4.

(1) 16-bit Timer Mode

➄ Comparator

These are 16-bit comparators which compare the

up-counter UC4/UC5 value with the set value of (TREG4,

TREG5)/(TREG6, TREG7) to detect the match. When a

match is detected, the comparators generate an interrupt

(INTT4, INTT5)/(INTT6, INTT7) respectively. The up-

counter UC4/UC5 is cleared only when UC4/UC5

Timer 4 and 5 operate independently.

Since both timers operate in exactly the same way, timer

4 is used for the purposes of explanation.

Generating interrupts at ﬁxed intervals:

In this example, the interval time is set in the timer register

TREG5 to generate the interrupt INTTR5.

7

–

1

6

x

1

5

–

0

4

0

3

–

1

2

–

0

1

–

0

–

0

TRUN

←

Stop timer 4.

INTET54

Enable INTTR5 and sets interrupt level 4. Disables

INTTR4.

T4FFCR

T4MOD

←

1

0

1

0

1

0

1

*

1

*

Disable trigger.

Select internal clock for input and disable the capture function.

(** = 01, 10, 11)

TREG5

TRUN

←

*

1

*

x

*

–

*

1

*

–

*

–

*

–

*

–

Set the interval timer (16 bits).

Start timer 4.

←

Note: x; don’t care

–; no change

(2) 16-bit Event Counter Mode

counter, ﬁrst perform “software capture” once and read the

captured value.

The counter counts at the rise edge of TI4/TI6 pin input.

TI4/TI6 pin can also be used as P80/INT4 and P84/INT6.

Since both timers operate in exactly the same way, timer

4 is used for the purposes of explanation.

In 16-bit timer mode as described in above, the timer can be

used as an event counter by selecting the external clock (TI4/

TI6 pin input) as the input clock. To read the value of the

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7

6

x

5

–

0

4

0

–

0

3

–

1

2

–

0

1

–

0

–

0

TRUN

←

–

1

Stop timer 4.

P8CR

–

1

Set P80 to input mode.

Enable INTTR5 and sets interrupt level 4, while

disables INTTR4.

INTET54

T4FFCR

T4MOD

TREG5

TRUN

←

1

0

*

1

0

*

x

0

1

*

0

*

0

*

0

1

*

1

0

*

1

0

*

Disable trigger.

Select TI4 as the input clock.

Set the number of counts (16 bits).

Start timer 4.

1

–

1

–

Note: When used as an event counter, set the prescaler in RUN mode.

(3)

16-bit Programmable Pulse Generation (PPG) Output

Mode

ﬂip-ﬂop TFF4 that is to be enabled by the match of the

up-counter UC4 with the timer register TREG4 or 5

and to be output to TO4 (also used as P82). In this

mode, the following conditions must be satisﬁed.

Since both timers operate in exactly the same way,

timer 4 is used for the purposes of explanation.

(Set value of TREG4) < (Set value of TREG5)

The PPG mode is obtained by inversion of the timer

7

–

*

6

x

*

x

5

–

*

x

4

0

*

x

3

–

*

2

–

*

1

–

*

0

–

*

TRUN

←

Stop timer 4.

TREG4

TREG5

T45CR

Set the duty (16 bits).

*

Set the cycle (16 bits).

0

–

1

Double buffer of TREG4 enable.

(Changes the duty and cycle at the interrupt INTTR5)

Set the mode to invert TFF4 at the match with

TREG4/TREG5, and also sets TFF4 to “0”.

Select internal clock for input and disables the capture function.

T4FFCR

T4MOD

←

1

0

1

0

1

0

1

0

1

0

*

0

*

(** = 01, 10, 11)

P8CR

P8FC

TRUN

←

–

x

–

x

–

x

–

x

–

1

–

x

–

x

Assign P82 as TO4.

Start timer 4.

)

1

–

1

–

Note: x; don’t care

–; no change

Figure 3.9 (11). Programmable Pulse Generation (PPG) Output Waveforms

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When the double buffer of TREG4 is enabled in this

mode, the value of register buffer 4 will be shifted in TREG4

at match with TREG5. This feature makes easy the handling of

low duty waves.

Figure 3.9 (12). Operation of Register Buffer

Shows the block diagram of this mode.

Figure 3.9 (13). Block Diagram of 16-Bit PPG Mode

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(4)

Application Examples of Capture Function

➀ One-Shot Pulse Output from External Trigger Pulse

The loading of up-counter (UC4) values into the cap-

ture registers CAP1 and CAP2, the timer ﬂip-ﬂop TFF4

inversion due to the match detection by comparators

CP4 and CP5, and the output of TFF4 status to TO4

pin can be enabled or disabled. Combined with inter-

rupt function, they can be applied in many ways, for

example:

Set the up-counter UC4 in free-running mode with the

internal input clock, input the external trigger pulse

from TI4 pin, and load the value of up-counter into

capture register CAP1 at the rise edge of the TI4 pin.

Then set to T4MOD <CAP12M1, 0> = 01.

When the interrupt INT4 is generated at the rise edge

of TI4 input, set the CAP1 value (c) plus a delay time (d)

to TREG4 (= c + d), and set the above set value (c + d)

plus a one-shot pulse width (p) to TREG5 (= c + d + p).

When the interrupt INT4 occurs the T4FFCR <EQ5T4,

EQ4T4> register should be set that the TFF4 inversion

is enabled only when the up-counter value matches

TREG4 or TREG5. When interrupt INTTR5 occurs, this

inversion will be disabled.

➀ One-shot pulse output from external trigger pulse

➁ Frequency measurement

➂ Pulse width measurement

➃ Time difference measurement

Figure 3.9 (14). One-Shot Pulse Output (with Delay)

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Setting Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TI4 pin.

Keep counting (Free-running).

Main setting

Count with φT1.

T4MOD

←

–

1

–

1

0

1

0

1

0

Load the up-counter value into CAP1 at the rise edge of TI4 pin input.

T4FFCR

←

Clear TFF4 to zero.

Disable TFF4 inversion.

P8CR

P8FC

←

–

x

–

x

–

x

–

1

–

x

–

x

Select P82 as the TO4 pin.

)

INTE45

INTET54

TRUN

←

–

1

–

0

x

–

0

–

0

1

–

1

0

–

0

–

0

–

Enable INT4, and disables INTTR4 and INTTR5.

Start timer 4.

Setting of INT4

TREG4

TREG5

T4FFCR

←

CAP1 + 3ms/φT1

TREG4 + 2ms/φT1

–

1

–

1

–

Enable TFF4 inversion when the up-counter value matches TREG4 or 5.

Enable INTTR5.

INTET54

←

1

0

–

Setting of INT5

T4FFCR

←

–

1

–

0

–

0

–

0

–

Disable TFF4 inversion when the up-counter value matches TREG 4 or 5.

Disable INTTR5.

INTET54

←

–

Note: x; don’t care –; no change

When delay time is unnecessary, invert timer ﬂip-ﬂop

inversion should be enabled when the up-counter (UC4) value

matches TREG5, and disabled when generating the interrupt

INTTR5.

TFF4 when the up-counter value is loaded into capture register

1 (CAP1), and set the CAP1 value (c) plus the one-shot pulse

width (p) to TREG5 when the interrupt INT4 occurs. The TFF4

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Figure 3.9 (15). One-Shot Pulse Output (without Delay)

➁ Frequency Measurement

into the capture register CAP1 at the rise edge of the

timer ﬂip-ﬂop TFF1 of 8-bit timers (Timer 0 and Timer 1),

and into CAP2 at its fall edge.

The frequency is calculated by the difference

between the loaded values in CAP1 and CAP2 when the

interrupt (INTT0 or INTT1) is generated by either 8-bit

timer.

The frequency of the external clock can be measured

in this mode. The clock is input through the TI4 pin, and

its frequency is measured by the 8-bit timers (Timer 0 and

Timer 1) and the 16-bit timer/event counter (Timer 4).

The TI4 pin input should be selected for the input

clock of Timer 4. The value of the up-counter is loaded

Figure 3.9 (16). Frequency Measurement

For example, if the value for the level “1” width of

TFF1 of the 8-bit timer is set to 0.5 sec. and the differ-

ence between CAP1 and CAP2 is 100, the frequency will

be 100/0.5 [sec.] = 200 [Hz].

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➂ Pulse Width Measurement

external trigger pulse respectively. The interrupt INT4

occurs at the falling edge of TI4.

The pulse width is obtained from the difference

between the values of CAP1 and CAP2 and the internal

clock cycle.

For example, if the internal clock is 0.8 microseconds

and the difference between CAP1 and CAP2 is 100, the

pulse width will be 100 x 0.8 = 80 microseconds.

This mode allows measuring the “H” level width of an

external pulse. While keeping the 16-bit timer/event

counter counting (free-running) with the internal clock

input, the external pulse is input through the TI4 pin. Then

the capture function is used to load the UC4 values into

CAP1 and CAP2 at the rising edge and falling edge of the

Figure 3.9 (17). Pulse Width Measurement

Note: Only in this pulse width measuring mode (T4MOD <CAP12M1, 0> = 10), external interrupt INT4 occurs at the falling edge of TI4 pin input. In other

modes, it occurs at the rising edge.

The width of “L” level can be measured from the dif-

ference between the ﬁrst C2 and the second C1 at the

second INT4 interrupt.

Keep the 16-bit timer/event counter (Timer 4) count-

ing (free-running) with the internal clock, and load the

UC4 value into CAP1 at the rising edge of the input pulse

to TI4. Then the interrupt INT4 is generated.

Similarly, the UC4 value is loaded into CAP2 at the

rising edge of the input pulse to TI5, generating the inter-

rupt INT5.

➃ Time Difference Measurement

The time difference between these pulses can be

obtained from the difference between the time counts at

which loading the up-counter value into CAP1 and CAP2

has been done.

This mode is used to measure the difference in time

between the rising edges of external pulses input through

TI4 and TI5.

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Figure 3.9 (18). Time Difference Measurement

(5) Different Phased Pulses Output Mode

When the value in up-counter UC4 and the value in

TREG4 (TREG5) match, the value in TFF4 (TFF5) is inverted

and output to TO4 (TO5).

In this output mode, signals with any different phase can be

outputted by free-running up-counter UC4.

This mode can only be used by 16-bit timer 4.

Figure 3.9 (19). Phase Output

Cycles (counter overﬂow time) of the above output waves

are listed below.

16MHz

1.024msec

20MHz

0.819msec

φT1

φT4

4.096msec

3.277msec

φT16

16.38 msec

13.11 msec

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3.10 Stepping Motor Control/Pattern Generation Port

the PG port.

PG0 and PG1 can be used independently.

All PG operate in the same manner except the following

points, and thus only the operation of PG0 will be explained

below.

The TMP96C141AF has two channels (PG0 and PG1) of 4-bit

hardware stepping motor control/pattern generation (herein

after called PG) which actuate in synchronization with the (8-

bit/16-bit) timers. The PG (PG0 and PG1) are shared in 8-bit I/

O ports P6.

Differences between PG0 and PG1

Channel 0 (PG0) is synchronous with 8-bit timer 0 or

timer 1, 16-bit timer 5, to update the output.

The PG ports are controlled by control registers

(PG01CR) and can select either stepping motor control mode

or pattern generation mode. Each bit of the P6 can be used as

PG0

PG1

Trigger Signal

from Timer 4

from Timer 5

Figure 3.10 (1). Port 6/PG Circuit

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Figure 3.10 (2a). Pattern Generation Control Register (PG01CR)

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Figure 3.10 (2b). Pattern Generation Control Register (PG01CR)

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7

6

5

4

3

2

1

0

PG0REG

(004CH)

bit Symbol

Read/Write

After reset

Function

PG03

PG02

PG01

PG00

SA03

SA02

SA01

SA00

W

R/W

0

Undeﬁned

Pattern Generation 0 (PG0) output latch register

(Reading the P6 that is set to the PG port allows to read-out.)

Shift alternate register 0

For the PG mode (4-bit write) register

Prohibit Read

modify write

Figure 3.10 (3). Pattern Generation 0 Register (PG0REG)

7

6

5

4

3

2

1

0

PG1REG

(004DH)

bit Symbol

Read/Write

After reset

Function

PG13

PG12

PG11

PG10

SA13

SA12

SA11

SA10

W

R/W

0

Undeﬁned

Pattern Generation 1 (PG1) output latch register

(Reading the P6 that is set to the PG port allows to read-out.)

Shift alternate register 1

For the PG mode (4-bit write) register

Prohibit Read

modify write

Figure 3.10 (4). Pattern Generation 1 Register (PG1REG)

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Figure 3.10 (5). 16-bit Timer Trigger Control Register (T45CR)

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Figure 3.10 (6). Connection of Timer and Pattern Generator

(1) Pattern Generation Mode

In this mode, set PG01CR <PG0M> and <PG1M> to 1,

and PG01CR <CCW0> and <CCW1> to 0.

The output of this pattern generator is output to port 6;

since port and functions can be switched on a bit basis using

port function control register P6FC, any port pin can be

assigned to pattern generator output.

PG functions as a pattern generation according to the setting

of PG01CR <PAT1>/PAT0>. In this mode, writing from CPU is

executed only on the shifter alternate register. Writing a new

data should be done during the interrupt operation of the timer

for shift trigger, and a pattern can be output synchronous with

the timer.

Figure 3.10 (7) shows the block diagram of this mode.

Example of pattern generation mode

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↑

Shift due to the shift trigger from timer

Figure 3.10 (7). Pattern Generation Mode Block Diagram (PG0)

In this pattern generation mode, only writing the output

latch is disabled by hardware, but other functions do the same

operation as 1-2 excitation in stepping motor control port

mode. Accordingly, the data shifted by trigger signal from a

timer must be written before the next trigger signal is output.

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(2) Stepping Motor Control Mode

Figure 3.10 (8) and Figure 3.10 (9) show the output

waveforms of 4-phase 1 excitation and 4-phase 2 excita-

tion, respectively when channel 0 (PG0) is selected.

➀ 4-phase 1-Step/2-Step Excitation

↑

Initial value of PG0REG ← 0100 x x x x

Note: bn indicates the initial value of PG0REG ← b7 b6 b5 b4 x x x x

➀ Normal Rotation

↑

Initial value of PG0REG ← 0100 x x x x

➁ Reverse Rotation

Figure 3.10 (8). Output Waveforms of 4-Phase 1-Step Excitation

(Normal Rotation and Reverse Rotation)

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↑

Initial value of PG0REG ← 0100 x x x x

Figure 3.10 (9). Output Waveforms of 4-Phase 2-Step Excitation (Normal Rotation)

The operation when channel 0 is selected is

explained below.

The output latch of PG0 (also used as P6) is shifted

at the rising edge of the trigger signal from the timer to be

output to the port.

The direction of shift is speciﬁed by PG01CR

<CCW0>: Normal rotation (PG00 → PG01 → PG02 →

PG03) when <CCW0> is set to “0”; reverse rotation

(PG00 ← PG01 ← PG02 ← PG03) when “1”. Four-phase

1-step excitation will be selected when only one bit is set

to “1” during the initialization of PG, while 4-phase 2-step

excitation will be selected when two consecutive bits are

set to “1”.

The value in the shift alternate registers are ignored

when the 4-phase 1-step/2-step excitation mode is

selected.

Figure 3.10 (10) shows the block diagram.

Figure 3.10 (10). Block Diagram of 4-Phase 1-Step Excitation/2-Step Excitation

(Normal Rotation)

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➁ 4-Phase 1-2 Step Excitation

phase 1 -2 step excitation when channel 0 is selected.

Figure 3.10 (11) shows the output waveforms of 4-

↑

Initial value of PG0REG ← 11001000

Note: bn denotes the initial value of PG0REG ← b7 b6 b5 b4 b3 b2 b1 b0

➀ Normal Rotation

↑

Initial value of PG0REG ← 10001100

➁ Reverse Rotation

Figure 3.10 (11). Output Waveforms of 4-Phase 1-2 Step Excitation

(Normal Rotation and Reverse Rotation)

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The initialization for 4-phase 1-2 step excitation is as

follows:

By rearranging the initial value “b7 b6 b5 b4 b3 b2

b1 b0” to “b7 b3 b6 b2 b5 b1 b4 b0”, the consecutive 3

bits are set to “1” and other bits are set to “0” (positive

logic).

For example, if b7, b3, and b6 are set to “1", the ini-

tial value becomes “11001000”, obtaining the output

waveforms as shown in Figure 3.10 (11).

example, to change the output waveform shown in Fig-

ure 3.10 (11) into negative logic, change the initial value

to “00110111”.

The operation will be explained below for channel 0.

The output latch of PG0 (shared by P6) and the

shifter alternate register (SA0) for Pattern Generation are

shifted at the rising edge of trigger signal from the timer

to be output to the port. The direction of shift is set by

PG01CR <CCW0>.

To get an output waveform of negative logic, set val-

ues 1s and 0’s of the initial value should be inverted. For

Figure 3.10 (12) shows the block diagram.

Figure 3.10 (12). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation)

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Setting example: To drive channel 0 (PG0) by 4-phase 1-2

step excitation (normal rotation) when

timer 0 is selected, set each register as follows:

7

–

0

x

6

x

5

–

x

4

–

x

3

–

1

*

2

–

0

*

1

–

0

1

*

0

1

0

*

TRUN

←

Stop timer 0, and clears it to zero.

TMOD

TFFCR

TREG0

P6CR

0

x

Set 8-bit timer mode and selects φT1 as the input clock of timer 0.

Clear TFF1 to zero and enables the inversion trigger by timer 0.

Set the cycle in timer register.

x

0

*

–

1

–

1

–

0

–

0

–

1

0

1

–

1

0

–

1

0

–

1

0

1

Set P60 ~ P63 bits to the output mode.

Set P60 ~ P63 bits to the PG output.

P6FC

PG01CR

PG0REG

TRUN

Select PG0 4-phase 1 - 2 step excitation mode and normal rotation.

Set an initial value.

Start timer 0.

Note: x; don’t care

–; no change

(3) Trigger Signal From Timer

equal to the trigger signal of timer ﬂip-ﬂop (TFF1, TFF4, TFF5,

and TFF6) and differs as shown in Table 3.10 (1) depending on

the operation mode of the timer.

The trigger signal from the timer which is used by PG is not

Table 3.10 (1) Select of Trigger Signal

TFF1 Inversion

PG Shift

8-bit timer mode

16-bit timer mode

Selected by TFFCR <TFF1IS> when the up-counter value matches

TREG0 or TREG1 value.

When the up-counter value matches with both TREG0 and TREG1

8

values. (The value of up-counter = TREG1*2 + TREG0)

PPG output mode

PWM output mode

When the up-counter value matches with both TREG0 and TREG1.

When the up-counter value matches TREG1 value (PPG cycle).

When the up-counter value matches TREG0 value and PWM cycle. Trigger signal for PG is not generated.

Note: To shift PG, TFFCR <TFF1IE> must be set to “1” to enable TFF1 inversion.

Channel 1 of PG can be synchronized with the 16-bit

timer Timer 4/Timer 5. In this case, the PG shift trigger signal

from the 16-bit timer is output only when the up-counter UC4/

UC5 value matches TREG5/TREG7.

T4FFCR <EQ5T4> or T4MOD <EQ5T5> to “1” and a trigger is

generated when the value in UC4 and the value in TREG5

match. When using a trigger signal from Timer 5, set T5FFCR

<EQ7T6> to 1. Generates a trigger when the value in UC5 and

the value in TREG7 match.

When using a trigger signal from Timer 4, set either

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(4) Application of PG and Timer Output

PPG mode will be explained below.

To drive a stepping motor, in addition to the value of each

phase (PG output), synchronizing signal is often required at the

timing when excitation is changed over. In this application, port

6 is used as a stepping motor control port to output a synchro-

nizing signal to the TO1 pin (shared by P71).

As explained in “Trigger signal from timer”, the timing to shift

PG and invert TFF differs depending on the mode of timer. An

application to operate PG while operating an 8-bit timer in

Figure 3.10 (13). Output Waveforms of 4-Phase 1-Step Excitation

Setting example:

7

6

–

0

x

5

–

x

4

–

x

3

–

x

2

–

x

1

0

1

*

0

1

x

*

–

x

1

*

1

TRUN

←

–

1

x

Stop timer 0, and clears it to zero.

TMOD

TFFCR

TREG0

TREG1

P7CR

Set timer 0 and timer 1 in PPG output mode and selectsφT1 as the input clock.

Enable TFF1 inversion and sets TFF1 to “1”.

Set the duty of TO1 to TREG0.

x

0

*

0

*

1

*

Set the cycle of TO1 to TREG1.

x

–

1

0

*

–

1

0

*

1

0

*

Assign P71 as TO1.

)

P7FC

x

P6CR

–

*

–

*

–

*

–

*

Assign P60 - 63 as PG0.

P6FC

PG01CR

PG0REG

TRUN

Set PG0 in 4-phase 1-step excitation mode.

Set an initial value.

1

x

–

1

Start timer 0 and timer 1.

Note: x; don’t care

–; no change

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3.11 Serial Channel

The TMP96C141AF contains two serial I/O channels for full

duplex asynchronous transmission (UART)

as well as for I/O extension.

The serial channel has the following operation modes:

● I/O interface mode

(channel 1 only)

Mode 0: To transmit and receive I/O data as well as

the synchronizing signal SCLK for extending I/O.

Note: TMP96C141AF/TMP96C041AF/

TMP96CM40F/TMP96PM40F with

Channel 0 and 1.

Mode 1: 7-bit data

Mode 2: 8-bit data

Mode 3: 9-bit data

● Asynchronous transmission

(UART) mode (channel 0 and 1)

In mode 1 and mode 2, a parity bit can be added. Mode

3 has wake-up function for making the master controller start

slave controllers in serial link (multi-controller system).

Figure 3.11 (1) shows the data format (for one frame) in

each mode.

When bit 8 = 1, address (select code) is denoted.

When bit 8 = 0, data is denoted.

Figure 3.11 (1). Data Formats

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detected to be normal at least twice in three samplings.

When the transmission buffer becomes empty and

requests the CPU to send the next transmission data, or when

data is stored in the receiving data register and the CPU is

requested to read the data, INTTX or INTRX interrupt occurs.

Besides, if an overrun error, parity error, or framing error occurs

during receiving operation, ﬂag SC0CR/SC1CR <OERR,

PERR, FERR> will be set.

The serial channel 0/1 includes a special baud rate gen-

erator, which can set any baud rate by dividing the frequency

of four clocks (φT0, φT2, φT8, and φT32) from the internal pres-

caler (shared by 8-bit/16-bit timer) by the value 2 to 16.

In I/O interface mode, it is possible to input synchronous

signals as well as to transmit or receive data by external clock.

The serial channel has a buffer register for transmitting

and receiving operations, in order to temporarily store trans-

mitted or received data, so that transmitting and receiving

operations can be done independently (full duplex).

However, in I/O interface mode, SCLK (serial clock) pin is

used for both transmission and receiving, the channel

becomes half-duplex.

The receiving data register is of a double buffer structure

to prevent the occurrence of overrun error and provides one

frame of margin before CPU reads the received data. The

receiving data register stores the already received data while

the buffer register receives the next frame data.

By using CTS and RTS (there is no RTS pin, so any one

port must be controlled by software), it is possible to halt data

send until CPU ﬁnishes reading receive data every time a frame

is received (Handshake function).

3.11.1 Control Registers

In the UART mode, a check function is added not to start

the receiving operation by error start bits due to noise. The

channel starts receiving data only when the start bit is

The serial channel is controlled by three control registers

SC0CR, SC0MOD, and BR0CR. Transmitted and received

data is stored in register SC0BUF.

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Note: There is SC1MOD (56H) in Channel 1

Figure 3.11 (2). Serial Mode Control Register (Channel 0, SC0MOD)

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Note: Serial control register for channel 1 is SC1CR (55H).

As all error ﬂags are cleared after reading, do not test only a single bit with a bit-testing instruction.

Figure 3.11 (3). Serial Control Register (Channel, SC0CR)

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Note: As all error ﬂags are cleared after reading, do not test only a single bit with a bit-testing instruction.

Figure 3.11 (4). Serial Channel Control (Channel 0, BR0CR)

7

6

5

4

3

2

1

0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0

(Transmission)

(Receiving)

SC0BUF

(50H)

7

6

5

4

3

2

1

0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

Figure 3.11 (5). Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF)

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Figure 3.11 (6). Serial Mode Control Register (Channel 1, SC1MOD)

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Note: As all error ﬂags are cleared after reading, do not test only a single bit with a bit-testing instruction.

Figure 3.11 (7). Serial Control Register (Channel 1, SC1CR)

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Note: To use baud rate generator, set TRUN <PRRUN> to “1", putting the prescaler in RUN mode.

Figure 3.11 (8). Baud Rate Generator Control Register (Channel 0, BR0CR)

7

6

5

4

3

2

1

0

(Transmission)

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0

SC1BUF

(0054H)

7

6

5

4

3

2

1

0

(Receiving)

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

Figure 3.11 (9). Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)

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Figure 3.11 (10). Port 9 Function Register (P9FC)

Port 3.11 (11). Port 9 Open Drain Enable Register (ODE)

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3.11.2 Conﬁguration

Figure 3.11 (12) shows the block diagram of the serial channel 0.

Figure 3.11 (12). Block Diagram of the Serial Channel 0

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Figure 3.11 (13) shows the block diagram of the serial channel 1.

Figure 3.11 (13). Block Diagram of the Serial Channel 1

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➀ Baud Rate Generator

of these input clocks is selected by the baud rate genera-

tor control register BR0CR/BR1CR <BR0CK1, 0/

BR1CK1, 0>.

The baud rate generator includes a 4-bit frequency

divider, which divides frequency by 2 to 16 values to

determine the transfer rate.

Baud rate generator comprises a circuit that gener-

ates transmission and receiving clocks to determine the

transfer rate of the serial channel.

The input clock to the baud rate generator, φT0 (fc/

4), φT2 (fc/16), φT8 (fc/64), or φT32 (fc/256) is generated

by the 9-bit prescaler which is shared by the timers. One

How to calculate a transfer rate when the baud rate

generator is used is explained below.

● UART mode

Transfer rate =

Input clock of baud rate generator

Frequency divisor of baud rate generator

÷ 16

● I/O interface mode

Transfer rate =

Input clock of baud rate generator

Frequency divisor of baud rate generator

÷ 2

The relation between the input clock and the source clock (fc) is as follows:

φT0 = fc/4

φT2 = fc/16

φT8 = fc/64

φT32 = fc/256

Accordingly, when source clock fc is 12.288 MHz, input clock is φT2 (fc/16), and frequency divisor is 5, the transfer rate

in UART mode becomes as follows:

Transfer rate =

fc/16

5

÷ 16

6

= 12.288 x 10 /16/5/16 = 9600 (bps)

Table 3.11 (1) shows an example of the transfer rate in UART mode.

Also with 8-bit timer 0, the serial channel can get a transfer rate. Table 3.11 (2) shows an example of baud rate using

timer 0.

Table 3.11 (1) Selection of Transfer Rate (1) (When Baud Rate Generator is Used)

Unit (kbps)

Input Clock

φT0

φT2

φT8

φT32

fc [Mhz]

Frequency

Divisor

(fc/4)

(fc/16)

(fc/64)

(fc/256)

9.830400

2

4

8

0

5

A

3

6

C

76.800

38.400

19.200

9.600

19.200

9.600

4.800

2.400

9.600

4.800

19.200

9.600

4.800

2.400

1.200

0.600

2.400

1.200

4.800

2.400

1.200

0.600

0.300

0.150

0.600

0.300

1.200

0.600

0.300

↑

12.288000

38.400

19.200

76.800

38.400

19.200

↑

14.745600

↑

Note: Transfer rate in I/O interface mode is 8 times as fast as the values given in the above table.

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Table 3.11 (2) Selection of Transfer Rate (1) (When Timer 0 (Input Clock φT1) is Used)

Unit (Kbps)

fc

12.288MHz

12MHz

9.8304MHz

8MHz

6.144MHz

TREG0

1H

2H

96

48

32

24

19.2

12

9.6

6

76.8

38.4

62.5

48

24

16

12

9.6

6

31.25

3H

31.25

4H

19.2

9.6

5H

8H

AH

10H

14H

4.8

3

4.8

2.4

How to calculate the transfer rate (when timer 0 is used):

Transfer rate =

fc

TREG0 x 8 x 16

↑

(When timer 0 (input clock φT1) is used)

Input clock of timer 0

fc

φT1 =

/8

fc

φT4 = /32

φT16 = /128

fc

Note: Timer 0 match detect signal cannot be used as the transfer clock in I/O interface mode.

➁ Serial Clock Generation Circuit

➂ Receiving Counter

This circuit generates the basic clock for transmitting

and receiving data.

The receiving counter is a 4-bit binary counter

used in asynchronous communication (UART) mode

and counts up by SIOCLK clock. Sixteen pulses of

SIOCLK are used for receiving one bit of data, and

the data bit is sampled three times at 7th, 8th and

9th clock.

With the three samples, the received data is

evaluated by the rule of majority.

For example, if the sampled data bit is “1", “0” and

“1” at 7th, 8th and 9th clock respectively, the received

data is evaluated as “1”. The sampled data “0", “0” and

“1” is evaluated that the received data is “0”.

1) I/O interface mode (channel 1 only)

When in SCLK output mode with the set-

ting of SC1CR <IOC> = “0", the basic clock

will be generated by dividing by 2 the output

of the baud rate generator as described

before. When in SCLK input mode with the

setting of SC1CR <IOC> = “1", the rising

edge or falling edge will be detected accord-

ing to the setting of SC1CR <SCLKC> regis-

ter to generate the basic clock.

➃ Receiving Control

1) I/O interface mode (channel 1 only)

2) Asynchronous Communication (UART) mode

When in SCLK1 output mode with the

setting of SC1CR <IOC> = “0", RxD1 signal

will be sampled at the rising edge of shift

clock which is output to SCLK pin.

When in SCLK input mode with the set-

ting SC1CR <IOC> = “1", RxD1 signal will be

sampled at the rising edge or falling edge of

SCLK input according to the setting of

SC1CR <SCLKS> register.

According to the setting of SC0CR and

SC1CR <SC1, 0>, the above baud rate gen-

erator clock, internal clock φ1 (500 Kbps @ fc

= 16 MHz), or the match detect signal from

timer 0 will be selected to generate the basic

clock SIOCLK.

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the receiving buffer 1. However, unless the receiving

2) Asynchronous Communication (UART) mode

buffer 2 (SC0BUF/SC1BUF) is read before all bits of the

next data are received by the receiving buffer 1, an over-

run error occurs. If an overrun error occurs, the contents

of the receiving buffer 1 will be lost, although the contents

of the receiving buffer 2 and SC0CR <RB8> SC1CR

<RB8> are still preserved.

The parity bit added in 8-bit UART mode and the

most signiﬁcant bit (MSB) in 9-bit UART mode are stored

in SC0CR <RB8>/SC1CR <RB8>.

The receiving control has a circuit for

detecting the start bit by the rule of majority.

When two or more “0” are detected during 3

samples, it is recognized as start bit and the

receiving operation is started.

Data being received is also evaluated by

the rule of majority.

When in 9-bit UART mode, the wake-up function of

the slave controllers is enabled by setting SC0MOD

<WU>/SC1MOD <WU> to “1", and interrupt INTRX0/

INTRX1 occurs only when SC0CR <RB8>/SC1CR

<RB8> is set to “1”.

➄ Receiving Buffer

To prevent overrun error, the receiving buffer has a

double buffer structure.

Received data is stored one bit by one bit in the

receiving buffer 1 (shift register type). When 7 bits or 8

bits of data are stored in the receiving buffer 1, the stored

data is transferred to another receiving buffer 2 (SC0BUF/

SC1BUF), generating an interrupt INTRX0/INTRX1. The

CPU reads only receiving buffer 2 (SC0BUF/SC1BUF).

Even before the CPU reads the receiving buffer 2

(SC0BUF/SC1BUF), the received data can be stored in

➅ Transmission Counter

Transmission counter is a 4-bit binary counter which

is used in asynchronous communication (UART) mode

and, like a receiving counter, counts by SIOCLK clock,

generating TxDCLK every 16 clock pulses.

Figure 3.11 (14). Generation of Transmission Clock

➆ Transmission Controller

pin at the rising edge or falling edge of SCLK

input according to the setting of SC1CR

<SCLKC> register.

1) I/O interface mode (channel 1 only)

2) Asynchronous Communication (UART) mode

In SCLK output mode with the setting of

SC1CR <IOC> = “0", the data in the trans-

mission buffer are output bit by bit to TxD1

pin at the rising edge of shift clock which is

output from SCLK1 pin.

In SCLK input mode with the setting

SC1CR <IOC> = “1", the data in the trans-

mission buffer are output bit by bit to TxD1

When transmission data is written in the

transmission buffer sent from the CPU, trans-

mission starts at the rising edge of the next

TxDCLK, generating a transmission shift

clock TxDSFT.

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Handshake function

again. The INTTX0 Interrupts are generated,

requests the next send data to the CPU.

Though there is no RTS pin, a hand-

shake function can be easily conﬁgured by

setting any port assigned to the RTS func-

tion. The RTS should be output “High” to

request data send halt after data receive is

completed by a software in the RXD interrupt

routine.

Serial channel 0 has a CTS0 pin. Using

this pin, data can be sent in units of one

frame; thus, overrun errors can be avoided.

The handshake function is enabled/disabled

by SC0MOD <CTSE>.

When the CTS0 pin goes high, after

completion of the current data send, data

send is halted until the CTS0 pin goes low

Figure 3.11 (15). Handshake Function

Note 1: If the CTS signal falls during transmission, the next data is not sent after the completion of the current transmission.

Note 2: Transmission starts at the ﬁrst TxDCLK clock fall after the CTS signal falls.

Figure 3.11 (16). Timing of CTS (Clear to Send)

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➇ Transmission Buffer

bit UART mode and with SC0MOD <RB8>/SC1MOD

<RB8> when in 8-bit UART mode. If they are not equal, a

parity error occurs, and SC0CR <PERR>/SC1CR

<PERR> ﬂag is set

Transmission buffer (SC0BUF/SC1BUF) shifts to and

sends the transmission data written from the CPU from

the least signiﬁcant bit (LSB) in order, using transmission

shift clock TxDSFT which is generated by the transmis-

sion control. When all bits are shifted out, the transmis-

sion buffer becomes empty and generates INTTX0/

INTTX1 interrupt.

➉ Error Flag

Three error ﬂags are provided to increase the reliabil-

ity of receiving data.

➈ Parity Control Circuit

1. Overrun error <OERR>

When serial channel control register SC0CR <PE>/

SC1CR <PE> is set to “1", it is possible to transmit and

receive data with parity. However, parity can be added

only in 7-bit UART or 8-bit UART mode. With SC0CR

<EVEN>/SC1CR <EVEN> register, even (odd) parity can

be selected.

For transmission, parity is automatically generated

according to the data written in the transmission buffer

SCBUF, and data are transmitted after being stored in

SC0BUF <TB7>/SC1BUF <TB7> when in 7-bit UART

mode while in SCMOD <TB8>/SCMOD <TB8> when in

8-bit UART mode. <PE> and <EVEN> must be set

before transmission data are written in the transmission

buffer.

If all bits of the next data are received in

receiving buffer 1 while valid data is stored in

receiving buffer 2 (SCBUF), an overrun error

will occur.

2. Parity error <PERR>

The parity generated for the data shifted

in receiving buffer 2 (SCBUF) is compared

with the parity bit received from RxD pin. If

they are not equal, a parity error occurs.

3. Framing error <FERR>

For receiving, data is shifted in the receiving buffer 1,

and parity is added after the data is transferred in the

receiving buffer 2 (SC0BUF/SC1BUF), and then com-

pared with SC0BUF <RB7>/SC1BUF <RB7> when in 7-

The stop bit of received data is sampled

three times around the center. If the majority

is “0", a framing error occurs.

11

Generating Timing

1) UART mode

Receiving

Mode

9-Bit

8-Bit + Parity

8-Bit, 7-Bit + Parity, 7-Bit

Interrupt timing

Center of last bit (Bit 8)

Center of stop bit

Center of last bit (parity bit)

Center of stop bit

Framing error timing

Parity error timing

Overrun error timing

Center of last bit (Bit 8)

Center of last bit (parity bit)

Note: Framing error occurs after an interrupt has occurred. Therefore, to check for framing error during interrupt operation, it is necessary to wait for 1 bit

period of transfer rate.

Transmitting

Mode

9-Bit

8-Bit + Parity

8-Bit, 7-Bit + Parity, 7-Bit

Interrupt timing

Just before last bit is transmitted.

←

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2) I/O Interface mode

SCLK output mode

SCLK input mode

Immediately after rise of last SCLK signal (See Figure 3.11 (19) ).

Transmission interrupt timing

Receiving interrupt timing

Immediately after rise of last SCLK signal (rising mode), or immediately after fall in falling mode

(See Figure 3.11 (20)).

Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after

last SCLK (See Figure 3.11 (21)).

SCLK output mode

SCLK input mode

Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after

SCLK (See Figure 3.11 (22)).

3.11.3 Operational Description

This mode is used to increase the number of I/O pins for trans-

mitting or receiving data to or from the external shifter register.

This mode includes SCLK output mode to output syn-

chronous clock SCLK and SCLK input mode to input external

synchronous clock SCLK.

(1) Mode 0 (I/O interface mode)

Figure 3.11 (17). Example of SCLK Output Mode Connection

FIgure 3.11 (18). Example of SCLK Input Mode Connection

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➀ Transmission

time the CPU writes data in the transmission buffer. When

all data is output, INTES1 <ITX1C> will be set to generate

INTTX1 interrupt.

In SCLK output mode, 8-bit data and synchronous clock

are output from TxD pin and SCLK pin, respectively, each

Figure 3.11 (19) Transmitting Operation in I/O Interface Mode (SCLK Output Mode)

In SCLK output mode, 8-bit data are output from TxD1

pin when SCLK input becomes active while data are

written in the transmission buffer by CPU.

When all data are output, INTES1 <ITXIC> will be set

to generate INTTX1 interrupt.

Figure 3.11 (20). Transmitting Operation in I/O Interface Mode (SCLK Input Mode)

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➁ Receiving

<IRX1C> is cleared by reading the received data.

When 8-bit data are received, the data will be trans-

ferred in the receiving buffer 2 (SC1BUF) at the timing

shown below, and INTES1 <IRX1C> will be set again

to generate INTRX1 interrupt.

In SCLK output mode, synchronous clock is output

from SCLK pin and the data is shifted in the receiving

buffer 1 whenever the receive interrupt ﬂag INTES1

Figure 3.11 (21). Receiving Operation in I/O Interface Mode (SCLK Output Mode)

In SCLK input mode, the data is shifted in the receiving

buffer 1 when SCLK input becomes active, while the

receive interrupt ﬂag INTES1 <IRX1C> is cleared by read-

ing the received data. When 8-bit data is received, the

data will be shifted in the receiving buffer 2 (SC1BUF) at

the timing shown below, and INTES1 <IRX1C> will be set

again to generate INTRX interrupt.

Figure 3.11 (22). Receiving Operation in I/O Interface Mode (SCLK Input Mode)

Note: For data receiving, the system must be placed in the receive enable state (SCMOD <RXE> = “1”)

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(2)

Mode 1 (7-bit UART Mode)

and even parity or odd parity is selected by SC0CR

<EVEN> /SC1CR <EVEN> when <PE> is set to “1”

(enable).

The 7-bit mode can be set by setting serial channel

mode register SC0MOD <SM1, 0> /SC1MOD <SM1,

0> to “01”.

In this mode, a parity bit can be added, and the addi-

tion of a parity bit can be enabled or disabled by serial

channel control register SC0CR <PE> /SC1CR <PE>,

Setting example: When transmitting data with the

following format, the control

registers should be set as described

below. Channel 0 is explained here.

Direction of transmission (transmission rate: 2400 bps @ fc = 12.288MHz)

7

x

0

1

*

6

x

0

1

x

1

*

5

4

3

2

1

0

P9CR

←

–

1

Select P90 as the TxD pin.

)

P9FC

–

1

–

0

*

x

0

–

0

*

–

0

x

1

0

1

–

*

SC0MOD

SC0CR

BR0CR

TRUN

1

x

0

–

*

Set 7-bit UART mode.

Add an even parity.

0

–

*

1

–

*

Set transfer rate at 2400 bps.

Start the prescaler for the baud rate generator.

Enable INTTX0 interrupt and sets interrupt level 4.

Set data for transmission.

INTES0

SC0BUF

Note: x; don’t care –; no change

SC1CR <PE>, and even parity or odd parity is selected

by SC0CR <EVEN>/SC1CR <EVEN> when <PE> is

set to “1” (enable).

(3)

Mode 2 (8-bit UART Mode)

The 8-bit UART mode can be speciﬁed by setting

SC0MOD <SM1, 0> / SC1MOD <SM1, 0> to “10”. In

this mode, parity bit can be added, the addition of a

parity bit is enabled or disabled by SC0CR <PE> /

Setting example: When receiving data with the

following format, the control register

should be set as described below.

Direction of transmission (transmission rate: 9600 bps @ fc = 12.288MHz)

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Main setting

7

x

6

x

5

–

1

0

–

4

–

x

3

–

1

x

2

–

0

x

1

0

–

0

–

1

0

1

–

0

P9CR

←

Select P91 (RxD) as the input pin.

Enable receiving in 8-bit UART mode.

Add an odd parity.

SC0MOD

SC0CR

BR0CR

TRUN

–

x

0

x

0

1

–

1

–

0

–

1

–

1

Set transfer rate at 9600 bps.

x

Start the prescaler for the baud rate generator.

Enable INTTX0 interrupt and sets interrupt level 4.

INTES0

–

Interrupt processing

Acc ← SC0CR and 00011100

If Acc ≠ 0 then ERROR

Acc ← SC0BUF

Check for error.

)

Read the received data.

Note: x; don’t care –; no change

(4)

Mode 3 (9-bit UART Mode)

Wake-up function

In 9-bit UART mode, the wake-up function of slave

controllers is enabled by setting SC0MOD <WU> /

SC1MOD <WU> to “1”. The interrupt INTRX1/INTRX0

occurs only when <RB8> = 1

The 9-bit UART mode can be speciﬁed by setting

SC0MOD <SM1, 0> /SC1MOD <SM1, 0> to “11”. In

this mode, parity bit cannot be added

For transmission, the MSB (9th bit) is written in SCM0D

<TB8>, while in receiving it is stored in SCCR <RB8>.

For writing and reading the buffer, the MSB is read or

written ﬁrst, then SC0BUF/SC1BUF.

.

Note: TxD pin of the slave controllers must be in open drain output mode.

Figure 3.11 (23). Serial Link Using Wake-Up Function

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➂ The master controller transmits one-frame data

Protocol

➀ Select the 9-bit UART mode for master and slave

including the 8-bit select code for the slave control-

lers. The MSB (bit 8) <TB8> is set to “1”.

controllers.

➁ Set SC0MOD <WU>/SC1MOD <WU> bit of each

slave controller to “1” to enable data receiving.

➃ Each slave controller receives the above frame, and

clears WU bit to “0” if the above select code matches

its own select code.

➄ The master controller transmits data to the specified

slave controller whose SC0MOD <WU>/SC1MOD

<WU> bit is cleared to “0.” The MSB (bit 8) <TB8> is

cleared to “0”.

➅ The other slave controllers (with the <WU> bit remain-

ing at “1”) ignore the receiving data because their

MSBs (bit 8 or <RB8>) are set to “0” to disable the

interrupt INTRX0/INTRX1.

The slave controllers (WU = 0) can transmit data

to the master controller, and it is possible to indicate

the end of data receiving to the master controller by

this transmission.

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TMP96C141AF

Setting Example: To link two slave controllers serially

the internal clock φ1 (fc/2) as the

transfer clock.

with the master controller, and use

Since serial channels 0 and 1 operate in exactly the

way, channel 0 is used for the purposes of explanation.

same

• Setting the master controller

Main setting

P9CR

P9FC

←

x

1

x

1

–

0

–

x

–

1

–

x

0

x

0

1

Select P90 as TxD pin and P91 as RxD pin.

)

INTES0

0

1

Enable INTTX0 and sets the interrupt level 4.

Enable INTRX0 and sets the interrupt level 5.

Set φ1 (fc/2) as the transmission clock in 9-bit UART mode.

Set the select code for slave controller 1.

SC0MOD

SC0BUF

←

1

0

1

0

1

0

1

0

1

0

1

INTTX0 interrupt

SC0MOD

SC0BUF

←

–

*

0

*

–

*

–

*

–

*

–

*

–

*

–

*

Set TB8 to “0”.

Set data for transmission.

• Setting the slave controller 2

Main setting

P9CR

←

x

1

0

x

1

0

–

x

–

x

–

x

–

x

0

x

1

0

Select P91 as RxD pin and P90 as TxD pin (open drain output).

Enable INTRX0 and INTTX0.

)

P9FC

ODE

x

–

1

INTES0

SC0MOD

0

1

Set <WU> to “1” in the 9-bit UART transmission mode with transfer

clock φ1 (fc/2).

INTRX0 interrupt

Acc ← SC0BUF

If Acc = Select Code

Then SC0MOD4

←

–

0

–

Clear <WU> to “0”.

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TMP96C141AF

Figure 3.12 (1) shows the block diagram of the A/D con-

verter. The 4-channel analog input pins (AN3 to AN0) are

shared by input-only P5 and so can be used as input port.

3.12 Analog/Digital Converter

The TMP96C141AF contains a high-speed analog/digital con-

verter (A/D converter) with 4-channel analog input that features

10-bit successive approximation.

Figure 3.12 (1). Block Diagram of A/D Converter

Note: This A/D converter does not have a built-in sample and hold circuit. Therefore, when A/D converting high-frequency signals, connect a sample and

hold circuit externally.

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TMP96C141AF

Figure 3.12 (2). A/D Control Register

140

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TMP96C141AF

7

6

5

4

3

2

1

0

ADREG0L

(0060H)

bit Symbol

Read/Write

After reset

Function

ADR01

ADR00

R

Undeﬁned

1

Lower 2 bits of A/D result for AN0 are stored.

7

6

5

4

3

2

1

0

ADREG0H

(0061H)

bit Symbol

Read/Write

After reset

Function

ADR09

ADR08

ADR07

ADR06

ADR05

ADR04

ADR03

ADR02

R

Undeﬁned

Upper 8 bits of A/D result for AN0 are stored.

7

6

5

4

3

2

1

0

ADREG1L

(0062H)

bit Symbol

Read/Write

After reset

Function

ADR11

ADR10

R

Undeﬁned

1

Lower 2 bits of A/D result for AN1 are stored.

7

6

5

4

3

2

1

0

ADREG1H

(0063H)

bit Symbol

Read/Write

After reset

Function

ADR19

ADR18

ADR17

ADR16

ADR15

ADR14

ADR13

ADR12

R

Undeﬁned

Upper 8 bits of A/D result for AN1 are stored.

Figure 3.12 (3-1). A/D Conversion Result Register (ADREG0, 1)

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TMP96C141AF

7

6

5

4

3

2

1

0

ADREG2L

bit Symbol

ADR21

ADR20

(0064H)

Read/Write

R

After reset

Function

Undeﬁned

1

Lower 2 bits of A/D result for AN2 are stored.

7

6

5

4

3

2

1

0

ADREG2H

bit Symbol

ADR29

ADR28

ADR27

ADR26

ADR25

ADR24

ADR23

ADR22

(0065H)

Read/Write

R

After reset

Function

Undeﬁned

Upper 8 bits of A/D result for AN2 are stored.

7

6

5

4

3

2

1

0

ADREG3L

bit Symbol

ADR31

ADR30

(0066H)

Read/Write

R

After reset

Function

Undeﬁned

1

Lower 2 bits of A/D result for AN3 are stored.

7

6

5

4

3

2

1

0

ADREG3H

bit Symbol

ADR39

ADR38

ADR37

ADR36

ADR35

ADR34

ADR33

ADR32

(0067H)

Read/Write

R

After reset

Function

Undeﬁned

Upper 8 bits of A/D result for AN3 are stored.

Figure 3.12 (3-2). A/D Conversion Result Register (ADREG2, 3)

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3.12.1 Operation

(1) Analog Reference Voltage

(5) A/D Conversion Speed Selection

There are two A/D conversion speed modes: high

speed mode and low speed mode. The selection is

executed by ADMOD <ADCS> register.

When reset, ADMOD <ADCS> will be initialized to “0,”

so that high speed conversion mode will be selected.

High analog reference voltage is applied to the VREF

pin, and low analog reference voltage is applied to

AGND pin.

The reference voltage between VREG and AGND is

divided by 1024 using ladder resistance, and com-

pared with the analog input voltage for A/D conversion.

(6)

A/D Conversion End and Interrupt

• A/D conversion single mode

(2)

Analog Input Channels

ADMOD <EOCF> for A/D conversion end will be

set to “1,” ADMOD <ADBF> ﬂag will be reset to “0,”

and INTAD interrupt will be enabled when A/D conver-

sion of speciﬁed channel ends in ﬁxed conversion

channel mode or when A/D conversion of the last

channel ends in channel scan mode.

Analog input channel is selected by ADMOD <ADCH1,

0>. However, which channel to select depends on the

operation mode of the A/D converter.

In ﬁxed analog input mode, one channel is selected by

ADMOD <ADCH1, 0> among four pins: AN0 to AN3.

• A/D conversion repeat mode

In analog input channel scan mode, the number of

channels to be scanned from AN0 is speciﬁed by

ADMOD <ADCH1, 0>, such as AN0 → AN1, AN0 →

AN1 → AN2, and AN0 → AN1 → AN2 → AN3.

For both ﬁxed conversion channel mode and con-

version channel scan mode, INTAD should be disabled

when in repeat mode. Always set the INTE0AD at

“000,” that disables the interrupt request.

Write “0” to ADMOD <REPET> to end the repeat

mode. Then, the repeat mode will be exited as soon as

the conversion in progress is completed.

When reset, A/D conversion channel register will be ini-

tialized to ADMOD <ADCH1, 0> = 00, so that AN0 pin

will be selected.

The pins which are not used as analog input channel

can be used as ordinary input port P5.

(7)

(8)

Storing the A/D Conversion Result

(3)

(4)

Starting A/D Conversion

The results of A/D conversion are stored in ADREG0 to

ADREG3 registers for each channel. In repeat mode,

the registers are updated whenever conversion ends.

A/D conversion starts when A/D conversion register

ADMOD <ADS> is written “1". When A/D conversion

starts, A/D conversion busy ﬂag ADMOD <ADBF>

which indicates “A/D conversion is in progress” will be

set to “1".

ADREG0 to ADREG3 are read-only registers.

Reading the A/D Conversion Result

The results of A/D conversion are stored in ADREG0 to

ADREG3 registers. When the contents of one of

ADREG0 to ADREG3 registers are read, ADMOD

<EOCF> will be cleared to “0".

A/D Conversion Mode

Both ﬁxed A/D conversion channel mode and A/D

conversion channel scan mode have two conversion

modes, i.e., single and repeat conversion modes.

In ﬁxed channel repeat mode, conversion of speciﬁed

one channel is executed repeatedly.

In scan repeat mode, scanning from AN0, → AN3 is

executed repeatedly.

A/D conversion mode is selected by ADMOD <REPET,

SCAN>.

Setting example: When the analog input voltage of the

AN3 pin is A/D converted and the

result is stored in the memory

…

address FF10H by A/D interrupt

INTAD routine.

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TMP96C141AF

Main setting

INTE0AD

ADMOD

←

1

x

1

x

0

–

0

–

1

–

1

–

1

Enable INTAD and sets interrupt level 4.

Specify AN3 pin as an analog input channel and starts A/D conversion in high speed

mode.

INTAD routine

WA

←

>

ADREG3

Read ADREG3L and ADREG3H values and writes to WA (16 bit).

Right-shifts WA six times and writes 0 in upper bits.

Writes contents of WA in memory at FF10H.

WA

>

6

(00FF10H)

←

WA

When the analog input voltage of AN0 ~ AN2 pins is A/D converted in high speed conversion channel scan repeat mode.

INTE0AD

ADMOD

←

1

x

0

x

0

1

–

1

–

0

–

1

–

1

–

0

Disable INTAD.

Start the A/D conversion of analog input channels AN0 ~ AN2 in the high-speed

scan repeat mode.

Note: x; don’t care –; no change

3.13 Watchdog Timer (Runaway Detecting Timer)

The TMP96C141AF is containing watchdog timer of Runaway

detecting.

The watchdog timer (WDT) is used to return the CPU to

the normal state when it detects that the CPU has started to

malfunction (runaway) due to causes such as noise. When the

watchdog timer detects a malfunction, it generates a non-

maskable interrupt to notify the CPU of the malfunction, and

outputs 0 externally from watchdog timer out pin WDTOUT to

notify the peripheral devices of the malfunction.

Connecting the watchdog timer output to the reset pin

internally forces a reset.

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3.13.1 Conﬁguration

Figure 3.13 (1) shows the block diagram of the watchdog timer (WDT).

Figure 3.13 (1). Block Diagram of Watchdog Timer

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TMP96C141AF

The watchdog timer is a 22-stage binary counter which

uses φ (fc/2) as the input clock. There are four outputs from the

binary counter: 2 /fc, 2 /fc, 2 /fc, and 2 /fc. Selecting one

of the outputs with the WDMOD register generates a watch-

dog interrupt, and outputs watchdog timer out when an over-

ﬂow occurs.

be reset. The watchdog timer out pin is set to 1 by clearing the

watchdog timer (by writing a clear code 4EH in the WDCR reg-

ister). In other words, the WDTOUT keeps outputting “0” until

the clear code is written.

The watchdog timer out pin can also be connected to the

reset pin internally. In this case, the watchdog timer out pin

(WDTOUT) outputs 0 at 8 to 20 states (800ns to 2µs @

20MHz) and resets itself.

16

18

20

22

Since the watchdog timer out pin (WDTOUT) outputs “0”

due to a watchdog timer overﬂow, the peripheral devices can

Figure 3.13 (2). Normal Mode

Figure 3.13 (3). Reset Mode

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3.13.2 Control Registers

Watchdog timer WDT is controlled by two control registers

WDMOD and WDCR.

To disable, it is necessary to clear this bit to “0” and

write the disable code (B1H) in the watchdog timer

control register WDCR. This makes it difﬁcult for the

watchdog timer to be disabled by runaway.

However, it is possible to return from the disable state

to enable state by merely setting <WDTE> to “1".

(1)

Watchdog Timer Mode Register (WDMOD)

➀ Setting the detecting time of watchdog timer

➂ Watchdog timer out reset connection <RESCR>

<WDTP>

This register is used to connect the output of the

watchdog timer with RESET terminal, internally. Since

WDMOD <RESCR> is initialized to 0 at reset, a reset

by the watchdog timer will not be performed.

This 2-bit register is used to set the watchdog timer

interrupt time for detecting the runaway. This register is

initialized to WDMOD <WDTP1, 0> = 00 when reset,

16

and therefore 2 /fc is set. (The number of states is

approximately 32,768).

(2)

Watchdog Timer Control Register (WDCR)

➁ Watchdog timer enable/disable control register

<WDTE>

This register is used to disable and clear the binary

counter of the watchdog timer function.

When reset, WDMOD <WDTE> is initialized to “1”

enable the watchdog timer.

• Disable control

WDMOD

WDCR

←

0

1

–

0

–

1

–

1

–

0

–

0

x

Clear WDMOD <WDTE> to “0".

Write the disable code (B1H).

0

1

• Enable control

counting by writing clear code (4EH) into the WDCR reg-

ister.

Set WDMOD <WDTE> to “1".

• Watchdog timer clear control

The binary counter can be cleared and resume

WDCR

←

0

1

0

1

0

Write the clear code (4EH).

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TMP96C141AF

Figure 3.13 (4). Watchdog Timer Mode Register

148

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TMP96C141AF

Figure 3.13 (5). Watchdog Timer Control Register

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TMP96C141AF

3.13.3 Operation

ation by an anti-malfunction program. By connecting the

watchdog timer out pin to peripheral devices’ resets, a CPU

malfunction can also be acknowledged to other devices.

The watchdog timer restarts operation immediately after

resetting is released.

The watchdog timer stops its operation in the IDLE and

STOP modes. In the RUN mode, the watchdog timer is

enabled.

The watchdog timer generates interrupt INTWD after the

detecting time set in the WDMOD <WDTP1, 0> register and

outputs a low level signal. The watchdog timer must be zero-

cleared by software before an INTWD interrupt is generated. If

the CPU malfunctions (runaway) due to causes such as noise,

but does not execute the instruction used to clear the binary

counter, the binary counter overﬂows and an INTWD interrupt

is generated. The CPU detects malfunction (runaway) due to

the INTWD Interrupt and it is possible to return to normal oper-

However, the function can be disabled when entering the

RUN mode.

Example:

➀ Clear the binary counter

WDCR

←

0

1

0

1

0

Write clear code (4EH).

18

➁ Set the watchdog timer detecting time to 2 /fc

WDMOD

←

1

0

1

–

x

➂ Disable the watchdog timer

WDMOD

WDCR

←

0

1

–

0

–

1

–

1

–

0

–

0

x

Clear WDTE to “0".

0

1

Write disable code (B1H).

➃ Set IDLE mode

WDMOD

WDCR

←

0

1

–

0

–

1

–

1

0

x

Disables WDT and sets IDLE mode.

Set the standby mode

0

1

Executes HALT command

16

➄ Set the STOP mode (warming up time: 2 /fc)

WDMOD

Executes HALT command

←

–

1

0

1

x

Set the STOP mode.

Execute HALT instruction. Set the standby mode.

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4. Electrical Characteristics

4.1 Absolute Maximum (TMP96C141AF)

Symbol

Parameter

Power Supply Voltage

Rating

Unit

V

-0.5 ~ 6.5

V

cc

V IN

Σ IOL

Input Voltage

-0.5 ~ V + 0.5

cc

Output Current (total)

100

-100

mA

mW

°C

Σ IOH

PD

°

Power Dissipation (Ta = 70 C)

Soldering Temperature (10s)

Storage Temperature

600

T SOLDER

T STG

T OPR

260

°

-65 ~ 150

-20 ~ 70

C

°

Operating Temperature

C

4.2 DC Characteristics (TMP96C141AF)

°

V

= 5V ± 10%, Ta = -20 ~ 70 C (Typical values are for Ta = 25 C and V = 5V)

cc

Symbol

V IL

Parameter

Min

Max

Unit

Test Condition

Input Low Voltage (AD0-15)

P2, P3, P4, P5, P6, P7, P8, P9

RESET, NMI, INTO (P87)

EA

-0.3

2.2

0.8

V

V IL1

V IL2

V IL3

V IL4

V IH

0.3V

cc

0.25V

cc

0.3

0.2V

X1

cc

Input High Voltage (AD0-15)

P2, P3, P4, P5, P6, P7, P8, P9

RESET, NMI, INTO (P87)

EA

V + 0.3

cc

V IH1

V IH2

V IH3

V IH4

V OL

0.7V

V

+ 0.3

cc

0.75V

cc

V

- 0.3

cc

X1

0.8V

cc

Output Low Voltage

Output High Voltage

0.45

I OL = 1.6mA

I OH = -400µA

I OH = -100µA

I OH = - 20µA

V OH

V OH1

V OH2

2.4

0.75V

cc

0.9V

cc

Darlington Drive Current

(8 Output Pins max.)

V EXT - 1.5V

R EXT = 1.1KΩ

I DAR

-1.0

-3.5

mA

I LI

Input Leakage Current

Output Leakage Current

0.02 (Typ)

0.05 (Typ)

±5

µA 0.0 ≤ V ≤ V

in cc

I LO

±10

µA 0.2 ≤ V ≤ V - 0.2

in cc

Operating Current (RUN)

IDLE

STOP (Ta = -20 ~ 70°C)

STOP (Ta = 0 ~ 50°C)

50

10

50

10

mA

t

= 16MHz

osc

26 (Typ)

1.7 (Typ)

0.2 (Typ)

I

cc

µA 0.2 ≤ V ≤ V - 0.2

in cc

in

cc

Power Down Voltage

(@STOP, RAM Back up)

V IL2 = 0.2V ,

cc

V STOP

2.0

50

6.0

V

V IH2 = 0.8V

cc

R RST

C IO

RESET Pull Up Register

Pin Capacitance

150

10

KΩ

pF tosc = 1MHz

Schmitt Width

RESET, NMI, INTO (P87)

V TH

R K

0.4

50

1.0 (Typ)

150

V

Pull Down/Up Register

KΩ

Note: I-DAR is guaranteed for a total of up to 8 ports.

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4.3 AC Electrical Characteristics (TMP96C141AF) V = 5V±10%, Ta = -20 ~ 70 C (4MHz ~ 20MHz)

°

cc

Variable

16MHz

20MHz

No.

Symbol

Parameter

Unit

Min

Max

250

Min

Max

Min

Max

1

t

Osc. Period (= x)

CLK width

50

62.5

85

50

60.0

50

ns

OSC

2

3

t

2x - 40

CLK

t

A0 - 23 Valid→CLK Hold

CLK Valid→A0 - 23 Hold

A0-15 Valid→ALE fall

ALE fall→A0 - 15 Hold

ALE High width

0.5x - 20

1.5x - 70

0.5x - 15

x - 40

11.0

240

160

23.0

1.0

AK

KA

4

50

5

t

100

-5

AL

LA

6

7

t

LL

LC

CL

8

t

ALE fall→RD/WR fall

0.5x - 30

0.5x - 20

x - 25

9

RD/WR rise→ALE rise

A0 - 15 Valid→RD/WR fall

A0 - 23 Valid→RD/WR fall

RD/WR rise→A0 - 23 Hold

A0 - 15 Valid→D0 - 15 input

A0 - 23 Valid→D0 - 15 input

RD fall→D0 - 15 input

RD Low width

11.0

38.0

44.0

11.0

50

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

t

250

25.0

5

ACL

ACH

t

1.5x - 50

0.5x - 20

t

CA

t

3.0x - 45

3.5x - 65

2.0x - 50

143

154

75

105

110

50

ADL

ADH

t

RD

t

2.0x - 40

0

85.0

0.0

60.0

0.0

RR

HR

t

RD rise→D0 - 15 Hold

RD rise→A0 - 15 output

WR Low width

t

x - 15

48.0

85.0

75.0

21.0

35.0

60.0

50.0

15.0

RAE

WW

t

2.0x - 40

2.0x - 50

0.5x - 10

t

D0 - 15 Valid→WR rise

WR rise→D0 - 15 Hold

A0 - 23 Valid→WAIT input (1WAIT + n mode)

A0 - 15 Valid→WAIT input (1WAIT + n mode)

RD/WR fall→WAIT Hold (1WAIT + n mode)

A0 - 23 Valid→PORT input

A0 - 23 Valid→PORT Hold

WR rise→PORT Valid

DW

WD

t

3.5x - 90

3.0x - 80

129

108

85

70

AEH

AWL

t

2.0x + 0

125.0

206.0

100.0

175.0

CW

t

2.5x - 120

200

80

36

APH

t

2.5x + 50

APH2

t

200

CP

t

A0 - 23 Valid→RAS fall

A0 - 15 Valid→RAS fall

RAS fall→D0 - 15 input

RAS fall→A0 - 15 Hold

RAS Low width

1.0x - 40

0.5x - 15

23.0

16.0

10.0

ASRH

t

ASRL

t

2.5x - 70

130

86

RAC

t

0.5x - 15

2.0x - 40

1.0x - 35

0.5x - 25

1.0x - 40

16.0

85.0

28.0

6.0

10.0

60.0

15.0

0.0

RAH

t

RAS

t

RAS High width

RP

t

CAS fall→RAS rise

RSH

RSC

RCD

CAC

RAS rise→CAS rise

t

RAS fall→CAS fall

23.0

100

CAS fall→D0 - 15 input

CAS Low width

1.5x - 65

29

10

t

1.5x - 30

64.0

40.0

CAS

AC Measuring Conditions

• Output Level:

High 2.2V

/Low 0.8V, CL50pF

(However CL = 100pF for AD0 ~ AD15, AD0 ~ AD23, ALE, RD, WR, HWR, R/W, CLK, RAS, CAS0 ~ CAS2)

• Input Level: High 2.4V /Low 0.45V (AD0 ~ AD15)

High 0.8Vcc /Low 0.2Vcc (Except for AD0 ~ AD15)

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(1) Read Cycle

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(2) Write Cycle

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4.4 A/D Conversion Characteristics (TMP96C141AF)

V

= 5V±10% TA = -20 ~ 70°C

cc

Symbol

Parameter

Analog reference voltage

Min

Typ

Max

Unit

V

V - 1.5

V

REF

cc

ss

cc

A

Analog reference voltage

Analog input voltage range

V

GND

ss

V

ss

AIN

REF

I

Analog current for analog reference voltage

0.5

1.5

±4.0

±6.0

mA

Low speed conversion mode

±1.5 (TBD)

±3.0 (TBD)

Error

4 ≤ fc

High speed conversion mode

(Quantize error of

±0.5 LSB not included)

≤ 16MHz

≤ 20MHz

LSB

Low speed conversion mode

High speed conversion mode

±1.5 (TBD)

±4.0 (TBD)

±4.0

±8.0

16 ≤ fc

4.5 Serial Channel Timing - I/O Interface Mode

V

= 5V±10% TA = -20 ~ 70°C

cc

(1) SCLK Input Mode

Variable

16MHz

20MHz

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

t

SCLK cycle

16x

1

0.8

100

150

0

µs

ns

SCY

OSS

OHS

Output Data→rising edge of SCLK

SCLK rising edge→output data hold

SCLK rising edge→input data hold

SCLK rising edge→effective data input

t

/2 - 5x - 50

137

212

0

SCY

t

5x - 100

0

t

HSR

SRD

t

- 5x - 100

587

450

SCY

(2) SCLK Output Mode

Variable

16MHz

20MHz

Symbol

Parameter

SCLK cycle (programmable)

Unit

Min

Max

Min

Max

Min

Max

t

16x

8192x

1

725

45

0

512

0.8

550

20

409.6

µs

ns

SCY

OSS

OHS

Output Data→rising edge of SCLK

SCLK rising edge→output data hold

SCLK rising edge→input data hold

SCLK rising edge→effective data input

t

- 2x - 150

SCY

t

2x - 80

0

t

0

HSR

t

- 2x - 150

725

550

SRD

SCY

4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7)

V

= 5V±10% TA = -20 ~ 70°C

cc

Variable

16MHz

20MHz

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

t

Clock cycle

8x + 100

4x + 40

600

290

500

240

ns

VCK

t

Low level clock pulse width

High level clock pulse width

VCKL

VCKH

t

TOSHIBA CORPORATION

155

TMP96C141AF

4.7 Interrupt Operation

V

= 5V±10% Ta = -20 ~ 70°C

cc

Variable

16MHz

Min Max

20MHz

Min Max

Symbol

Parameter

Unit

Min

Max

t

NMI, INT0 Low level pulse width

NMI, INT0 High level pulse width

INT4 ~ INT7 Low level pulse width

INT4 ~ INT7 High level pulse width

4x

250

600

200

500

ns

INTAL

t

4x

INTAH

t

8x + 100

INTBL

INTBH

t

156

TOSHIBA CORPORATION

TMP96C141AF

4.8 Timing Chart for I/O Interface Mode

TOSHIBA CORPORATION

157

TMP96C141AF

4.9 Timing Chart for Bus Request (BUSRQ)/BUS Acknowledge (BUSAK)

Variable

16MHz

20MHz

Symbol

Parameter

BUSRQ setup time for CLK

Unit

Min

Max

Min

Max

Min

Max

t

120

ns

BRC

t

CLK→BUSAK falling edge

CLK→BUSAK rising edge

Output buffer is off to BUSAK

1.5x + 120

0.5x + 40

80

214

71

195

65

CBAL

CBAH

t

0

80

0

80

ABA

BAA

BUSAK

output buffer is on.

80

Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “Wait” cycle.

Note 2: This line only shows the output buffer is off-states. They don’t indicate the signal levels are ﬁxed. After the bus is released, the signal level is kept

dynamically before the bus is released by the external capacitance. Therefore, to ﬁx the signal level by an external resistance under the bus is releasing,

the design must be carefully because of the level-ﬁx will be delayed. The internal programmable pull-up/pull-down resistance is switched active by the

internal signal.

158

TOSHIBA CORPORATION

TMP96C141AF

4.10 Interrupt Operation

= 5V, Ta = -25°C, unless otherwise noted

V

cc

TOSHIBA CORPORATION

159

TMP96C141AF

(1) I/O port

(2) I/O port control

(3) Timer control

5. Table of Special Function Registers

(SFRs)

(SFR; Special Function Register)

(4) Pattern Generator control

(5) Watch Dog Timer control

(6) Serial Channel control

(7) A/D converter control

(8) Interrupt control

The special function registers (SFRs) include the I/O ports

and peripheral control registers allocated to the 128-byte

addresses from 000000H to 00007FH.

(9) Chip Select/Wait Control

Conﬁguration of the table

160

TOSHIBA CORPORATION

TMP96C141AF

Table 5 I/O Register Address Map

Name Address Name

40H TREG6L

Address

000000H P0

Name

Address

20H TRUN

Address

60H ADREG0L

Name

1H P1

2H P0CR

3H

21H

41H TREG6H

42H TREG7L

43H TREG7H

44H CAP3L

45H CAP3H

46H CAP4L

47H CAP4H

48H T5MOD

49H T5FFCR

4AH

61H ADREG0H

62H ADREG1L

63H ADREG1H

64H ADREG2L

65H ADREG2H

66H ADREG3L

67H ADREG3H

68H B0CS

69H B1CS

6AH B2CS

6BH

22H TREG0

23H TREG1

24H TMOD

25H TFFCR

26H TREG2

27H TREG3

28H P0MOD

29H P1MOD

2AH PFFCR

2BH

4H P1CR

5H P1FC

6H P2

7H P3

8H P2CR

9H P2FC

AH P3CR

BH P3FC

CH P4

4BH

2CH

4CH PG0REG

4DH PG1REG

4EH PG01CR

4FH

6CH

DH P5

2DH

6DH

EH P4CR

FH

2EH

6EH

2FH

6FH

10H P4FC

11H

30H TREG4L

31H TREG4H

32H TREG5L

50H SC0BUF

51H SC0CR

52H SC0MOD

53H BR0CR

54H SC1BUF

55H SC1CR

56H SC1MOD

57H BR1CR

58H ODE

59H

70H INTE0AD

71H INTE45

72H INTE67

73H INTET10

74H INTEPW10

75H INTET54

76H INTET76

77H INTES0

78H INTES1

79H

12H P6

13H P7

14H P6CR

15H P7CR

16H P6FC

17H P7FC

18H P8

19H P9

1AH P8CR

1BH P9CR

1CH P8FC

1DH P9FC

1EH

33H TREG5H

34H CAP1L

35H CAP1H

36H CAP2L

37H CAP2H

38H T4MOD

39H TFF4CR

3AH T45CR

3BH

5AH

7AH

5BH

7BH IIMC

7CH DMA0V

7DH DMA1V

7EH DMA2V

7FH DMA3V

3CH

5CH WDMOD

5DH WDCR

5EH ADMOD

5FH

3DH

3EH

1FH

3FH

TOSHIBA CORPORATION

161

TMP96C141AF

(1) I/O Port

Symbol

Name

Address

7

6

5

4

3

2

1

0

P07

P06

P05

P04

P03

P02

P01

P00

R/W

P0

PORT0

00H

Input mode

Undeﬁned

P17

P16

P15

P14

P13

P12

P11

P10

R/W

P1

P2

P3

P4

PORT1

PORT2

PORT3

PORT4

01H

06H

07H

0CH

Input mode

0

P27

P26

P25

P24

P23

P22

P21

P20

R/W

Input mode

0

P37

P36

P35

P34

P33

P32

P31

P30

R/W

Input mode

Output mode

1

P41

1

P42

P40

R/W

Input mode

1

0

1

P53

P63

P52

P51

P50

R

P5

P6

PORT5

PORT6

0DH

12H

Input mode

P67

1

P66

1

P65

1

P64

1

P62

P61

P60

R/W

Input mode

1

P73

P72

P71

P70

R/W

P7

P8

P9

PORT7

PORT8

PORT9

13H

18H

19H

Input mode

1

P87

1

P86

1

P85

P84

P83

P82

P81

P80

R/W

Input mode

1

P95

P94

P93

P92

P91

P90

R/W

Input mode

1

Note: When P30 pin is deﬁned as RD signal output mode (P30F = 1), clearing the output latch register P30 to “0” outputs the RD strobe from P30 pin for

PSRAM, even when the internal address is accessed. If the output latch register P30 remains “1”, the RD strobe is output only when the external

address is accessed.

Read/Write

R/W

R

W

;

Either read or write is possible

Only read is possible

Only write is possible

Prohibit RWM

Prohibit Read Modify Write. (Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF Instruction)

162

TOSHIBA CORPORATION

TMP96C141AF

(2) I/O Port Control (1/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

P07C

P06C

P05C

P04C

P03C

P02C

P01C

P00C

02H

(Prohibit

RMW)

W

PORT0

Control

P0CR

0

P17C

0

P16C

0

P11C

0

P10C

0

0 : IN 1 : OUT (When external access, set as AD7 - 0 and cleared to “0".)

P15C

0

P14C

0

P13C

0

P12C

0

04H

(Prohibit

RMW)

W

PORT1

Control

P1CR

P1FC

P2CR

P2FC

P3CR

<<Refer to the “P1FC”>>

P27F

0

P26F

0

P25F

0

P24F

0

P23F

0

P22F

0

P21F

0

P20F

0

05H

(Prohibit

RMW)

W

PORT1

Function

P1FC/ P1CR = 00 : IN, 01 : OUT, 10 : AD15 - 8, 11 : A23 - 16

P27C

0

P26C

0

P25C

0

P24C

0

P23C

0

P22C

0

P21C

0

P20C

0

08H

(Prohibit

RMW)

W

PORT2

Control

<<Refer to the “P2FC”>>

P27F

0

P26F

0

P25F

0

P24F

0

P23F

0

P22F

0

P21F

0

P20F

0

09H

(Prohibit

RMW)

W

PORT2

Function

P2FC/ P2CR = 00 : IN, 01 : OUT, 10 : A7 - 0, 11 : A23 - 16

P37C

0

P36C

0

P35C

0

P34C

0

P33C

P32C

0

0AH

(Prohibit

RMW)

W

PORT3

Control

0

0 : IN 1 : OUT

P37F

P36F

P35F

P34F

P32F

P31F

0

P30F

0

0BH

(Prohibit

RMW)

W

PORT3

Function

P3FC

0

O : PORT

1 : RAS

O : PORT

1 : R/W

O : PORT

1 : BUSAK

O : PORT

1 : BUSRQ

O : PORT

1 : HWR

O : PORT

1 : WR

O : PORT

1 : RD

P42C

P41C

P40C

0EH

(Prohibit

RMW)

W

PORT4

Control

P4CR

P4FC

0

0 : IN 1 : OUT

P42F

0

P41F

P40F

0

10H

(Prohibit

RMW)

W

PORT4

Function

0

0 : PORT 1 : CS/CAS

Note: With the TMP96C141A/TMP96C141A/TMP96C041A, which requires an external ROM, PORT0 functions as AD0 to AD7; PORT1, AD8 to AD15; P30,

the RD signal; P31, the WR signal, regardless of the values set in P0CR, P1CR, P1FC, P30F and P31F.

TOSHIBA CORPORATION

163

TMP96C141AF

I/O Port Control (2/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

P67C

P66C

P65C

P64C

P63C

P62C

P61C

P60C

14H

(Prohibit

RMW)

W

PORT6

Control

P6CR

0

P72C

0

P71C

0

P70C

0

0 : IN 1 : OUT

P73C

15H

(Prohibit

RMW)

W

PORT7

Control

P7CR

P6FC

0

P63F

0

0 : IN 1 : OUT

P67F

0

P66F

0

P65F

0

P64F

0

P62F

P61F

0

P60F

0

16H

(Prohibit

RMW)

W

PORT6

Function

0

0 : PORT 1 : PG1 - OUT

0 : PORT 1 : PGO - OUT

P73F

P72F

W

P71F

17H

(Prohibit

RMW)

PORT7

Function

P7FC

0

0 : PORT

1 : TO3

0 :PORT

1 : TO2

0 : PORT

1 : TO1

P87C

0

P86C

0

P85C

0

P84C

0

P83C

P82C

P81C

P80C

0

1AH

(Prohibit

RMW)

W

PORT8

Control

P8CR

P9CR

0

0 : IN 1 : OUT

P95C

0

P94C

P93C

P92C

0

P91C

0

P90C

0

1BH

(Prohibit

RMW)

W

PORT9

Control

0

0:IN 1:OUT

P83F

P86F

W

P82F

W

1CH

(Prohibit

RMW)

W

0

PORT8

Function

P8FC

P9FC

0

0 : PORT

1 : TO6

0 : PORT

1 : TO5

0 : PORT

1 : TO4

P95F

W

P93F

W

P92F

W

P90F

W

1DH

(Prohibit

RMW)

PORT9

Function

0

0 : PORT

1 : SCLK1

0 : PORT

1 : TxD1

0 : PORT

1 : SCLK0

0 : PORT

1 : TxD0

164

TOSHIBA CORPORATION

TMP96C141AF

(3) Timer Control (1/4)

Symbol

Name

Address

7

6

5

4

3

2

1

0

PRRUN

R/W

0

T5RUN

T4RUN

P1RUN

P0RUN

T1RUN

T0RUN

R/W

Timer

Control

0

TRUN

20H

Prescaler and Timer Run/Stop CONTROL

0 : Stop and Clear

1 : Run (Count up)

22H

(Prohibit

RMW)

–

8bit Timer

Register 0

TREG0

TREG1

W

Undeﬁned

–

23H

8bit Timer

Register 1

(Prohibit

RMW)

W

Undeﬁned

T10M1

0

T10M0

0

PWMM1

0

PWMM0

T1CLK1

T1CLK0

0

T0CLK1

0

T0CLK0

0

W

8bit Timer

Source CLK

and MODE

24H

(Prohibit

RMW)

0

TMOD

00 : 8-bit Timer

00 : –

01 : 2 - 1

10 : 2 - 1

11 : 2 - 1

00 : TO0TRG

00 : TI0 Input

6

01 : 16-bit Timer

10 : 8-bit PPG

11 : 8-bit PWM

PWM

01 : φT1

10 : φT16

11 : φT256

01 : φT1

10 : φT4

11:φT16

7

8

DBEN

R/W

0

TFF1C1

TFF1C0

0

TFF1IE

TFF1IS

0

W

R/W

8bit Timer

Flip-ﬂop

Control

0

TFFCR

25H

1 : Double

Buffer

00 : Invert TFF1

01 : Set TFF1

1 : TFF1

Invert

0 : Inverted

by

Enable

10 : Clear TFF1

11 : Don’t care

Enable

Timer 0

–

PWM Timer

Register 2

TREG2

TREG3

26H

27H

(R)/W (Can read double buffer values.)

Undeﬁned

–

PWM Timer

Register 3

(R)/W (Can read double buffer values.)

Undeﬁned

FF2RD

DB2EN

PWM0INT

PWM0M

T2CLK1

T2CLK0

0

PWM0S1

0

PWM0S0

0

R

–

W

0

28H

0

(Prohibit

RMW)

P0MOD PWM0 MODE

6

TFF2 output 1 : Double

0 : Overﬂow 0 : PWM

Interrupt Mode

1: Compare/ 1 : Timer

00 : φP1(fc/4)

00 : 2 - 1

7

value

Buffer

Enable

01 : φP4(fc/16)

10 : φP16(fc/64)

11 : Don’t care

01 : 2 - 1

8

10 : 2 - 1

Match

Mode

11 : Don’t care

Interrupt

FF3RD

DB3EN

0

PWM1INT

PWM1M

T3CLK1

T3CLK0

PWM1S1 PWM1S0

R

–

W

29H

0

(Prohibit

RMW)

P1MOD PWM1 MODE

6

TFF3 output 1 : Double

0 : Overﬂow 0 : PWM

Interrupt Mode

1 : Compare/ 1 : Timer

00 : φP1(fc/4)

00 : 2 - 1

7

value

Buffer

Enable

01 : φP4(fc/16)

10 : φP16(fc/64)

11 : Don’t care

01 : 2 - 1

8

10:2 - 1

11:Don’t care

Match

Mode

Interrupt

TOSHIBA CORPORATION

165

TMP96C141AF

Timer Control (2/4)

Symbol

Name

Address

7

6

5

4

3

2

1

0

FF3C1

FF3C0

FF3TRG1

FF3TRG0

FF2C1

FF2C0

FF2TRG1

FF2TRG0

W

R/W

W

R/W

0

PWM

Flip-ﬂop

Control

00 : Don’t care

01 : Set TFF3

10 : Clear TFF3

11 : Don’t care

00 : Prohibit TFF3

Inverted

01 : Invert if matched

10 : Set if matched;

Clear if overﬂowed

11 : Clear if matched;

set if overﬂowed

00 : Don’t care

01 : Set TFF2

10 : Clear TFF2

11 : Don’t care

00 : Prohibit TFF2

Inverted

01 : Invert if matched

10 : Set if matched;

Clear if overﬂowed

11 : Clear if matched;

set if overﬂowed

PFFCR

2AH

30H

(Prohibit

RMW)

–

16-bit Timer

Register 4L

TREG4L

TREG4H

TREG5L

TREG5H

CAP1L

W

Undeﬁned

31H

(Prohibit

RMW)

–

16-bit Timer

Register 4H

W

Undeﬁned

32H

(Prohibit

RMW)

–

16-bit Timer

Register 5L

W

Undeﬁned

33H

(Prohibit

RMW)

–

16-bit Timer

Register 5H

W

Undeﬁned

–

Capture

Register 1L

34H

35H

36H

37H

R

Undeﬁned

–

Capture

Register 1H

CAP1H

CAP2L

R

Undeﬁned

–

Capture

Register 2L

R

Undeﬁned

–

R

Capture

Register 2H

CAP2H

Undeﬁned

CAP2T5

EQ5T5

CAP1IN

CAP12M1

CAP12M0

CLE

T4CLK1

T4CLK0

0

R/W

W

0

R/W

16-bit Timer 4

Source

CLK and

MODE

0

T4MOD

38H

TFF5 INV TRG

O: TRG Disable

1: TRG Enable

0 : Soft-

Capture

1 : Don’t care

Capture Timing

00 : Disable

01 : T14 ↑ T15

10 : T14 ↑ T14

1 : UC4

Clear

Enable

Source Clock

00 : TI4

01 : φT1

10 : φT4

11 :φT16

↑

↓

11 : TFF1 ↑ TFF1 ↓

166

TOSHIBA CORPORATION

TMP96C141AF

Timer Control (3/4)

Symbol

Name

Address

7

6

5

4

3

2

1

0

TFF5C1

TFF5C0

CAP2T4

CAP1T4

EQ5T4

EQ4T4

TFF4C1

TFF4C0

W

R/W

W

16bit Timer 4

Flip-ﬂop

Control

0

T4FFCR

39H

00 : Invert TFF5

01 : Set TFF5

10 : Clear TFF5

11 : Don’t care

TFF4 Invert Trigger

0 : Trigger Disable

1 : Trigger Enable

Source Clock

00 : Invert TFF4

01 : Set TFF4

10 : Clear TFF4

11 : Don’t care

–

PG1T

PG0T

0

DB6EN

DB4EN

R/W

0

T45CR T4, T5 Control

3AH

PG1 shift

trigger

0 : Timer 0, 1 O : Timer 0, 1

PG0 shift

trigger

1 : Double

Buffer

Fix at “0”

Enable

1 : Timer 5

1 : Timer 4

–

40H

(Prohibit

RMW)

16bit Timer

TREG6L

W

Register 6L

Undeﬁned

–

41H

(Prohibit

RMW)

16bit Timer

TREG6H

W

Register 6H

Undeﬁned

–

42H

(Prohibit

RMW)

16bit Timer

TREG7L

W

Register 7L

Undeﬁned

–

43H

(Prohibit

RMW)

16bit Timer

TREG7H

W

Register 7H

Undeﬁned

–

Capture

CAP3L

44H

45H

46H

47H

R

Register 3L

Undeﬁned

–

Capture

CAP3H

R

Register 3H

Undeﬁned

–

Capture

CAP4L

R

Register 4L

Undeﬁned

–

R

Capture

CAP4H

Register 4H

Undeﬁned

CAP3IN

0

CAP34M1

CAP34M0

CLE

0

T5CLK1

0

T5CLK0

0

R/W

W

16bit Timer 5

0

T5MOD

48H

Source

CLK and

MODE

Capture Timing

00 : Disable

01 : T16 ↑ T17

10 : T16 ↑ T16

Source Clock

00 : Invert TFF6

01 : Set TFF6

10 : Clear TFF6

11 : Don’t care

0 : Soft-

Capture

1 : Don’t care

1 : UC5

Clear

Enable

↑

↓

11 : TFF1 ↑ TFF1 ↓

TOSHIBA CORPORATION

167

TMP96C141AF

Timer Control (4/4)

Symbol

Name

Address

7

6

5

4

3

2

1

0

CAP4T6

CAP3T6

EQ7T6

EQ6T6

TFF6C1

TFF6C0

R/W

W

16bit Timer 5

Flip-ﬂop

Control

0

T5FFCR

49H

00 : Invert TFF6

01 : Set TFF6

10 : Clear TFF6

11 : Don’t care

TFF6 Invert Trigger

0 : Trigger Disable

1 : Trigger Enable

(4) Pattern Generator

Symbol Name

Address

7

6

5

4

3

2

1

0

PG03

PG02

PG01

PG00

SA03

SA02

SA01

SA00

4CH

(Prohibit

RMW)

PG0REG PGO Register

PG1REG PG1 Register

W

R/W

0

Undeﬁned

PG13

PG12

PG11

PG10

SA13

SA12

SA11

SA10

4DH

(Prohibit

RMW)

R/W

0

Undeﬁned

PAT1

CCW1

PG1M

PG1TE

PAT0

0

CCW0

PG0M

PG0TE

R/W

4EH

(Prohibit

RMW)

0

PG01CR PG0, 1 Control

0 : Normal

Rotation

1 : 4bit write 1 : Reverse

Rotation

PG1 trigger

0 : 4bit Step input

1 : 8bit Step enable

0 : Normal

Rotation

1 : 4bit write 1 : Reverse

Rotation

PG0 trigger

0 : 4bit Step input

1 : 8bit Step enable

0 : 8bit write

1 : Enable

(5) Watch Dog Timer

Symbol

Name

Address

7

6

5

4

3

2

1

0

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

R/W

1

0

WD-

MOD

Watch Dog

Timer Mode

5CH

Standby Mode

1 : Connect

internally

WDT out

pin to

16

00 : 2 /fc

Warming up

Time

1 : Drive

the pin

in STOP

Mode

00 : RUN Mode

01 : STOP Mode

10 : IDLE Mode

11 : Don’t care

18

1 : WDT

Enable

01 : 2 /fc

20

14

10 : 2 /fc

0 : 2 /fc

22

16

11 : 2 /fc

1 : 2 /fc

Reset Pin

–

W

–

Watch Dog

Timer

Control

Register

WDCR

5DH

B1H : WDT Disable Code 4EH : WDT Clear Code

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TMP96C141AF

(6) Serial Channel (1/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

RB7

TB7

RB6

TB6

RB5

TB5

RB4

TB4

RB3

TB3

RB2

TB2

RB1

TB1

RB0

TB0

Serial

Channel 0

Buffer

SC0BUF

50H

R (Receiving)/W (Transmission)

Undeﬁned

RB8

R

EVEN

0

PE

0

OERR

PERR

FERR

–

0

–

0

R/W

R (Cleared to 0 by reading)

R/W

0

Serial

Channel 0

Control

SC0CR

51H

52H

1 : Error

Parity

0 : Odd

1 : Even

1: Input

SCLK0 pin

(Note)

Receiving

data bit 8

1 : Parity

Enable

Overrun

WU

Parity

SM1

0

Framing

SM0

0

TB8

0

CTSE

0

RXE

0

SC1

0

SC0

0

R/W

Serial

Channel 0

Mode

0

SC0-

MOD

00 : Unused

00 : TO0 Trigger

Transmission 1 : CTS

1 : Receive

Enable

1 : Wake up

Enable

01 : UART 7bit

10 : UART 8bit

11 : UART 9bit

01 : Baud rate generator

10 : Internal clock φ1

11 : Don’t care

data bit 8

Enable

–

R/W

0

BR0CK1

0

BR0CK0

BR053

BR052

BR051

BR050

R/W

0

Baud Rate

Control

BR0CR

53H

54H

00 : φt0 (fc/4)

01 : φt2 (fc/16)

10 : φt8 (fc/64)

11 :φt32 (fc/256)

Set frequency divisor

0 ~ F

(“1” prohibited)

Fix at “0”

RB7

TB7

RB6

TB6

RB5

TB5

RB4

TB4

RB3

TB3

RB2

TB2

RB1

TB1

RB0

TB0

Serial

Channel 1

Buffer

SC1BUF

R (Receiving)/W (Transmission)

Undeﬁned

RB8

R

EVEN

0

PE

OERR

PERR

FERR

SCLKS

0

IOC

0

R/W

R (Cleared to 0 by reading)

R/W

0

Serial

Channel 1

Control

1 : Error

SC1CR

55H

Parity

0 : Odd

1 : Even

Receiving

data bit 8

1 : Parity

Enable

1 : Input

SCLK1 pin

Overrun

Parity

Framing

TB8

0

–

0

RXE

0

WU

0

SM1

0

SM0

0

SC1

0

SC0

0

R/W

Serial

Channel 1

Mode

SC1-

MOD

56H

00 : I/O Interface

01 : UART 7bit

10 : UART 8-bit

11 : UART 9bit

00 : TO0 Trigger

Transmission

data bit 8

1 : Receive

Enable

1 : Wake up

Enable

01 : Baud rate generator

10 : Internal clock φ1

11 : Don’t care

Fix at “0”

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TMP96C141AF

Serial Channel (2/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

–

R/W

0

BR1CK1

BR1CK0

BR153

R/W

0

BR152

BR151

BR150

0

Baud Rate

Control

BR1CR

57H

00 : φt0 (fc/4)

01 : φt2 (fc/16)

10 : φt8 (fc/64)

11 :φt32 (fc/256)

Set frequency divisor

0 ~ F

(“1” prohibited)

Fix at “0”

–

ODE1

ODE0

0

R/W

Special

Open Drain

Enable

ODE

58H

0

1 : P93

1 : P90

Open-drain

(7) A/D Converter Control

Symbol

Name

Address

7

6

5

4

3

2

1

0

EOCF

ADBF

REPET

SCAN

ADCS

ADS

ADCH1

ADCH0

R

R/W

AD-

MOD

A/D Converter

Mode reg

5EH

0

1 :

Busy

1 : Repeat

mode

1 : Scan

mode

1 : Slow

mode

1 : End

ADR01

1 : START

Analog Input Channel Series

ADR00

*1)

AD Result

Reg 0 low

60H

61H

62H

63H

64H

65H

66H

67H

R

AD

REG0L

Undeﬁned

ADR09

1

ADR08

ADR07

ADR06

ADR05

ADR04

ADR03

ADR02

AD Result

Reg 0 high

AD

REG0H

Undeﬁned

ADR11

ADR19

ADR21

ADR10

*1)

AD Result

Reg 1 low

R

AD

REG1L

Undeﬁned

1

ADR18

ADR20

ADR28

ADR30

ADR17

ADR16

ADR15

ADR14

ADR13

ADR12

AD Result

Reg 1 high

R

AD

REG1H

Undeﬁned

*1)

AD Result

Reg 2 low

R

AD

REG2L

Undeﬁned

1

ADR29

ADR31

ADR39

ADR27

ADR26

ADR25

ADR24

ADR23

ADR22

AD Result

Reg 2 high

R

AD

REG2H

Undeﬁned

*1)

AD Result

Reg 3 low

R

AD

REG3L

Undeﬁned

ADR38

1

ADR37

ADR36

ADR35

ADR34

ADR33

ADR32

AD

REG3H

AD Result

Reg 3 high

R

Undeﬁned

*1:

Data to be stored in A/D Conversion Result Reg Low are the lower 2 bits of the conversion result. The contents of the lower 6 bits of this register are

always read as “1”.

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TMP96C141AF

(8) Interrupt Control (1/2)

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TMP96C141AF

Interrupt Control (2/2)

Symbol

Name

Address

7

6

5

4

3

2

1

0

µDMA0 start vector

DMA 0

request

Vector

7CH

(Prohibit

RMW)

DMA0V8

DMA0V7

DMA0V6

DAM0V5

DMA0V4

DMA0V

W

0

µDMA1 start vector

DMA 1

request

Vector

7DH

(Prohibit

RMW)

DMA01V8

DMA1V7

DMA1V6

DAM1V5

0

DMA1V4

0

DMA1V

DMA2V

DMA3V

W

0

µDMA2 start vector

DMA 2

request

Vector

7EH

(Prohibit

RMW)

DMA2V8

DMA2V7

DMA2V6

DAM2V5

0

DMA2V4

0

W

0

DMA3V8

0

DMA3V7

0

µDMA3 start vector

DMA 3

request

Vector

7FH

(Prohibit

RMW)

DMA3V6

DAM3V5

DMA3V4

W

0

I0LE

W

0

I0IE

W

0

NMIREE

W

0

7BH

(Prohibit

RMW)

Interrupt Input

Mode Control

0 : INTO

edge

mode

1 : INTO

level

IIMC

1 : Operate

even at

NMI rise

edge

1 : INT0

input

enable

mode

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TMP96C141AF

(9) Chip Select/Wait Controller

Symbol

Name

Address

7

6

5

4

3

2

1

0

B0E

W

B0SYS

B0CAS

B0BUS

B0W1

B0W0

B0C1

W

B0C0

W

0

W

0

W

0

W

0

W

0

Block 0

CS/WAIT

control

68H

(Prohibit

RMW)

0

B0CS

00 : 2WAIT

01 : 1WAIT

10 : 1WAIT + n

11 : 0WAIT

00 : 7F00H ~ 7FFFH

01 : 400000H ~

10 : 800000H ~

11 : C00000H ~

register

1 : CS

Enable

1 : SYSTEM 0 : CS0

only

0 : 16bit Bus

1 : 8bit Bus

1 : CAS0

B1E

W

B1SYS

B1CAS

B1BUS

B1W1

B1W0

B1C1

B1C0

W

0

W

0

W

0

W

0

W

0

W

0

Block 1

CS/WAIT

control

69H

(Prohibit

RMW)

0

B1CS

B2CS

00 : 2WAIT

01 : 1WAIT

10 : 1WAIT + n

11 : 0WAIT

00 : 480H ~ 7FFFH

01 : 400000H ~

10 : 800000H ~

11 : C00000H ~

register

1 : CS

Enable

1 : SYSTEM 0 : CS1

only

0 : 16bit Bus

1 : 8bit Bus

1 : CAS1

B2E

W

B2SYS

B2CAS

B2BUS

B2W1

B2W0

B2C1

B2C0

W

0

W

0

W

0

W

0

W

0

W

Block 2

CS/WAIT

control

6AH

(Prohibit

RMW)

0

00 : 2WAIT

01 : 1WAIT

10 : 1WAIT + n

11 : 0WAIT

00 : 8000H ~

register

1 : CS

Enable

1 : SYSTEM 0 : CS2

only 1 : CAS2

0 : 16bit Bus

1 : 8bit Bus

01 : 400000H ~

10 : 800000H ~

11 : C00000H ~

Note 1: After reset, only “Block 2” is set to enable.

→ After reset, the program starts in 16-bit data bus, 2-wait state.

Note 2: These registers can be accessed only in system mode.

Note 3: TMP96C141A for internal RAM less is 80H ~ 7FFFH.

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TMP96C141AF

STOP: This signal becomes active “1” when the hold mode

setting register is set to the STOP mode and the CPU

executes the HALT instruction. When the drive enable

bit [DRIVE] is set to “1”, however, STP remains at “0”.

• The input protection resistor ranges from several tens of

ohms to several hundreds of ohms.

6. Port Section Equivalent Circuit Diagram

• Reading The Circuit Diagram

Basically, the gate singles written are the same as

those used for the standard CMOS logic IC [74HCXX]

series.

The dedicated signal is described below.

• PO (AD0 ~ AD7), P1 (AD8 ~ 15, A8 ~ 15), P2 (A2 - 23, A0 ~7)

• P30 (RD), P31 (WR)

• P32 ~ 37, P40 ~ 41, P6, P7, P80 ~ 86, P91 ~ 92, P94 ~ 95

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TMP96C141AF

• P42 (CS2, CAS2)

• P5 (AN0 ~ 3)

• P87 (INT0)

• P90 (TXD0), P93 (TXD1)

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TMP96C141AF

• NMI

• WDTOUT

• CLK

• EA, AM8/16

• ALE

• RESET

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TMP96C141AF

• X1, X2

• VREF, AGND

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external oscillator. As a result, it takes warming up time

from inputting the releasing request to outputting the

system clock.

7. Guidelines and Restrictions

(1)

Special Expression

➂ High Speed µDMA (DRAM) refresh mode)

➀ Explanation of a built-in I/O register: Register

When the bus is released (BUSAK = “0”) for waiting to

accept the interrupt, DRAM refresh is not performed

because of the high speed µDMA is generated by an

interrupt.

Symbol

ex) TRUN <TRUN>

. . .

Bit T0RUN of Register TRUN

➁ Read, Modify and Write Instruction

④ Programmable Pull Up/Down Resistance

An instruction which CPU executes following by one

instruction.

The programmable pull up/down resistors can be

selected ON/OFF by program when they are used as

the input ports. The case of they are used as the out-

put ports, they cannot be selected ON/OFF by pro-

gram.

1. CPU reads data of the memory.

2. CPU modiﬁes the data.

3. CPU writes the data to the same memory.

➄ Bus Releasing Function

. . .

ex1) SET 3, (TRUN)

set bit3 of TRUN

ex2) INC1, (100H) increment the data of 100H

Refer to the “Note about the Bus Release” in 3.5 Func-

tions of Ports because the pin state when the bus is

released is written.

• The representative Read, Modify and Write

Instruction in the TLCS-900

SET

CHG

INC

imm, mem,

A, mem,

RES

TSET

DEC

ADD

imm, mem

imm, reg

➅ Watch Dog Timer

When the bus is released, both internal memory and

internal I/O cannot be accessed. But internal I/O

cantinues to operate. So, the watch dog timer contin-

ues to run. Therefore, be carefull about the bus releas-

ing time and set the detection timer of watch dog

timer.

RLD

➂ 1 state

One cycle clock divided by 2 oscillation frequency is

called 1 state

⑦ Watch Dog Timer

ex) The case of oscillation frequency is 20MHz.

Guidelines

The watch dog timer starts operation immediately after

the reset is released. When the watch dog timer is not

used, set watch dog timer to disable.

(2)

➀ EA, pin

⑧ CPU (High SpeedµDMA)

Fix these pins VCC or GND unless changing voltage.

➁ Warming-up Counter

Only the “LDC cr, r”, “LDC r, cr” instruction can be

used to access the control register like transfer source

address register (DMASn) in the CPU.

The warming-up counter operates when the STOP

mode. is released even the system which is used an

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型号：	TMP96C141AF
厂家：	TOSHIBA
描述：	IC MICROCONTROLLER, PQFP80, QFP-80, Microcontroller 时钟微控制器外围集成电路
文件：	总178页 (文件大小：5556K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMP96C141AF [TOSHIBA]

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