TMS370C358ANMA_技术文档

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

FN/FZ PACKAGE

(TOP VIEW)

CMOS/EEPROM/EPROM Technologies on a

Single Device

– Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

9

8

7

6

5

4

3

2

1

6867 66 65 6463 62 61

60

C3 10

D1 / CSH3

11

12

13

14

15

16

59

58

57

56

55

54

C4

C5

C6

D2 / CSH2

D3 / SYSCLK

D4 / R / W

C7

D5 / CSPF

V

D6/CSH1/EDS

D7/CSE1/WAIT

RESET

CC2

Internal System Memory Configurations

– On-Chip Program Memory Versions

– ROM: 4K to 48K Bytes

V

SS2

A0 17

53

52

51

50

49

48

47

18

19

20

21

22

23

A1

A2

A3

A4

A5

A6

A7

INT1

INT2

INT3

SPISOMI

SPISIMO

– EPROM: 16K to 48K Bytes

– ROM-less

SPICLK

T1IC/CR

T1PWM

T1EVT

24

25

26

46

45

44

– Data EEPROM: 256 or 512 Bytes

– Static RAM: 256 to 3.5K Bytes

– External Memory/Peripheral Wait States

– Precoded External Chip-Select Outputs

in Microcomputer Mode

T2AEVT

T2AIC2/PWM

27 28 2930 31 32 3334 35 3637 38 39 4041 42 43

Flexible Operating Features

JN/NM PACKAGE

(TOP VIEW)

– Low-Power Modes: STANDBY and HALT

– Commercial, Industrial, and Automotive

Temperature Ranges

B5

B6

B7

C0

MC

C1

C2

B4

B3

B2

B1

B0

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

– Clock Options

4

– Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)

– Divide-by-1 (2 MHz – 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

5

D0 / CSE2 / OCF

6

V

7

SS1

CC1

V

SS1

C3

8

D1 / CSH3

D3 / SYSCLK

D4 / R / W

D6 / CSH1 / EDS

D7 / CSE1 / WAIT

RESET

9

– Supply Voltage (V ): 5 V ± 10%

C4

C5

C6

C7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CC

Eight-Channel 8-Bit Analog-to-Digital

Converter 1 (ADC1)

AN0

A0

A1

INT1

Two 16-Bit General-Purpose Timers

On-Chip 24-Bit Watchdog Timer

INT2

A2

INT3

A3

SPISOMI

SPISIMO

SPICLK

A4

Two Communication Modules

– Serial Communications Interface 1 (SCI1)

– Serial Peripheral Interface (SPI)

A5

A6

T1IC / CR

T1PWM

A7

T2AEVT

T2AIC2 / PWM

T2AIC1 / CR

SCICLK

SCIRXD

SCITXD

XTAL2 / CLKIN

XTAL1

AN7

T1EVT

Flexible Interrupt Handling

TMS370 Series Compatibility

V

SS1

AN6

AN5

AN4

AN3

AN2

AN1

CMOS/Package /TTL-Compatible I/O Pins

– 64-Pin Plastic and Ceramic Shrink

Dual-In-Line Packages/44 Bidirectional,

9 Input Pins

– 68-Pin Plastic and Ceramic Leaded Chip

Carrier Packages/46 Bidirectional,

9 Input Pins

V

CC1

CC3

V

SS3

Workstation/PC-Based Development

System

– C Compiler and C Source Debugger

– Real-Time In-Circuit Emulation

– Extensive Breakpoint/Trace Capability

– Software Performance Analysis

– Multi-Window User Interface

– Microcontroller Programmer

– All Peripheral Function Pins Are

Software Configurable for Digital I/O

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Pin Descriptions

†

I/O

‡

DESCRIPTION

ALTERNATE

FUNCTION

SDIP

(64)

LCC

(68)

NAME

A0

A1

A2

A3

A4

A5

A6

A7

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

15

16

17

18

19

20

21

22

17

18

19

20

21

22

23

24

Single-chip mode: Port A is a general-purpose bidirectional I/O port.

I/O Expansion mode: Port A can be individually programmed as the external

bidirectional data bus (DATA0–DATA7).

B0

B1

B2

B3

B4

B5

B6

B7

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

60

61

62

63

64

1

65

66

67

68

1

2

3

4

Single-chip mode: Port B is a general-purpose bidirectional I/O port.

I/O Expansion mode: Port B can be individually programmed as the low-order address

output bus (ADDR0–ADDR7).

2

3

C0

C1

C2

C3

C4

C5

C6

C7

ADDR8

ADDR9

4

6

7

5

7

8

10

11

12

13

14

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

Single-chip mode: Port C is a general-purpose bidirectional I/O port.

I/O Expansionmode:PortCcanbeindividuallyprogrammedasthehigh-orderaddress

output bus (ADDR8–ADDR15).

9

10

11

12

13

INT1

INT2

INT3

NMI

—

50

49

48

52

51

50

I

External (nonmaskable or maskable) interrupt/general-purpose input pin

I/O External maskable interrupt input/general-purpose bidirectional pin

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

E0

E1

E2

E3

E4

E5

E6

E7

14

34

35

36

37

38

39

42

36

37

38

39

40

41

42

43

ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7)

Port E can be individually programmed as general-purpose input pins if not used

as ADC1 analog input or positive reference input.

I

V

CC3

V

SS3

32

33

34

35

ADC1 positive-supply voltage and optional positive-reference input pin

ADC1 ground reference pin

System reset bidirectional pin. RESET, as an input, initializes the microcontroller;

RESET

MC

51

5

53

6

I/O as open-drain output, RESET indicates an internal failure was detected by the

watchdog or oscillator fault circuit.

Mode control (MC) pin. MC enables EEPROM write-protection override (WPO)

I

mode, also EPROM V

.

PP

XTAL2/CLKIN

XTAL1

29

30

31

32

I

O

Internal oscillator crystal input/external clock source input

Internal oscillator output for crystal

33,

61

V

31, 57

—

Positive supply voltage

CC1

15,63

CC2

†

‡

I = input, O = output

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Pin Descriptions (Continued)

†

I/O

‡

DESCRIPTION

ALTERNATE

FUNCTION

SDIP

(64)

LCC

(68)

NAME

8,

58,40

V

9

Ground reference for digital logic

Ground reference for digital I/O logic

SS1

—

16,62

SS2

Single-chip mode: Port D is a general-purpose bidirectional I/O port. Each of

the port D pins can be individually configured as a general-purpose I/O pin,

primary memory control signal (function A), or secondary memory control

signal (function B). All chip selects are independent and can be used for

memory bank switching. Refer to Table 1 for function A memory accesses.

FUNCTION

A

B

I/O pin A: Chip select eighth output 2 goes low during memory accesses

I/O pin B: Opcode fetch goes low during the opcode fetch memory cycle.

D0

D1

D2

CSE2

CSH3

CSH2

OCF

—

59

56

—

64

60

59

I/O pin A: Chip select half output 3 goes low during memory accesses.

I/O pin B: Reserved

I/O pin A: Chip select half output 2 goes low during memory accesses.

I/O pin B: Reserved

—

D3

D4

SYSCLK SYSCLK

55

54

58

57

I/O pin A, B: Internal clock signal is 1/1 (PLL) or 1/4 XTAL2/CLKINfrequency.

I/O pin A, B: Read/write output pin

R/W

I/O

I/O pin A: Chip select peripheral output for peripheral file goes low during

D5

CSPF

—

56

memory accesses.

I/O pin B: Reserved

I/O pin A: Chip select half output 1 goes low during memory accesses.

I/O pin B: External data strobe output goes low during memory accesses from

external memory and has the same timings as the five chip selects.

D6

D7

CSH1

CSE1

EDS

53

52

55

54

I/O pin A: Chip select eighth output goes low during memory accesses.

I/O pin B: Wait input pin extends bus signals.

WAIT

SCITXD

SCIRXD

SCICLK

SCIIO1

SCIIO2

SCIIO3

28

27

26

30

29

28

SCI transmit data output pin/general-purpose bidirectional pin (see Note 1)

I/O SCI receive data input pin/general-purpose bidirectional pin

SCI bidirectional serial clock pin/general-purpose bidirectional pin

Timer1 input capture/counter reset input pin/general-purpose bidirectional

T1IC/CR

T1PWM

T1EVT

T1IO1

T1IO2

T1IO3

44

43

41

46

45

44

I/O Timer1 pulse-width-modulation (PWM) output pin/general-purpose

bidirectional pin

Timer1 external event input pin/general-purpose bidirectional pin

Timer2Ainputcapture1/counterresetinputpin/general-purposebidirectional

Timer2A input capture 2/PWM output pin/general-purpose bidirectional pin

Timer2A external event input pin/general-purpose bidirectional pin

T2AIC1/CR

T2AIC2/PWM

T2AEVT

T2AIO1

T2AIO2

T2AIO3

25

24

23

27

26

25

I/O

SPISOMI

SPISIMO

SPICLK

SPIIO1

SPIIO2

SPIIO3

47

46

45

49

48

47

SPI slave output pin, master input pin/general-purpose bidirectional pin

I/O SPI slave input pin, master output pin/general-purpose bidirectional pin

SPI bidirectional serial clock pin/general-purpose bidirectional pin

†

I = input, O = output

‡

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK.

NOTE 1: The three-pin configuration SCI is referred to as SCI1.

Table 1. Function A: Memory Accesses Locations for ‘x5x Devices

FUNCTION A

‘X50, ‘X52, ‘X53, AND ‘X56

2000h – 3FFFh (8K bytes)

8000h – FFFFh (32K bytes)

10C0h – 10FFh (64 bytes)

‘X58

‘X59

CSEx

CSHx

CSPF

A000h – BFFFh (8K bytes)

C000h – FFFFh (16K bytes)

10C0h – 10FFh (64 bytes)

E000h – EFFFh (4K bytes)

F000h – FFFFh (4K bytes)

10C0h – 10FFh (64 bytes)

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

functional block diagram

E0–E7

or

AN0–AN7

INT1 INT2 INT3 XTAL1 XTAL2/

CLKIN

MC RESET

V

CC3

Clock Options:

Divide-by-4 or

Divide-by-1(PLL)

Analog-to-Digital

Converter 1

Interrupts

System Control

SS3

SPISOMI

SPISIMO

SPICLK

Serial

Peripheral

Interface

RAM

256, 512, 1K, 1.5K, or

3.5K Bytes

CPU

SCIRXD

SCITXD

SCICLK

Serial

Communications

Interface 1

Program Memory

ROM: 4K, 8K, 12K, 16K,

32K, or 48K Bytes

EPROM: 16K, 32K, or

48K Bytes

Data EEPROM

0, 256, or 512 Bytes

T2AIC1/CR

T2AEVT

Timer 2A

Timer 1

T2AIC2/PWM

T1IC/CR

T1EVT

T1PWM

Memory Expansion

Watchdog

†

Port A

8

Port B

Port C

Port D

V

CC1

V

SS1

8

8/6

V

SS2

V

CC2

†

For the 64-pin devices, there are only six pins for port D.

description

The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control

through integration of advanced peripheral function modules and various on-chip memory configurations. The

TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families:

the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and

SE370C75x.

The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and

EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of

CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the

TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control,

computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory

configuration overview of the TMS370Cx5x devices.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

description (continued)

Table 2. Memory Configurations

PROGRAM

MEMORY

(BYTES)

DATA MEMORY

(BYTES)

OPERATING

MODES

OFF-CHIP

MEMORY

EXP. (BYTES)

PACKAGES

68 PIN PLCC/CLCC, OR

64 PIN PSDIP/CSDIP

DEVICE

†

µP

ROM EPROM

RAM

EEPROM

µC

TMS370Cx50: TMS370C050, TMS370C150, TMS370C250, AND TMS370C350

TMS370C050A

TMS370C150A

TMS370C250A

TMS370C350A

4K

—

112K

56K

256

—

√

—

√

FN – PLCC / NM –PSDIP

FN – PLCC

—

56K

256

—

FN – PLCC

4K

112K

FN – PLCC / NM –PSDIP

TMS370Cx52: TMS370C052, TMS370C352, AND TMS370C452

TMS370C052A

TMS370C352A

TMS370C452A

8K

—

112K

256

—

√

FN – PLCC / NM –PSDIP

FN – PLCC

‡

256

TMS370Cx53: TMS370C353

112K 1.5K

TMS370C353A

12K

—

√

FN – PLCC

TMS370Cx56: TMS370C056, TMS370C156, TMS370C256, TMS370C356, TMS370C456, AND TMS370C756

TMS370C056A

TMS370C156A

TMS370C256A

TMS370C356A

TMS370C456A

TMS370C756A

16K

—

112K

56K

512

—

√

—

√

FN – PLCC / NM –PSDIP

FN – PLCC

—

56K

512

—

FN – PLCC

16K

—

112K

FN – PLCC / NM –PSDIP

FN – PLCC

‡

—

512

√

16K

√

FN – PLCC / NM –PSDIP

TMS370Cx58: TMS370C058, TMS370C358, AND TMS370C758

TMS370C058A

TMS370C358A

32K

—

64K

1K

256

—

√

FN – PLCC / NM –PSDIP

TMS370C758A,

TMS370C758B

—

32K

64K

1K

256

√

FN – PLCC / NM –PSDIP

TMS370Cx59: TMS370C059 AND TMS370C759

§

TMS370C059A

48K

—

20K

3.5K

256

√

FN – PLCC

§

TMS370C759A

48K

EPROM DEVICE: SE370C756, SE370C758, and SE370C759

¶

SE370C756A

—

16K

32K

48K

112K

64K

20K

512

256

√

FZ – CLCC / JN –CSDIP

FZ – CLCC

¶

SE370C758A ,

1K

¶

SE370C758B

§¶

SE370C759A

3.5K

†

µC – Microcomputer mode

µP – Microprocessor mode

TMS370C45x support ROM memory security. Refer to the program ROM section.

Only operate up to 3 MHz SYSCLK

System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

‡

§

¶

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

description (continued)

The suffix letter (A or B) appended to the device names shown in the device column of Table 2 indicates the

configuration of the device. ROM or an EPROM devices have different configurations as indicated in Table 3.

ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 3. Suffix Letter Configuration

†

DEVICE

WATCHDOG TIMER

Standard

Hard

CLOCK

LOW-POWER MODE

Enabled

EPROM A

EPROM B

Divide-by-4 (Standard oscillator)

Divide-by-1 (PLL)

Enabled

Standard

Hard

ROM A

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

Simple

ROM-less A

Standard

Divide-by-4

Enabled

†

Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.

Unless otherwise noted, the terms TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58,

TMS370Cx59, and SE370C75x refer to the individual devices listed in Table 2 and described in this data sheet.

All TMS370Cx5x devices contain the following on-chip peripheral modules:

Eight-channel, 8-bit analog-to-digital converter 1 (ADC1)

Serial communications interface 1 (SCI1)

Serial peripheral interface (SPI)

One 24-bit general-purpose watchdog timer

Two 16-bit general-purpose timers (one with an 8-bit prescaler)

TMS370C756, TMS370C758, and TMS370C759 are one-time programmable (OTP) devices that are available

in plastic packages. This microcomputer is effective to use for immediate production updates for other members

of the TMS370Cx5x family or for low-volume production runs when the mask charge or cycle time for low-cost

mask ROM devices is not practical.

The SE370C756, SE370C758, and SE370C759 have windowed ceramic packages to allow reprogramming of

the program EPROM memory during the development/prototyping phase of design. The SE370C75x devices

allow quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx5x family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no

instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain

active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral

configuration bits throughout both low-power modes.

The TMS370Cx5x features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx5x family is fully

instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller

family.

The SPI and the two operational modes of the SCI1 give three methods of serial communications. The SCI1

allows standard RS-232-C communications interface between other common data transmission equipment,

while the SPI gives high-speed communications between simpler shift-register type devices, such as display

drivers, ADC1 converter, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

description (continued)

For large memory applications, the TMS370Cx5x family provides an external bus with non-multiplexed address

and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system

implementations. Wait-state support facilitates performance matching among the CPU, external memory, and

the peripherals. All pins associated with memory expansion interface are individually software configurable for

general purpose digital input/output (I/O) pins when operating in the microcomputer mode.

The TMS370Cx5x family provides the system designer with very economical, efficient solution to real-time

control applications. The TMS370 family extended development system (XDS ) and compact development

tool (CDT ) solve the challenge of efficiently developing the software and hardware required to design the

TMS370Cx5x into an ever-increasing number of complex applications. The application source code can be

written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family

XDS development tools communicate through a standard RS-232-C interface with an existing personal

computer. This allows the use of the personal computer editors and software utilities already familiar to the

designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen

windowing so that a system designer with minimal training can begin developing software. Precise real-time

in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware

implementation as well as reduced time-to-market cycle.

The TMS370Cx5x family together with the TMS370 family XDS/22, CDT370, design kit, starter kit, software

tools, theSE370C75xreprogrammabledevices, comprehensiveproductdocumentation, andcustomersupport

provide a complete solution to the needs of the system designer.

modes

The TMS370Cx5x has four operating modes, two basic modes with each mode having two memory

configurations. The basic operating modes are the microcomputer and microprocessor modes, which are

selected by the voltage level applied to the dedicated MC pin two cycles before RESET goes inactive. The two

memory configurations then are selected through software programming of the internal system configuration

registers. Thefouroperatingmodesarethemicrocomputersinglechip, microcomputerwithexternalexpansion,

microprocessor without internal program memory, and microprocessor with internal program memory. These

modes are described in the following list.

Microcomputer single chip mode:

–

Operates as a self-contained microcomputer with all memory and peripherals on-chip.

Maximizes the general-purpose I/O capability for real-time control applications.

Microcomputer with external expansion mode:

–

Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM,

EPROM, and data EEPROM) remains active.

–

Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port

control, to become external memory as follows:

–

Port A: 8-bit data memory

Port B and C: 16-bit address memory

Port D: 8-bit control memory (pin not used as function A or B can be configured as I/O)

–

Utilizes the pins available (not used for address, data, or control memory) as general-purpose

input/output by programming them individually.

Lowers the system cost by not requiring an external address/data latch (address memory and data

memory are nonmultiplexed).

XDS and CDT are trademarks of Texas Instruments Incorporated.

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

modes (continued)

–

Reduces external interface decode logic by using the precoded chip select outputs that provide direct

memory/peripheral chip select or chip enable functions.

Function A maps up to 112K bytes of external memory into the address space by using CSE1, CSE2,

CSH1, CSH2, and CSH3 as memory-bank selects under software control.

Function B maps up to 40K bytes of external memory into the address space by using EDS under

software control.

Microprocessor without internal program memory mode:

–

Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses

for interface to external memory and peripherals.

–

On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled.

Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.

Microprocessor with internal program memory mode:

–

Configured as the microprocessor without internal program memory mode with respect to the external

bus interface.

–

Application program in external memory enables the internal program ROM or EPROM to be active in

the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control

register accomplishes this.)

memory/peripheral wait operation

The TMS370Cx5x enhances interface flexibility by providing WAIT-state support, decoupling the cycle time of

the CPU from the read/write access of the external memory or peripherals. External devices can extend the

read/write accesses indefinitely by placing an active low on the WAIT-input pin. The CPU continues to wait as

long as WAIT remains active.

Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller.

Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions

and memory and peripheral accesses automatically, thus making every external access a minimum of three

system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE

bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended

independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait

states can be used in conjunction with the external WAIT pin. In applications where the external device

read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state

generation can eliminate external WAIT interface logic, lowering system cost.

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

CPU

The CPU used on TMS370Cx5x devices is the high-performance 8-bit TMS370 CPU module. The ’x5x

implements an efficient register-to-register architecture that eliminates the conventional accumulator

bottleneck. The complete ’x5x instruction set is summarized in Table 23. Figure 1 illustrates the CPU registers

and memory blocks.

Program Counter

15

0

Legend:

Stack Pointer (SP)

7

0

C=Carry

N=Negative

Status Register (ST)

Z=Zero

C

7

N

6

Z

5

V

4

IE2 IE1

V=Overflow

IE2=Level2 interrupts Enable

IE1=Level1 interrupts Enable

3

2

1

0

0000h

0100h

256-Byte RAM (0000h–00FFh)

512-Byte RAM (0000h–01FFh)

1K-Byte RAM (0000h–03FFh)

1.5K-Byte RAM (0000h–05FFh)

3.5K-Byte RAM (0000h–0DFFh)

0200h

0400h

0600h

0E00h

†

Reserved

1000h

10C0h

1100h

Peripheral File

Peripheral Exp

†

Reserved

RAM (Includes 256-Byte Registers File)

1E00h

1F00h

512-Byte (1E00h–1FFFh)

Data EEPROM

0000h

R0(A)

R1(B)

0001h

0002h

0003h

256-Byte (1F00h–1FFFh)

R2

R3

2000h

4000h

5000h

16K-Byte ROM/EPROM (4000h–7FFFh)

12K-Byte ROM (5000h–7FFFh)

8K-Byte ROM (6000h–7FFFh)

4K-Byte ROM (7000h–7FFFh)

6000h

7000h

7FC0h

R127

007Fh

Interrupts and Reset Vectors;

Trap Vectors

8000h

A000h

32K-Byte ROM/EPROM (2000h–9FFFh)

48K-Byte ROM/EPROM (2000h–DFFFh)

Memory Expansion

E000h

FFFFh

R255

00FFh

Reserved means the address space is reserved for future expansion.

†

Figure 1. Programmer’s Model

9

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

CPU (continued)

The ’x5x CPU architecture provides the following components:

CPU registers:

–

A stack pointer that points to the last entry in the memory stack

A status register that monitors the operation of the instructions and contains the global-interrupt-enable

bits

–

A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes :

–

256-, 512-, 1K-, 1.5K-, or 3.5K-byte general-purpose RAM that can be used for data-memory storage,

program instructions, general-purpose register, or the stack (can be located only in the first 256 bytes)

A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

256- or 512-byte EEPROM module that provides in-circuit programmability and data retention in

power-off conditions

4K-, 8K-, 12K-, 16K-, 32K-, or 48K-byte ROM or 16K-, 32K-, or 48K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. Typically the stack

is used to store the return address on subroutine calls as well as the status-register contents during interrupt

sequences.

The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed

onto the stack and decrements after data is popped from the stack. The stack can be located only in the first

256 bytes of the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits:

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional-jump instructions) use these status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

The ST register, status bit notation, and status bit definitions are shown in Table 4.

Table 4. Status Registers

7

C

6

N

5

Z

4

V

3

2

1

0

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

10

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

CPU (continued)

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists

of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These

registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH

(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is

loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of

6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

Program Counter (PC)

Memory

PCH

60

PCL

00

0000h

60

00

7FFEh

7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx5x architecture is based on the Von Neuman architecture, where the program memory and data

memory share a common address space. All peripheral input/output is memory mapped in this same common

address space. In the expansion mode, external memory peripherals are also memory-mapped into this

common address. As shown in Figure 3, the TMS370Cx5x provides a 16 bit-address range to access internal

or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt

vectors.

The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM,

EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous

addresses located from 1000h to 10FFh. The 256 contiguous addresses are divided logically into 16 peripheral

file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral

control and data information is passed. The TMS370Cx5x has its on-chip peripherals and system control

assigned to peripheral file frames 1 through 7, addresses 1010h through 107Fh.

11

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

memory map (continued)

Peripheral File Control

Registers

’X59

’X56

’X53

’X52

’X50

’X59

’X56

’X52

’X50

’X59

’X56

’X52

’X50

’X59

’X56

’X52

’X50

’X58

’X53

’X58

’X53

’X58

’X53

0000h

0100h

0200h

0400h

0600h

0E00h

1000h

10C0h

0000h

0100h

0200h

0400h

0600h

256-Byte RAM

(0000h–00FFh)

(Register File/Stack)

†

Reserved

1000h–100Fh

1010h–101Fh

1020h–102Fh

1030h–103Fh

1040h–104Fh

1050h–105Fh

1060h–106Fh

1070h–107Fh

512-Byte RAM

(0000h–01FFh)

System Control

1K-Byte RAM

(0000h–03FFh)

Digital Port Control

1.5K-Byte RAM

(0000h–05FFh)

SPI Peripheral

Control

3.5K-Byte RAM

(0000h–0DFFh)

Timer 1 Peripheral

Control

0E00h

1000h

†

SCI1 Peripheral

Control

Reserved

External

Reserved

Timer 2A Peripheral

Control

Peripheral File

ADC1 Peripheral

Control

Not Avail-

10C0h

1100h

§

Peripheral Expansion

External

‡

able

(N /A)

1100h

1E00h

1F00h

†

Reserved

1080h–108Fh

†

Reserved

1E00h

1F00h

512K-Byte Data

EEPROM

(1E00h–1FFFh)

256-Byte Data

EEPROM

(1F00h–1FFFh)

Vectors

2000h

4000h

5000h

6000h

7000h

2000h

4000h

5000h

6000h

7000h

7FC0h

§

Trap 15–0

External

7FC0h–7FDFh

‡

N / A

16K-Byte ROM

(4000h–7FFFh)

‡

N / A

†

Reserved

ADC1

7FE0h–7FFBh

7FECh–7FEDh

7FEEh–7FEFh

7FF0h–7FF1h

7FF2h–7FF3h

7FF4h–7FF5h

7FF6h–7FF7h

7FF8h–7FF9h

7FFAh–7FFBh

7FFCh–7FFDh

7FFEh–7FFFh

12K-Byte ROM

(5000h–7FFFh)

8K-Byte ROM

(6000h–7FFFh)

Timer 2A

4K-Byte ROM

(7000h–7FFFh)

Serial Comm I/F TX

Serial Comm I/F RX

Timer 1

External

Interrupts and

Reset Vectors;

Trap Vectors

8000h

A000h

8000h

A000h

32K-Byte ROM

(2000h–9FFFh)

Serial Peripheral I/F

Interrupt 3

‡

§

External

Not Available

48K-Byte ROM

(2000h–DFFFh)

External

Interrupt 2

E000h

FFFFh

E000h

FFFFh

Interrupt 1

Memory Expansion

Reset

¶

Microprocessor Mode

Microcomputer

Single Chip Mode

Microcomputer

Mode With External

Expansion

Microprocessor With

Internal Program

Memory

On-Chip For TMS370Cx59 Devices

On-Chip For TMS370Cx58 Devices

On-Chip For TMS370Cx56 Devices

On-Chip For TMS370Cx53 Devices

On-Chip For TMS370Cx52 Devices

On-Chip For TMS370Cx50 Devices

†

‡

§

¶

Reserved = the address space is reserved for future expansion.

Not available (N/A) = address space unavailable in the mode illustrated.

Precoded chip select outputs available on external expansion bus.

Microprocessor mode is designed for ROM-less devices (’x50 and ’x56). ROM and EPROM devices can also be used in this mode but all on-chip

memory is ignored.

Figure 3. TMS370Cx5x Memory Map

12

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

RAM/register file (RF)

Locations within RAM address space can serve as either register file or general-purpose read/write memory,

program memory, or stack instructions. The TMS370Cx50 and TMS370Cx52 devices contain 256 bytes of

internal RAM, mapped beginning at location 0000h and continuing through location 00FFh which is shown in

Table 5 along with other ’x5x devices.

Table 5. RAM Memory Map

‘x50 and ‘x52

256 Bytes

‘x56

‘x58

‘x53

‘x59

RAM Size

512 Bytes

1K Bytes

1.5K Bytes

0000h – 05FFh

3.5K Bytes

Memory Mapped

0000h – 00FFh

0000h – 01FFh

0000h – 03FFh

0000h – 0DFFh

The first 256 bytes of RAM (0000h – 00FFh) are register files, R0 through R255 (see Figure 1). The first two

registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A

or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer

is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx5x control registers contain all the registers necessary to operate the system and peripheral

modules on the device. The instruction set includes some instructions that access the PF directly. These

instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal

designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at

address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6

shows the TMS370Cx5x peripheral files.

Table 6. TMS370Cx5x Peripheral File Address map

PERIPHERAL FILE

ADDRESS RANGE

DESCRIPTION

DESIGNATOR

P000–P00F

P010–P01F

P020–P02F

P030–P03F

P040–P04F

P050–P05F

P060–P06F

P070–P07F

P080–P0BF

P0C0–P0FF

1000h–100Fh

1010h–101Fh

1020h–102Fh

1030h–103Fh

1040h–104Fh

1050h–105Fh

1060h–106Fh

1070h–107Fh

1080h–10BFh

10C0h–10FFh

Reserved for factory test

System and EEPROM/EPROM control registers

Digital I/O port control registers

Serial peripheral interface registers

Timer 1 registers

Serial communication interface 1 registers

Timer 2A registers

Analog-to-digital converter 1 registers

Reserved

External peripheral control

data EEPROM

The TMS370Cx56 devices contain 512 bytes of data EEPROM, which are memory mapped beginning at

location 1E00h and continuing through location 1FFFh as shown in Table 7 along with other ‘x5x devices.

Table 7. Data-EEPROM Memory Map

‘x50, ‘x52, ‘x58, and ‘x59

256 Bytes

‘x56

‘X53

None

Data-EEPROM Size

Memory Mapped

512 Bytes

1E00h–1FFFh

1F00h–1FFFh

13

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

data EEPROM (continued)

Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the

write-protection register (WPR). Programming algorithm examples are available in the TMS370 Family User’s

Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). The

data EEPROM features include the following:

Programming:

–

Bit, byte, and block write/erase modes

Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.

Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A.

–

In-circuit programming capability: There is no need to remove the device to program it.

Write-protection: Writes to the data EEPROM are disabled during the following conditions:

–

Reset: All programming of the data EEPROM module is halted.

Write protection active: There is one write-protect bit per 32-byte EEPROM block.

Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 8 shows the memory map of the control registers.

Table 8. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

P014

SYMBOL

NAME

Program EPROM control register – high array

Reserved

EPCTLH

P015–P016

P017

INT1

INT2

External interrupt 1 control register

External interrupt 2 control register

External interrupt 3 control register

Data EEPROM control register

Reserved

P018

P019

INT3

P01A

DEECTL

P01B

P01C

EPCTLM

EPCTLL

Program EPROM control register – middle array

Reserved

P01D

P01E

Program EPROM control register – low array

For the 16K-byte EPROM device, program memory is controlled by P01C; for the 32K-byte EPROM device,

the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory

is controlled by P014, P01C, and P01E.

program EPROM

The ‘370C756 consists of a 16K-byte array of EPROM at address locations 4000h through 7FFFh. The

‘370C758 consists of 32K bytes made up of two 16K-byte arrays of EPROM; the first 16K-bytes array is located

ataddresslocations2000hthrough5FFFh, andthesecond16Kbytearrayislocatedataddresslocations6000h

through 9FFFh. The ’370C759 consists of 48K bytes that is made up of three 16K byte arrays of EPROM; the

first 16K bytes array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located

at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h

through DFFFh (see Figure 3).

14

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

program EPROM (continued)

The EPROM memory map in Table 9 expresses the following:

The programming control register for program EPROM (EPCTLM) for 16K-byte EPROM is located at

address 101Ch (P01C).

For the 32K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the

second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C).

For the 48K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the

second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C); the third 16K-byte array is

controlled by EPCTLH, located at 1014h (P014).

Table 9. EPROM Memory Map

’756

’758

’759

EPROM size

16K Bytes

32K Bytes

48K Bytes

16K

4000h–7FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

Third 16K

A000h–DFFFh

Memory Mapped

EPCTLM

P01C

EPCTLL

P01E

EPCTLM

P01C

EPCTLL

P01E

EPCTLM

P01C

EPCTLH

P014

Contol Registers

Reading the program-EPROM modules is identical to reading other internal memory. During programming, the

EPROM is controlled by the EPCTL. The program EPROM modules’ features include:

Programming

–

In-circuit programming capability if V is applied to MC

PP

Control register: Program EPROM programming is controlled by the program EPROM control registers

(EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 8.

–

Programming one EPROM module while executing the other

Write protection: Writes to the program EPROM are disabled under the following conditions:

–

Reset: All programming to the EPROM module is halted.

Low-power modes

13 V not applied to MC

program ROM

The program ROM consists of 4K to 48K bytes of mask-programmable ROM. The program ROM is used for

permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device

fabrication. ROM security is a feature of the ‘45x devices, which inhibits reading of the data using the

programmer.

†

Table 10. ROM Memory Map

‘x50

‘x52

‘x53

‘x56

‘x58

‘x59

ROM Size

4K Bytes

8K Bytes

12K Bytes

16K Bytes

32K Bytes

48K Bytes

Memory Mapped

7000h – 7FFFh

6000h – 7FFFh

5000h – 7FFFh

4000h – 7FFFh

3000h – 9FFFh

2000h – DFFFh

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI ), and addresses 7FECh through 7FFFh are reserved for

interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh.

TI is a trademark of Texas Instruments Incorporated.

15

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx5x CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

internally generated, while one (RESET) is controlled externally. These actions are as follows:

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key

register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 User’s

Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B)

for more information.

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See

the TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature

number SPNS014B) for more information.

External RESET Pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number

SPNS014B) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x5x device to reset external system components. Additionally, if a cold-start condition

(V is off for several hundred milliseconds) occurs, oscillator failure occurs, or RESET pin is held low, then the

CC

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag

(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 11 lists the reset sources.

Table 11. Reset Sources

REGISTER

SCCR0

ADDRESS

1010h

PF

BIT NO.

CONTROL BIT

COLD START

SOURCE OF RESET

Cold (power-up)

P010

P04A

7

4

5

SCCR0

1010h

OSC FLT FLAG

Oscillator out of range

Watchdog timer timeout

T1CTL2

104Ah

WD OVRFL INT FLAG

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers initialize: ST = 00h, SP = 01h (reset state).

2. Registers A and B initialize to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to by the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control

register bits are initialized to their reset state. During RESET, the two basic operating modes which are the

microcomputer and microprocessor modes can be selected by applying the desired voltage level to the

dedicated MC pin two cycles before RESET goes inactive (refer to page 7 for operating modes description).

16

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TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure

incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of

the status register.

Each system interrupt is configured independently to either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is configured selectively on either the high- or

low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx5x has nine hardware system interrupts (plus RESET) as shown in Table 12. Each system

interrupt has a dedicated vector located in program memory through which control is passed to the interrupt

service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt

sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the

associated PF. Each interrupt source FLAG bit is individually readable for software polling or determining which

interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in

Figure 4.

17

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8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

interrupts (continued)

EXT INT 3

INT 3

EXT INT 2

INT 2

TIMER 2A

Overflow

TIMER 1

INT3 PRI

Overflow

Compare1

Ext Edge

INT2 PRI

Ext Edge

EXT INT1

CPU

Compare2

Input Capture 1

Watchdog

INT1

Input Capture 1

Input Capture 2

NMI

T2A PRI

T1 PRI

Priority

Logic

INT1 PRI

STATUS REG

IE1

Level 1 INT

Level 2 INT

IE2

Enable

AD INT

AD PRI

SCI INT

SPI INT

SPI PRI

TX

RX

TXPRI

RXPRI

BRKDT

TXRDY

RXRDY

A/D

SPI

Figure 4. Interrupt Control

On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported.

Softwareconfiguration of the external interrupts is performed through the INT1, INT2, and INT3 control registers

in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling

edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or

non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or

global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should

be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts

INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not

required (INT1 can be similarly configured as an input pin). Table 12 shows the interrupt vector sources,

corresponding addresses, and hardware priorities.

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interrupts (continued)

Table 12. Hardware System Interrupts

SYSTEM

INTERRUPT

VECTOR

ADDRESS

†

INTERRUPT SOURCE

INTERRUPT FLAG

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

PRIORITY

External RESET

Watchdog overflow

Oscillator fault detect

‡

RESET

7FFEh, 7FFFh

1

‡

External INT1

INT1 FLAG

INT2 FLAG

INT3 FLAG

SPI INT FLAG

INT1

INT2

INT3

7FFCh, 7FFDh

7FFAh, 7FFBh

7FF8h, 7FF9h

7FF6h, 7FF7h

2

3

4

5

External INT2

External INT3

SPI RX/TX complete

SPIINT

Timer 1 overflow

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC1 INT FLAG

WD OVRFL INT FLAG

Timer 1 compare 1

Timer 1 compare 2

Timer 1 external edge

Timer 1 input capture 1

Watchdog overflow

§

T1INT

7FF4h, 7FF5h

6

SCI RX data register full

SCI RX break detect

RXRDY FLAG

BRKDT FLAG

‡

RXINT

7FF2h,7FF3h

7FF0h, 7FF1h

7

8

SCI TX data register empty

TXRDY FLAG

TXINT

T2AINT

ADINT

Timer 2A overflow

T2A OVRFL INT FLAG

T2AC1 INT FLAG

T2AC2 INT FLAG

T2AEDGE INT FLAG

T2AIC1 INT FLAG

T2AIC2 INT FLAG

Timer 2A compare 1

Timer 2A compare 2

Timer 2A external edge

Timer 2A input capture 1

Timer 2A input capture 2

7FEEh, 7FEFh

7FECh, 7FEDh

9

A/D conversion complete

AD INT FLAG

10

†

‡

§

Relative priority within an interrupt level

Releases microcontroller from STANDBY and HALT low-power modes.

Releases microcontroller from STANDBY low-power mode.

privileged operation and EEPROM write-protection override

The TMS370Cx5x family has significant flexibility to enable the designer to software-configure the system and

peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation

ensures the integrity of the system configuration, once it is defined for an application. Following a hardware

reset, the TMS370Cx5x operates in the privileged mode, where all peripheral file registers have unrestricted

read/write access, and the application program configures the system during the initialization sequence

following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set

to 1 to enter the nonprivileged mode; disabling write operations to specific configuration control bits within the

peripheral file. Table 13 displays the system configuration bits that are write-protected during the nonprivileged

mode and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write-protection override (continued)

Table 13. Privileged Bits

†

REGISTER

CONTROL BIT

PF AUTOWAIT

NAME

LOCATION

P010.5

P010.6

SCCRO

OSC POWER

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR1

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN/IDLE

HALT/STANDBY

P03F.5

P03F.6

P03F.7

SPI ESPEN

SPI PRIORITY

SPI STEST

SPIPRI

SCIPRI

P05F.4

P05F.5

P05F.6

P05F.7

SCI ESPEN

SCIRX PRIORITY

SCITX PRIORITY

SCI STEST

P04F.6

P04F.7

T1 PRIORITY

T1 STEST

T1PRI

P06F.6

P06F.7

T2A PRIORITY

T2A STEST

T2APRI

P07F.5

P07F.6

P07F.7

AD ESPEN

AD PRIORITY

AD STEST

ADPRI

†

The privileged bits are shown in a bold typeface in Table 15.

The write-protect override (WPO) mode provides an external hardware method for overriding the

write-protection registers of data EEPROM on the TMS370Cx5x. The WPO mode is entered by applying a 12-V

input to MC after RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not the

programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are

generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data

EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC

pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx5x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time when the mask is manufactured.

The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The

HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.

In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial

communications interface remain active. System processing is suspended until a qualified interrupt (hardware

RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial

communications interface 1) is detected.

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low-power and IDLE modes (continued)

In the HALT mode (HALT/STANDBY = 1), the TMS370Cx5x is placed in its lowest power consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level

on the receive pin of the serial communications interface 1) is detected. The low-power mode selection bits are

summarized in Table 14.

Table 14. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

MODE SELECTED

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

1

0

1

STANDBY

HALT

1

0

X

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6–7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This

means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status

registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the

STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘x5x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard

oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of

a TMS370 microcontroller. The ‘x5x ROM-masked devices offer both options to meet system engineering

requirements. Only one of the two clock options is allowed on each ROM device. The ‘75xA EPROM has only

the standard divide-by-4, while the ‘75xB EPROM has the divide-by-1.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock

(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external

resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock

module then divides the resulting signal by four to provide the four-phased internal system clock signals. The

resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows

external resonator frequency

4

CLKIN

4

Divide-by-4 option : SYSCLK

Divide-by-1 option : SYSCLK

external resonator frequency

4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of

low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators.

The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a

steeper decay of emissions produced by the oscillator.

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system configuration registers

Table 15 contains system configuration and control functions and registers for controlling EEPROM

programming. The privileged bits are shown in a bold typeface and shaded.

Table 15. Peripheral File Frame 1: System Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

—

SCCR0

AUTOWAIT

DISABLE

MEMORY

DISABLE

P011

P012

—

SCCR1

SCCR2

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

—

P013

P014

Reserved

BUSY

VPPS

—

W0

EXE

EPCTLH

P015

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT3

FLAG

INT3

PIN DATA

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

P01A

P01B

P01C

P01D

P01E

P01F

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTLM

EPCTLL

Reserved

—

W0

Reserved

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digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 16 lists the specific

addresses, registers, and control bits within this peripheral file frame.

Table 16. Peripheral File Frame 2: Digital Port Control Registers

PF

P020

P021

P022

P023

P024

P025

P026

P027

P028

P029

P02A

P02B

P02C

P02D

P02E

P02F

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Reserved

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2

Port A Data

Port A Direction

Reserved

BPORT1

BPORT2

BDATA

BDIR

Port B Control Register 2

Port B Data

Port B Direction

Reserved

CPORT1

CPORT2

CDATA

CDIR

Port C Control Register 2

Port C Data

Port C Direction

Port D Control Register 1

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2

Port D Data

Port D Direction

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

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digital port control registers (continued)

Table 17. Port Configuration Register Setup

FUNCTION B

(µP MODE)

INPUT

XPORT1 = 0

OUTPUT

FUNCTION A

†

XPORT1 = 1

XPORT1 = 0

PORT

XPORT2 = 0

XDATA = y

XDIR = 0

XPORT2 = 0

XDATA = q

XDIR = 1

XPORT2 = 1

XDATA = x

XDIR = x

XPORT2 = 1

XDATA = x

XDIR = x

A

B

C

0–7

Data In y

Data Out q

Data Bus

Low ADDR

Hi ADDR

Reserved

0

1

2

3

4

5

6

7

CSE2

CSH3

CSH2

SYSCLK

R/W

CSPF

CSH1

CSE1

OCF

—

SYSCLK

R/W

—

EDS

WAIT

D

Data In y

Data Out q

XPORT1 = 1

XPORT2 =0

Not defined

XDATA = x

XDIR = x

†

DPORT only

timer 1 module

The programmable timer 1 (T1) module of the TMS370Cx5x provides the designer with the enhanced timer

resources required to perform realtime system control. The T1 module contains the general-purpose timer and

the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock

sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and

compare) for special timer function control. The T1 module includes three external device pins that can be used

for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. T1 module is

shown in Figure 5.

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timer 1 module (continued)

Edge

Select

16-Bit

Capt/Comp

Register

T1IC/CR

16-Bit

Counter

PWM

Toggle

MUX

T1PWM

16

16-Bit

Compare

Register

Interrupt

Logic

8-Bit

Prescaler

T1EVT

Interrupt

Logic

16-Bit

MUX

WatchdogCounter

(Aux. Timer)

Figure 5. Timer 1 Block Diagram

Three T1 I/O pins:

–

T1IC/CR: T1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin

T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin

T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin

Two operation modes:

–

Dual-compare mode: Provides PWM signal

Capture/compare mode: Provides input capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a

capture or compare register

One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if

watchdog feature is not needed.

Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T1IC/CR)

25

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8-BIT MICROCONTROLLER

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timer 1 module (continued)

Interrupts that can be generated on the occurrence of:

–

A capture

A compare equal

A counter overflow

An external edge detection

Sixteen T1 module control registers located in the PF frame, beginning at address P040

Table 18 shows the T1 module control register.

Table 18. T1 Module Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Capture/Compare

P040 Bit 15

P041 Bit 7

P042 Bit 15

P043 Bit 7

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 15

T1 Counter MSbyte

T1 Counter LSbyte

Bit 8 T1CNTR

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Watchdog Reset Key

Bit 8 T1C

Bit 0

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Bit 0 WDRST

WD

INPUT

SELECT2

WD

INPUT

SELECT1

WD

INPUT

†

SELECT0

T1

INPUT

SELECT2

T1

INPUT

SELECT1

WD OVRFL

TAP SEL

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

WD OVRFL WD OVRFL WD OVRFL T1 OVRFL

T1 OVRFL

INT FLAG

T1 SW

RESET

—

†

RST ENA

INT ENA

INT FLAG

INT ENA

Mode: Dual-Compare

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

T1

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

MODE = 0

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

—

MODE = 1

OUT ENA

Modes: Dual-Compare and Capture/Compare

T1EVT

DATA IN

T1EVT

DATA DIR

P04D

P04E

—

T1PC1

T1PC2

T1PRI

DATA OUT FUNCTION

T1IC/CR T1IC/CR

DATA OUT FUNCTION

T1PWM

DATA IN

T1PWM

DATA OUT FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA DIR

T1

P04F T1 STEST

—

PRIORITY

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT

SELECT2 bits are ignored.

26

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8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

timer 1 module (continued)

The T1 capture/compare mode block diagram is illustrated in Figure 6. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,

bit 0, in the T1CTL2 register.

T1CC.15-0

16-Bit

LSB

T1C1

OUT ENA

Capt/Comp

Register

Prescale

Clock

Source

MSB

T1PC2.7-4

T1PWM

T1CTL4.6

T1CNTR.15-0

LSB

MSB

16-Bit

Counter

16

T1 PRIORITY

0

1

T1C1 INT FLAG

T1CTL3.5

T1PRI.6

Level 1 Int

Level 2 Int

Compare=

Reset

T1CTL3.0

T1C.15-0

T1 SW

RESET

T1C1 INT ENA

16-Bit

LSB

T1C1

RST ENA

Compare

Register

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL4.4

T1CTL2.4

T1 OVRFL INT ENA

T1PC2.3-0

T1IC/CR

T1EDGE DET ENA

T1EDGE INT FLAG

T1CTL3.7

Edge

Select

T1CTL4.0

T1CTL3.2

T1EDGE INT ENA

T1CTL4.2

T1EDGE POLARITY

Figure 6. Capture/Compare Mode

27

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TMS370Cx5x

8-BIT MICROCONTROLLER

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timer 1 module (continued)

The T1 dual-compare mode block diagram is illustrated in Figure 7. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,

bit 0, in the T1CTL2 register.

T1CC.15-0

16-Bit

Capt/Comp

Register

T1C2 INT FLAG

T1CTL3.6

LSB

Prescaler

Clock

Source

MSB

Output

Enable

T1CTL3.1

T1C2 INT ENA

T1CTL4.5

Compare=

T1CNTR.15-0

T1PC2.7-4

T1PWM

T1C2 OUT ENA

T1CTL4.6

LSB

MSB

16-Bit

Counter

16

T1C1 INT FLAG

T1CTL3.5

Reset

Compare=

T1C1 OUT ENA

T1CTL4.3

T1CTL3.0

T1C1 INT ENA

T1C1

RST ENA

T1C.15-0

T1 SW

RESET

16-Bit

Compare

Register

LSB

T1CTL4.4

T1CR OUT ENA

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL2.4

T1 OVRFL INT ENA

T1CTL4.1

T1CR

RST ENA

T1PC2.3-0

T1IC/CR

Edge

Select

T1 PRIORITY

T1PRI.6

T1CTL4.0

0

1

Level 1 Int

Level 2 Int

T1EDGE INT FLAG

T1CTL3.7

T1EDGE DET ENA

T1CTL4.2

T1CTL3.2

T1EDGE INT ENA

T1EDGE POLARITY

Figure 7. Dual-Compare Mode

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TMS370Cx5x

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timer 1 module (continued)

The TMS370Cx5x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be

software-programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not

desired. The WD function is to monitor software and hardware operation and to implement a system reset when

the WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect

value). The WD can be configured as one of the three mask options: standard watchdog, hard watchdog, or

simple counter.

Standard watchdog configuration (see Figure 8) – for ’C75xA EPROM and mask-ROM devices

–

Watchdog mode

–

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

AWDresetkey(WDRST)registerisusedtoclearthewatchdogcounter(WDCNTR)whenacorrect

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

Awatchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

–

Non-watchdog mode

–

Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer

WDCNTR.15-0

WD OVRFL

INT FLAG

T1CTL2.6

16-Bit

Watchdog Counter

T1CTL2.5

Interrupt

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL1.7

T1CTL2.7

WD OVRFL

TAP SEL

System Reset

WD OVRFL

RST ENA

Watchdog Reset Key

WDRST.7-0

Figure 8. Standard Watchdog

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timer 1 module (continued)

Hard watchdog configuration (see Figure 9) – for ‘C75xB EPROM and mask-ROM devices

–

Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK.

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

–

Automatic activation of the WD timer upon power-up reset

INT1 is enabled as nonmaskable interrupt during low-power modes

A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

WDCNTR.15-0

WD OVRFL

INT FLAG

16-Bit

Watchdog Counter

T1CTL2.5

Reset

Clock

Prescaler

T1CTL1.7

System Reset

WD OVRFL

TAP SEL

Watchdog Reset Key

WDRST.7-0

Figure 9. Hard Watchdog

30

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timer 1 module (continued)

Simple-counter configuration (see Figure 10) – for mask-ROM devices only

–

The simple counter can be configured as an event counter, pulse accumulator, or an interval timer

WDCNTR.15-0

WD OVFL

16-Bit

Watchdog Counter

T1CTL2.6

INT FLAG

Interrupt

T1CTL2.5

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL1.7

WD OVRFL

TAP SEL

Watchdog Reset Key

WDRST.7-0

Figure 10. Simple Counter

timer 2A module

The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter, 16-bit compare

register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture

register in one mode and as a compare register in the other mode. The T2A module adds an additional timer

that provides an event count, input capture, and compare functions. The T2A module includes three external

device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module is

shown in Figure 11.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

timer 2A module (continued)

Edge

Detect

T2AIC1/CR

16–Bit

Capt/Comp

Register

Edge

Detect

T2AIC2/PWM

(Dual-Capture Mode)

PWM

Toggle

T2AIC2/PWM

16–Bit

Capture

Register

INT

Logic

(Dual-Compare Mode)

16

16–Bit

Compare

Register

Clock

Select

16–Bit

Counter

T2AEVT

Figure 11. Timer 2A Block Diagram

The T2A module features include the following:

Three T2A I/O pins:

–

T2AIC1/CR: T2A input-capture 1/counter-reset input pin, or general-purpose bidirectional I/O pin

T2AIC2/PWM: T2A input-capture 2/pulse-width-modulation (PWM) output pin, or general-purpose

bidirectional I/O pin

–

T2AEVT: Timer 2A event-input pin, or general-purpose bidirectional I/O pin

Two operational modes:

–

Dual-compare mode: Provides PWM signal

Dual-capture mode: Provides input-capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture register with associated capture logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a

capture or compare register

T2A clock sources can be any of the following:

–

System clock

No clock (the counter is stopped)

External clock synchronized to the system clock (event counter)

System clock while external input is high (pulse accumulation)

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

timer 2A module (continued)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T2AIC1/CR)

Interrupts that can be generated on the occurrence of:

–

A compare equal to dedicated compare register

A compare equal to capture-compare register

A counter overflow

An external edge 1 detection

An external edge 2 detection

Fourteen T2A module-control registers: Located in the PF frame beginning at address P060

The T2A module-control registers are illustrated in Table 19.

Table 19. Timer 2A Module Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Dual-Capture

P060 Bit 15

P061 Bit 7

P062 Bit 15

P063 Bit 7

P064 Bit 15

P065 Bit 7

P066 Bit 15

P067 Bit 7

T2A Counter MSbyte

T2A Counter LSbyte

Bit 8

T2ACNTR

T2AC

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Capture Register 2 MSbyte

Capture Register 2 LSbyte

T2ACC

T2AIC

T2A

T2A OVRFL

OVRFL INT

INT ENA

T2A

INPUT

SELECT1

T2A INPUT

SELECT0

T2A SW

RESET

P06A

—

T2ACTL1

FLAG

Mode: Dual-Compare

T2AEDGE1

INT FLAG

T2AC2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1

INT ENA

T2AC2

INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 0

T2AC1

OUT ENA

T2AC2

OUT ENA

T2AC1

RST ENA

T2AEDGE1 T2AEDGE1

RST ENA

OUT ENA

POLARITY

DET ENA

Mode: Dual-Capture

T2AEDGE1

INT FLAG

T2AEDGE2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1

INT ENA

T2AEDGE2

INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 1

T2AC1

RST ENA

T2AEDGE2 T2AEDGE1

DET ENA

—

POLARITY

DET ENA

Modes: Dual-Compare and Dual-Capture

T2AEVT

DATA IN

T2AEVT

DATA OUT

T2AEVT

FUNCTION

T2AEVT

DATA DIR

P06D

P06E

P06F

—

T2APC1

T2APC2

T2APRI

T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC1/CR

T2AIC1/CR

DATA OUT

T2AIC1/CR

FUNCTION

T2AIC1/CR

DATA DIR

DATA IN

DATA OUT

FUNCTION

DATA DIR

DATA IN

T2A

PRIORITY

T2A STEST

—

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

timer 2A module (continued)

The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,

bit 0, in the T2ACTL2 register.

T2ACC.15-0

16-Bit

LSB

Capt/Comp

Register

MSB

Output

Enable

Clock

Source

T2AC2 INT FLAG

T2ACTL2.6

T2ACTL2.1

T2AC2 INT ENA

T2ACTL3.5

Compare=

16

T2ACNTR.15-0

T2APC2.7-4

T2AC2 OUT ENA

T2ACTL3.6

LSB

MSB

16-Bit

Counter

T2AIC2/PWM

T2AC1 INT FLAG

T2ACTL2.5

T2ACTL2.0

T2AC1 INT ENA

Reset

Compare=

T2AC.15-0

T2AC1 OUT ENA

T2ACTL3.3

T2A SW

RESET

T2AC1

RST ENA

T2ACTL3.4

16-Bit

Compare

Register

LSB

T2ACTL1.0

T2AEDGE1

OUT ENA

MSB

T2A OVRFL INT FLAG

T2ACTL1.3

T2ACTL3.1

T2AEDGE1

RST ENA

T2ACTL1.4

T2APC2.3-0

T2AIC1/CR

T2A OVRFL INT ENA

Edge 1

Select

T2A PRIORITY

T2APRI.6

T2ACTL3.0

T2AEDGE1 DET ENA

0

1

T2AEDGE1 INT FLAG

T2ACTL2.7

Level 1 Int

Level 2 Int

T2ACTL3.2

T2ACTL2.2

T2AEDGE1 POLARITY

T2AEDGE1 INT ENA

Figure 12. Dual-Compare Mode

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

timer 2A module (continued)

The T2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,

bit 0, in the T2ACTL2 register.

T2AIC.15–0

T2ACC.15–0

16-Bit

Capture

Register 2

16-Bit

Capt/Comp

Register 1

LSB

MSB

Clock

Source

T2ACNTR.15–0

LSB

16-Bit

Counter

16

MSB

T2A PRIORITY

T2APRI.6

0

1

T2AC1 INT FLAG

T2ACTL2.5

Level 1 Int

Level 2 Int

Compare =

Reset

T2ACTL2.0

T2AC.15–0

T2AC1 INT ENA

T2A SW

RESET

T2A OVRFL INT FLAG

T2ACTL1.3

16-Bit

Compare

Register

LSB

T2AC1

RST ENA

MSB

T2ACTL1.0

T2ACTL1.4

T2A OVRFL INT ENA

T2ACTL3.4

T2ACTL3.0

T2AEDGE1 INT FLAG

T2AEDGE1 DET ENA

T2ACTL2.7

T2APC2.3–0

Edge1

Select

T2ACTL2.2

T2AIC1/CR

T2ACTL3.2

T2AEDGE1 INT ENA

T2AEDGE1 POLARITY

T2ACTL3.1

T2AEDGE2 INT FLAG

T2ACTL2.6

T2APC2.7–4

T2AIC2/PWM

Edge 2

Select

T2AEDGE2 DET ENA

T2ACTL3.3

T2ACTL2.1

T2AEDGE2 POLARITY

T2AEDGE2 INT ENA

Figure 13. Dual-Capture Mode

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

serial peripheral interface (SPI) module

The SPI is a high-speed, synchronous, serial I/O port that allows a serial bit stream of programmed length

(1 to 8 bits) to be shifted into, and out of, the device at a programmable bit-transfer rate.The SPI is used normally

for communications between the microcontroller and external peripherals or another microcontroller. Typical

applicationsincludeexternalI/Oorperipheralexpansionthroughdevicessuchasshiftregisters, displaydrivers,

and analog-to-digital converters. The master/slave operation of the SPI supports multi-device communications.

The SPI module features include the following:

Three external pins:

–

SPISOMI: SPI slave output/master input pin or general purpose bidirectional I/O pin

SPISIMO: SPI slave input/master output pin or general purpose bidirectional I/O pin

SPICLK: SPI serial clock pin or general purpose bidirectional I/O pin

Two operational modes: master and slave

Baud rate: Eight different programmable rates

–

Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK

SYSCLK

2

SPI BAUD RATE

2^b

–

Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK.

For maximum slave SPI BAUD RATE < SYSCLK/8

where b = bit rate in SPICCR.5-3 (range 0–7)

Data word format: one to eight data bits

Simultaneous receive and transmit operation (transmit function can be disabled in software)

Transmitter and receiver operations are accomplished through either interrupt driven or polled algorithms.

Seven SPI module control registers located in control register frame beginning at address P030h

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

serial peripheral interface (SPI) module (continued)

The SPI module control registers are illustrated in Table 20.

Table 20. SPI Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SPI SW

RESET

CLOCK

POLARITY

SPI BIT

RATE2

SPI BIT

RATE1

SPI BIT

RATE0

SPI

CHAR2

SPI

CHAR1

SPI

CHAR0

P030

SPICCR

RECEIVER

OVERRUN

SPI INT

FLAG

MASTER/

SLAVE

SPI INT

ENA

P031

—

TALK

SPICTL

P032

to

Reserved

P036

P037

P038

P039

RCVD7

SDAT7

RCVD6

SDAT6

RCVD5

SDAT5

RCVD4

RCVD3

Reserved

SDAT3

RCVD2

SDAT2

RCVD1

SDAT1

RCVD0

SDAT0

SPIBUF

SPIDAT

SDAT4

P03A

to

Reserved

P03C

SPICLK

DATA IN

SPICLK

DATA DIR

P03D

P03E

P03F

—

SPIPC1

SPIPC2

SPIPRI

DATA OUT FUNCTION

SPISOMI SPISOMI

DATA OUT FUNCTION

SPISIMO

DATA IN

SPISIMO

DATA OUT FUNCTION

SPISIMO

DATA DIR

SPISOMI

DATA IN

SPISOMI

DATA DIR

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

—

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

serial peripheral interface (SPI) module (continued)

The SPI block diagram is illustrated in Figure 14.

RECEIVER

SPIBUF.7-0

OVERRUN

SPIBUF Buffer

SPICTL.7

Register

SPIPRI.6

8

SPICTL.0

SPI INT FLAG

0

Level 1 INT

Level 2 INT

SPICTL.6

1

SPIINT ENA

SPIPC2.7-4

SPISIMO

SPIDAT

Data Register

SPIDAT.7-0

SPICTL.1

SPIPC2.3-0

SPISOMI

TALK

State Control

†

MASTER/SLAVE

SPICCR.2-0

SPI CHAR

SPICTL.2

2

1

0

SPIPC1.3-0

SPICLK

System

Clock

SPICCR.6

CLOCK POLARITY

SPICCR.5-3

5

4

3

SPI BIT RATE

The diagram is shown in slave mode.

†

Figure 14. SPI Block Diagram

serial communications interface 1 (SCI1) module

The TMS370x5x devices include a serial communications interface (SCI1) module. The SCI1 module supports

digital communications between the TMS370 devices and other asynchronous peripherals and uses the

standard non-return-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and

each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in

the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun,

and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a

16-bit baud-select register.

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

Features of the SCI1 module include:

Three external pins:

–

SCITXD: SCI transmit output pin or general-purpose bidirectional I/O pin

SCIRXD: SCI receive input pin or general-purpose bidirectional I/O pin

SCICLK: SCI bidirectional serial clock pin, or general-purpose bidirectional I/O pin

†

Two communications modes: asynchronous and isosynchronous

Baud rate: 64K different programmable rates

–

Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK

SYSCLK

(BAUD REG 1) 32

ASYNCHRONOUS BAUD

–

Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK

SYSCLK

(BAUD REG 1)

ISOSYNCHRONOUS BAUD

2

Data-word format

–

One start bit

Data-word length programmable from 1 to 8 bits

Optional even/odd/no parity bit

One or two stop bits

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: Idle-line and address bit

Half or full-duplex operation

Double-buffered receive and transmit functions

Interrupt driven or polled algorithms with status flags accomplish transmitter (TX) and receiver (RX)

operations.

–

Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX

EMPTY flag (transmitter shift register is empty)

–

Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR monitoring four interrupt conditions

–

Separate enable bits for transmitter and receiver interrupts

NRZ (non return-to-zero) format

Eleven SCI1 module control registers are located in control register frame beginning at address P050h.

†

Isosynchronous = Isochronous

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

The SCI1 module control registers are illustrated in Table 21.

Table 21. SCI1 Module Control Register Memory Map

PF

P050 STOP BITS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

EVEN/ODD

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS/

IDLE WUP

SCI CHAR2 SCI CHAR1 SCI CHAR0 SCICCR

SCI SW

RESET

P051

P052

P053

P054

P055

—

CLOCK

BAUDC

BAUD4

—

TXWAKE

BAUDB

BAUD3

—

SLEEP

BAUDA

BAUD2

—

TXENA

BAUD9

BAUD1

—

RXENA

BAUD8

SCICTL

BAUDF

(MSB)

BAUDE

BAUD6

TX EMPTY

RXRDY

BAUDD

BAUD5

—

BAUD MSB

BAUD LSB

TXCTL

BAUD0

(LSB)

BAUD7

TXRDY

SCI TX

INT ENA

RX

ERROR

SCI RX

INT ENA

BRKDT

FE

OE

PE

RXWAKE

RXCTL

P056

P057

P058

Reserved

RXDT7

TXDT7

RXDT6

TXDT6

RXDT5

TXDT5

RXDT4

RXDT3

RXDT2

TXDT2

RXDT1

TXDT1

RXDT0

TXDT0

RXBUF

TXBUF

Reserved

P059

P05A

P05B

P05C

TXDT4

TXDT3

Reserved

SCICLK

DATA IN

SCICLK

DATA DIR

P05D

P05E

—

SCIPC1

SCIPC2

SCIPRI

DATA OUT FUNCTION

SCIRXD SCIRXD

DATA OUT FUNCTION

SCITXD

DATA IN

SCITXD

DATA OUT FUNCTION

SCITXD

DATA DIR

SCIRXD

DATA IN

SCIRXD

DATA DIR

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

P05F SCI STEST

—

The SCI1 module block diagram is illustrated in Figure 15.

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

TXBUF.7–0

TXWAKE

SCICTL.3

Frame Format and Mode

SCI TX Interrupt

SCITX PRIORITY

Transmit Data

Buffer Reg.

PARITY

EVEN/ODD ENABLE

1

0

1

SCIPRI.6

SCI TX INT ENA

TXRDY

TXCTL.7

Level 1 INT

Level 2 INT

SCICCR.6 SCICCR.5

WUT

TXCTL.0

8

TX EMPTY

TXCTL.6

SCIPC2.7–4

SCITXD

TXENA

SCITXD

TXSHF Reg.

BAUD MSB. 7–0

SCICTL.1

Baud Rate

MSbyte Reg.

CLOCK

SCIPC1.3–0

SCICLK

SYSCLK

SCICTL.4

BAUD LSB. 7–0

Baud Rate

LSbyte Reg.

SCIPC2.3–0

SCIRXD

RXSHF Reg.

RXWAKE

RXCTL.1

SCIRX PRIORITY

SCI RX Interrupt

RXENA

0

1

SCIPRI.5

SCI RX INT ENA

RXCTL.0

RXRDY

RXCTL.6

Level 1 INT

Level 2 INT

RX ERROR

SCICTL.0

8

RXCTL.4–2

FE OE PE

RXCTL.7

ERR

BRKDT

Receive Data

Buffer Reg.

RXCTL.5

RXBUF.7–0

Figure 15. SCI1 Block Diagram

analog-to-digital converter 1 (ADC1) module

The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal

sample-and-hold circuitry. The module has eight multiplexed analog input channels that allow the processor to

convert the voltage levels from up to eight different sources. The ADC1 module features include the following:

Minimum conversion time: 32.8 µs at 5-MHz SYSCLK

Ten external pins:

–

Eight analog input channels (AN0–AN7), any of which can be software configured as digital inputs

(E0–E7) if not needed as analog channels

–

AN1–AN7 can also be configured as positive-input voltage reference.

V

: A/D module high-voltage reference input

CC3

: A/D module low-voltage reference input

SS3

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

analog-to-digital converter 1 (ADC1) module (continued)

The ADDATA register, which contains the digital result of the last ADC1 conversion

ADC1 operations can be accomplished through either interrupt driven or polled algorithms.

Six ADC1 module control registers are located in the control-register frame beginning at address 1070h.

The ADC1 module control registers are illustrated in Table 22.

Table 22. ADC1 Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

CONVERT

START

SAMPLE

START

REF VOLT

SELECT2

REF VOLT

SELECT1

REF VOLT

SELECT0

AD INPUT

SELECT2

AD INPUT

SELECT1

AD INPUT

SELECT0

P070

ADCTL

AD INT

FLAG

AD INT

ENA

P071

P072

—

AD READY

ADSTAT

ADDATA

A-to-D Conversion Data Register

Reserved

P073

to

P07C

P07D

P07E

Port E Data Input Register

Port E Input Enable Register

ADIN

ADENA

AD

PRIORITY

P07F AD STEST

AD ESPEN

—

ADPRI

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

analog-to-digital converter 1 (ADC1) module (continued)

The ADC1 module block diagram is illustrated in Figure 16.

Port E Input

Port E Data

ENA 0

AN 0

ADENA.0

SAMPLE

START

CONVERT

START

ADIN.0

2

1

0

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ADCTL.2–0

ADCTL.6

ADCTL.7

Port E Input

ENA 1

Port E Data

AN 1

AD INPUT SELECT

ADENA.1

ADIN.1

Port E Input

ENA 2

Port E Data

AN 2

ADENA.2

ADIN.2

Port E Input

ENA 3

Port E Data

AN 3

ADENA.3

ADIN.3

ADC1

Port E Input

ENA 4

Port E Data

AN 4

ADENA.4

ADIN.4

ADDATA.7–0

Port E Input

ENA 5

Port E Data

AN 5

A-to-D

Conversion

ADENA.5

ADIN.5

Data Register

Port E Input

ENA 6

AD READY

ADSTAT.2

Port E Data

AN 6

ADENA.6

ADIN.6

5

4

3

AD PRIORITY

ADCTL.5–3

Port E Input

ENA 7

Port E Data

AN 7

0

1

Level 1 INT

Level 2 INT

ADPRI.6

REF VOLTS SELECT

ADENA.7

ADIN.7

V

AD INT FLAG

ADSTAT.1

CC3

V

SS3

ADSTAT.0

AD INT ENA

Figure 16. ADC1 Block Diagram

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

instruction set overview

Table 23 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the

‘370Cx5x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode

while the numbers at the left side of the table represent the least significant nibble. The instruction of these two

opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes

in eight SYSCLK cycles.

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit

emulator (XDS/22), CDT, and an EEPROM/UVEPROM programmer.

Assembler/linker (Part No. TMDS3740850–02 for PC)

–

Includes extensive macro capability

Features high-speed operation

Includes format conversion utilities for popular formats

ANSI C-Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3

or Sun-4 )

–

Generates assembly code for the TMS370 that can be inspected easily

Improves code execution speed and reduces code size with optional optimizer pass

Enables direct reference of the TMS370’s port registers by using a naming convention

Provides flexibility in specifying the storage for data objects

Interfaces C functions and assembly functions easily

Includes assembler and linker

CDT370 (compact development tool) real-time in-circuit emulation

–

Base (Part Number EDSCDT370 – for PC, requires cable)

–

Cable for 68-pin PLCC (Part No. EDSTRG68PLCC)

Cable for 64-pin SDIP (Part No. EDSTRG64SDIL)

–

Provides EEPROM and EPROM programming support

Allows inspection and modification of memory locations

Allows uploading/downloading of program and data memory

Provides capability to execute programs and software routines

Includes 1024 samples trace buffer

Includes single-step executable instructions

Allows use of software breakpoints to halt program execution at selected address

XDS/22 (extended development support) in-circuit emulator

–

Base (Part Number TMDS3762210 for PC, requires cable)

Cable for 68-pin PLCC/64-Pin SDIP (Part No. TMDS3788868)

Contains all of the features of the CDT370 described above but does not have the capability to program

the data EEPROM and program EPROM

–

Contains sophisticated breakpoint trace and timing hardware that provides up to 2047 qualified trace

samples with symbolic disassembly

Allowsbreakpoints to be qualified by address and/or data on any type of memory acquisition. Up to four

levels of events can be combined to cause a breakpoint

Provides timers for analyzing total and average time in routines

HP700 is a trademark of Hewlett-Packard Company.

Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

development system support (continued)

–

Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and

for tracing display

Microcontroller programmer

–

Base (Part No. TMDS3760500A – for PC, requires programmer head)

–

Single unit head for 68-pin PLCC (Part No. TMDS3780510A)

Single unit head for 64-pin SDIP (Part No. TMDS3780511A)

Personal computer-based, window/function-key oriented user interface for ease of use and rapid

learning environment

Design kit (Part No. TMDS3770110 – for PC)

–

Includes TMS370 Application Board and TMS370 Assembler diskette and documentation.

Supports quick evaluation of TMS370 functionality

Provides capability to upload and download code

Provides capability to execute programs and software routines, and to single-step executable

instructions

–

Allows software breakpoints to halt program execution at selected addresses

Includes wire-wrap prototype area

Includes reverse assembler

Starter Kit (Part No. TMDS37000 – For PC)

–

Includes TMS370 Assembler diskette and documentation

Includes TMS370 Simulator

Includes programming adapter board and programming software

Does not include – (to be supplied by the user):

–

+ 5 V power supply

ZIF sockets

9-pin RS232 cable

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

device numbering conventions

Figure 17 illustrates the numbering and symbol nomenclature for the TMS370Cx5x family.

TMS 370 C

7

5

2

A FN T

Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator (window EPROM) that is used for

prototyping purpose.

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology:

Program Memory Types:

C = CMOS

0 = Mask ROM

1 = ROM-less, No Data EEPROM

2 = ROM-less

3 = Mask ROM, No Data EEPROM

4 = ROM memory with security

7 = EPROM

Device Type:

5 = ’x5x device containing the following modules:

– Timer 1

– Timer 2A

– Serial Peripheral Interface

– Serial Communications Interface 1

– Analog-to-Digital Converter 1

Memory Size:

0 = 4K bytes

2 = 8K bytes

3 = 12K bytes

6 = 16K bytes

8 = 32K Bytes

9 = 48K Bytes

Temperature Ranges:

Packages:

A = –40°C to 85°C

L =

0°C to 70°C

T = –40°C to 105°C

FN = Plastic Leaded Chip Carrier

FZ = Ceramic Leaded Chip Carrier

NM = Plastic Shrink Dual-In-Line

JN = Ceramic Shrink Dual-in-Line

ROM and EPROM Option:

A = For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog

– A hard watchdog

– A simple watchdog

The clock can be either:

– Divide-by-4 clock

– Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled

– Disabled

A = For ROM-less device, a standard watchdog, a divide-by-4

clock, and low-power modes are enabled.

A = For EPROM device, a standard watchdog, a divide-by-4

clock, and low-power modes are enabled.

B = For EPROM device, a hard watchdog, a divide-by-1

(PLL) clock, and low-power modes are enabled.

Figure 17. TMS370Cx5x Family Nomenclature

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

device part numbers

Table 24 provides a list of all the ‘x5x devices available. The device part number nomenclature is designed to

assist ordering. Upon ordering, the customer must specify not only the device part number but also the clock

and watchdog timer options desired. Remember that each device can have only one of the three possible

watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders

involving ROM devices.

Table 24. Device Part Numbers

DEVICE PART NUMBERS

FOR 68 PINS

DEVICE PART NUMBERS

FOR 64 PINS

DEVICE PART NUMBERS

FOR 68 PINS

DEVICE PART NUMBERS

FOR 64 PINS

TMS370C050AFNA

TMS370C050AFNL

TMS370C050AFNT

TMS370C050ANMA

TMS370C050ANML

TMS370C050ANMT

TMS370C356AFNA

TMS370C356AFNL

TMS370C356AFNT

TMS370C356ANMA

TMS370C356ANML

TMS370C356ANMT

TMS370C456AFNA

TMS370C456AFNL

TMS370C456AFNT

TMS370C150AFNT

TMS370C250AFNT

—

TMS370C756AFNT

TMS370C756ANMT

TMS370C350AFNA

TMS370C350AFNL

TMS370C350AFNT

TMS370C350ANMA

TMS370C350ANML

TMS370C350ANMT

TMS370C058AFNA

TMS370C058AFNL

TMS370C058AFNT

TMS370C058ANMA

TMS370C058ANML

TMS370C058ANMT

TMS370C052AFNA

TMS370C052AFNL

TMS370C052AFNT

TMS370C052ANMA

TMS370C052ANML

TMS370C052ANMT

TMS370C358AFNA

TMS370C358AFNL

TMS370C358AFNT

TMS370C358ANMA

TMS370C358ANML

TMS370C358ANMT

TMS370C352AFNA

TMS370C352AFNL

TMS370C352AFNT

TMS370C352ANMA

TMS370C352ANML

TMS370C352ANMT

TMS370C758AFNT

TMS370C758BFNT

TMS370C758ANMT

TMS370C452AFNA

TMS370C452AFNL

TMS370C452AFNT

—

TMS370C758BNMT

†

TMS370C059AFNA

TMS370C353AFNA

TMS370C353AFNL

TMS370C353AFNT

†

TMS370C059AFNL

—

†

TMS370C059AFNT

TMS370C056AFNA

TMS370C056AFNL

TMS370C056AFNT

TMS370C056ANMA

TMS370C056ANML

TMS370C056ANMT

†

TMS370C759AFNT

‡

SE370C756AFZT

SE370C758AFZT

SE370C758BFZT

TMS370C156AFNT

—

‡

SE370C756AJNT

SE370C758AJNT

SE370C758BJNT

TMS370C256AFNT

†‡

SE370C759AFZT

†

‡

Only operate up to 3 MHz SYSCLK

System evaluators are for use only in prototype environment, and their reliability has not been characterized.

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

new code release form

Figure 18 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

DATE:

TMS370 MICROCONTROLLER PRODUCTS

To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name:

Street Address:

City:

Contact Mr./Ms.:

Phone: (

)

Ext.:

State

Zip

Customer Purchase Order Number:

Customer Print Number *Yes:

No:

*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM

code processing starts.

#

Customer Part Number:

Customer Application:

(Std. spec to be followed)

TMS370 Device:

TI Customer ROM Number:

(provided by Texas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLATOR FREQUENCY

Low Power Modes

[] Enabled

[] Disabled

Watchdog counter

[] Standard

[] Hard Enabled

[] Simple Counter

Clock Type

[] Standard (/4)

[] PLL (/1)

MIN

TYP

MAX

[] External Drive (CLKIN)

[] Crystal

[] Ceramic Resonator

NOTE:

Non ’A’ version ROM devices of the TMS370 microcontrollers will have the

“Low-powermodesEnabled”, “Divide-by-4”Clock, and“Standard”Watchdog

options. See the TMS370 Family User’s Guide (literature number SPNU127)

or the TMS370 Family Data Manual (literature number SPNS014B).

[] Supply Voltage MIN:

(std range: 4.5V to 5.5V)

MAX:

TEMPERATURE RANGE

PACKAGE TYPE

[] ’L’:

[] ’A’:

[] ’T’:

0° to 70°C (standard)

–40° to 85°C

–40° to 105°C

[] ’N’ 28-pin PDIP

[] “FN” 28-pin PLCC

[] “N” 40-pin PDIP

[] “FN” 44-pin PLCC

[] “FN” 68-pin PLCC

[] “NM” 64-pin PSDIP

[] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZATION

BUS EXPANSION

[] TI standard symbolization

[] YES

[] NO

[] TI standard w/customer part number

[] Customer symbolization

(per attached spec, subject to approval)

NON-STANDARD SPECIFICATIONS:

ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the

satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard

TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the

TI part number.

RELEASE AUTHORIZATION:

This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification

code is approved by the customer.

1. Customer:

Date:

2. TI: Field Sales:

Marketing:

Prod. Eng.:

Proto. Release:

Figure 18. Sample New Code Release Form

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Table 25 is a listing of all the peripheral file frames using the ’Cx5x (provided for a quick reference).

Table 25. Peripheral File Frame Compilation

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SYSTEM CONFIGURATION REGISTERS

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

P011

P012

—

SCCR0

SCCR1

SCCR2

AUTOWAIT

DISABLE

MEMORY

DISABLE

—

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

—

P013

P014

Reserved

BUSY

VPPS

—

W0

EXE

EPCTLH

P015

to

P016

Reserved

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

DATA DIR

DATA OUT

INT3

FLAG

INT3

PIN DATA

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

DATA DIR

DATA OUT

P01A

P01B

P01C

P01D

P01E

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTLM

EPCTLL

Reserved

—

W0

DIGITAL PORT CONTROL REGISTERS

Reserved

P01F

P020

P021

P022

P023

P024

P025

P026

P027

P028

P029

P02A

P02B

P02C

P02D

P02E

P02F

Reserved

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2

Port A Data

Port A Direction

Reserved

BPORT1

BPORT2

BDATA

BDIR

Port B Control Register 2

Port B Data

Port B Direction

Reserved

CPORT1

CPORT2

CDATA

CDIR

Port C Control Register 2

Port C Data

Port C Direction

Port D Control Register 1

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2

Port D Data

Port D Direction

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Table 25. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SPI MODULE CONTROL REGISTER

SPI SW

RESET

CLOCK

POLARITY

SPI BIT

RATE2

SPI BIT

RATE1

SPI BIT

RATE0

SPI

CHAR2

SPI

CHAR1

SPI

CHAR0

P030

P031

SPICCR

SPICTL

RECEIVER

OVERRUN

SPI INT

FLAG

MASTER/

SLAVE

SPI INT

ENA

—

TALK

P032

to

Reserved

P036

P037

P038

P039

RCVD7

SDAT7

RCVD6

SDAT6

RCVD5

SDAT5

RCVD4

SDAT4

RCVD3

Reserved

SDAT3

RCVD2

SDAT2

RCVD1

SDAT1

RCVD0

SDAT0

SPIBUF

SPIDAT

P03A

to

Reserved

P03C

SPICLK

DATA IN

SPICLK

DATA OUT

SPICLK

FUNCTION

SPICLK

DATA DIR

P03D

P03E

P03F

—

SPIPC1

SPIPC2

SPIPRI

SPISIMO

DATA IN

SPISIMO

DATA OUT

SPISIMO

FUNCTION

SPISIMO

DATA DIR

SPISOMI

DATA IN

SPISOMI

DATA OUT

SPISOMI

FUNCTION

SPISOMI DATA

DIR

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

—

TIMER 1 MODULE REGISTER

Modes: Dual-Compare and Capture/Compare

P040 Bit 15

P041 Bit 7

T1 Counter MSbyte

T1 Counter LSbyte

Bit 8 T1CNTR

Bit 0

P042

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Watchdog Reset Key

Bit 8 T1C

Bit 0

Bit 15

P043 Bit 7

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 15

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Bit 0 WDRST

WD

INPUT

SELECT2

WD

INPUT

SELECT1

WD

INPUT

SELECT0

T1

INPUT

SELECT2

T1

INPUT

SELECT1

WD OVRFL

TAP SEL

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

T1 SW

RESET

—

†

RST ENA

Mode: Dual-Compare

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

T1

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

MODE = 0

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

—

T1CTL3

INT FLAG

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdogandtothesimplecounter. Inthehardwatchdog, thesebitscanbemodifiedatanytime;theWDINPUTSELECT2

bits are ignored.

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Table 25. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Mode: Capture/Compare (Continued)

T1

T1C1

OUT ENA

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

P04C

—

T1CTL4

MODE = 1

Modes: Dual-Compare and Capture/Compare

T1EVT DATA T1EVT DATA

T1EVT

FUNCTION

T1EVT DATA

DIR

P04D

P04E

P04F

—

T1PC1

T1PC2

T1PRI

IN

OUT

T1PWM

DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR

DATA DIR

T1

T1 STEST

—

PRIORITY

SCI1 MODULE CONTROL REGISTER

EVEN/ODD

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS/

IDLE WUP

P050 STOP BITS

SCI CHAR2

SLEEP

BAUDA

BAUD2

—

SCI CHAR1

TXENA

BAUD9

BAUD1

—

SCI CHAR0 SCICCR

SCI SW

RESET

P051

P052

P053

P054

P055

—

CLOCK

BAUDC

BAUD4

—

TXWAKE

BAUDB

BAUD3

—

RXENA

BAUD8

SCICTL

BAUDF

(MSB)

BAUD

MSB

BAUDE

BAUD6

TX EMPTY

RXRDY

BAUDD

BAUD5

—

BAUD0

(LSB)

BAUD

LSB

BAUD7

TXRDY

SCI TX

INT ENA

TXCTL

RXCTL

RX

ERROR

SCI RX

INT ENA

BRKDT

FE

OE

PE

RXWAKE

P056

P057

P058

P059

Reserved

RXDT7

TXDT7

RXDT6

TXDT6

RXDT5

TXDT5

RXDT4

RXDT3

RXDT2

TXDT2

RXDT1

TXDT1

RXDT0

TXDT0

RXBUF

TXBUF

Reserved

TXDT3

TXDT4

P05A

P05B

P05C

Reserved

SCICLK

DATA IN

SCICLK

DATA OUT

SCICLK

FUNCTION

SCICLK

DATA DIR

P05D

P05E

—

SCIPC1

SCIPC2

SCIPRI

SCITXD

DATA IN

SCITXD

DATA OUT

SCITXD

FUNCTION

SCITXD

DATA DIR

SCIRXD

DATA IN

SCIRXD

DATA OUT

SCIRXD

FUNCTION

SCIRXD

DATA DIR

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

P05F SCI STEST

—

T2A MODULE REGISTER

Modes: Dual-Compare and Dual-Capture

P060 Bit 15

P061 Bit 7

P062

T2A Counter MSbyte

T2A Counter LSbyte

Bit 8

T2ACNTR

T2AC

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Capture Register 2 MSbyte

Capture Register 2 LSbyte

Bit 15

P063 Bit 7

P064 Bit 15

P065 Bit 7

P066 Bit 15

P067 Bit 7

T2ACC

T2AIC

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Table 25. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Dual-Capture (Continued)

T2A

INPUT

SELECT1

T2A OVRFL-

INT ENA

T2A OVRFL

INT FLAG

T2A INPUT

SELECT0

T2A SW

RESET

P06A

—

T2ACTL1

Mode: Dual-Compare

T2AEDGE1

INT FLAG

T2AC2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1

INT ENA

T2AC2

INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 0

T2AC1

OUT ENA

T2AC2

OUT ENA

T2AC1

RST ENA

T2AEDGE1

OUT ENA

T2AEDGE1

POLARITY

T2AEDGE1

RST ENA

T2AEDGE1

DET ENA

Mode: Dual-Capture

T2AEDGE1

INT FLAG

T2AEDGE2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1

INT ENA

T2AEDGE2

INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 1

T2AC1

RST ENA

T2AEDGE2

POLARITY

T2AEDGE1

POLARITY

T2AEDGE2

DET ENA

T2AEDGE1

DET ENA

—

Modes: Dual-Compare and Dual-Capture

T2AEVT

DATA IN

T2AEVT

DATA OUT

T2AEVT

FUNCTION

T2AEVT

DATA DIR

P06D

P06E

P06F

—

T2APC1

T2APC2

T2APRI

T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC1/CR

T2AIC1/CR

DATA OUT

T2AIC1/CR

FUNCTION

T2AIC1/CR

DATA DIR

DATA IN

DATA OUT

FUNCTION

DATA DIR

DATA IN

T2A

PRIORITY

T2A STEST

—

ADC1 MODULE CONTROL REGISTER

CONVERT

START

SAMPLE

START

REF VOLT

SELECT2

REF VOLT

SELECT1

REF VOLT

SELECT0

AD INPUT

SELECT2

AD INPUT

SELECT1

AD INPUT

SELECT0

P070

ADCTL

AD INT

FLAG

P071

P072

—

AD READY

AD INT ENA ADSTAT

ADDATA

A-to-D Conversion Data Register

Reserved

P073

to

P07C

P07D

P07E

Port E Data Input Register

Port E Input Enable Register

ADIN

ADENA

AD

PRIORITY

P07F

AD STEST

AD ESPEN

—

ADPRI

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range,V

, V

(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

CC1

CC2 CC3

Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input clamp current, I (V < 0 or V > V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

IK

I

CC1)

Output clamp current, I

(V < 0 or V > V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

OK

O

CC1

§

Continuous output current per buffer, I (V = 0 to V )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA

O

CC1

Maximum I

current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA

CC

Maximum I current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 170 mA

SS

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

Operating free-air temperature range, T L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A:

A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C

T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 105°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

§

V

= V

CC

CC1

Electrical characteristics are specified with all output buffers loaded with specified I current. Exceeding the specified I current in any buffer

O

can affect the levels on other buffers.

NOTE 2: Unless otherwise noted, all voltage values are with respect to V

.

SS1

recommended operating conditions

MIN

4.5

NOM

MAX

5.5

0.3

0.8

0.3

UNIT

Supply voltage (see Note 2)

5

V

CC1

RAM data-retention supply voltage (see Note 3)

Digital I/O supply voltage (see Note 2)

Analog supply voltage (see Note 2)

Digital I/O supply ground

3

V

CC2

V

CC3

V

SS2

V

SS3

4.5

5

0

V

4.5

– 0.3

V

Analog supply ground

All pins except MC

MC, normal operation

V

SS1

V

IL

Low-level input voltage

V

SS1

All pins except MC, XTAL2/CLKIN, and

RESET

2

V

CC1

MC (non-WPO mode)

XTAL2/CLKIN

V

–0.3

V

+0.3

V

High-level input voltage

CC1

V

IH

0.8 V

0.7 V

V

CC1

RESET

V

CC1

13

EEPROM write protect override (WPO)

11.7

12

EPROM programming voltage (V

Microprocessor

Microcomputer

L version

)

13

13.2

13.5

MC (mode control) voltage

(see Note 4)

PP

V

MC

V

CC1

–0.3

+0.3

CC1

0.3

V

SS1

0

70

85

T

A

Operating free-air temperature

A version

– 40

°C

T version

105

NOTES: 2. Unless otherwise noted, all voltage values are with respect to V

.

SS1

3. RESET must be externally activated when V

or SYSCLK is not within the recommended operating range.

4. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin

CC1

two system-clock cycles (t ) before RESET goes inactive (high). The WPO mode can be selected anytime a sufficient voltage is

c

present on MC.

electrical characteristics over recommended operating free-air temperature range (unless

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

otherwise noted)

PARAMETER

TEST CONDITIONS

= 1.4 mA

MIN

TYP

MAX

UNIT

V

Low-level output voltage (see Note 5)

I

0.4

V

OL

OH

= –50 µA

0.9 V

CC1

High-level output voltage

V

OH

= –2 mA

2.4

0 V < V ≤ 0.3 V

10

50

I

0.3 V < V < V

–0.3 V

CC1

I

µA

MC

V

–0.3 V ≤ V ≤ V

+0.3 V

10

CC1

I

CC1

I

Input current

+ 0.3 V < V ≤ 13 V

650

50

CC1

I

12 V ≤ V ≤ 13 V

See Note 6

mA

µA

I

I/O pins

0 V ≤ V ≤ V

± 10

I

CC1

I

Low-level output current (see Note 5)

V

OL

V

OH

V

OH

= 0.4 V

1.4

– 50

– 2

mA

µA

OL

= 0.9 V

= 2.4 V

CC1

High-level output current

OH

mA

TMS370Cx50A

TMS370Cx52A

30

35

20

25

45

56

30

36

TMS370Cx53A

TMS370Cx56A

TMS370Cx58A

SYSCLK = 5 MHz

See Notes 7 and 8

Supply current

TMS370Cx58B

(operating mode)

OSC POWER bit = 0

(see Note 9)

TMS370Cx50A

TMS370Cx52A

mA

TMS370Cx53A

TMS370Cx56A

TMS370Cx58A

TMS370Cx58B

SYSCLK = 3 MHz

See Notes 7 and 8

†

TMS370Cx59A

46

5

55

11

I

TMS370Cx50A

TMS370Cx52A

CC

Supply current

TMS370Cx53A

TMS370Cx56A

TMS370Cx58A

TMS370Cx58B

(operating mode)

OSC POWER bit = 0

(see Note 9)

SYSCLK = 0.5 MHz

See Notes 7 and 8

mA

13

18

†

TMS370Cx59A

22

12

8

28

17

11

3.5

8.6

3

SYSCLK = 5 MHz,

SYSCLK = 3 MHz,

SYSCLK = 0.5 MHz,

SYSCLK = 3 MHz,

SYSCLK = 0.5 MHz,

See Notes 7 and 8

Supply current (STANDBY mode)

OSC POWER bit = 0 (see Note 10)

2.5

6

Supply current (STANDBY mode)

OSC POWER bit = 1 (see Note 11)

mA

2

Supply current (HALT mode)

XTAL2/CLKIN < 0.2 V, See Note 7

2

30

µA

†

TMS370Cx59 only operate up to 3 MHz SYSCLK

NOTES: 5. In prior versions of the TMS370 family, the I

current was equal to 2 mA for ports A, B, C, and D and the RESET pin.

OL

is a maximum of 50 mA only when the EPROM is being programmed.

6. Input current I

PP

7. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ V

– 0.2V.

CC

8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current

can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance

in pF).

9. Maximum operating current for TMS370Cx50A and TMS370Cx52A = 7.6 (SYSCLK) + 7 mA. Maximum operating current for

TMS370Cx53A, TMS370Cx56A, TMS370Cx58A, and TMS370Cx58B = 10 (SYSCLK) + 5.8 mA.

10. Maximum standby current for TMS370Cx5xA = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

11. Maximum standby current for TMS370Cx5xA and TMS370Cx5xB = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, valid only up

to 3 MHz of SYSCLK.)

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

XTAL2/CLKIN

XTAL1

XTAL2/CLKIN

XTAL1

C3

(see Note B)

C1

(see Note B)

C2

Crystal/Ceramic

Resonator

(see Note A)

External

Clock Signal

(see Note B)

NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic

resonators.

Figure 19. Recommended Crystal/Clock Connections

Load Voltage

1.2 kΩ

V

O

20 pF

Case 1: V = V

= 2.4 V; Load Voltage = 0 V

= 0.4 V; Load Voltage = 2.1 V

O

OH

OL

Case 2: V = V

O

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

Figure 20. Typical Output Load Circuit (see Note A)

V

CC

V

CC

Pin Data

300 Ω

30 Ω

6 kΩ

Output

Enable

I/O

INT1

20 Ω

GND

Figure 21. Typlcal Buffer Circuitry

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

A

Address

Array

RXD

S

SCIRXD

Slave mode

SYSCLK

SCICLK

SPISIMO

SPISOMI

SPICLK

SCITXD

Write

AR

B

Byte

SC

CI

D

XTAL2/CLKIN

Data

SCC

SIMO

SOMI

SPC

TXD

W

E

EDS

FE

IE

M

Final

Initial

Master mode

Program

Read

PGM

R

WT

WAIT

Lowercase subscripts and their meanings are:

c

d

f

cycle time (period)

delay time

r

rise time

su

v

setup time

fall time

valid time

h

hold time

w

pulse duration (width)

The following additional letters are defined as follows:

H

L

High

Low

V

Z

Valid

High impedance

All timings are measured between high and low measurement points as indicated in Figure 22 and Figure 23.

0.8 V

V (High)

2 V (High)

CC

0.8 V (Low)

Figure 22. XTAL2/CLKIN Measurement Points

Figure 23. General Measurement Points

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

†

external clocking requirements for clock divided by 4

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 12)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

t

30

100

20

5

ns

r(Cl)

3

t

Fall time, XTAL2/CLKIN

ns

f(CI)

4

t

Delay time, XTAL2/CLKIN rise to SYSCLK fall

Crystal operating frequency

ns

d(CIH-SCL)

‡

CLKIN

2

MHz

§

¶

SYSCLK

System clock

0.5

†

‡

§

¶

For V and V , refer to recommended operating conditions.

IL IH

’x59A operates up to 12 MHz CLKIN

’x59A operates up to 3 MHz SYSCLK

SYSCLK = CLKIN/4

NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

2

3

4

SYSCLK

Figure 24. External Clock Timing for Divide-by-4

†

external clocking requirements for clock divided by 1 (PLL)

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 12)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

t

30

100

5

ns

r(Cl)

3

t

Fall time, XTAL2/CLKIN

ns

f(CI)

4

t

Delay time, XTAL2/CLKIN rise to SYSCLK rise

Crystal operating frequency

ns

d(CIH-SCH)

#

CLKIN

2

MHz

§

||

System clock

SYSCLK

5

†

§

#

||

For V and V , refer to recommended operating conditions.

IL IH

’x59A operates up to 3 MHz SYSCLK

’x59A operates up to 3 MHz CLKIN (for divide-by-1 clock option)

SYSCLK = CLKIN/1

NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

2

3

4

SYSCLK

Figure 25. External Clock Timing for Divide-by-1

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

general purpose output signal-switching time requirements

MIN NOM

MAX

UNIT

ns

t

Rise time

Fall time

30

r

ns

f

t

r

t

f

Figure 26. Signal-Switching Timing

recommended EEPROM timing requirements for programming

MIN

10

MAX

UNIT

ms

t

Pulse duration, programming signal to ensure valid data is stored (byte mode)

Pulse duration, programming signal to ensure valid data is stored (array mode)

w(PGM)B

20

ms

w(PGM)AR

recommended EPROM operating conditions for programming

MIN NOM

MAX

6

UNIT

V

Supply voltage

4.75

13

5.5

13.2

30

CC1

Supply voltage at MC pin

13.5

50

5

V

PP

I

Supply current at MC pin during programming (V

= 13 V)

mA

PP

Divide-by-4

Divide-by-1

0.5

2

SYSCLK

System clock

MHz

5

recommended EPROM timing requirements for programming

MIN NOM

0.40 0.50

MAX

UNIT

t

Pulse duration, programming signal (see Note 13)

3

ms

w(EPGM)

NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and V

(EPCTL.6) are set.

PPS

61

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

switching characteristics and timing requirements for external read and write (see Figure 27 and

†

Figure 28)

NO.

PARAMETER

MIN

200

MAX

2000

500

UNIT

Divide-by-4 clock

Divide-by-1 PLL

5

t

c

Cycle time, SYSCLK (system clock)

ns

6

7

t

Pulse duration, SYSCLK low

Pulse duration, SYSCLK high

0.5t –25

0.5t

c

ns

w(SCL)

c

0.5t

0.5t +20

c

w(SCH)

c

Delay time, SYSCLK low to address R/W and OCF

valid

8

t

0.25t +75

ns

d(SCL-A)

c

Valid time, address to EDS, CSE1, CSE2, CSH1,

CSH2, CSH3, and CSPF low

9

t

0.5t –90

ns

v(A)

c

‡

0.75t –80

c

10

11

12

13

Setup time, write data time to EDS high

su(D)

Hold time, address, R/W and OCF from EDS, CSE1,

CSE2, CSH1, CSH2, CSH3, and CSPF high

0.5t –60

h(EH-A)

h(EH-D)W

d(DZ-EL)

c

Hold time, write data time from EDS high

0.75t +15

c

Delay time, data bus high impedance to EDS low (read

cycle)

0.25t –35

c

14

15

16

17

18

19

t

Delay time, EDS high to data bus enable (read cycle)

Delay time, EDS low to read data valid

Hold time, read time from EDS high

1.25t –40

c

ns

d(EH-D)

‡

t –95

d(EL-DV)R

h(EH-D)R

su(WT-SCH)

h(SCH-WT)

d(EL-WTV)

c

0

§

Setup time, WAIT time to SYSCLK high

Hold time, WAIT time from SYSCLK high

Delay time, EDS low to WAIT valid

0.25t +70

c

0

0.5t –60

c

Pulse duration, EDS, CSE1, CSE2, CSH1, CSH2,

CSH3, and CSPF low

‡

20

t

w

t –80

c

t +40

c

ns

‡

21

22

23

t

Delay time, address valid to read data valid

Delay time, address valid to WAIT valid

1.5t –115

ns

d(AV-DV)R

d(AV-WTV)

d(AV-EH)

c

t –115

c

‡

1.5t –85

Delay time, address valid to EDS high (end of write)

c

†

‡

§

t = system-clock cycle time = 1/SYSCLK

If wait states, PFWait, or the autowait feature is used, add t to this value for each wait state invoked.

If the autowait feature is enabled, the WAIT input can assume a “don’t care” condition until the third cycle of the access. The WAIT signal must

be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.

c

62

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

7

5

8

6

SYSCLK

ADDRESS

11

20

EDS, CSE1, CSE2, CSH1,

CSH2, CSH3, CSPF

14

9

21

13

16

15

Read Data Read Data

Valid Disable

370 Drives

Data

370 Drives Data

Read Data Drive

DATA

WAIT

19

22

17

18

R/W

OCF

Figure 27. Switching Characteristics and Timing Requirements for External-Read

63

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

7

5

6

SYSCLK

8

ADDRESS

11

20

EDS, CSE1, CSE2, CSH1,

CSH2, CSH3, CSPF

9

10

23

12

DATA

19

22

17

18

WAIT

R/W

Figure 28. Switching Characteristics and Timing Requirements for External-Write

64

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

†

SCI1 isosynchronous mode timing characteristics and requirements for internal clock

(see Note 14 and Figure 29)

NO.

24

25

26

27

28

29

30

MIN

2t

MAX

UNIT

ns

t

Cycle time, SCICLK

131072t

c

c(SCC)

c

Pulse duration, SCICLK low

t

– 45

– 50

0.5t

+45

ns

w(SCCL)

c

c(SCC)

Pulse duration, SCICLK high

ns

w(SCCH)

c

c(SCC)

60

Delay time, SCITXD valid after SCICLK low

Valid time, SCITXD data valid after SCICLK high

Setup time, SCIRXD to SCICLK high

Valid time, SCIRXD data valid after SCICLK high

ns

d(SCCL-TXDV)

v(SCCH-TXD)

su(RXD-SCCH)

v(SCCH-RXD)

t

– 50

ns

w(SCCH)

0.25 t + 145

c

ns

0

ns

NOTE 14: t = system-clock cycle time = 1/SYSCLK

c

24

26

25

SCICLK

28

27

Data Valid

SCITXD

29

30

Data Valid

SCIRXD

†

Figure 29. SCI1 Isosynchronous Mode Timing for Internal Clock

†

Isosynchronous = Isochronous

65

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

†

SCI1 isosynchronous mode timing characteristics and requirements for external clock

(see Note 14 and Figure 30)

NO.

31

32

33

34

35

36

37

MIN

10t

MAX

UNIT

ns

t

Cycle time, SCICLK

c(SCC)

c

Pulse duration, SCICLK low

4.25t + 120

ns

w(SCCL)

c

Pulse duration, SCICLK high

t

c

+ 120

ns

w(SCCH)

Delay time, SCITXD valid after SCICLK low

Valid time, SCITXD data valid after SCICLK high

Setup time, SCIRXD to SCICLK high

Valid time, SCIRXD data after SCICLK high

4.25t + 145

ns

d(SCCL-TXDV)

v(SCCH-TXD)

su(RXD-SCCH)

v(SCCH-RXD)

c

t

ns

w(SCCH)

40

ns

2t

c

ns

NOTE 14: t = system-clock cycle time = 1/SYSCLK

c

31

33

32

SCICLK

35

34

Data Valid

SCITXD

36

37

Data Valid

SCIRXD

†

Figure 30. SCI1 Isosynchronous Timing for External Clock

†

Isosynchronous = Isochronous

66

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

SPI master mode external timing characteristics and requirements (see Note 14 and Figure 31)

NO.

38

39

40

41

42

43

MIN

2t

MAX

256t

UNIT

ns

t

Cycle time, SPICLK

c(SPC)M

c

Pulse duration, SPICLK low

t

– 45

– 55

– 65

0.5t

+45

ns

w(SPCL)M

c

c(SPC)

Pulse duration, SPICLK high

ns

w(SPCH)M

c

c(SPC)

50

Delay time, SPISIMO valid after SPICLK low (polarity = 1)

Valid time, SPISIMO data valid after SPICLK high (polarity =1)

Setup time, SPISOMI to SPICLK high (polarity = 1)

ns

d(SPCL-SIMOV)M

v(SPCH-SIMO)M

su(SOMI-SPCH)M

t

– 50

ns

w(SPCH)

0.25 t + 150

c

ns

Valid time, SPISOMI data valid after SPICLK high

(polarity = 1)

44

t

0

ns

v(SPCH-SOMI)M

NOTE 14: t = system-clock cycle time = 1/SYSCLK

c

38

40

39

SPICLK

41

42

Data Valid

SPISIMO

43

44

Data Valid

SPISOMI

NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.

Figure 31. SPI Master External Timing

67

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

SPI slave mode external timing characteristics and requirements (see Note 14 and Figure 32)

NO.

45

46

47

48

49

50

51

MIN

8t

MAX

UNIT

ns

t

Cycle time, SPICLK

c(SPC)S

c

Pulse duration, SPICLK low

4t – 45 0.5t

c

+45

ns

w(SPCL)S

c(SPC)S

Pulse duration, SPICLK high

4t – 45 0.5t

c

ns

w(SPCH)S

c(SPC)S

Delay time, SPISOMI valid after SPICLK low (polarity = 1)

Valid time, SPISOMI data valid after SPICLK high (polarity =1)

Setup time, SPISIMO to SPICLK high (polarity = 1)

Valid time, SPISIMO data after SPICLK high (polarity = 1)

3.25t + 130

ns

d(SPCL-SOMIV)S

v(SPCH-SOMI)S

su(SIMO-SPCH)S

v(SPCH-SIMO)S

c

t

ns

w(SPCH)S

0

ns

3t + 100

c

ns

NOTE 14: t = system-clock cycle time = 1/SYSCLK

c

45

47

46

SPICLK

48

49

Data Valid

SPISIMO

50

51

Data Valid

SPISOMI

NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.

Figure 32. SPI-Slave External Timing

68

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

The ADC1 has a separate power bus for its analog circuitry. These pins are referred to as V

and V

. The

CC3

SS3

purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry that can

be present on V and V from coupling into the ADC1 analog stage. All ADC1 specifications are given with

SS1

SS3

CC1

respect to V

unless otherwise noted.

Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values)

Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes

Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00 for VI ≤ V

Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 t

≤; FF for VI ≤ V

)

SS3

ref

c

recommended operating conditions

MIN

NOM

MAX

UNIT

4.5

5

5.5

V

Analog supply voltage

Analog ground

V

CC3

V

–0.3

CC1

V

+0.3

CC1

V

–0.3

SS1

V

+0.3

SS1

V

SS3

†

V

ref

Non-V

CC3

reference

2.5

V

+ 0.1

CC3

Analog input for conversion

V

ref

SS3

†

V

ref

must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time.

operating characteristics over recommended ranges operating conditions

PARAMETER

MIN

MAX

±1.5

±0.9

2

UNIT

LSB

mA

µA

‡

Absolute accuracy

V

= 5.5 V

V

= 5.1 V

CC3

ref

‡§

Differential/integral linearity error

V

ref

CC3

Converting

I

Analog supply current

CC3

Nonconverting

5

Input current, AN0–AN7

0 V ≤ V ≤ 5.5 V

2

µA

I

input charge current

1

mA

kΩ

ref

SYSCLK ≤ 3 MHz

24

10

Z

Source impedance of V

ref

3 MHz < SYSCLK ≤ 5 MHz

kΩ

‡

§

Absolute resolution = 20 mV. At V = 5 V, this is one LSB. As V decreases, LSB size decreases; therefore, the absolute accuracy and

differential/integral linearity errors in terms of LSBs increase.

Excluding quantization error of 1/2 LSB

ref

69

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the

sample time is user-defined so that the high-impedance can be accommodated without penalty to the

low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register

(ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START,

ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE START and CONVERT START bits,

signaling that a conversion has started and that the analog signal can be removed.

analog timing requirements

MIN

MAX

UNIT

ns

t

Setup time, analog to sample command

0

su(S)

h(AN)

w(S)

Hold time, analog input from start of conversion

Pulse duration, sample time per kilohm of source impedance

18t

ns

c

†

1

µs/kΩ

†

The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1 kΩ, use a minimum sampling time of 1µs.

Analog Stable

Analog In

t

su(S)

Sample Start

Convert Start

t

h(AN)

t

w(S)

Figure 33. Analog Timing

70

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Table 26 is designed to aid the user in referencing a device part number to a mechanical drawing. The table

shows a cross-reference of the device part number to the TMS370 generic package name and the associated

mechanical drawing by drawing number and name.

Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

PKG TYPE NO. AND

MECHANICAL NAME

TMS370 GENERIC NAME

DEVICE PART NUMBERS

TMS370C050AFNA

TMS370C050AFNL

TMS370C050AFNT

TMS370C150AFNT

TMS370C250AFNT

TMS370C350AFNA

TMS370C350AFNL

TMS370C350AFNT

TMS370C052AFNA

TMS370C052AFNL

TMS370C052AFNT

TMS370C352AFNA

TMS370C352AFNL

TMS370C352AFNT

TMS370C452AFNA

TMS370C452AFNL

TMS370C452AFNT

TMS370C353AFNA

TMS370C353AFNL

TMS370C353AFNT

TMS370C056AFNA

TMS370C056AFNL

TMS370C056AFNT

TMS370C156AFNT

TMS370C256AFNT

TMS370C356AFNA

TMS370C356AFNL

TMS370C356AFNT

TMS370C456AFNA

TMS370C456AFNL

TMS370C456AFNT

TMS370C756AFNT

TMS370C058AFNA

TMS370C058AFNL

TMS370C058AFNT

TMS370C358AFNA

TMS370C358AFNL

TMS370C358AFNT

TMS370C758AFNT

TMS370C758BFNT

TMS370C059AFNA

TMS370C059AFNL

TMS370C059AFNT

TMS370C759AFNT

FN – 68 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

SE370C756AFZT

SE370C758AFZT

SE370C758BFZT

SE370C759AFZT

FZ – 68 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

SE370C756AJNT

SE370C758AJNT

SE370C758BJNT

JN – 64 pin

(70-mil pin spacing)

CERAMIC SHRINK DUAL-IN-LINE

PACKAGE (CSDIP)

JN(R-CDIP-T64) CERAMIC DUAL-IN-LINE

PACKAGE

71

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference (Continued)

PKG TYPE

(mil pin spacing)

PKG TYPE NO. AND

MECHANICAL NAME

TMS370 GENERIC NAME

DEVICE PART NUMBERS

TMS370C050ANMA

TMS370C050ANML

TMS370C050ANMT

TMS370C350ANMA

TMS370C350ANML

TMS370C350ANMT

TMS370C052ANMA

TMS370C052ANML

TMS370C052ANMT

TMS370C352ANMA

TMS370C352ANML

TMS370C352ANMT

TMS370C056ANMA

TMS370C056ANML

TMS370C056ANMT

TMS370C356ANMA

TMS370C356ANML

TMS370C356ANMT

TMS370C756ANMT

TMS370C058ANMA

TMS370C058ANML

TMS370C058ANMT

TMS370C358ANMA

TMS370C358ANML

TMS370C358ANMT

TMS370C758ANMT

TMS370C758BNMT

NM – 64 pin

(70-mil pin spacing)

PLASTIC SHRINK DUAL-IN-LINE

PACKAGE (PSDIP)

NM(R-PDIP-T64) PLASTIC SHRINK

DUAL-IN-LINE PACKAGE

72

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

MECHANICAL DATA

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

0.050 (1,27)

9

13

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

73

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

MECHANICAL DATA

FZ (S-CQCC-J**)

J-LEADED CERAMIC CHIP CARRIER

28 LEAD SHOWN

0.040 (1,02)

45°

Seating Plane

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

A

B

1

0.120 (3,05)

26

4

25

5

0.050 (1,27)

C

(at Seating

Plane)

A

B

0.032 (0,81)

0.026 (0,66)

0.020 (0,51)

0.014 (0,36)

19

11

18

12

0.025 (0,64) R TYP

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

A

B

C

JEDEC

NO. OF

PINS**

OUTLINE

MIN

MAX

MIN

MAX

MIN

MAX

0.485

0.495

0.430

0.455

0.410

0.430

MO-087AA

MO-087AB

MO-087AC

MO-087AD

28

44

52

68

(12,32)

(12,57)

(10,92)

(11,56)

(10,41)

(10,92)

0.685

0.695

0.630

0.655

0.610

0.630

(17,40)

(17,65)

(16,00)

(16,64)

(15,49)

(16,00)

0.785

0.795

0.730

0.765

0.680

0.740

(19,94)

(20,19)

(18,54)

(19,43)

(17,28)

(18,79)

0.985

0.995

0.930

0.955

0.910

0.930

(25,02)

(25,27)

(23,62)

(24,26)

(23,11)

(23,62)

4040219/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

74

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

MECHANICAL DATA

JN (R-CDIP-T64)

CERAMIC DUAL-IN-LINE PACKAGE

2.424 (61,57)

2.376 (60,35)

64

33

0.750 (19,05)

0.730 (18,54)

1

32

0.040 (1,02) TYP

0.094 (2,39)

0.078 (1,98)

0.760 (19,30)

0.740 (18,80)

0.060 (1,52)

0.040 (1,02)

Seating Plane

0.088 (2,24)

0.072 (1,83)

0.175 (4,45) TYP

0.020 (0,51)

0.016 (0,41)

0.012 (0,31)

0.009 (0,23)

0.070 (1,78)

See Note C

2.178 (55,32)

2.162 (54,91)

4040224/A 09/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Each pin centerline located within 0.010 (0,26) of it true longitudinal position.

75

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

MECHANICAL DATA

NM (R-PDIP-T64)

PLASTIC SHRINK DUAL-IN-LINE PACKAGE

2.280 (57,91) MAX

64

33

0.680 (17,27)

0.670 (17,02)

1

32

0.048 (1,216)

0.032 (0,816)

0.222 (5,64) MAX

0.760 (19,30)

0.740 (18,80)

0.020 (0,51) MIN

Seating Plane

0°–15°

0.010 (0,25) NOM

4040056/B 05/95

0.070 (1,78)

0.010 (0,25)

0.125 (3,18) MIN

0.022 (0,56)

0.014 (0,36)

M

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

76

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TMS370C358ANMA
厂家：	ETC
描述：	8-Bit Microcontroller 8位微控制器\n 微控制器外围集成电路装置光电二极管时钟
文件：	总77页 (文件大小：1169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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