TMS370C380AFNL_技术文档

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

N PACKAGE

(TOP VIEW)

CMOS/EEPROM/EPROM Technologies on

a Single Device

1

40

39

38

37

36

35

34

33

32

31

C2

C3

C1

– Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations

– On-Chip Program Memory Versions

– ROM: 4K Bytes

– EPROM: 16K Bytes

– Data EEPROM: 256 Bytes

– Static RAM: 128 or 256 Bytes Usable as

Registers

Flexible Operating Features

2

C0

3

C4

B0

4

C5

B1

5

RESET

INT1

INT2

INT3

NC

B2

6

B3

7

MC

8

XTAL2/CLKIN

XTAL1

9

10

11

12

13

14

15

16

17

18

19

20

V

B7

CC

A7

30 B6

29 B5

28 B4

A6

A5

A4

A3

A2

A1

A0

D7

D4

27

V

SS

26 T1IC/CR

25 T1PWM

24 T1EVT

D5

D6

D3

23

22

21

– Low-Power Modes: STANDBY and HALT

– Commercial, Industrial, and Automotive

Temperature Ranges

FZ AND FN PACKAGES

(TOP VIEW)

– Clock Options

– Divide-by-1 (2 MHz–5 MHz SYSCLK) PLL

– Divide-by-4 (0.5 MHz–5 MHz SYSCLK)

– Supply Voltage (V ) 5 V ±10%

CC

16-Bit General Purpose Timer

– Software Configurable as

6

5

4

3 2 1

44 43 42 41 40

39

INT1

INT2

INT3

MC

7

8

9

XTAL2/CLKIN

38

37

36

35

34

33

32

31

30

29

a 16-Bit Event Counter, or

XTAL1

B7

V

10

11

12

13

14

15

16

17

a 16-Bit Pulse Accumulator, or

a 16-Bit Input Capture Functions, or

Two Compare Registers, or a

Self-Contained Pulse Width Modulation

(PWM) Function

CC

NC

A7

A6

B6

B5

NC

B4

V

SS

A5

A4

A3

C7

C6

On-Chip 24-Bit Watchdog Timer

– EPROM/OTP Device: Standard

Watchdog

NC

18 19 20 21 22 23 24 25 26 27 28

– Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

Flexible Interrupt Handling

– Two S/W Programmable Interrupt Levels

– Global- and Individual-Interrupt Masking

– Programmable Rising- or Falling-Edge

Detect

– Individual Interrupt Vectors

TMS370 Series Compatibility

– Register-to-Register Architecture

– 256 General-Purpose Registers

– 14 Powerful Addressing Modes

– Instructions Upwardly Compatible With

all TMS370 Devices

CMOS/Package/TTL Compatible I/O Pins

– 40-Pin Plastic Dual-In-Line Packages/

32 Bidirectional Pins, 1 Input Pin

– 44-Pin Plastic Leaded Chip Carrier (LCC)

Packages/34 Bidirectional Pins,

1 Input Pin

Workstation/PC-Based Development

System

– C Compiler and C Source Debugger

– Real-Time In-Circuit Emulation

– Extensive Breakpoint/Trace Capability

– Multi-Window User Interface

– Microcontroller Programmer

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

Pin Descriptions

PINS

TYPE†

DESCRIPTION

PDIP

(40)

LCC

(44)

NAME

A0

A1

A2

A3

A4

A5

A6

A7

18

17

16

15

14

13

12

11

20

19

18

17

16

15

13

12

I / O

Port A is a general-purpose bidirectional I/O port.

B0

B1

B2

B3

B4

B5

B6

B7

38

37

36

35

28

29

30

31

43

42

41

40

32

34

35

36

I / O

Port B is a general-purpose bidirectional I/O port.

C0

C1

C2

C3

C4

C5

C6

C7

39

40

1

2

3

4

—

44

1

2

3

4

5

30

31

I / O

Port C is a general-purpose bidirectional I/O port.

D3

D4

D5

D6

D7

21

20

23

22

19

23

22

25

24

21

I / O

Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.

INT1

INT2

INT3

6

7

8

7

8

9

I

External (non-maskable or maskable) interrupt/general-purpose input pin

External maskable interrupt input/general-purpose bidirectional pin

I / O

T1IC/CR

T1PWM

T1EVT

26

25

24

28

27

26

Timer1 input capture/counter reset input pin /general-purpose bidirectional pin

Timer1 PWM output pin/general-purpose bidirectional pin

Timer1 external event input pin/general-purpose bidirectional pin

I / O

System reset bidirectional pin: as input pin, RESET initializes the microcontroller; as

open-drain output, RESET indicates that an internal failure was detected by the watchdog or

oscillator fault circuit.

RESET

5

6

I / O

I

Mode control pin; enables EEPROM write-protection override (WPO) mode, also EPROM

MC

34

39

V

PP

XTAL2/CLKIN

XTAL1

33

32

38

37

I

O

Internal oscillator crystal input/external clock source input

Internal oscillator output for crystal

V

10

27

10

14

Positive supply voltage

CC

Ground reference for digital logic

SS

11, 29,

33

NC

9

These pins have no connection to the internal die.

†

I = input, O = output

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

functional block diagram

XTAL2/

CLKIN

INT1

INT2

INT3

XTAL1

MC

RESET

Clock Options:

Divide-By-4 or

Divide-By-1 (PLL)

System

Control

Interrupts

RAM

128 or 256 Bytes

CPU

Program Memory

ROM: 4K Bytes

EPROM: 16K Bytes

Data EEPROM

0 or 256 Bytes

T1IC/CR

Timer 1

T1EVT

T1PWM

Watchdog

V

CC

†

Port A

8

Port B

Port C

Port D

V

SS

8

8/6

5

†

For the 40-pin devices, there are only six pins for port C.

description

The TMS370C080, TMS370C380, TMS370C686, and SE370C686 devices are members of the TMS370 family

of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx8x refers to these devices.

The TMS370 family provides cost-effective real-time system control through integration of advanced

peripheral-function modules and various on-chip memory configurations.

The TMS370Cx8x family of devices is implemented using high-performance silicon-gate CMOS EPROM and

EEPROMtechnologies. Low-operatingpower, wideoperatingtemperaturerange, andnoiseimmunityofCMOS

technology coupled with the high performance and extensive on-chip peripheral functions make the

TMS370Cx8x devices attractive for system designs for automotive electronics, industrial motors, computer

peripheral controls, telecommunications, and consumer applications.

All TMS370Cx8x devices contain the following on-chip peripheral modules:

One 24-bit general-purpose watchdog timer

One 16-bit general-purpose timer with an 8-bit prescaler

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx8x devices.

Table 1. Memory Configurations

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

PACKAGES

44-PIN PLCC/CLCC,

OR 40-PIN PDIP

DEVICE

ROM

4K

EPROM

RAM

EEPROM

TMS370C080

TMS370C380A

TMS370C686A

—

128

256

—

N – PDIP

FN – PLCC

FZ – CLCC

4K

—

16K

—

†

SE370C686A

—

†

System evaluators and development are for use only in prototype environment and their reliability has not been characterized.

The suffix letter (A) appended to the device names shown in the device column of Table 1 and Table 2 indicates

the configuration of the device. ROM or EPROM devices have different configurations as indicated in Table 2.

ROM devices with the suffix letter A are configured through a programmable contact during manufacture. For

a detailed description of the differences between the TMS370C080 and TMS370Cx8xA contact options (as

indicated by the suffix letter nomenclature), refer to Appendix A of the TMS370 Microcontroller Family User’s

Guide (literature number SPNU127).

For a detailed description of the differences between the TMS370C080 and the TMS370Cx8xA contact options

(asindicatedbythesuffixletternomenclature), refertoAppendixAoftheTMS370MicrocontrollerFamilyUser’s

Guide (literature number SPNU127).

Table 2. Suffix Letter Configuration

‡

DEVICE

WATCHDOG TIMER

Standard

Hard

CLOCK

LOW-POWER MODE

EPROM A

Divide-by-4 (Standard oscillator)

Enabled

ROM A

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

Simple

ROM without A

Standard

Divide-by-4 (Standard oscillator)

Enabled

‡

Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering.

The 4K bytes of mask-programmable ROM in the associated TMS370C380 device is replaced in the

TMS370C686 with 16K bytes of EPROM. All other on-chip peripherals are identical. The one-time

programmable (OTP) (TMS370C686) device and reprogrammable (SE370C686) device are available. The

4K-byte (TMS370C080) mask-programmable ROM device relies on the 68-pin (TMS370C758) development

devices and a converter socket (part # TMDS37788OTP) for prototyping and programming purposes.

TMS370C686 OTP devices are available in plastic packages. This microcontroller is effective to use for

immediate production updates for other members of the TMS370Cx8x family or for low-volume production runs

when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C686 has a windowed ceramic package to allow reprogramming of the program EPROM memory

during the development/prototyping phase of design. The SE370C686 devices allow quick updates to

breadboards and prototype systems while iterating initial designs.

The TMS370Cx8x family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In

the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode,

all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both

low-power modes.

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

The TMS370Cx8x features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx8x family is fully

instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller

family.

The TMS370Cx8x family provides the system designer with economical, efficient solutions to real-time control

applications. The TMS370 family compact development tool (CDT ) solves the challenge of efficiently

developing the software and hardware required to design the TMS370Cx8x into an ever-increasing number of

complex applications. The application source code can be written in assembly and C languages, and the output

code can be generated by the linker. The TMS370 family CDT development tool communicates through a

standard RS-232-C interface with an existing personal computer. This allows the designer to use familiar

personal computer editors and software utilities. Precise real-time, in-circuit emulation and extensive symbolic

debug and analysis tools ensure efficient software and hardware implementation as well as reducing the

time-to-market cycle.

The TMS370Cx8x family together with the TMS370 family CDT370, software tools, the SE370C686 and

SE370C758 (FZ package) reprogrammable devices, comprehensive product documentation, and customer

support provide a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU on the TMS370Cx8x device is the high-performance 8-bit TMS370 CPU module. The ’x8x implements

an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The

complete ’x8x instruction map is shown in Table 15 in the TMS370Cx8x instruction set overview section.

The ’370Cx8x CPU architecture provides the following components:

CPU registers:

–

A stack pointer that points to the last entry in the memory stack

A status register that monitors the operation of the instructions and contains the global interrupt-enable

bits

–

A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes:

–

128- or 256-byte general-purpose RAM that can be used for data memory storage, program

instructions, general purpose register, or the stack

A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off

conditions

4K-byte ROM or 16K-byte EPROM program memory

CDT is a trademark of Texas Instruments Incorporated.

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

Figure 1 illustrates the CPU registers and memory blocks.

Program Counter

15

0

Legend:

Stack Pointer (SP)

7

0

C=Carry

N=Negative

Status Register (ST)

Z=Zero

C

7

N

6

Z

5

V

4

IE2 IE1

V=Overflow

IE2=Level 2 Interrupt Enable

IE1=Level 1 Interrupt Enable

3

2

1

0

RAM (Includes up to 256-Byte Registers File)

0000h

R0(A)

R1(B)

128-Byte RAM (0000h–007Fh)

256-Byte RAM (0000h–00FFh)

007Fh

0080h

0001h

0002h

0003h

00FFh

0100h

OFFFh

1000h

104Fh

1050h

1EFFh

1F00h

1FFFh

2000h

†

Reserved

R2

R3

Peripheral File

†

Reserved

256-Byte Data EEPROM

‡

Not Available

3FFFh

4000h

R127

007Fh

16K-Byte EPROM (4000h–7FFFh)

4K-Byte ROM (7000h–7FFFh)

6FFFh

7000h

7FBFh

7FC0h

Interrupts and Reset Vectors;

Trap Vectors

R255

00FFh

7FFFh

†

‡

Reserved means the address space is reserved for future expansion.

Not available means the address space is not accessible.

Figure 1. Programmer’s Model

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. Typically, the stack

isusedtostorethereturnaddressonsubroutinecallsaswellasthestatusregister(ST)contentsduringinterrupt

sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed

onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the

on-chip RAM.

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

status register

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits.

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional-jump instructions) use the status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

The ST, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

7

C

6

N

5

Z

4

V

3

2

1

0

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists

of two 8-bit registers in the CPU: the program counter high (PCH), and the program counter low (PCL). These

registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the

PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the

contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the

contents of the reset vector.

Program Counter (PC)

Memory

PCH

60

PCL

00

0000h

60

00

7FFEh

7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx8x architecture is based on the Von Neuman architecture, in which the program memory and

data memory share a common address space. All peripheral input/output is memory-mapped in this same

common address space. As shown in Figure 3, the TMS370Cx8x provides memory-mapped RAM, ROM, data

EEPROM, I/O pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all I/O port control, peripheral status and control, EEPROM, EPROM, and

system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to

10FFh and is divided logically into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

TMS370Cx8x CPU (continued)

assigned to a separate frame through which peripheral control and data information is passed. The

TMS370Cx8x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 4,

addresses 1010h through 104Fh.

Peripheral File Control Registers

†

1000h – 100Fh

1010h – 101Fh

1020h – 102Fh

Reserved

0000h

System Control

Digital Port Control

Reserved

128-Byte RAM

(Register File/Stack)

007Fh

0080h

256-Byte RAM

1030h – 103Fh

1040h – 104Fh

(Register File/Stack)

00FFh

0100h

0FFFh

1000h

†

Timer 1

Reserved

Peripheral Control

Peripheral File

104Fh

1050h

†

Reserved

1EFFh

1F00h

256-Byte Data EEPROM

1FFFh

2000h

Vectors

‡

Not Available

Trap 15–0

7FC0h – 7FDFh

7FE0h – 7FF3h

7FF4h – 7FF5h

3FFFh

4000h

Reserved

Timer 1

16K-Byte EPROM

(4000h - 7FFFh)

†

6FFFh

7000h

Reserved

7FF6h – 7FF7h

7FF8h – 7FF9h

7FFAh – 7FFBh

7FFCh – 7FFDh

7FFEh – 7FFFh

4K-Byte ROM

(7000h - 7FFFh)

Interrupt 3

Interrupt 2

Interrupt 1

Reset

7FBFh

7FC0h

7FFFh

8000h

Interrupts and Reset Vectors;

Trap Vectors

‡

Not Available

FFFFh

†

‡

Reserved means that the address space is reserved for future expansion, means the address space is not accessible.

Not available means that the address space is not accessible.

Figure 3. TMS370Cx8x Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program

memory, or the stack instructions. The TMS370C080 and TMS370C380 contain 128 bytes of internal RAM

memory mapped beginning at location 0000h (R0) and continuing through location 007Fh (R127), which is

shown in Table 4 along with ’x86 devices.

Table 4. RAM Memory Map

’x80

’x86

RAM size

128 bytes

256 bytes

Memory mapped

0000h–007Fh

0000h–00FFh

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly

use register A or B; for example, the instruction load SP (LDSP) assumes that the value to be loaded into the

stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

peripheral file (PF)

The TMS370Cx8x control registers contain all the registers necessary to operate the system and peripheral

modules on the device. The instruction set includes some instructions that access the PF directly. These

instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal

designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at

address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 5

shows the TMS370Cx8x PF address map.

Table 5. TMS370Cx8x Peripheral File Address Map

PERIPHERAL FILE

ADDRESS RANGE

DESCRIPTION

DESIGNATOR

P000–P00F

P010–P01F

P020–P02F

P030–P03F

P040–P04F

P050–P0FF

1000h–100Fh

1010h–101Fh

1020h–102Fh

1030h–103Fh

1040h–104Fh

1050h–10FFh

Reserved

System and EPROM/EEPROM control registers

Digital I/O port control registers

Reserved

Timer 1 registers

Reserved

data EEPROM

The TMS370C080 device, containing 256 bytes of data EEPROM, has a memory mapped beginning at location

1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data

EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm

examples are available in the TMS370 Family User’s Guide (literature number SPNU127) or the

TMS370FamilyDataManual(literaturenumberSPNS014B). ThedataEEPROMfeaturesincludethefollowing:

Programming:

–

Bit-, byte-, and block-write/erase modes

Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.

Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A. See Table 6.

–

In-circuit programming capability. There is no need to remove the device to program.

Write-protection. Writes to the data EEPROM are disabled during the following conditions.

–

Reset. All programming of the data EEPROM module is halted.

Write-protection active. There is one write-protect bit per 32-byte EEPROM block.

Low-power mode operation

Write-protection can be overridden by applying 12 V to MC.

Table 6. Data EEPROM and PROGRAM EPROM Control Registers Memory Map

ADDRESS

P01A

SYMBOL

DEECTL

—

NAME

Data EEPROM Control Register

Reserved

P01B

P01C

EPCTL

Program EPROM Control Register

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

†

program EPROM

The TMS370C686 device contains 16K bytes of EPROM memory, mapped beginning at location 4000h and

continuing through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical

to reading other internal memory. During programming, the EPROM is controlled by the EPROM control register

(EPCTL). The program EPROM module features include:

Programming

–

In-circuit programming capability if V is applied to MC

PP

Control register EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01C as shown in Table 6.

Write-protection writes to the program EPROM are disabled under the following conditions

–

Reset all programming to the EPROM module is halted

Low-power modes

13 V not applied to MC

†

program ROM

The program ROM consists of 4K bytes of mask-programmable read-only memory. The program ROM is used

for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device

fabrication.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx8x CPU-based device.

There are up to three different actions that can cause the system to reset the device. Two of these actions are

generated internally, while one (RESET pin) is controlled externally. These actions are as follows:

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key

register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 User’s

Guide (literature number SPNU127) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.

See the TMS370 User’s Guide (literature number SPNU127) for more information.

External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x8x device to reset external system components. Additionally, if a cold start (V

is off

CC

for several hundred milliseconds) condition or oscillator failure occurs, or the RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag

(COLD START, SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 7 depicts the reset sources.

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments Incorporated, and 7FF4h through 7FF5h along with 7FF8h

through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between

addresses 7FC0h and 7FDFh.

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system reset (continued)

Table 7. Reset Sources

REGISTER

SCCR0

ADDRESS

1010h

PF

BIT NO.

CONTROL BIT

COLD START

SOURCE OF RESET

Cold (power-up)

P010

P04A

7

4

5

SCCR0

1010h

OSC FLT FLAG

Oscillator out of range

Watchdog timer timeout

T1CTL2

104Ah

WD OVRFL INT FLAG

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Register A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode-fetch from the address pointed to the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control

register bits are initialized to their reset state.

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interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure

incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of

the ST.

EXT INT 3

INT 3

EXT INT 2

TIMER1

INT 2

Overflow

INT3 PRI

Compare1

Ext Edge

INT2 PRI

Compare2

Input Capture1

Watchdog

EXT INT1

CPU

INT1

NMI

T1 PRI

Priority

Logic

INT1 PRI

STATUS REG

IE1

Level 1 INT

Level 2 INT

IE2

Enable

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is selectively configured on either the high- or

low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx8x has four hardware-system interrupts (plus RESET) as shown in Table 8. Each system

interrupt has a dedicated vector located in program memory through which control is passed to the interrupt

service routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are

individually maskable by local interrupt-enable control bits in the associated peripheral file. Each interrupt

source FLAG bit is individually readable for software polling or to determine which interrupt source generated

the associated system interrupt.

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interrupts (continued)

One of the system interrupts is generated by on-chip peripheral functions, and three external interrupts are

supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3

control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input

polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as

either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked

by the individual or global enable mask bits. The INT1 NMI bit is protected during non-privileged operation. It,

therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,

external interrupts INT2 and INT3 can be software-configured as general-purpose input/output pins if the

interrupt function is not required (INT1 can be similarly configured as an input pin).

Table 8. Hardware System Interrupts

SYSTEM

INTERRUPT

VECTOR

ADDRESS

†

INTERRUPT SOURCE

External RESET

Watchdog Overflow

Oscillator Fault Detect

INTERRUPT FLAG

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

PRIORITY

‡

RESET

7FFEh, 7FFFh

1

‡

External INT1

External INT2

External INT3

INT1 FLAG

INT2 FLAG

INT3 FLAG

INT1

INT2

INT3

7FFCh, 7FFDh

7FFAh, 7FFBh

7FF8h, 7FF9h

2

3

4

Timer 1 Overflow

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC1 INT FLAG

WD OVRFL INT FLAG

Timer 1 Compare 1

Timer 1 Compare 2

Timer 1 External Edge

Timer 1 Input Capture 1

Watchdog Overflow

§

T1INT

7FF4h, 7FF5h

5

†

Relative priority within an interrupt level

‡

§

Release microcontroller from STANDBY and HALT low-power modes

Release microcontroller from STANDBY low-power mode

privileged operation and EEPROM write-protection override

The TMS370Cx8x family is designed with significant flexibility to enable the designer to software-configure the

system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of

operation ensures the integrity of the system configuration once it is defined for an application. Following a

hardware reset, the TMS370Cx8x operates in the privileged mode, where all peripheral file registers have

unrestricted read/write access, and the application program configures the system during the initialization

sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is

set to 1 to enter the nonprivileged mode, thus disabling write operations to specific configuration-control bits

within the PF. Table 9 displays the system-configuration bits, which are write-protected during the nonprivileged

mode and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write-protection override (continued)

Table 9. Privilege Bits

†

REGISTER

CONTROL BIT

PF AUTO WAIT

NAME

LOCATION

P010.5

P010.6

SCCRO

OSC POWER

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR1

SCCR2

T1PRI

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN/IDLE

HALT/STANDBY

P04F.6

P04F.7

T1 PRIORITY

T1 STEST

†

The privilege bits are shown in a bold typeface in the peripheral file

frame 1 section.

The WPO mode provides an external hardware method of overriding the write-protection registers (WPRs) of

data EEPROM on the TMS370C080. WPO mode is entered by applying a 12-V input to the MC pin after the

RESET pin input goes high (logic 1). The high voltage on the MC pin during the WPO mode is not the

programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are

generated on-chip. The WPO mode provides hardware-system-level capability to modify the content of the data

EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC

pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx8x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time when the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The

HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, and Timer 1 remain active. System processing is suspended until a

qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected.

In the HALT mode (HALT/STANDBY = 1), the TMS370Cx8x is placed in its lowest power-consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, or INT3) is

detected. The power-down mode-selection bits are summarized in Table 10.

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low-power and IDLE modes (continued)

Table 10. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

MODE SELECTED

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

1

0

1

STANDBY

HALT

1

0

†

X

IDLE

†

Don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6-7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method for always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This

means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (SP, PC, and ST), I/O pin direction and output data, and status registers of all on-chip peripheral

functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking

of the WD timer is inhibited.

clock modules

The ’x8x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and

divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the

manufacturing process of a TMS370 microcontroller. The ’x8x masked ROM devices offer both options to meet

system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’686A

EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system

clock (SYSCLK) frequency, whereas the divide-by-4 option produces a SYSCLK which is one-fourth of the

frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator

is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased

internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. These are formulated

as follows:

external resonator frequency

4

CLKIN

4

Divide-by-4 option : SYSCLK

Divide-by-1 option : SYSCLK

external resonator frequency

4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of

low-speed resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators.

The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a

steeper decay of emissions produced by the oscillator.

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system configuration registers

Table 11 contains system-configuration, control functions, and registers for controlling EEPROM programming.

The privileged bits are shown in bold typeface in shaded areas.

Table 11. Peripheral File Frame 1: System-Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

—

SCCR0

AUTO

WAIT

DISABLE

MEMORY

DISABLE

P011

—

SCCR1

SCCR2

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

P012

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT3

FLAG

INT3

PIN DATA

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

P01A

P01B

P01C

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTL

P01D

P01E

P01F

Reserved

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digital port-control registers

Peripheralfileframe2containsthedigitalI/Opinconfigurationandcontrolregisters. Table 12 shows thespecific

addresses, registers, and control bits within this peripheral file frame. Table 13 shows the port-configuration

register setup.

Table 12. Peripheral File Frame 2: Digital Port-Control Registers

PF

P020

P021

P022

P023

P024

P025

P026

P027

P028

P029

P02A

P02B

P02C

P02D

P02E

P02F

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

Reserved

BIT 2

BIT 1

BIT 0

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2 (must be 0)

Port A Data

Port A Direction

Reserved

BPORT1

BPORT2

BDATA

BDIR

Port B Control Register 2 (must be 0)

Port B Data

Port B Direction

Reserved

CPORT1

CPORT2

CDATA

CDIR

Port C Control Register 2 (must be 0)

Port C Data

Port C Direction

Port D Control Register 1 (must be 0)

—

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 13. Port-Configuration Register Setup

abcd

00q1

abcd

00y0

PORT

A

B

C

D

0 – 7

3 – 7

Data Out q

Data In y

a = Port x Control Register 1

b = Port x Control Register 2

c = Data

d = Direction

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TMS370Cx8x

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programmable timer 1

The programmable Timer 1 (T1) module of the TMS370Cx8x provides the designer with the enhanced timer

resources required to perform real-time system control. The T1 module contains the general-purpose timer and

the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD timer, allow program selection of input

clock sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and

compare) for special timer function control. The Timer 1 module includes three external device pins that can

be used for multiple counter functions (operation-mode dependent), or used as general-purpose I/O pins. The

T1 module block diagram is shown in Figure 5.

Edge

Select

16-Bit

Capt/Comp

T1IC/CR

Register

16-Bit

Counter

PWM

Toggle

MUX

T1PWM

16

16-Bit

Compare

Register

Interrupt

Logic

8-Bit

Prescaler

T1EVT

Interrupt

Logic

16-Bit

MUX

Watchdog Counter

(Aux. Timer)

Figure 5. Timer 1 Block Diagram

Three Timer1 I/O pins

–

T1IC/CR: T1 input capture / counter-reset input pin, or general-purpose bidirectional I/O pin

T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin

T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin

Two operational modes:

–

Dual-compare mode: Provides PWM signal

Capture/compare mode: Provides input capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either

capture or compare registers.

One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if WD

feature is not needed.

Prescaler/clock sources that determines one of eight clock sources for general-purpose timer

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programmable timer 1 (continued)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T1IC/CR)

Interrupts that can be generated on the occurrence of:

–

A capture

A compare equal

A counter overflow

An external-edge detection

Sixteen T1 module control registers located in the PF frame beginning at address P040

The T1 module control registers are illustrated in Table 14.

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programmable timer 1 (continued)

Table 14. Timer 1 Module Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Mode: Dual-Compare and Capture/Compare

P040 Bit 15

P041 Bit 7

P042 Bit 15

P043 Bit 7

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 7

T1Counter MSbyte

T1 Counter LSbyte

Bit 8 T1CNTR

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Bit 8 T1C

Bit 0

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Watchdog Reset Key

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Bit 0 WDRST

WD OVRFL WD INPUT

WD INPUT

SELECT1

WD INPUT

SELECT0

T1 INPUT

SELECT2

T1 INPUT

SELECT1

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

TAP SEL

SELECT2

WD OVRFL WD OVRFL WD OVRFL T1 OVRFL

T1 OVRFL

INT FLAG

T1

—

†

RST ENA

INT ENA

INT FLAG

INT ENA

—

SW RESET

Mode: Dual-Compare

T1EDGE

T1C2

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

MODE=0

OUT ENA

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

—

MODE = 1

OUT ENA

Mode: Dual-Compare and Capture/Compare

T1EVT

DATA IN

T1EVT

DATA DIR

P04D

P04E

—

T1PC1

T1PC2

T1PRI

DATA OUT FUNCTION

T1IC/CR T1IC/CR

DATA OUT FUNCTION

T1PWM

DATA IN

T1PWM

DATA OUT FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA DIR

T1

P04F T1 STEST

—

PRIORITY

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2

bits are ignored.

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programmable timer 1 (continued)

Figure 6 shows the Timer 1 capture/compare mode block diagram. The annotations on the diagram identify the

register and the bit(s) in the PF. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2

register.

T1CC.15-0

16-Bit

LSB

Capt/Comp

T1C1

MSB

Prescale

Clock

Source

Register

OUT ENA

T1PC2.7-4

T1PWM

T1CTL4.6

T1CNTR.15–0

LSB

MSB

16-Bit

Counter

16

T1 PRIORITY

0

1

T1C1 INT FLAG

T1CTL3.5

T1PRI.6

Level 1 Int

Level 2 Int

Compare=

Reset

T1CTL3.0

T1C.15-0

T1 SW

RESET

T1C1 INT ENA

16-Bit

LSB

T1C1

RST ENA

Compare

Register

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL4.4

T1CTL2.4

T1 OVRFL INT ENA

T1PC2.3-0

T1IC/CR

T1EDGE DET ENA

T1EDGE INT FLAG

T1CTL3.7

Edge

Select

T1CTL4.0

T1CTL3.2

T1EDGE INT ENA

T1CTL4.2

T1EDGE POLARITY

Figure 6. Capture/Compare Mode

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programmable timer 1 (continued)

Figure 7 shows the Timer 1 dual-compare mode block diagram. The annotations on the diagram identify the

register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in

the T1CTL2 register.

T1CC.15-0

16-Bit

Capt/Comp

Register

T1C2 INT FLAG

T1CTL3.6

LSB

Prescaler

Clock

Source

MSB

Output

Enable

T1CTL3.1

T1C2 INT ENA

T1CTL4.5

Compare=

T1CNTR.15-0

T1PC2.7-4

T1PWM

T1C2 OUT ENA

T1CTL4.6

LSB

MSB

16-Bit

Counter

16

T1C1 INT FLAG

T1CTL3.5

T1CTL3.0

Reset

Compare=

T1C1 OUT ENA

T1CTL4.3

T1C1

RST ENA

T1C.15-0

T1 SW

RESET

T1C1 INT ENA

16-Bit

Compare

Register

LSB

T1CTL4.4

T1CR OUT ENA

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL2.4

T1 OVRFL INT ENA

T1CTL4.1

T1CR

RST ENA

T1PC2.3-0

T1IC/CR

Edge

Select

T1 PRIORITY

T1PRI.6

0

1

T1CTL4.0

T1EDGE INT FLAG

T1CTL3.7

Level 1 Int

Level 2 Int

T1EDGE DET ENA

T1CTL4.2

T1CTL3.2

T1EDGE INT ENA

T1EDGE POLARITY

Figure 7. Dual-Compare Mode

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TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

programmable timer 1 (continued)

The TMS370Cx8x device includes a 24-bit WD timer, contained in the T1 module, which can be programmed

as an event counter, pulse accumulator, or interval timer if the watchdog function is not used. The WD function

is to monitor software and hardware operation and to implement a system reset when the WD counter is not

properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The WD can be

configured as one of three mask options as follows: standard watchdog, hard WD, or simple counter.

Standard watchdog configuration (see Figure 8) for EPROM and mask-ROM devices:

–

Watchdog mode

–

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

AWDresetkey(WDRST)registerisusedtoclearthewatchdogcounter(WDCNTR)whenacorrect

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

Awatchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

–

Non-watchdog mode

–

Watchdog timer can be configured as an event counter, pulse accumulator or an interval timer

WDCNTR.15-0

WD OVRFL

INT FLAG

T1CTL2.6

16-Bit

Watchdog Counter

T1CTL2.5

Interrupt

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL1.7

T1CTL2.7

WD OVRFL

TAP SEL

System Reset

WD OVRFL

RST ENA

Watchdog-Reset Key

WDRST.7-0

Figure 8. Standard Watchdog

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8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

programmable timer 1 (continued)

Hard watchdog configuration (see Figure 9) for mask-ROM devices:

–

Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the WDRST or if the counter overflows.

A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system

reset.

–

Automatic activation of the WD timer upon power-up reset

INT1 is enabled as a nonmaskable interrupt during low-power modes.

WDCNTR.15-0

WD OVRFL

INT FLAG

16-Bit

Watchdog Counter

T1CTL2.5

Reset

Clock

Prescaler

T1CTL1.7

System Reset

WD OVRFL

TAP SEL

Watchdog-Reset Key

WDRST.7-0

Figure 9. Hard Watchdog

24

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

programmable timer 1 (continued)

Simple counter configuration (see Figure 10) for mask-ROM devices only

–

Simple counter can be configured as an event counter, pulse accumulator or an internal timer.

WDCNTR.15-0

WD OVFL

16-Bit

Watchdog Counter

T1CTL2.6

INT FLAG

Interrupt

T1CTL2.5

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL1.7

WD OVRFL

TAP SEL

Watchdog-Reset Key

WDRST.7-0

Figure 10. Simple Counter

instruction set overview

Table 15 provides an opcode-to-instruction cross reference of all 73 instructions and 274 opcodes of the

‘370Cx8x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the

opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instruction

of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes

in eight SYSCLK cycles.

25

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, CDT and an

EEPROM/UVEPROM programmer.

Assembler/linker (Part No. TMDS3740850–02 for PC)

–

Includes extensive macro capability

Provides high-speed operation

Includes format conversion utilities for popular formats

ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3

or Sun-4 )

–

Generates assembly code for the TMS370 that can be inspected easily

Improves code execution speed and reduces code size with optional optimizer pass

Enables direct reference to the TMS370’s port registers by using a naming convention

Provides flexibility in specifying the storage for data objects

Interfaces C functions and assembly functions easily

Includes assembler and linker

CDT370 (Compact Development Tool) real-time in-circuit emulation

–

Base (Part Number EDSCDT370 – for PC, requires cable)

–

Cable for 40-pin DIP (Part No. EDSTRG40DIL8X)

Cable for 44-pin PLCC (Part No. EDSTRG44PLCC8X)

–

Provides EEPROM and EPROM programming support

Allows inspection and modification of memory locations

Includes compatibility to upload/download program and data memory

Executes programs and software routines

Includes 1024-sample trace buffer

Includes single-step executable instructions

Uses software breakpoints to halt program execution at selected address

Provides timers for analyzing total and average time in routines

Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and

to trace display

Microcontroller programmer

–

Base (Part No. TMDS3760500A – for PC, requires programmer head)

–

Single unit head for 44-pin PLCC (Part No. TMDS3780510A)

Single unit head for 40-pin DIP (Part No. TMDS3780511A)

PC-based, window/function-key-orienteduserinterfaceforeaseofuseandrapidlearningenvironment

Converter Socket (Part No. TMDS37788OTP)

HP700 is a trademark of Hewlett-Packard Company.

Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated.

28

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

device numbering conventions

Figure 11 illustrates the numbering and symbol nomenclature for the TMS370Cx8x family.

TMS 370 C

6

8

6

A FN L

Prefix:

TMS

SE

=

Standard prefix for fully qualified devices

System evaluator (window EPROM) that is used for

prototyping purpose.

Family:

370

C

=

TMS370 8-Bit Microcontroller Family

CMOS

Technology:

Program Memory Types:

0

3

6

=

Mask ROM

Mask ROM, No Data EEPROM

EPROM, No Data EEPROM

Device Type:

Memory Size:

8

=

’x8x device containing a Timer1 module

0

6

=

4K bytes

16K bytes

Temperature Ranges:

Packages:

A

L

T

=

–40°C to 85°C

0°C to 70°C

–40°C to 105°C

FN

FZ

N

=

Plastic Leaded Chip Carrier

Ceramic Leaded Chip Carrier

Plastic Dual-In-Line

ROM and EPROM Option: A

=

For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog

– A hard watchdog

– A simple watchdog

The clock can be either:

– Divide-by-4 clock

– Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled

– Disabled

Without A = For ROM device, a standard watchdog,

a divide-by-4 clock, and low-power modes are enabled

A = For EPROM device, a standard watchdog,

a divide-by-4 clock, and low-power modes are enabled

Figure 11. TMS370Cx8x Family Nomenclature

29

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

device part numbers

Table 16 provides all of the ’x8x devices available. The device part number nomenclature is designed to assist

ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and

watchdog timer options desired. Each device can have only one of the three possible watchdog timer options

and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices.

Table 16. Device Part Numbers

DEVICES PART NUMBERS

FOR 44 PINS (LCC)

DEVICES PART NUMBERS

FOR 40 PINS (PDIP)

TMS370C380AFNA

TMS370C380AFNL

TMS370C380AFNT

TMS370C080NA

TMS370C080NL

TMS370C080NT

TMS370C686AFNT

—

†

SE370C686AFZT

†

System evaluators are for use in prototype environment and their

reliability has not been characterized.

30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

new code release form

Figure 12 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

DATE:

TMS370 MICROCONTROLLER PRODUCTS

To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name:

Street Address:

City:

Contact Mr./Ms.:

Phone: (

)

Ext.:

State

Zip

Customer Purchase Order Number:

Customer Print Number *Yes:

No:

*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM

code processing starts.

#

Customer Part Number:

Customer Application:

(Std. spec to be followed)

TMS370 Device:

TI Customer ROM Number:

(provided by Texas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLATOR FREQUENCY

Low Power Modes

[] Enabled

[] Disabled

Watchdog counter

[] Standard

[] Hard Enabled

[] Simple Counter

Clock Type

[] Standard (/4)

[] PLL (/1)

MIN

TYP

MAX

[] External Drive (CLKIN)

[] Crystal

[] Ceramic Resonator

NOTE:

Non ’A’ version ROM devices of the TMS370 microcontrollers will have the

“Low-powermodesEnabled”, “Divide-by-4”Clock, and“Standard”Watchdog

options. See the TMS370 Family User’s Guide (literature number SPNU127)

or the TMS370 Family Data Manual (literature number SPNS014B).

[] Supply Voltage MIN:

(std range: 4.5V to 5.5V)

MAX:

TEMPERATURE RANGE

PACKAGE TYPE

[] ’L’:

[] ’A’:

[] ’T’:

0° to 70°C (standard)

–40° to 85°C

–40° to 105°C

[] ’N’ 28-pin PDIP

[] “FN” 28-pin PLCC

[] “N” 40-pin PDIP

[] “FN” 44-pin PLCC

[] “FN” 68-pin PLCC

[] “NM” 64-pin PSDIP

[] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZATION

BUS EXPANSION

[] TI standard symbolization

[] YES

[] NO

[] TI standard w/customer part number

[] Customer symbolization

(per attached spec, subject to approval)

NON-STANDARD SPECIFICATIONS:

ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the

satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard

TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the

TI part number.

RELEASE AUTHORIZATION:

This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification

code is approved by the customer.

1. Customer:

Date:

2. TI: Field Sales:

Marketing:

Prod. Eng.:

Proto. Release:

Figure 12. Sample New Code Release Form

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

Table 17 is a collection of all the peripheral file frames used in the ’Cx8x (provided for a quick reference).

Table 17. Peripheral File Frame Compilation

System Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

—

BIT 0

REG

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

SCCR0

AUTO

WAIT

DISABLE

MEMORY

DISABLE

P011

P012

—

SCCR1

SCCR2

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT3

FLAG

INT3

PIN DATA

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

P01A

P01B

P01C

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTL

P01D

P01E

P01F

Reserved

Digital Port Control Registers

P020

P021

P022

P023

P024

P025

P026

P027

P028

P029

P02A

P02B

P02C

P02D

P02E

P02F

Reserved

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2 (must be 0)

Port A Data

Port A Direction

Reserved

BPORT1

BPORT2

BDATA

BDIR

Port B Control Register 2 (must be 0)

Port B Data

Port B Direction

Reserved

CPORT1

CPORT2

CDATA

CDIR

Port C Control Register 2 (must be 0)

Port C Data

Port C Direction

Port D Control Register 1 (must be 0)

—

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

Timer1 Module Register Memory Map

Modes: Dual-Compare and Capture/Compare

P040

P041

T1CNTR

Bit 15

Bit 7

T1Counter MSbyte

T1 Counter LSbyte

Bit 8

Bit 0

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

Table 17. Peripheral File Frame Compilation (Continued)

PF

BIT 7

Modes: Dual-Compare and Capture/Compare (Continued)

Compare Register MSbyte

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P042 Bit 15

P043 Bit 7

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 7

Bit 8 T1C

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Bit 0

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Watchdog Reset Key

Bit 0 WDRST

WD OVRFL

TAP SEL

WD INPUT

SELECT2

WD INPUT

SELECT1

WD INPUT

SELECT0

T1 INPUT

SELECT2

T1 INPUT

SELECT1

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

T1

—

†

RST ENA

SW RESET

Mode: Dual-Compare

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

—

T1CTL3

T1CTL4

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

P04C T1 MODE=0

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

—

MODE = 1

OUT ENA

Modes: Dual-Compare and Capture/Compare

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT

DATA DIR

P04D

P04E

P04F

—

T1PC1

T1PC2

T1PRI

T1PWM

DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR DATA

DIR

T1

T1 STEST

—

PRIORITY

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2

bits are ignored.

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range,V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

CC

Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input clamp current, I (V < 0 or V > V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

IK

I

CC)

Output clamp current, I

OK

O

CC

Continuous output current per buffer, I (V = 0 to V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA

O

CC)

Maximum I

current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA

CC

Maximum I current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 170 mA

SS

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

Operating free-air temperature range, T : L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C

T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 105°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Unless otherwise noted, all voltage values are with respect to V

.

SS

2. Electrical characteristics are specified with all output buffers loaded with specified I current. Exceeding the specified I current in

O

any buffer can affect the levels on other buffers.

recommended operating conditions

MIN

4.5

3

NOM

MAX

5.5

UNIT

V

Supply voltage (see Note 1)

5

V

CC

RAM data-retention supply voltage (see Note 3)

All pins except MC

MC, normal operation

5.5

V

SS

0.8

Low-level input voltage

High-level input voltage

V

IL

V

SS

0.3

All pins except MC, XTAL2/CLKIN, and

RESET

2

V

CC

V

IH

XTAL2/CLKIN

0.8 V

0.7 V

V

CC

RESET

V

CC

13

EEPROM write protect override (WPO)

11.7

13

12

MC (mode control) voltage

EPROM programming voltage (V

Microcomputer

L version

)

13.2

13.5

0.3

70

V

MC

PP

V

SS

0

T

A

Operating free-air temperature

A version

– 40

85

°C

T version

105

NOTES: 1. Unless otherwise noted, all voltage values are with respect to V

.

SS

3. RESET must be externally activated when V

CC

or SYSCLK is not within the recommended operating range.

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

Low-level output voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

I

= 1.4 mA

= –50 µA

= –2 mA

0.4

V

OL

OH

0.9 V

CC

High-level output voltage

Input current

V

OH

2.4

0 V < V ≤ 0.3 V

10

I

µA

0.3 V < V ≤ 13 V

650

I

MC

I

See Note 4

50

mA

12 V ≤ V ≤ 13 V

I

I/O pins

0 V ≤ V ≤ V

± 10

µA

mA

µA

I

CC

I

Low-level output current

High-level output current

V

OL

V

OH

V

OH

= 0.4 V

1.4

– 50

– 2

OL

= 0.9 V

= 2.4 V

CC

OH

mA

See Notes 5 and 6

SYSCLK = 5 MHz

30

20

7

45

30

11

Supply current (operating mode)

OSC POWER bit = 0 (see Note 7)

See Notes 5 and 6

SYSCLK = 3 MHz

mA

See Notes 5 and 6

SYSCLK = 0.5 MHz

See Notes 5 and 6

SYSCLK = 5 MHz

10

8

17

11

Supply current (STANDBY mode)

OSC POWER bit = 0 (see Note 8)

See Notes 5 and 6

SYSCLK = 3 MHz

I

CC

See Notes 5 and 6

SYSCLK = 0.5 MHz

2

3.5

8.6

3.0

30

See Notes 5 and 6

SYSCLK = 3 MHz

6

Supply current (STANDBY mode)

OSC POWER bit = 1 (see Note 9)

mA

See Notes 5 and 6

SYSCLK = 0.5 MHz

2

See Note 5

XTAL2/CLKIN < 0.2 V

Supply current (HALT mode)

2

µA

NOTES: 4. Input current I

is a maximum of 50 mA only when you are programming EPROM.

PP

5. Single-chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ V

– 0.2V.

CC

6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current

can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance

in pF).

7. Maximum operating current = 7.6 (SYSCLK) + 7 mA.

8. Maximum standby current = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

9. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, only valid up to 3 MHz SYSCLK).

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

XTAL2/CLKIN

XTAL1

XTAL2/CLKIN

XTAL1

C1

(see Note B)

C2

C3

Crystal/Ceramic

Resonator

(see Note A)

External

Clock Signal

(see Note B)

NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

B. The values of C1 and C2 are typically 15 pF and the value of C3 is typically 50 pF. See the manufacturer’s recommendations for

ceramic resonators.

Figure 13. Recommended Crystal/Clock Connections

Load Voltage

1.2 kΩ

V

O

20 pF

Case 1: V = V

= 2.4 V; Load Voltage = 0 V

= 0.4 V; Load Voltage = 2.1 V

O

OH

OL

Case 2: V = V

O

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

Figure 14. Typical Output Load Circuit (See Note A)

V

CC

V

CC

Pin Data

300 Ω

30 Ω

6 kΩ

Output

Enable

I/O

INT1

20 Ω

GND

Figure 15. Typical Buffer Circuitry

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

AR

B

Array

Byte

CI

XTAL2/CLKIN

SYSCLK

SC

Lowercase subscripts and their meanings are:

c

d

f

cycle time (period)

delay time

fall time

su

v

setup time

valid time

w

pulse duration (width)

r

rise time

The following additional letters are used with these meanings:

H

L

High

Low

Valid

V

All timings are measured between high and low measurement points as indicated in Figure 16 and Figure 17.

0.8 V

V (High)

2 V (High)

CC

0.8 V (Low)

Figure 16. XTAL2/CLKIN Measurement Points

Figure 17. General Measurement Points

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

external clocking requirements for clock divided by 4 (see Note 10 and Figure 18)

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 11)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

30

100

20

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK fall

Crystal operating frequency

ns

d(CIH-SCL)

CLKIN

2

MHz

†

SYSCLK

Internal system clock operating frequency

0.5

†

SYSCLK = CLKIN/4

NOTES: 10. For V and V , refer to recommended operating conditions.

IL IH

11. This pulse may be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

2

3

4

SYSCLK

Figure 18. External Clock Timing for Divide-by-4

external clocking requirements for clock divided by 1 (PLL) (see Note 10 and Figure 19)

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 11)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

30

100

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK rise

Crystal operating frequency

ns

d(CIH-SCH)

CLKIN

2

MHz

‡

SYSCLK

Internal system clock operating frequency

5

‡

SYSCLK = CLKIN/1

NOTES: 10. For V and V , refer to recommended operating conditions.

IL IH

11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

4

2

3

SYSCLK

Figure 19. External Clock Timing for Divide-by-1

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

switching characteristics and timing requirements (see Note 12)

NO.

PARAMETER

MIN

200

MAX

2000

500

UNIT

Divide-by-4

Divide-by-1

5

t

c

Cycle time, SYSCLK (system clock)

ns

6

7

t

Pulse duration, SYSCLK low

Pulse duration, SYSCLK high

0.5 t –20

0.5 t

c

ns

w(SCL)

c

0.5 t

0.5 t + 20

c

w(SCH)

c

NOTE 12: t = system-clock cycle time = 1/SYSCLK

c

5

7

6

SYSCLK

Figure 20. SYSCLK Timing

general purpose output signal switching time requirements

MIN NOM

MAX

UNIT

ns

t

Rise time

Fall time

30

r

ns

f

t

r

t

f

Figure 21. Signal Switching Timing

recommended EEPROM timing requirements for programming

MIN

10

MAX

UNIT

ms

t

Pulse duration, programming signal to ensure valid data is stored (byte mode)

Pulse duration, programming signal to ensure valid data is stored (array mode)

w(PGM)B

20

ms

w(PGM)AR

recommended EPROM operating conditions for programming

MIN NOM

MAX

6

UNIT

V

Supply voltage

4.75

13

5.5

13.2

30

CC

Supply voltage at MC pin

13.5

50

5

V

PP

I

Supply current at MC pin during programming (V

= 13 V)

mA

PP

Divide-by-4

Divide-by-1

0.5

2

SYSCLK

System clock

MHz

5

recommended EPROM timing requirements for programming

MIN NOM

0.40 0.50

MAX

UNIT

t

Pulse duration, programming signal (see Note 13)

3

ms

w(EPGM)

NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

Table 18 is designed to aid the user in referencing a device part number to a mechanical drawing. The table

shows a cross-reference of the device part number to the TMS370 generic package name and the associated

mechanical drawing by drawing number and name.

Table 18. TMS370Cx8x Family Package Type and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

PKG TYPE NO. AND

MECHANICAL NAME

TMS370 GENERIC NAME

DEVICE PART NUMBERS

TMS370C380AFNA

TMS370C380AFNL

TMS370C380AFNT

TMS370C686AFNT

FN – 44 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

FZ – 44 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

SE370C686AFZT

TMS370C080NA

TMS370C080NL

TMS370C080NT

N – 40 pin

(100-mil pin spacing) (PDIP)

PLASTIC DUAL-IN-LINE PACKAGE

N(R-PDIP-T**) PLASTIC DUAL-IN-LINE

PACKAGE

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

A

24

13

0.560 (14,22)

0.520 (13,21)

1

12

0.060 (1,52) TYP

0.200 (5,08) MAX

0.020 (0,51) MIN

0.610 (15,49)

0.590 (14,99)

Seating Plane

0.100 (2,54)

0.125 (3,18) MIN

0.010 (0,25) NOM

0°–15°

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

PINS **

M

24

1.270

28

32

40

48

52

DIM

1.450

1.650

2.090

2.450

2.650

A MAX

(32,26) (36,83) (41,91) (53,09) (62,23) (67,31)

1.230

1.410

1.610

2.040

2.390

2.590

A MIN

(31,24) (35,81) (40,89) (51,82) (60,71) (65,79)

4040053/B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-011

D. Falls within JEDEC MS-015 (32 pin only)

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

J-LEADED CERAMIC CHIP CARRIER

Seating Plane

MECHANICAL DATA

FZ (S-CQCC-J**)

28 LEAD SHOWN

0.040 (1,02)

45°

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

A

B

1

0.120 (3,05)

26

4

25

5

0.050 (1,27)

C

(at Seating

Plane)

A

B

0.032 (0,81)

0.026 (0,66)

0.020 (0,51)

0.014 (0,36)

19

11

18

12

0.025 (0,64) R TYP

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

A

B

C

JEDEC

NO. OF

PINS**

OUTLINE

MIN

MAX

MIN

MAX

MIN

MAX

0.485

0.495

0.430

0.455

0.410

0.430

MO-087AA

MO-087AB

MO-087AC

MO-087AD

28

44

52

68

(12,32)

(12,57)

(10,92)

(11,56)

(10,41)

(10,92)

0.685

0.695

0.630

0.655

0.610

0.630

(17,40)

(17,65)

(16,00)

(16,64)

(15,49)

(16,00)

0.785

0.795

0.730

0.765

0.680

0.740

(19,94)

(20,19)

(18,54)

(19,43)

(17,28)

(18,79)

0.985

0.995

0.930

0.955

0.910

0.930

(25,02)

(25,27)

(23,62)

(24,26)

(23,11)

(23,62)

4040219/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

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型号：	TMS370C380AFNL
厂家：	ETC
描述：	8-Bit Microcontroller 8位微控制器\n 微控制器外围集成电路时钟
文件：	总44页 (文件大小：638K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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