TN83C196KD [ETC]
Microcontroller ; 微控制器\n
| 型号： | TN83C196KD |
| 厂家： | 
ETC |
| 描述： | Microcontroller
|
| 文件： | 总25页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8XC196KD/8XC196KD20
COMMERCIAL CHMOS MICROCONTROLLER
87C196KDÐ32 Kbytes of On-Chip OTPROM
83C196KDÐ32 Kbytes of ROM
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16 MHz and 20 MHz Available
Full Duplex Serial Port
Y
Y
Y
Y
Y
Y
1000 Byte Register RAM
High Speed I/O Subsystem
16-Bit Timer
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
Peripheral Transaction Server
1.4 ms 16 x 16 Multiply (20 MHz)
2.4 ms 32/16 Divide (20 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
16-Bit Up/Down Counter with Capture
3 Pulse-Width-Modulated Outputs
Four 16-Bit Software Timers
8- or 10-Bit A/D Converter with
Sample/Hold
Y
HOLD/HLDA Bus Protocol
I
OTP One-Time Programmable Version
16-Bit Watchdog Timer
I Extended Temperature Available
Dynamically Configurable 8-Bit or
16-Bit Buswidth
The 8XC196KD 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family.
É
The 8XC196KD is an enhanced 80C196KC device with 1000 bytes RAM, 16 MHz operation and an optional
32 Kbytes of ROM/EPROM. Intel’s CHMOS III process provides a high performance processor along with low
power consumption.
The 8XC196KD has a maximum guaranteed frequency of 16 MHz. The 8XC196KD20 has a maximum guaran-
teed frequency of 20 MHz. Unless otherwise noted, all references to the 8XC196KD also refer to the
8XC196KD20.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temp-
erature range of the 0°C to +70°C. With the extended (express) temperature range option, operational charac-
teristics are guaranteed over the temperature range of -40°C to +85°C. Unless otherwise noted, the specifica-
tions are the same for both options.
See the packaging information for extended temperature designators.
*Other brands and names may be claimed as the property of others.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 2 0 0 2
May 2002
Order Number: 272145-004
8XC196KD/8XC196KD20
272145–1
Figure 1. 8XC196KD Block Diagram
87C196KD ENHANCED FEATURE SET
OVER THE 87C196KC
IOC3 (0CH HWIN1 READ/WRITE)
1. The 87C196KD has twice the RAM and twice the
OTPROM space of the 87C196KC.
2. The vertical windowing scheme has been extend-
ed to allow all 1000 bytes of register RAM to be
windowed into the lower register file.
272145–2
NOTE:
*RSVÐReserved bits must be
e
0
Figure 2. 87C196KD New SFR Bit
(CLKOUT Disable)
2
8XC196KD/8XC196KD20
Table 3. 32-Byte Windows
8XC196KD VERTICAL WINDOWING
MAP
Address to
Remap
Device
Series
WSR Contents
Table 1. 128-Byte Windows
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
03E0H
03C0H
03A0H
0380H
0360H
0340H
0320H
0300H
02E0H
02C0H
02A0H
0280H
0260H
0240H
0220H
0200H
01E0H
01C0H
01A0H
0180H
0160H
0140H
0120H
0100H
00E0H
00C0H
00A0H
0080H
0060H
0040H
0020H
0000H
KD
X101 1111B
X101 1110B
X101 1101B
X101 1100B
X101 1011B
X101 1010B
X101 1001B
X101 1000B
X101 0111B
X101 0110B
X101 0101B
X101 0100B
X101 0011B
X101 0010B
X101 0001B
X101 0000B
X100 1111B
X100 1110B
X100 1101B
X100 1100B
X100 1011B
X100 1010B
X100 1001B
X100 1000B
X100 0111B
X100 0110B
X100 0101B
X100 0100B
X100 0011B
X100 0010B
X100 0001B
X100 0000B
5FH
5EH
5DH
5CH
5BH
5AH
59H
58H
57H
56H
55H
54H
53H
52H
51H
50H
4FH
4EH
4DH
4CH
4BH
4AH
49H
48H
47H
46H
45H
44H
43H
42H
41H
40H
Address to
Remap
Device
Series
WSR Contents
KD
e
e
e
e
e
e
e
e
0380H
0300H
0280H
0200H
0180H
0100H
0080H
0000H
KD
X001 0111B
X001 0110B
X001 0101B
X001 0100B
X001 0011B
X001 0010B
X001 0001B
X001 0000B
17H
16H
15H
14H
13H
12H
11H
10H
KD
KD
KD
KD
KD
KD
KD
KC, KD
KC, KD
KC, KD
KC, KD
KD
KD
KD
KD
Window in Lower Register File: 80H–FFH
KD
KD
Table 2. 64-Byte Windows
KD
Address to
Remap
Device
Series
WSR Contents
KD
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
03C0H
0380H
0340H
0300H
02C0H
0280H
0240H
0200H
01C0H
0180H
0140H
0100H
00C0H
0080H
0040H
0000H
KD
X010 1111B
X010 1110B
X010 1101B
X010 1100B
X010 1011B
X010 1010B
X010 1001B
X010 1000B
X010 0111B
X010 0110B
X010 0101B
X010 0100B
X010 0011B
X010 0010B
X010 0001B
X010 0000B
2FH
2EH
2DH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
23H
22H
21H
20H
KD
KD
KD
KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KD
KD
KD
KD
KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
KC, KD
Window in Lower Register File: C0H–FFH
Window in Lower Register File: E0H–FFH
3
8XC196KD/8XC196KD20
Table 5. 8XC196KD Memory Map
PROCESS INFORMATION
Description
Address
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliabili-
ty information is available in Intel’s Components
Quality and Reliability Handbook, Order Number
210997.
External Memory or I/O
0FFFFH
0A000H
Internal ROM/OTPROM or External
Memory (Determined by EA)
9FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
ROM/OTPROM Security Key
203FH
2030H
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
T=Extended temperature -40°C to +85°C
with Intel Standard Burn-in
Reserved. Must Contain 20H
(Note 5)
2019H
EXAMPLE: N87C196KD20
OTPROM, 20 MHz.
is
68-Lead
PLCC
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
CCB
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Lower Interrupt Vectors
2013H
2000H
Figure 3. The 8XC196KD Family Nomenclature
Port 3 and Port 4
1FFFH
1FFEH
Table 4. Thermal Characteristics
Package
External Memory
1FFDH
0400H
i
i
jc
ja
Type
PLCC
QFP
1000 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1, 3)
03FFH
0018H
35 C/W
§
56 C/W
§
68 C/W
13 C/W
§
12 C/W
§
15.5 C/W
0017H
0000H
SQFP
§
§
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
NOTES:
1. Code executed in locations 0000H to 03FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
4
8XC196KD/8XC196KD20
272145–3
Figure 4. 68-Pin PLCC Package
5
8XC196KD/8XC196KD20
272145–4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 5. 80-Pin QFP Package
6
8XC196KD/8XC196KD20
272145–20
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 6. 80-Pin SQFP Package
7
8XC196KD/8XC196KD20
PIN DESCRIPTIONS
Symbol
Name and Function
V
V
V
Main supply voltage (5V).
Digital circuit ground (0V). There are multiple V pins, all of which must be connected.
CC
SS
SS
Reference voltage for the A/D converter (5V). V
is also the supply voltage to the analog
REF
REF
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
.
V
SS
V
Timing pin for the return from powerdown circuit. This pin also supplies the programming
voltage on the EPROM device.
PP
XTAL1
Input of the oscillator inverter and of the internal clock generator.
Output of the oscillator inverter.
XTAL2
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency.
RESET
Reset input and open drain output.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA
Input for memory select (External Access). EA equal high causes memory accesses to
locations 2000H through 9FFFH to be directed to on-chip ROM/EPROM. EA equal low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
READY
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external
writes where an odd byte is being written. BHE/WRH is activated only during external
memory writes.
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. When the external memory is not being used, READY has no
effect.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
8
8XC196KD/8XC196KD20
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Port 0
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1
Port 2
8-bit quasi-bidirectional I/O port.
8-bit multi-functional port. All of its pins are shared with other functions in the 8XC196KD.
Pins 2.6 and 2.7 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD
HLDA
BREQ
Bus Hold input requesting control of the bus.
Bus Hold acknowledge output indicating release of the bus.
Bus Request output activated when the bus controller has a pending external memory
cycle.
PMODE
PACT
Determines the EPROM programming mode.
A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates that ports 3 and 4 contain valid programming address/command
information (input to slave).
PROG
PVER
CPVER
AINC
A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave).
A high signal in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates the byte programmed correctly.
Cummulative Program Output Verification. Pin is high if all locations have programmed
correctly since entering a programming mode.
Auto Increment. Active low input enables the auto increment mode. Auto increment allows
reading or writing sequential EPROM locations without address transactions across the
PBUS for each read or write.
9
8XC196KD/8XC196KD20
ELECTRICAL CHARACTERISTICS
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. It is valid for the devices indicated in
the revision history. The specifications are subject to
change without notice.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55 C to 125 C
b
a
§
§
§
§
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
Voltage On Any Pin to V
SS
(1)
b
a
Except EA and V ÀÀÀÀÀÀÀÀÀÀ 0.5V to 7.0V
PP
Voltage from EA or
b
a
V
to V or ANGND ÀÀÀÀÀÀÀ 0.5V to 13.00V
SS
(2)
PP
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
NOTES:
1. This includes V and EA on ROM or CPU only devices.
PP
2. Power dissipation is based on package heat transfer lim-
itations, not device power consumption.
OPERATING CONDITIONS
Symbol
Description
Ambient Temperature Under Bias Commercial Temp.
Ambient Temperature Under Bias Extended Temp.
Digital Supply Voltage
Min
0
Max
Units
a
T
A
70
C
§
T
A
-40
4.50
4.00
b
+85
5.50
5.50
°C
V
CC
V
V
REF
Analog Supply Voltage
V
(1)
V
a
16
20
ANGND
Analog Ground Voltage
V
0.4
V
0.4
SS
SS
F
OSC
F
OSC
Oscillator Frequency (8XC196KD)
Oscillator Frequency (8XC196KD20)
8
8
MHz
MHz
NOTE:
1. ANGND and V should be nominally at the same potential.
SS
DC CHARACTERISTICS (Over Specified Operating Conditions)
Symbol
Description
Min
Max
0.8
a
Units
Test Conditions
b
V
V
V
V
V
V
Input Low Voltage
0.5
V
V
IL
a
Input High Voltage (Note 1)
Hysteresis on RESET
0.2 V
1.0
V
0.5
IH
CC
CC
e
5.0V
300
mV
V
V
HYS
IH1
IH2
OL
CC
a
a
Input High Voltage on XTAL 1
Input High Voltage on RESET
Output Low Voltage
0.7 V
V
V
0.5
0.5
CC
CC
2.2
V
CC
e
e
e
0.3
0.45
1.5
V
V
V
I
I
I
200 mA
2.8 mA
7 mA
OL
OL
OL
e a
V
V
Output Low Voltage
in RESET on P2.5 (Note 2)
I
0.4 mA
OL1
OH
OL
0.8
V
b
b
b
e b
e b
e b
Output High Voltage
(Standard Outputs) (Note 4)
V
V
V
0.3
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
CC
OH
OH
OH
0.7
1.5
CC
CC
b
b
b
e b
e b
e b
V
Output High Voltage
(Quasi-bidirectional Outputs)
(Note 3)
V
CC
V
CC
V
CC
0.3
0.7
1.5
V
V
V
I
I
I
10 mA
30 mA
60 mA
OH1
OH
OH
OH
10
8XC196KD/8XC196KD20
DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Symbol
Description
Min Typ
Max
Units
Test Conditions
b
e
b
1.5V
CC
I
Logical 1 Output Current in Reset
on P2.0. Do not exceed this or
device may enter test modes.
0.8
mA
V
V
V
OH1
IH
IN
b
e
I
Logical 0 Input Current in Reset
on P2.0. Maximum current that
must be sunk by external device
to ensure test mode entry.
12.0
mA
0.45V
IL2
a
e
I
I
Logical 1 Input Current. Maximum
current that external device must
source to initiate NMI.
200
mA
mA
V
0
2.4V
IH1
IN
k
k
b
g
Input Leakage Current (Std.
Inputs) (Note 5)
10
V
V
V
V
0.3V
LI
IN
IN
CC
k
k
g
I
I
Input Leakage Current (Port 0)
3
mA
mA
0
LI1
REF
b
e
1 to 0 Transition Current (QBD
Pins)
650
V
2.0V
TL
IN
b
e
e
I
I
I
Logical 0 Input Current (QBD Pins)
AD Bus in Reset
70
70
mA
mA
mA
V
V
0.45V
0.45V
IL
IN
IN
b
IL1
CC
e
Active Mode Current in Reset
(8XC196KD)
65
80
17
21
75
XTAL1
e
16 MHz
e
e
e
e
e
V
V
PP
V
REF
5.5V
5.5V
5.5V
CC
e
20 MHz
I
I
I
Active Mode Current in Reset
(8XC196KD20)
92
25
30
mA
mA
mA
XTAL1
e
CC
e
V V
PP
V
CC
REF
e
16 MHz
Idle Mode Current (8XC196KD)
Idle Mode Current (8XC196KD20)
XTAL1
e
IDLE
IDLE
e
V
V
PP
V
CC
REF
e
XTAL1
20 MHz
e
e
e
e
e
e
e
V
CC
V
CC
V
CC
V
CC
V
V
V
V
V
V
5.5V
5.5V
5.5V
PP
PP
PP
REF
e
e
I
I
Powerdown Mode Current
A/D Converter Reference Current
Reset Pullup Resistor
8
2
15
5
mA
mA
X
PD
REF
REF
REF
e
R
6K
65K
10
5.5V, V
4.0V
RST
IN
C
Pin Capacitance (Any Pin to V
)
SS
pF
S
NOTES:
1. All pins except RESET and XTAL1.
2. Violating these specifications in Reset may cause the part to enter test modes.
3. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
4. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The V specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
OH
5. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
6. Maximum current per pin must be externally limited to the following values if V is held above 0.45V or V
is held
OL OH
b
on Output pins: 10 mA
on quasi-bidirectional pins: self limiting
on Standard Output pins: 10 mA
below V
0.7V:
CC
I
I
I
OL
OH
OH
g
7. Maximum current per bus pin (data and control) during normal operation is 3.2 mA.
8. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
I
I
I
: 29 mA
: 29 mA
: 13 mA
I
I
I
is self limiting
: 26 mA
: 11 mA
: 52 mA
: 13 mA
OL
OH
HSO, P2.0, RXD, RESET
P2.5, P2.7, WR, BHE
AD0–AD15
OL
OH
OH
OL
I
I
: 52 mA
OL
: 13 mA
I
OH
RD, ALE, INST–CLKOUT
I
OH
OL
11
8XC196KD/8XC196KD20
272145–5
e
e
c
c
a
a
I
I
I
I
Max
Typ
4.13
3.50
e
Frequency
Frequency
9 mA
9 mA
a
CC
CC
c
c
Max
Typ
1.25
0.88
Frequency 5 mA
a
Frequency 3 mA
IDLE
IDLE
e
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 7. I and I
CC
vs Frequency
IDLE
AC CHARACTERISTICS
For use over specified operating conditions.
e
e
e
16/20 MHz
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The system must meet these specifications to work with the 80C196KD:
Symbol
Description
Min
Max
Units
ns
Notes
b
OSC
T
T
T
T
T
T
T
T
T
T
T
Address Valid to READY Setup
Non READY Time
2 T
68
AVYV
YLYH
CLYX
LLYX
AVGV
CLGX
AVDV
RLDV
CLDV
RHDZ
RXDX
No upper limit
ns
b
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to Buswidth Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
0
T
30
ns
(Note 1)
(Note 1)
OSC
b
b
b
T
15
2 T
40
68
ns
OSC
OSC
OSC
2 T
ns
0
ns
b
3 T
55
ns
(Note 2)
(Note 2)
OSC
b
T
T
22
ns
OSC
OSC
b
45
ns
T
ns
OSC
0
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
e
2. If wait states are used, add 2 T
* N, where N
number of wait states.
OSC
12
8XC196KD/8XC196KD20
AC CHARACTERISTICS (Continued)
For use over specified operating conditions.
e
e
e
16/20 MHz
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The 80C196KD will meet these specifications:
Symbol
Description
Min
8
Max
Units
MHz
MHz
ns
Notes
(Note 1)
(Note 1)
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1 (8XC196KD)
Frequency on XTAL1 (8XC196KD20)
16
20
XTAL
XTAL
OSC
8
I/F
I/F
(8XC196KD)
62.5
50
125
125
XTAL
XTAL
(8XC196KD20)
ns
OSC
a
a
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
20
110
ns
XHCH
CLCL
CHCL
CLLH
LLCH
LHLH
LHLL
2 T
ns
OSC
b
a
15
15
CLKOUT High Period
T
10
T
15
ns
OSC
OSC
b
a
a
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
5
ns
b
20
ns
4 T
ns
(Note 4)
OSC
b
b
b
b
a
ALE High Period
T
T
T
T
10
T
10
ns
OSC
OSC
OSC
OSC
OSC
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
15
35
30
AVLL
LLAX
LLRL
ns
ns
ns
ns
ns
ns
ns
ns
a
a
4
30
RLCL
RLRH
RHLH
RLAZ
LLWL
CLWL
QVWH
CHWH
WLWH
WHQX
WHLH
WHBX
WHAX
RHBX
RHAX
b
T
5
(Note 4)
(Note 2)
OSC
a
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
T
T
25
OSC
OSC
a
5
b
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
T
T
10
23
OSC
a
a
0
25
15
b
(Note 4)
(Note 4)
(Note 2)
(Note 3)
(Note 3)
OSC
b
5
ns
ns
ns
ns
ns
ns
ns
ns
b
b
b
b
b
b
b
T
T
T
T
T
T
T
20
25
10
10
30
10
25
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE, INST after WR Rising Edge
AD8–15 HOLD after WR Rising
BHE, INST after RD Rising Edge
AD8–15 HOLD after RD Rising
a
T
15
OSC
NOTES:
1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are used, add 2 T
e
number of wait states.
* N, where N
OSC
13
8XC196KD/8XC196KD20
System Bus Timings
272145–6
14
8XC196KD/8XC196KD20
READY Timings (One Wait State)
272145–7
Buswidth Timings
272145–8
15
8XC196KD/8XC196KD20
HOLD/HLDA TIMINGS
Symbol
Description
Min
Max
Units
ns
Notes
a
b
b
T
T
T
T
T
T
T
T
T
T
HOLD Setup
55
15
15
(Note 1)
HVCH
a
a
a
a
a
a
CLKOUT Low to HLDA Low
15
15
15
20
15
15
ns
CLHAL
CLBRL
HALAZ
HALBZ
CLHAH
CLBRH
HAHAX
HAHBV
CLLH
CLKOUT Low to BREQ Low
ns
HLDA Low to Address Float
ns
HLDA Low to BHE, INST, RD, WR Weakly Driven
CLKOUT Low to HLDA High
ns
b
b
b
b
15
15
15
10
ns
CLKOUT Low to BREQ High
ns
HLDA High to Address No Longer Float
HLDA High to BHE, INST, RD, WR Valid
CLKOUT Low to ALE High
ns
a
a
15
15
ns
b
5
ns
NOTE:
1. To guarantee recognition at next clock.
DC SPECIFICATIONS IN HOLD
Description
Min
Max
Units
e
e
e
Weak Pullups on ADV, RD,
WR, WRL, BHE
50K
250K
V
5.5V, V
0.45V
2.4
CC
CC
IN
e
Weak Pulldowns on ALE, INST
10K
50K
V
5.5V, V
IN
272145–9
16
8XC196KD/8XC196KD20
MAXIMUM HOLD LATENCY
Bus Cycle Type
Internal Execution
1.5 States
2.5 States
4.5 States
16-Bit External Execution
8-Bit External Execution
EXTERNAL CLOCK DRIVE (8XC196KD)
Symbol
1/T
Parameter
Oscillator Frequency
Oscillator Period
High Time
Min
8
Max
16.0
125
Units
MHz
ns
XLXL
T
T
T
T
T
62.5
20
XLXL
ns
XHXX
XLXX
XLXH
XHXL
Low Time
20
ns
Rise Time
10
10
ns
Fall Time
ns
EXTERNAL CLOCK DRIVE (8XC196KD20)
Symbol
1/T
Parameter
Oscillator Frequency
Oscillator Period
High Time
Min
8
Max
20.0
125
Units
MHz
ns
XLXL
T
T
T
T
T
50
17
17
XLXL
ns
XHXX
XLXX
XLXH
XHXL
Low Time
ns
Rise Time
8
8
ns
Fall Time
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272145–10
17
8XC196KD/8XC196KD20
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
272145–13
272145–14
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and V . When
SS
NOTE:
*Required if TTL driver used.
Not needed if CMOS driver is used.
e
e
20 pF.
using ceramic crystals, C1
20 pF, C2
When using ceramic resonators consult manufacturer
for recommended capacitor values.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272145–11
AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
272145–12
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs, and Begins to Float
when a 150 mV change from the Loaded V /V Level occurs;
OH OL
e
g
15 mA.
I
/I
OL OH
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
HÐ High
Signals:
AÐ Address
BÐ BHE
LÐ ALE/ADV
BRÐ BREQ
LÐ Low
VÐ Valid
CÐ CLKOUT
DÐ DATA
GÐ Buswidth
HÐ HOLD
HAÐ HLDA
RÐ RD
XÐ No Longer Valid
ZÐ Floating
WÐ WR/WRH/WRL
XÐ XTAL1
YÐ READY
QÐ Data Out
18
8XC196KD/8XC196KD20
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE (MODE 0)
Symbol Parameter
Min
6 T
Max
Units
ns
t
Serial Port Clock Period (BRR 8002H)
T
T
XLXL
OSC
b
a
Serial Port Clock Falling Edge
t
to Rising Edge (BRR 8002H)
4 T
50
50
4 T
2 T
50
50
ns
XLXH
OSC
OSC
e
T
T
Serial Port Clock Period (BRR
8001H)
4 T
ns
ns
XLXL
OSC
b
a
Serial Port Clock Falling Edge
e
2 T
XLXH
OSC
OSC
to Rising Edge (BRR
8001H)
b
b
T
QVXH
T
XHQX
T
XHQV
T
DVXH
T
XHDX
T
XHQZ
Output Data Valid to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge
Input Data Hold after Clock Rising Edge
Last Clock Rising to Output Float
2 T
2 T
50
50
ns
ns
ns
ns
ns
ns
OSC
OSC
a
2 T
50
OSC
a
T
50
OSC
0
1 T
OSC
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE (MODE 0)
272145–15
19
8XC196KD/8XC196KD20
A to D CHARACTERISTICS
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V
.
REF
10-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
a
T
A
Ambient Temperature Commercial Temp.
0
70
C
§
T
A
Ambient Temperature Extended Temp.
Digital Supply Voltage
-40
4.50
4.00
+85
5.50
5.50
°C
V
V
V
CC
Analog Supply Voltage
V
REF
b
a
ANGND
Analog Ground Voltage
V
0.40
V
CC
0.40
V
SS
(1)
T
T
F
F
Sample Time
1.0
10
ms
SAM
CONV
OSC
OSC
(1)
ms
Conversion Time
20
Oscillator Frequency (8XC196KD)
Oscillator Frequency (8XC196KD20)
8.0
8.0
16.0
20.0
MHz
MHz
NOTE:
1. The value of AD TIME is selected to meet these specifications.
Ð
10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
(1)
Parameter
Resolution
Typical
Minimum
Maximum
Units*
Notes
1024
10
1024
10
Levels
Bits
g
Absolute Error
0
3
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
0.25 0.5
Full Scale Error
g
0.25 0.5
Zero Offset Error
g
1.0 2.0
g
a
Non-Linearity
0
3
2
1
l
b
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
1
g
g
0.1
0
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.009
0.009
0.009
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
b
Off Isolation
Feedthrough
60
dB
dB
dB
X
2, 3
2
b
b
60
60
V
Power Supply Rejection
2
CC
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
750
1.2K
4
b
a
ANGND
0.5
V
0.5
V
5, 6
REF
g
0
3.0
mA
pF
Sampling Capacitor
3
NOTES:
*An ‘‘LSB’’ as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms.)
1. These values are expected for most parts at 25 C but are not tested or guaranteed.
2. DC to 100 KHz.
§
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
g
5. These values may be exceeded if the pin current is limited to 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
20
8XC196KD/8XC196KD20
8-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Ambient Temperature Commercial Temp.
Ambient Temperature Extended Temp.
Digital Supply Voltage
Min
0
Max
Units
a
T
A
70
C
§
T
A
-40
4.50
4.00
+85
5.50
5.50
°C
V
CC
V
V
REF
Analog Supply Voltage
V
b
a
ANGND
Analog Ground Voltage
V
0.40
V
0.40
V
SS
SS
(1)
T
T
F
F
Sample Time
1.0
7
ms
SAM
CONV
OSC
OSC
(1)
ms
Conversion Time
20
Oscillator Frequency (8XC196KD)
Oscillator Frequency (8XC196KD20)
8.0
8.0
16.0
20.0
MHz
MHz
NOTE:
1. The value of AD TIME is selected to meet these specifications.
Ð
8-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
(1)
Parameter
Resolution
Typical
Minimum
Maximum
Units*
Notes
256
8
256
8
Levels
Bits
g
Absolute Error
0
1
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
g
Full Scale Error
0.5
0.5
Zero Offset Error
g
a
Non-Linearity
0
1
1
1
l
b
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
1
g
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.003
0.003
0.003
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
b
Off Isolation
Feedthrough
60
dB
dB
dB
X
2, 3
2
b
b
60
60
V
CC
Power Supply Rejection
2
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
750
1.2K
4
b
a
V
0.5
V
0.5
V
5, 6
SS
REF
g
0
3.0
mA
pF
Sampling Capacitor
3
NOTES:
*An ‘‘LSB’’ as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25 C but are not tested or guaranteed.
2. DC to 100 KHz.
§
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
g
5. These values may be exceeded if pin current is limited to 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
21
8XC196KD/8XC196KD20
OTPROM SPECIFICATIONS
OPERATING CONDITIONS
Symbol
Description
Min
20
Max
30
Units
T
Ambient Temperature During Programming
Supply Voltage During Programming
Reference Supply Voltage During Programming
Programming Voltage
C
A
(1)
V
V
V
V
V
4.5
5.5
CC
(1)
V
4.5
5.5
REF
PP
(2)
V
12.25
12.25
6.0
12.75
12.75
8.0
(2)
V
EA Pin Voltage
EA
F
F
F
Oscillator Frequency during Auto and Slave
Mode Programming
MHz
MHz
MHz
OSC
Oscillator Frequency during
Run-Time Programming (8XC196KD)
6.0
6.0
16.0
20.0
OSC
OSC
Oscillator Frequency during
Run-Time Programming (8XC196KD20)
NOTES:
1. V and V
2. V and V must never exceed the maximum specification, or the device may be damaged.
should nominally be at the same voltage during programming.
REF
CC
PP EA
3. V and ANGND should nominally be at the same potential (0V).
SS
e
4. Load capacitance during Auto and Slave Mode programming
150 pF.
AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)
Symbol
Description
Reset High to First PALE Low
PALE Pulse Width
Min
1100
50
Max
Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
SHLL
LLLH
AVLL
LLAX
PLDV
PHDX
DVPL
PLDX
Address Setup Time
0
Address Hold Time
100
PROG Low to Word Dump Valid
Word Dump Data Hold
Data Setup Time
50
50
0
Data Hold Time
400
50
(1)
PROG Pulse Width
PLPH
PHLL
LHPL
PHPL
PHIL
ILIH
PROG High to Next PALE Low
PALE High to PROG Low
PROG High to Next PROG Low
PROG High to AINC Low
AINC Pulse Width
220
220
220
0
240
50
PVER Hold after AINC Low
AINC Low to PROG Low
PROG High to PVER Valid
ILVH
ILPL
170
220
PHVL
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.
22
8XC196KD/8XC196KD20
DC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
Max
Units
I
V
Supply Current (When Programming)
PP
100
mA
PP
NOTE:
Do not apply V until V
PP
damaged.
is stable and within specifications and the oscillator/clock has stabilized or the device may be
CC
OTPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
272145–16
NOTE:
P3.0 must be high (‘‘1’’)
23
8XC196KD/8XC196KD20
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
272145–17
NOTE:
P3.0 must be low (‘‘0’’)
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND
AUTO INCREMENT
272145–18
24
8XC196KD/8XC196KD20
3. Changed QFP Package i
to 56 C/W from
§
JA
8XC196KC TO 8XC196KD DESIGN
CONSIDERATIONS
42 C/W.
§
4. Changed V
to 300 mV from 150 mV.
HYS
1. Memory Map. The 8XC196KD has 1024 bytes of
RAM/SFRs and 32K of OTPROM. The extra 512
bytes of RAM reside in locations 0200H to
03FFH, and the extra 16 Kbytes of OTPROM re-
side in locations 6000H to 9FFFH. On the
87C196KC these locations are always external,
so KC code may have to be modified to run on
the KD.
5. Changed I Typical specification at 16 MHz to
CC
65 mA from 50 mA.
6. Changed I
Maximum specification at 16 MHz
CC
to 75 mA from 70 mA.
7. Changed I
IDLE
from 15 mA.
Typical specification to 17 mA
Maximum specification to 25 mA
8. Changed I
IDLE
from 30 mA.
2. The vertical window scheme has been extended
to include all on-chip RAM.
9. Changed I Typical specification to 8 mA from
PD
3. IOC3.1 controls the CLKOUT signal. This bit must
be 0 to enable CLKOUT.
15 mA.
10. Added I Maximum specification.
PD
4. The 87C196KD has a different autoprogramming
algorithm to support 32K of on-chip OTPROM.
11. Changed T
b
Maximum specification to
b
50.
CLDV
45 from T
T
OSC
OSC
12. Changed T
b
Minimum specification to
b
40.
LLAX
35 from T
T
8XC196KD ERRATA
1. 83C196KD can possibly miss interrupts on P0.7.
See techbit MC0893.
OSC
OSC
b
5
13. Changed T
b
from 10.
Minimum specification to
CHWH
14. Changed T
b
Minimum specification to
b
30.
RHAX
25 from T
T
OSC
OSC
DATA SHEET REVISION HISTORY
15. Changed
a
T
Maximum specification to
HALAZ
a
15 from 10.
This data sheet is valid for devices with a ‘‘D’’ and
‘‘E’’ at the end of the topside tracking number. Data
sheets are changed as new device information be-
comes available. Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices.
16. Changed
a
T
Maximum specification to
HALBZ
a
20 from 15.
17. Added T
Maximum specification.
HAHBV
18. Changed T
3 ms.
for 10-bit mode to 1 ms from
SAM
The following are important differences between the
272145-002 and 272145-003 data sheets:
19. Changed T
for 8-bit mode to 1 ms from 2 ms.
SAM
e
2.4V from
20. Changed I
5.5V.
test condition to V
IH1
IN
1. I
specification (logic 0 input current in reset)
.
IL1
was misnamed. It is renamed I
IL2
a
200
21. Changed I
maximum specification to
IH1
2. T
and T
were removed. These specifi-
LLYV
LLGV
a
mA from 100 mA.
22. Removed NMI from list of standard inputs.
23. Updated I and I vs frequency graph.
cations are not necessary for high-speed system
designs.
CC
IDLE
3. An errata with 83C196KD P0.7 EXTINT was add-
ed to the errata section.
24. Updated note under DC EPROM Programming
Characteristics.
The following are important differences between the
272145-001 and 272145-002 data sheets:
b
12
25. Changed I
maximum specification to
LI1
b
mA from 6 mA.
1. Added 20 MHz specifications.
2. Added 80-lead SQFP package pinout.
25
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ETC
TN83C198-16
16-Bit MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
TN83C251SA
Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQCC44, PLASTIC, LCC-44Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INTEL
TN83C251SA16
HIGH-PERFORMANCE CHMOS MICROCONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INTEL
TN83C251SB
8-Bit MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
TN83C251SB16
HIGH-PERFORMANCE CHMOS MICROCONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INTEL
TN83C251SP
Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQCC44, PLASTIC, LCC-44Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INTEL
TN83C251SP16
HIGH-PERFORMANCE CHMOS MICROCONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INTEL
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