TPS3610U50PWR [ETC]
Analog IC ; 模拟IC\n
| 型号： | TPS3610U50PWR |
| 厂家： | 
ETC |
| 描述： | Analog IC
|
| 文件： | 总16页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
features
typical applications
Fax Machines
Supply Current of 40 µA (Max)
Battery Supply Current of 20 nA (Max)
Set-Top Boxes
Precision Supply-Voltage Monitor,
1.8 V, 5 V; Other Options on Request
Advanced Voice Mail Systems
Portable Battery-Powered Equipment
Computer Equipment
Watchdog Timer With 800-ms Time-Out
Backup-Battery Voltage can Exceed V
DD
Advanced Modems
Power-On Reset Generator With Fixed
100-ms Reset Delay Time
Automotive Systems
Portable Long-Time Monitoring Equipment
Point of Sale Equipment
Battery-OK Output
Voltage Monitor for Power-Fail or
Low-Battery Monitoring
PW PACKAGE
(TOP VIEW)
Manual Switchover to Battery-Backup
Mode
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT
V
BAT
RESET
WDI
LOWLINE
CEOUT
BATTOK
PFO
Chip-Enable Gating . . . 3 ns (at V
Max Propagation Delay
= 5 V)
DD
V
DD
GND
MSWITCH
CEIN
BATTON
PFI
Battery-Freshness Seal
14-pin TSSOP Package
Temperature Range . . . –40°C to 85°C
8
–
typical operating circuit
Address
Decoder
Power
Supply
0.1 µF
External
CEIN
CE
CMOS
RAM
CE
CMOS
RAM
CEOUT
Address Bus
Real-
Time
Clock
Backup
Battery
Source
V
DD
V
BAT
R
R
x
y
TPS3610
uC
V
V
V
CC
CC
CC
PFI
8
8
RESET
I/O
RESET
WDI
Data Bus
16
I/O
PFO
I/O
BATTOK
BATTON
I/O
MR
Switchover
Capacitor
Manual
Reset
MSWITCH
GND
V
OUT
V
CC
0.1 µF
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
description
TheTPS3610familyofsupervisorycircuitsmonitorsandcontrolsprocessoractivitybyprovidingbackup-battery
switchover for data retention of CMOS RAM. Other features include an additional power-fail comparator,
low-line indication, watchdog function, battery-status indicator, manual switchover, and write protection for
CMOS RAM.
The TPS3610 family allow usage of 3-V or 3.6-V lithium batteries as the backup supply in systems with, e.g.,
V
= 1.8 V. During power-on, RESET is asserted when the supply voltage (V or V
) becomes higher than
DD
DD
BAT
1.1 V. Thereafter, the supply-voltage supervisor monitors V
remains below the threshold voltage V . An internal timer delays the return of the output to the inactive state
(high) to ensure proper system reset. The delay time starts after V has risen above the threshold voltage V .
When the supply voltage drops below the threshold voltage V , the output becomes active (low) again.
and keeps RESET output active as long as V
DD
DD
IT
DD
IT
IT
The product spectrum is designed for supply voltages of 1.8 V and 5 V. The circuits are available in a 14-pin
TSSOPpackage. TPS3610 devices are characterized for operation over a temperature range of –40°C to 85°C.
standard and application-specific versions
TPS3610U 18
PW
R
Standard Versions
PACKAGED DEVICES
Tape and Reel
T
A
TI Package Designator
Nominal Supply Voltage
Nominal Battok Threshold Voltage
TPS3610U18PWR
TPS3610T50PWR
–40°C to 85°C
APPLICATION-SPECIFIC VERSIONS,
NOMINAL SUPPLY VOLTAGE
APPLICATION-SPECIFIC VERSIONS,
BATTOK SUPPLY VOLTAGE
NOMINAL BATTOK
NOMINAL SUPPLY
PACKAGED DEVICES
PACKAGED DEVICES
THRESHOLD
‡
T
A
VOLTAGE, V
(V)
T
A
DD(NOM)
†
†
TSSOP (PW)
TSSOP (PW)
VOLTAGE , V
IT(BOK)
(V)
2.4
1.6
1.8
2.5
3
TPS3610x18PWR
TPS3610x25PWR
TPS3610x30PWR
TPS3610x33PWR
TPS3610TXxPWR
TPS3610UXXPWR
–40°C to 85°C
–40°C to
85°C
3.3
5
TPS3610x50PWR
†
‡
The PW package is only available taped and reeled (indicated by the R suffix on the device type).
Application specific versions for the BATTOK threshold voltage can be manufactured in the range from 1.5 V to 4.8 V in 50-mV steps.
NOTE: For the application specific versions, contact your local TI sales office for availability and order lead time.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
TRUTH TABLES
OUTPUTS
INPUTS
V
DD
> V
V
DD
> V
V
DD
> V
BAT
MSWITCH
CEIN
OUT
BATTON
LOWLINE
RESET
CEOUT
LL
IT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
0
1
0
1
0
1
0
1
0
1
0
1
0
BAT
BAT
BAT
BAT
DD
DD
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V
V
V
V
V
V
V
V
BAT
BAT
DD
DD
V
V
V
V
BAT
BAT
DD
DD
V
V
V
V
BAT
BAT
DD
DD
V
V
V
V
BAT
BAT
DD
DD
V
1
0
1
V
BAT
V
BAT
BATTOK
POWER-FAIL
V
BAT
> V
BATTOK
PFI > V
PFI
PFO
BOK
0
1
0
1
0
1
0
1
COND.: V
DD
> V
min
DD
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
functional block diagram
MSWITCH
V
BAT
+
_
Switch
Control
OUT
V
DD
BATTON
BATTOK
+
_
Reference
Voltage
of 1.15 V
_
+
RESET
Logic
+
RESET
GND
Timer
+
_
LOWLINE
Oscillator
_
+
PFO
PFI
V
O
Transition
Detector
Watchdog
Logic + Control
WDI
40 kΩ
CEOUT
CEIN
timing diagram
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
Terminal Functions
TERMINAL
NAME
BATTOK
I/O
DESCRIPTION
NO.
9
O
O
I
Battery status output
BATTON
CEIN
6
Logic output/external bypass switch driver output
Chip-enable input
5
CEOUT
10
O
Chip-enable output
GND
3
11
4
I
O
I
Ground
LOWLINE
MSWITCH
OUT
Early power-fail warning output
Manual switch to force device into battery-backup mode
Supply output
1
O
I
PFI
7
Power-fail comparator input
Power-fail comparator output
Active-low reset output
Backup-battery input
PFO
8
O
O
I
RESET
13
14
2
V
V
BAT
I
Input supply voltage
DD
WDI
12
I
Watchdog timer input
detailed description
battery freshness seal
The battery freshness seal of the TPS3610 family disconnects the backup battery from internal circuitry until
it is needed. This function ensures that the backup battery connected to V willbefreshwhenthefinalproduct
BAT
is put to use. The following steps explain how to enable the freshness seal mode:
1. Connect V (V > V min or V min)
BAT BAT
BAT
DD
2. Ground PFO
3. Connect PFI to V
(PFI = V
)
DD
DD
4. Connect V
to power supply (V
> V ) and keep connected for 5 ms < t < 35 ms
DD IT
DD
The battery freshness seal mode is disabled by the positive-going edge of RESET when V
is applied.
DD
BATTOK output
BATTOK is a logic feedback of the device to indicate the status of the backup battery. The supervisor checks
the battery voltage every 200 ms with a voltage divider load of approximately 100 kΩ and a measurement cycle
on-time of 25 µs. The measurement cycle starts after the reset is released. If the battery voltage V
is below
BAT
the negative-going threshold voltage V
, the indicator BATTOK does a high-to-low transition. Otherwise
IT(BOK)
it retains its status to V
level.
OUT
I
25 µs
200 ms
100 µA
t
Figure 1. BATTOK Timing
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
detailed description (continued)
chip-enable signal gating
The internal gating of chip-enable, CE, signals prevents erroneous data from corrupting CMOS RAM during an
undervoltage condition. The TPS3610 use a series transmission gate from CEIN to CEOUT. During normal
operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short
CE propagation delay from CEIN to CEOUT enables TPS3610 devices to be used with most processors.
The CE transmission gate is disabled and CEIN is high-impedance (disable mode) while reset is asserted.
During a power-down sequence, when V
crosses the reset threshold, the CE transmission gate will be
DD
disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low while
reset is asserted, the CE transmission gate will be disabled at the same time CEIN goes high, or 10 µs after
rest asserts, whichever occurs first. This will allow the current write cycle to complete during power-down. When
the CE transmission gate is enabled, the impedance of CEIN appears as a 50-Ω resistor in series with the load
at CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and
a low-output-impedance driver should be used.
During disable mode, the transmission gate is off and an active pull-up connects CEOUT to OUT. The pullup
turns off when the transmission gate is enabled.
V
DD
V
BAT
V
(BOK)
V
(SWP)
(SWN)
V
V
IT
1.1 V
CEIN
V
DD
V
BAT
V
(BOK)
(SWP)
(SWN)
V
V
V
IT
COUT
10 µs
10 µs
RESET
t
d
t
d
t
d
V
(SWN)
V
IT
Undefined Behavior
Figure 2. Chip-Enable Timing
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
detailed description (continued)
V
V
DD
DD
V
BAT
3.6 V
TPS3610
25-Ω Equivalent
Source Impedance
50-Ω Cable
CEIN
CEOUT
50 Ω
50 Ω
†
C
L
GND
50 pF
†
Includes load capacitance and scope-probe capacitance.
Figure 3. CE Propagation Delay Test Circuit
power-fail comparator (PFI and PFO)
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The
power-fail-input (PFI) will be compared with an internal voltage reference of 1.15 V. If the input voltage falls
below the power-fail threshold V
of typical 1.15 V, the power-fail output (PFO) goes low. If V
goes
IT(PFI)
IT(PFI)
above 1.15 V, plus about 20-mV hysteresis, the output returns to high. By connecting two external resistors, it
is possible to supervise any voltages above 1.15 V. The sum of both resistors should be about 1 MΩ, to minimize
power consumption and also to guarantee that the current in the PFI pin can be neglected compared with the
current through the resistor network. The tolerance of the external resistors should be not more than 1% to
ensure minimal variation of sensed voltage. If the power-fail comparator is unused, PFI should be connected
to ground and PFO left unconnected.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
detailed description (continued)
LOWLINE
The lowline comparator monitors V with a threshold voltage typically 2% above the reset threshold (V ). For
DD
IT
normaloperation(V abovetheresetthreshold), LOWLINEispulledtoV . LOWLINEcanbeusedtoprovide
DD
DD
a nonmaskable interrupt (NMI) to the processor when power begins to fall. In most battery-operated portable
systems, reserveenergyinthebatteryprovidesenoughtimetocompletetheshutdownroutineoncethelow-line
warning is encountered and before reset asserts. If the system must also contend with a more rapid V
fall
DD
time, such as when the main battery is disconnected or a high-side switch is opened during normal operation,
a capacitor can be used on the V line to provide enough time for executing the shutdown routine. First of all,
DD
the worst-case settling time (t ) required for the system to perform its shutdown routine needs to be defined.
sd
Now, using the worst-case load current (I ) that can be drained from the capacitor, and the minimum reset
L
threshold voltage (V min), the capacitor value (C ) can be calculated as follows:
IT
H
I
t
L
sd
C
H
V min 0.012
IT
BATTON
Most often BATTON is used as a gate or base drive for an external pass transistor for high-current applications.
In addition it can be used as a logic output to indicate the battery switchover status. BATTON is high when OUT
is connected to V
.
BAT
BATTON can be connected directly to the base of a PNP transistor (see Figure 4a) or to the gate of a PMOS
transistor (see Figure 4b). No current-limiting resistor is required, but a resistor connecting the base of the PNP
to BATTON can be used to limit the current drawn from V —prolonging battery life in portable equipment.
DD
However, if a PMOS transistor is used, it must be connected in the reverse of the traditional method (see
Figure 4b), which orients the body diode from V
through the FET when its gate is high.
to V
and prevents the backup battery from discharging
DD
OUT
PMOS FET
Body Diode
3 V or 3.3 V
To CMOS RAM
D
S
G
V
DD
BATTON
TPS3610
V
O
V
DD
BATTON
V
O
TPS3610
GND
GND
(b)
(a)
Figure 4. Driving an External Transistor With BATTON
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
detailed description (continued)
backup-battery switchover
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at V , the device automatically switches the connected RAM to backup power when V fails. In
BAT
DD
order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than V , these supervisors
DD
willnotconnectV
toOUTwhenV
isgreaterthanV .V
onlyconnectstoOUT(througha20-Ωswitch)
BAT
BAT
DD BAT
when V falls below V and V
is greater than V . When V recovers, switchover is deferred either until
DD
crossesV
IT
BAT
DD DD
V
,oruntilV risesabovetheresetthresholdV .OUTwillconnecttoV througha1-Ω(max)
DD
BAT DD IT DD
PMOS switch when V
crosses the reset threshold.
DD
FUNCTION TABLE
> V
V
DD
> V
1
V
DD
OUT
BAT
IT
1
V
DD
V
DD
V
DD
1
0
1
0
0
0
V
BAT
V
DD
Mode
V
IT
Hysteresis
V
BAT
Mode
VBSW Hysteresis
Undefined
V
BAT
– Backup-Battery Supply Voltage – V
Figure 5. Normal Supply Voltage vs Backup-Battery Supply Voltage
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
detailed description (continued)
manual switchover (MSWITCH)
While operating in the normal mode from V , the device can be forced manually to operate in battery-backup
DD
mode by connecting MSWITCH to V . Refer to Table 1 for different switchover modes.
DD
Table 1. Switchover Modes
MSWITCH
STATUS
GND
V
mode
DD
V
mode
DD
V
DD
GND
Switch to battery-backup mode
Battery-backup mode
Battery-backup mode
V
DD
Battery-backup mode
If the manual switchover feature is not used, MSWITCH must be connected to ground.
watchdog
In a microprocessor- or DSP-based system, it is important not only to supervise the supply voltage, but also to
ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an
indefinite loop. The microprocessor, microcontroller or DSP has to toggle the watchdog input within typically
0.8 s to avoid the occurence of a time-out. Either a low-to-high or a high-to-low transition resets the internal
watchdog timer. If the input is unconnected, the watchdog is disabled and will be retriggered internally.
saving current while using the watchdog
The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then the input
momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum
overall power consumption), WDI should be left low for the majority of the watchdog time-out period, and pulsed
low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is
externally driven high for the majority of the timeout period, a current of, e.g., 5 V/40 kΩ ≈ 125 µA, can flow into
WDI.
V
V
DD
V
IT
BAT
WDI
Time-Out
RESET
t
t
d
d
Figure 6. Watchdog Timing
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous output current at OUT, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
O(OUT)
Continuous output current (all other pins) I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h
continuously.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
PW
700 mW
5.6 mW/°C
448 mW 364 mW
recommended operating conditions
MIN
MAX
5.5
UNIT
V
Supply voltage, V
DD
1.65
1.5
0
Battery supply voltage, V
5.5
V
BAT
Input voltage, V
V
V
I
DD+0.3
High-level input voltage, V
IH
0.7xV
V
DD
Low-level input voltage, V
0.3×V
DD
V
IL
Continuous output current at OUT, I
300
100
1
mA
ns/V
V/µs
°C
O(OUT)
Input transition rise and fall rate at WDI, MSWITCH, ∆t/∆V
Slew rate at V or V
DD
BAT
Operating free-air temperature range, T
–40
85
A
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 1.8 V,
I
= –400 µA
V
V
–0.2 V
DD
OH
DD
RESET,
BATTOK
V
DD
V
DD
= 3.3 V,
= 5 V,
I
I
= –2 mA,
= –3 mA
OH
OH
–0.4 V
–0.2 V
–0.4 V
–0.3 V
–0.4 V
–0.2 V
–0.3 V
DD
V
= 1.8 V,
I
= –400 µA
V
V
O(OUT)
OH
OUT
BATTON
V
V
= 3.3 V,
= 5 V,
I
I
= –2 mA,
= –3 mA
O(OUT)
O(OUT)
OH
OH
OUT
V
DD
= 1.8 V,
I
= –20 µA
V
V
OH
DD
V
OH
High-level output voltage
V
LOWLINE,
PFO
V
DD
V
DD
= 3.3 V,
= 5 V,
I
I
= –80 µA,
= –120 µA
OH
OH
DD
V
= 1.8 V,
I
= –1 mA
V
O(OUT)
OH
OUT
OUT
CEOUT,
Enable mode,
CEIN = V
V
V
= 3.3 V,
= 5 V,
I
I
= –2 mA,
= –5 mA
O(OUT)
O(OUT)
OH
OH
V
OUT
CEOUT,
Enable mode
V
V
= 3.3 V,
I
= –0.5 mA
V –0.4 V
OUT
O(OUT)
OH
OL
= 1.8 V,
I
= 400 µA
0.2
0.4
0.2
0.4
0.2
0.3
DD
RESET, PFO,
BATTOK,
LOWLINE
V
DD
V
DD
= 3.3 V,
= 5 V,
I
I
= 2 mA,
= 3 mA
OH
OH
V
= 1.8 V,
I
= 500 µA
O(OUT)
OH
V
OL
Low-level output voltage
BATTON
V
V
V
V
= 3.3 V,
= 5 V,
I
I
= 3 mA,
= 5 mA
O(OUT)
O(OUT)
OH
OH
V
= 1.8 V,
I
= 1 mA
O(OUT)
OH
CEOUT,
Enable mode,
CEIN = 0 V
V
V
= 3.3 V,
= 5 V,
I
I
= 2 mA
= 5 mA
O(OUT)
O(OUT)
OH
OH
V
DD
= 0 V to 5.5 V,
OR
= 0 V, to 5.5 V,
V
> 1.1 V,
BAT
OR
Power-up reset voltage (see Note 2)
0.4
V
BAT
V
> 1.1 V,
= 1.8 V,
= 3.3 V,
= 5 V,
DD
DD
DD
DD
DD
DD
I
I
V
= 20 µA
OL
= 8.5 mA,
= 0 V
V
V
V
V
V
O(OUT)
BAT
V
DD
–50 mV
I
V
= 125 mA,
= 0 V
O(OUT)
BAT
V
–150 mV
–200 mV
Normal mode
DD
DD
I
V
= 200 mA,
= 0 V
O(OUT)
BAT
V
V
OUT
V
I
V
= 0.5 mA,
= 1.5 V
= 0 V,
O(OUT)
BAT
V
BAT
–20 mV
Battery-backup mode
I
V
= 7.5 mA,
= 3.3 V
= 0 V,
O(OUT)
V
–113 mV
BAT
BAT
NOTE 2: The lowest supply voltage at which RESET becomes active. t
V
≥ 15 µs/V
r, DD
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
1.68
2.21
2.59
2.88
4.46
1.13
2.33
1.55
+1.2%
TYP
1.71
2.25
2.63
2.93
4.55
1.15
2.4
1.6
+2%
20
MAX
1.74
2.30
2.69
3
UNIT
TPS3610x18
TPS3610x25
TPS3610x30
TPS3610x33
TPS3610x50
PFI
Negative-going
input threshold
T
A
= –40°C to 85°C
V
V
IT
4.64
1.17
2.47
1.65
+2.8%
voltage (see Note 3)
V
V
V
IT(PFI)
IT(BOK)
IT(LL)
TPS3610Txx
TPS3610Uxx
LOWLINE
V
IT
V
IT
V
IT
V
1.65 V < V < 2.5 V
IT
V
IT
2.5 V < V < 3.5 V
IT
40
3.5 V < V < 5.5 V
IT
60
1.65 V < V < 2.5 V
LL
20
2.5 V < V < 3.5 V
LL
40
LOWLINE
3.5 V < V < 5.5 V
LL
60
V
hys
Hysteresis
mV
1.65 V < V
BOK
< 2.5 V
20
BATTOK
PFI
2.5 V < V
< 3.5 V
40
BOK
3.5 V < V
< 5.5 V
60
IBOK
12
V
BSW
V
DD
= 1.8 V
55
(see Note 5)
I
IH
High-level input current
Low-level input current
WDI = V
= 5 V
150
WDI
(see Note 4)
DD
µA
I
IL
WDI = 0 V,
V
DD
= 5 V
–150
PFI,
MSWITCH
I
I
Input current
–25
25
nA
V
V
= 1.8 V
= 3.3 V
–0.3
–1.1
DD
DD
I
I
Short-circuit output current
PFO
BAT
PFO = 0 V
mA
OS
V
DD
= 5 V
–2.4
40
V
V
V
V
= V
= V
= V
= V
O(OUT)
O(OUT)
O(OUT)
O(OUT)
DD
Supply current at V
µA
DD
DD
40
0.1
0.5
±1
BAT
DD
–0.1
I
I
Supply current (see Figure 2) at V
Leakage current at CEIN
µA
µA
BAT
BAT
Disable mode
lkg
V
V
to OUT on-resistance
V
V
= 5 V
0.6
8
1
DD
DD
r
Ω
DS(on)
to OUT on-resistance
= 3.3 V
15
BAT
BAT
C
Input capacitance
V = 0 V to 5 V
I
5
pF
i
NOTES: 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals.
4. For details on how to optimize current consumption when using WDI. Refer to detailed description section, watchdog.
5. For V
< 1.6 V, V
switches to V regardless of V
BAT BAT
DD
O(OUT)
timing requirements at R = 1 MΩ, C = 50 pF, T = –40°C to 85°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
At V
DD
V
V
= V + 0.2 V,
IT
V
IL
V
= V –0.2 V
IT
6
IH
t
w
Pulse width
At WDI
= V + 0.2 V,
IT
= 0.3 × V
,
V
= 0.7 × V
DD
100
ns
DD
IL
DD
IH
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
switching characteristics at R = 1 MΩ, C = 50 pF, T =–40°C to 85°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
60
TYP
100
0.8
MAX
140
UNIT
ms
s
t
d
Delay time
V
> V +0.2 V
DD
IT
(see timing diagram
Watchdog timeout
0.48
1.12
Propagation (delay) time, low-to-
high-level output
t
15
µs
50% RESET to 50% CEOUT
50% CEIN to 50% CEOUT,
PLH
V
V
V
= 1.8 V
= 3.3 V
= 5 V
15
5
DD
DD
DD
ns
C
= 50 pF only (see Figure 4
L
and Note 6)
3
Propagation (delay) time, high-to-
low-level output
t
PHL
V
V
= V –0.2 V,
IT
IL
IH
V
DD
to RESET
2
3
5
5
= V +0.2 V
IT
µs
µs
V
V
= V
= V
–0.2 V,
PFI
PFI
IL
IH
PFI to PFO
+0.2 V
V
V
V
= V
= V
= V
+ 200 mV,
– 200 mV,
IH
IL
BAT
BAT
BAT
IT
t
t
Transition time
V
DD
to BATTON
3
NOTE 6: Specified by design
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3610U18, TPS3610T50
BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327 – DECEMBER 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2000, Texas Instruments Incorporated
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