TPS3613-50DGSR [ETC]
Analog IC ; 模拟IC\n
ETC 
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
D
D
D
Supply Current of 40 µA (Max)
typical applications
Battery Supply Current of 100 nA (Max)
D
D
D
D
D
D
D
D
D
Fax Machines
Supply Voltage Supervision Range:
– Adjustable
– Other Versions Available on Request
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
D
D
Backup-Battery Voltage Can Exceed V
DD
Power-On Reset Generator With Fixed
100-ms Reset Delay Time
Advanced Modems
Automotive Systems
D
Active-High and Active-Low Reset Output
Portable Long-Time Monitoring Equipment
Point of Sale Equipment
D
Chip-Enable Gating . . . 3 ns (at V
Max Propagation Delay
= 5 V)
DD
D
D
10-Pin MSOP Package
DGS PACKAGE
(TOP VIEW)
Temperature Range . . . –40°C to 85°C
description
V
V
BAT
1
2
3
4
5
10
9
OUT
V
RESET
SENSE
RESET
CEOUT
The TPS3613-01 supervisory circuit monitors and
DD
controls processor activity by providing backup-
battery switchover for data retention of CMOS
RAM.
GND
MR
8
7
6
CEIN
ACTUAL SIZE
3,05 mm x 4,98 mm
typical operating circuit
Address
Power
Decoder
Supply
0.1 µF
Monitored
CE
CMOS
RAM
CE
CMOS
RAM
CEIN
CEOUT
Address Bus
uC
Real-
Time
Clock
Backup
Battery
Voltage
V
DD
V
BAT
R
R
x
y
TPS3613
SENSE
V
V
CC
V
CC
CC
8
8
RESET
RESET
Data Bus
16
MR
Switchover
Capacitor
Manual
Reset
V
OUT
V
CC
0.1 µF
GND
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
description (continued)
During power on, RESET is asserted when the supply voltage (V
or V ) becomes higher than 1.1 V.
Bat
DD
Thereafter,thesupplyvoltagesupervisormonitorsV andkeepsRESEToutputactiveaslongasV remains
DD
DD
below the threshold voltage V . An internal timer delays the return of the output to the inactive state (high) to
IT
ensure proper system reset. The delay time starts after V
has risen above the threshold voltage V .
DD
IT
When the supply voltage drops below the threshold voltage V , the output becomes active (low) again.
IT
The TPS3613-01 is available in a 10-pin MSOP package and is characterized for operation over a temperature
range of –40°C to 85°C.
PACKAGE INFORMATION
T
A
DEVICE NAME
MARKING
†
‡
–40°C to 85°C TPS3613–01DGSR
TPS3613–01DGST
AFK
†
The DGSR passive indicates tape and reel of 2500 parts.
w
ordering information application specific versions
TPS361
3
–
01
DGS
R
NOMINAL VOLTAGE, V
NOM
DEVICE NAME
Adjustable
TPS3613x01 DGS
Reel
Package
Nominal Supply Voltage
Functionality
‡
1.8 V
TPS3613x18 DGS
TPS3613x25 DGS
TPS3613x30 DGS
TPS3613x33 DGS
‡
‡
‡
‡
2.5 V
3.0 V
3.3 V
5.0 V
TPS3613x50 DGS
Family
‡
For the application specific versions please contact the local TI
sales office for availability and lead-time.
FUNCTION TABLE
SENSE > V
V
DD
> V
0
MR
0
CEIN
0
V
OUT
RESET
RESET
CEOUT
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
0
IT
BAT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
V
BAT
V
BAT
V
BAT
V
BAT
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
1
0
0
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
1
0
1
V
1
1
0
V
V
V
V
V
V
V
V
V
V
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
0
DIS
DIS
0
1
0
1
1
1
0
1
1
1
1
functional schematic
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
TPS3613
V
BAT
+
_
Switch
Control
V
OUT
V
DD
R
RESET
Logic
+
MR
RESET
RESET
+
_
SENSE
Timer
Reference
Voltage
V
OUT
or 1.15 V
CEIN
CEOUT
timing diagram
V
DD
V
BAT
V
IT
t
t
t
t
CEIN
15 µs
15 µs
CEOUT
RESET
t
t
t
d
d
d
Undefined Behavior
Terminal Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
TERMINAL
NAME NO.
CEIN
I/O
DESCRIPTION
5
6
I
O
I
Chip-enable input
Chip-enable output
Ground
CEOUT
GND
3
MR
4
I
Manual reset input
Active-high reset output
Active-low reset output
Adjustable sense input
Backup-battery input
RESET
RESET
SENSE
7
O
O
I
9
8
V
BAT
10
I
V
2
1
I
Input supply voltage
Supply output
DD
V
OUT
O
detailed description
backup-battery switchover
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at V , the device automatically switches the connected RAM to backup power when V fails. In
BAT
DD
order to allow the backup battery (e.g., 3.6-V lithium cells) to have a higher voltage than V , these supervisors
DD
OUT
will not connect V
to V
when V
is greater than V . V
only connects to V
(through a 15-Ω
BAT
OUT
BAT
DD BAT
switch) when V
falls below V and V
is greater than V . When V
recovers, switchover is deferred
DD
IT
BAT
DD
DD
eitheruntilV crossesV
,orwhenV risesabovetheresetthresholdV .V
willconnecttoV through
DD
BAT
DD
IT OUT DD
a 1-Ω (max) PMOS switch when V
crosses the reset threshold.
DD
V
>V
V
>V
V
OUT
DD BAT
1
DD IT
1
0
1
0
V
DD
DD
DD
1
0
0
V
V
V
BAT
V
DD
– Mode
V
IT
Hysteresis
V
BAT
– Mode
VBSW Hysteresis
Undefined
V
BAT
– Backup-Battery Supply Voltage
Figure 1. V
– V
Switchover
BAT
DD
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
detailed description (continued)
chip-enable signal gating
The internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM during
an under-voltage condition. The TPS3613 use a series transmission gate from CEIN to CEOUT. During normal
operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short
CE propagation delay from CEIN to CEOUT enables the TPS3613 device to be used with most processors.
chip-enable signal gating (continued)
The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted.
During a power-down sequence when V
crosses the reset threshold, the CE transmission gate will be
DD
disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low when
reset is asserted, the CE transmission gate will be disabled same time when CEIN goes high, or 10 µs after reset
asserts, whichever occurs first. This will allow the current write cycle to complete during power down. When the
CE transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT.
The overall device propagation delay through the CE transmission gate depends on V
, the source
OUT
impedance of the drive connected to CEIN, and the load at CEOUT. To achieve minimum propagation delay,
the capacitive load at CEOUT should be minimized, and a low-output-impedance driver is used.
In the disabled mode, the transmission gate is off and an active pullup connects CEOUT to V
turns off when the transmission gate is enabled.
. This pullup
OUT
V
DD
V
BAT
V
IT
t
CEIN
t
CEOUT
V
BAT
t
RESET
t
t
d
d
t
Figure 2. Chip-Enable Timing
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
detailed description (continued)
V
V
DD
DD
V
BAT
SENSE
SENSE
3.6 V
TPS3613
50-Ω Cable
CEIN
CEOUT
50 Ω
†
C
L
50 Ω
50 pF
GND
{
C
Includes load capacitance and scope probe capacitance.
L
Figure 3. CE Propagation Delay Test Circuit
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous output current at V , I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
OUT O
Continuous output current (all other pins), I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h
continuously.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DGS
424 mW
3.4 mW/°C
271 mW 220 mW
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
recommended operating conditions
MIN
1.65
1.5
MAX
5.5
UNIT
V
Supply voltage, V
DD
Battery supply voltage, V
5.5
V
BAT
Input voltage, V
0
V
DD
+ 0.3
V
I
High-level input voltage, V
IH
0.7 x V
V
DD
Low-level input voltage, V
0.3 x V
300
100
1
V
IL
Continuous output current at V
DD
, I
mA
ns/V
V/µs
°C
OUT O
Input transition rise and fall rate at MR, ∆t/∆V
Slew rate at V or V
DD
bat
Operating free-air temperature range, T
–40
85
A
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 1.8 V
I
= –400 µA
V
V
V
V
– 0.2 V
DD
OH
DD
DD
DD
DD
RESET
RESET
V
DD
V
DD
= 3.3 V,
= 5 V,
I
I
= –2 mA
= –3 mA
OH
OH
– 0.4 V
– 0.3 V
– 0.4 V
– 0.2 V
– 0.3 V
V
DD
= 1.8 V,
I
= –20 µA
OH
V
DD
V
DD
= 3.3 V,
= 5 V,
I
I
= –80 µA
= –120 µA
OH
OH
V
OH
High-level output voltage
V
CEOUT
V
OUT
= 1.8 V, I
= –1 mA
V
V
OH
OUT
Enable mode
V
OUT
V
OUT
= 3.3 V, I
= 5 V,
= –2.0 mA
= –5.0 mA
OH
OH
OUT
CEIN = V
I
OUT
CEOUT
Disable mode
RESET
V
V
= 3.3 V, I
= –0.5 mA
V
OUT
– 0.4 V
OUT
OH
OL
= 1.8 V,
I
= 400 µA
0.2
0.4
0.2
0.3
DD
V
V
= 3.3 V,
= 5 V,
I
I
= 2.0 mA
= 3.0 mA
DD
DD
OL
OL
RESET
V
OL
Low-level output voltage
V
V
CEOUT
V
OUT
= 1.8 V, I
= 1.0 mA
OL
Enable mode
CEIN = 0 V
V
OUT
V
OUT
= 3.3 V, I
= 5 V,
= 2 mA
= 5 mA
OL
OL
I
V
> 1.1 V or V
= 20 µA
> 1.1 V,
DD
BAT
V
res
Power-up reset voltage (see Note 2)
0.4
I
OL
I
V
= –8.5 mA,
OUT
DD
V
DD
– 50 mV
= 1.8 V,
V
BAT
= 0 V
= 0 V
= 0 V
I
V
= –125 mA
OUT
V
DD
– 150 mV
– 200 mV
Normal mode
= 3.3 V, V
DD
BAT
I
V
= –200 mA
OUT
V
DD
V
OUT
V
= 5 V,
V
BAT
DD
I
V
= –0.5 mA
= 1.5 V, V
OUT
BAT
V
BAT
– 20 mV
= 0 V
DD
Battery-backup mode
I
V
= –7.5 mA
= 3.3 V, V
OUT
BAT
V
BAT
– 113 mV
= 0 V
DD
NOTE 2: The lowest supply voltage at which RESET becomes active. t
≥ 15 µs/V.
r,(VDD)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
on-resistance
TEST CONDITIONS
MIN
TYP
0.6
MAX
UNIT
Ω
V
V
to V
V
V
= 5 V
1
DD
OUT
to V
DD
R
DS(on)
on-resistance
= 3.3 V
8
1.15
12
15
BAT
OUT
BAT
V
V
Negative-going input threshold voltage (see Note 3)
1.13
1.17
V
IT
Sense
1.1 V < V < 1.65 V
IT
Hysteresis
mV
hys
V
(see Note 4)
VDD = 1.8 V
55
BSW
MR
SENSE
I
I
I
High-level input current
Low-level input current
Input current
MR = 0.7 x V , V
= 5.0 V
= 5.0 V
–33
–110
–25
–76
–255
25
IH
DD DD
µA
nA
µA
MR = 0 V, V
IL
I
DD
= 1.15 V
V
V
V
V
V
DD
= V
= V
= V
= V
40
OUT
OUT
OUT
OUT
DD
I
V
supply current
DD
DD
40
BAT
DD
–0.1
0.1
0.5
±1
I
I
V
BAT
supply current
µA
BAT
BAT
CEIN leakage current
Input capacitance
Disable mode, V < V
µA
lkg
I
DD
C
V = 0 V to 5 V
5
pF
i
I
NOTES: 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals.
4. For V < 1.6 V, V switches to V regardless of V
DD
OUT
BAT
BAT
timing requirements at R = 1 MΩ, C = 50 pF, T = –40°C to 85°C
L
L
A
PARAMETER
SENSE
MR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
V
V
= V + 0.2 V,
IT
V
V
= V – 0.2 V
IT
6
IH
IL
t
w
Pulse width
> V + 0.2 V
IT
= 0.3 x V
,
V
= 0.7 x V
DD
100
ns
SENSE
IL
DD
IH
switching characteristics at R = 1 MΩ, C = 50 pF, T = –40°C to 85°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
60
TYP
MAX
UNIT
V
≥ V + 0.2 V,
IT
SENSE
t
d
Delay time
MR ≥ 0.7 x V
,
100
140
ms
DD
See timing diagram
50% RESET to 50% CEOUT
SENSE to RESET
V
= V
15
2
OUT
IT
V
V
= V – 0.2 V,
IT
5
1
IL
IH
= V + 0.2 V
Propagation (delay) time,
low-to-high-level output
IT
t
µs
PLH
V
V
V
≥ V + 0.2 V,
= 0.3 x V
= 0.7 x V
0.1
SENSE
IL
IH
IT
DD
DD
,
MR to RESET
5
1.6
1
15
5
50% CEIN to 50% CEOUT,
V
V
V
= 1.8 V
= 3.3 V
= 5 V
DD
DD
DD
C
= 50 pF only (see Figure 3)
L
(see Note 5)
ns
50% CEIN to 50% CEOUT,
C
= 50 pF only (see Figure 3)
3
L
Propagation (delay) time,
high-to-low-level output
(see Note 5)
t
PHL
V
V
= V – 0.2 V,
2
5
IL
IH
IT
µs
µs
SENSE to RESET
= V + 0.2 V
IT
V
V
V
≥ V + 0.2 V,
IT
= 0.3 x V
= 0.7 x V
0.1
1
3
SENSE
IL
IH
,
MR to RESET
DD
DD
V
V
V
= V
= V
< V
+ 0.2 V,
– 0.2 V,
IH
IL
BAT
BAT
BAT
IT
Transition time
V
DD
to V
µs
BAT
NOTE 5: Assured by design
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3613-01
ADJUSTABLE BATTERY-BACKUP SUPERVISOR
FOR RAM RETENTION
SLVS340 – DECEMBER 2000
MECHANICAL DATA
DGS (S-PDSO-G10)
PLASTIC SMALL-OUTLINE PACKAGE
0,27
0,17
M
0,25
0,50
10
6
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–ā6°
1
5
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073272/A 03/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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