TPS5300DAP [ETC]
Analog IC ; 模拟IC\n
| 型号： | TPS5300DAP |
| 厂家： | 
ETC |
| 描述： | Analog IC
|
| 文件： | 总16页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
DAP PACKAGE
(TOP VIEW)
D
D
Single-Chip Speed Step Solution
Hysteretic Controller Provides Fast
Transient Response Time and Reduced
Output Capacitance
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DRV_CLK
VSENSE_CLK
DT_SET
ANAGND
VSENSE_CORE
SLOWST
VREFB
DRV_IO
VSENSE_IO
VBIAS
ENABLE_EXT
RAMP
VID0
VID1
VID2
VID3
VID4
2
3
D
D
Two Linear Regulator Controllers
Regulating Clock and I/O Voltages
4
5
Internal 2-A (Typ) Gate Drivers With
Bootstrap Diode Which Increase Efficiency
6
7
D
5-Bit Dynamic VID
8
VHYST
OCP
DROOP
9
D
Active Droop Compensation Enables Tight
Dynamic Regulation for Reduced Output
Capacitance
10
11
12
13
14
15
16
IOUT
PSM/LATCH
IS–
VR_ON
BOOT
TG
D
Power Saving Mode (PSM) Promotes Long
Battery Life
IS+
VGATE
DRVGND
PH
D
High Bandwidth Current Sense Amplifier
V
CC
D
Adaptive Dead-Time Control Circuit
Prevents Cross Conduction
BG
D
D
OVP, OCP, UVLO, UVP, and Thermal System
Protection
VGATE Terminal Provides Power-Good
Signal for All Three Outputs
D
Enable External Terminal (ENABLE_EXT)
D
32-Pin TSSOP PowerPAD Enhances
Thermal Performance
D
1% Reference Voltage Accuracy
description
The TPS5300 is a hysteretic synchronous-buck controller, with two on-chip linear regulator controllers,
incorporating speed-step output voltage positioning technology. The TPS5300 provides a precise,
programmable supply voltage to a mobile processor. A ripple regulator provides the core voltage, while two
linear regulator drivers regulate external NPN power transistors for the I/O and CLK voltages. A 5-bit voltage
identification (VID) DAC allows programming for the ripple regulator voltage to values between 0.925 V to
1.275 V in 25 mV steps and 1.30 V to 2 V in 50 mV. The fast transient response time and active voltage DROOP
positioning reduce the number of output capacitors required to keep the output voltage within tight dynamic
voltage regulation limits. The power saving mode (PSM) allows the user to select a single operating ramp or
allows the controller to automatically switch to lower frequencies at low loads. The high-gain current sense
differential amplifier allows the use of small-value sense resistors that minimize conduction losses. The
TPS5300 includes high-side and low-side gate drivers rated at 2 A typical, that enable efficient operation at
higher frequencies and drive larger or multiple power MOSFETs. An adaptive dead-time circuit minimizes
dead-time losses while preventing cross-conduction of high-side and low-side switches. All three outputs power
up together as they track the same user programmable slowstart voltage. The enable external (ENABLE_EXT)
terminal allows the TPS5300 to activate external switching controllers for additional system power
requirements. The TPS5300 features undervoltage lockout, overvoltage, undervoltage, and
user-programmable overcurrent protection, and is packaged in a small 32-pin TSSOP PowerPAD package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
functional schematic
32
31
29
15
1
2
9
11
10
Protection Circuitry
V
V
is dominant if
< V CLK
ref
SS
SS
22
VR_ON
UVLO Enables
IC When
VR_ON > 2.5 V
and
UVLO
V
SS
V
> 4.46 V
BIAS
13
14
V
CLK
IS–
IS+
ref
x 25
OCP_OVP
Enables Device
When
Shutdown
PWRGD
is LOW if
OCP Core > 200 mV
Vss is dominant
OCP_OVP
V
Vsense Core
or Vsense IO
or Vsense CLK
> 0.93 of their
BIAS
or Vsense Core
if Vss < V IO
PWRGD
ref
or Vsense IO
30
or Vsense CLK
> 1.15 of their Vref
BIAS
V
SS
V
ref
V
CC
V
ref
IO
UVP is
Enabled When
SS
18
V
V
> V CLK,
Q
S
ref
Shutdown
(+5 V)1
CC
and
Vsense Core
or Vsense IO
or Vsense CLK
< 0.75 of their
Vref
ShutdownB
Clock and IO
Regulator
Drivers
Q
R
UVP
21
Latch
BOOT
disabled
20
19
TG
PH
Core Voltage
Regulator
Controller
V
is dominant if V
< V
SS ref
SS
_
27
26
VID0
VID1
VID2
VID3
V
ref
+
V
17
16
SS
BG
V
CC
Bandgap
25
24
23
V
ref
DRVGND
and DAC
Power
Save
Mode
4
ANAGND
Hyst.
Set
VID4
Control
7
8
6
3
5
12
28
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
Terminal Functions
TERMINAL
NAME
ANAGND
I/O
DESCRIPTION
NO.
4
Analog ground
BG
17
21
O
I
Bottom gate drive. BG is an output drive to the low-side synchronous rectifier FET.
BOOT
Bootstrap. Connect a 1-µF low ESR ceramic capacitor to PH to generate a floating drive for the high-side
FET driver.
DROOP
10
1
I
Active voltage droop position voltage. DROOP is a voltage input used to set the amount of output-voltage,
set-pointdroop as a function of load current. The amount of droop compensation is set with a resistor divider
between IOUT and ANAGND. A voltage divider from V to VSENSE_CORE sets the no load offset.
O
DRV_CLK
O
CLK voltage regulator. DRV_CLK drives an external NPN bipolar power transistor for regulating CLK
voltage to VREF_CLK.
DRVGND
DRV_IO
DT_SET
16
32
3
Drive ground. Ground for FET drivers. Connect to FET PWRGND
O
I
Drives an external NPN bipolar power transistor for regulating IO voltage to VREF_IO.
DT_SET sets the transition time for speed step output voltage positioning. Attach a capacitor from DT_SET
to ground to program time.
ENABLE_EXT
29
O
Open drain output. ENABLE_EXT enables external converters when the internal enable signal is high
(good),anddisableswhenthereisafaultwithanyregulator(OVP, UVP, OCPrr), VR_ON UVLO is low, orthe
VBIAS UVLO is low. Can be connected to the enable terminal of an external linear regulator or switching
controller. A pullup resistor is required to set the desired voltage rail.
IS–
IS+
13
14
I
I
Current sense negative Kelvin connection. Connect to the node between the current sense resistor and the
output capacitors. Keep the PCB trace short and route trace next to the IS+ trace to help reduce loop
inductance noise pickup and cancel common mode noise through mutual coupling.
Current sense positive Kelvin connection. Connect to the node between the output inductor and the current
sense resistor. Keep the PCB trace short and route trace next to the IS-trace to help reduce loop inductance
noise and cancel common mode noise through mutual coupling.
IOUT
11
9
O
I
Current sense differential amplifier output. The voltage on IOUT equals 25 x (V
– V ) = 25 x
I(–)
I(+)
(R
x I ).
L
(sense)
Overcurrentprotection. CurrentlimittrippointissetwitharesistordividerbetweenIOUTandANAGND. The
typicalOCPtrippointshouldbesetat1.30×I .TheOCPvoltagealsosetsthePSMautomatictrippoints.
OCP
(max)
PH
19
12
I/O Phasevoltagenode. PHisusedforbootstraplowreference. PHconnectstothejunctionofthehigh-sideand
low-side FET’s.
PSM/LATCH
I
PSM. Power saving mode boosts efficiency at low load current by automatically decreasing the switching
frequency toward the natural converter operating frequency. A logic low (<1.8) disables PSM, maintaining
the higher switching frequency range set by CT.
LATCH. Allows disabling fault latch. Recommend enabling fault latch protection
RAMP
28
6
I
I
Setsaramponthefeedbacksignaltoincreasetheswitchingfrequency.AddaresistorfromPHtoRAMPand
connect RAMP to VSENSE_CORE for a dc-coupled ramp. Add a capacitor from RAMP to VSENSE_CORE
to set an ac-coupled ramp.
SLOWST
Slow start (soft start). A capacitor from SLOWST to GND sets the slowstart time for the ripple regulator and
the two linear regulators. The three converters will ramp up together while tracking the output voltage. A
current equal to IVrefb/5 charges the capacitor.
TG
20
30
18
15
O
I
Top gate drive. TG is an output drive to the high-side power switching FET’s. It is also used in the
anticross-conduction circuit to eliminate shoot-through current.
VBIAS
AnalogVBIAS.Itisrecommendedthatatleasta1-µFcapacitorbeconnectedtoANAGND.SupplyfromV
through RC filter
CB
V
CC
Supply voltage. V
is the supply voltage for the FET drivers. Add an external resistor/capacitor filter from
VCC to VBIAS. It is recommended that a 1-µF capacitor be connected to the DRVGND terminal.
CC
VGATE
O
Logical and output of the combined core, IO, and CLK powergoods. VGATE outputs a logic high when all
(core, IO, CLK)outputvoltagesarewithin7%ofthereferencevoltage. Anopendrainoutputallowssettingto
desired voltage level through a pullup resistor.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
Terminal Functions (Continued)
TERMINAL
NAME
VHYST
I/O
DESCRIPTION
NO.
8
I
Ripple regulator hysteresis set terminal. The hysteresis is set with a resistor divider from VREFB to GRD.
The hysteresis voltage window will be ± the voltage between VREFBand VHYST.
VID0
VID1
VID2
VID3
VID4
VREFB
27
26
25
24
23
7
I
I
Voltage identification inputs 0, 1, 2, 3, and 4. These terminals are digital inputs that set the output voltage of
theconverter. The code pattern for setting the output voltage islocatedintheterminalfunctionstable. These
terminals are internally pulled up to VBIAS.
I
I
I
O
I
Buffered ripple regulator reference voltage from VID network
VR_ON
22
Enables the drive signals to the MOSFET drivers. It is recommended that an external pullup resistor be
connected to 5 V.
VSENSE_CLK
2
5
I
I
CLK feedback voltage sense. Connect to CLK linear regulator output voltage to regulate
VSENSE_CORE
Feedback voltage sense input for the core. Connect to ripple regulator output voltage to sense and regulate
output voltage. It is recommended that an RC low-pass filter be connected at this pin to filter high frequency
noise.
VSENSE_IO
31
I
I/O feedback voltage sense. Connect to I/O linear regulator output voltage to regulate
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V : VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
VR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VID0, VID1, VID2, VID3, VID4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
PSM/LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
IS–, IS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
VSENSE_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VSENSE_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VSENSE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
All other input terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
BOOT to DRVGND voltage (high-side driver on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
BOOT to PH voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
BOOT to TG voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
PH to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 35 V
ANAGND to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Output voltage, V : VGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
O
ENABLE_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Continuous power dissipation, P : Without PowerPad soldered, T = 25°C, T = 125°C . . . . . . . . . . . 1.2 W
D
A
J
With PowerPad soldered, T = 25°C, T = 125°C . . . . . . . . . . . . . 6.25 W
C
J
Operating junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
J
Storage temperature, T
Lead temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
(soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
stg
(lead)
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
dc and ac recommended operating conditions, 0 < T < 125°C (unless otherwise noted)
J
MIN NOM
MAX
UNIT
Supply voltage, V
batt
3
3
12.5
3.3
5
28
6
V
V
V
Linear regulator supply voltage, V
I(IO+CLK)
Supply voltage range, V , VBIAS
CC
4.5
6
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 4.3 V – 28 V (unless otherwise noted)
IN
PARAMETER
Reference/Voltage Identification
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-level input voltage,
D0–D4
V
Current source pullup to V
CC
2.25
V
V
IH(VID)
IL(VID)
Low-level input voltage,
D0–D4
V
1
Cumulative Reference (see Note 1)
0.925 V ≤ V
ref(core)
≤ 2 V,
–1.5%
–1%
1.5%
1%
Hysteresis window = 30 mV
Initial accuracy ripple regula-
tor
V
0.925 V ≤ V ≤ 2 V,
(CUM_ACCRR)
ref(core)
T = 25°C (see Note 2)
J
Hysteresis window = 30 mV
Buffered Reference
Output voltage, VREFB
Hysteretic Comparator (core)
V
I
= 50 µA
V
ref
– 5 mV
V
ref
V – 5 mV
ref
V
O(VREFB)
(REFB)
V
V
V
Input offset voltage
V
V
pin grounded (see Note 2)
–4
–5
60
4
5
mV
mV
mV
OS(HYSCMPrr)
(DROOP)
– V
= 15 mV
(VHYST)
(VREFB)
Hysteresis accuracy
hys(ACCrr)
(Hysteresis window = 30 mV)
Maximum hysteresis setting
hys(SETrr)
Propagation delay time from
(AC) VSENSE_CORE to TG
or BG (excluding deadtime)
10-mV overdrive,
t
220
250
225
ns
PHL(HC)
0.925 V ≤ V ≤ 2 V, (see Note 2)
ref
Overcurrent Protection (core)
Trip point, OCP
Overvoltage Protection (core, IO, CLK)
Normal operation
180
112
70
200
300
V
mV
(OCP)
During dynamic VID change
V
V
Trip point, OVP
Hysteresis
Upper threshold
115
10
120 %V
ref
(OVP)
Upper-lower thresholds (see Note 2)
mV
hys(OVP)
Undervoltage Protection (IO, CLK)
V
V
Trip point, UVP
Hysteresis
Lower threshold
75
10
80 %V
ref
(UVP)
Upper-lower thresholds (see Note 2)
mV
hys(UVP)
NOTES: 1. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals to the average of the low-level and high-level thresholds of the hysteretic comparator.
2. Ensured by design, not production tested.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 4.3 V – 28 V (unless otherwise noted) (continued)
IN
PARAMETER
Bias UVLO (Resets fault latch)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Start threshold
Stop threshold
4.46
V
V
IT(startUVLO)
IT(stopUVLO)
V
3.3
VR_ON connected to GND and V above
I
UVLO start threshold
VBIAS quiescent current, I
(ving1)
10
15
µA
VR_ON UVLO (Resets fault latch)
V
V
Start threshold
Stop threshold
2.1
2.5
V
V
IT(startVRON)
1.3
IT(stopVRON)
Slowstart
V
= 0.5 V,
I
= 65 µA VREFB
(SS)
= 1.3 V;
(VREFB)
I
Charge current (I
= (I /5)
(REFB)
10.4
13
3
15.6
µA
(chg)
(chg)
I
= (I
/5)
(chg)
= 1.3 V,
(VREFB)
= 4.5 V
V
(SS)
Design for V
I
Discharge current
mA
(dischg)
IN(min)
VGATE (CORE, IO, CLK) (PWRGD of three outputs with open drain output)
Undervoltage trip point
(VSENSE_CORE, _IO, & _CLK)
V
V
and V above UVLO thresholds
(drv)
87.5
90
92.5 %Vref
(VGATE)
IN
= 2.5 mA
O
V
Output saturation voltage
I
0.5
0.75
0.75
V
V
(olVGATE)
Enable EXT (SHUTDOWNB of IC with open-drain output. Use pullup resistor to 5 V or 3.3 V)
V
Output saturation voltage
I
O
= 2.5 mA
0.5
(olEN_EXT)
DROOP Compensation
V
Initial accuracy
V
= 50 mV
–4
8
mV
ns
(DROOP_ACC)
(DROOP)
15-mV to 150-mV swing,
1.3 V ≤ V ≤ 3.3 V, V
(see Note 2)
t
Propagation delay
= 5 V
CC
200
25
500
PHL(HC)
ref
Current Sensing
With chopper stabilization (backup dis-
able with metal mask)
G
Gain
24
–3
26
3
V/V
mV
(CS)
V
IO
Input offset
V
IS–
= 1.3 V,
V
– V
= 10 mV
IS+
IS–
V
IS–
V
IS–
V
CC
= 0.925 V – 2 V, V
is pulsed from
IS+
Response time (measured from 50% of
t
to (V
+ 50 mV),
500
ns
(VDSRESP)
IS–
= 5 V (see Note 2)
(V
IS+
– V
) to 50% of V )
(IOUT)
IS–
NOTES: 2. Ensured by design, not production tested.
3. The VBIAS voltage is required to be a quiet bias supply for the TPS5300 control logic. External noisy loads should use VCC instead
of the VBIAS voltage.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 4.3 V – 28 V (unless otherwise noted) (continued)
IN
PARAMETER
PSM/LATCH Power Saving Mode (PSM Comparator)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
V
V
PSM comparator start threshold
PSM comparator stop threshold
2.1
2.3
V
V
(startINH)
(stopINH)
(PSMth1)
(PSMth2)
(PSMth3)
(PSMth4)
1.8
54
39
24
9
60
45
30
15
66
51
36
21
Sweep OCP through thresholds
PH to Ct, PSM = GND,
OCP voltage trip points for PSM
mV
R
R
R
R
V
– V = 60 mV
(IS–)
5.3
8
6.67
10
8
12
24
(tPSM1)
(tPSM2)
(tPSM3)
(tPSM4)
(IS+)
(see Note 3)
PH to Ct, PSM = GND,
– V = 45 mV
V
kΩ
(IS+)
(IS–)
(see Note 3)
PSM ramp timing resistance
PH to Ct, PSM = GND,
– V = 30 mV
V
16
1
20
(IS+)
(IS–)
(see Note 3)
PH to Ct, PSM = GND,
– V = 15 mV
V
MΩ
(IS+)
(IS–)
(see Note 3)
PSM/LATCH Fault Latch Disable
Disable latch threshold PSM
enabled
V
VBIAS + 0.3
ANAGND
V
(No_Latch/PSM)
Disable latch threshold PSM
disabled
V
V
ANAGND – 0.3
VBIAS
V
V
(No_Latch)
Enable latch threshold
(Latch_enabled)
Thermal Shutdown
T
T
Over temperature trip point
Hysteresis
See Note 2
See Note 2
160
10
°C
°C
(OTP)
(hyst)
Dynamic VID Change (No current limit)
Voltage change timing current
NOTES: 2. Ensured by design, not production tested.
V
V
= 5 V,
= 2 V,
CC
(ref1)
Ι
13.3
14
14.7
µA
∆tSRC
DT_SET = 0.925 V
3. The BIAS voltage is required to be a quiet bias supply for the TPS5300 control logic. External noisy loads should use VCC instead
of the BIAS voltage.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 4.3 V – 28 V (see test circuits) (unless otherwise noted) (continued)
IN
PARAMETER
Output Drivers (see Note 4)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Duty cycle < 2%, tpw < 100 µs,
I
I
V
V
– V = 4.5 V,
(PH)
(PH)
1.2
1.2
2
A
A
O(srcTG)
(BOOT)
– V
= 0.5 V (src)
(TG)
Duty cycle < 2%, tpw < 100 µs,
V
V
– V = 4.5 V,
(PH)
3.3
O(sinkTG)
(BOOT)
– V
Peak output current (see Notes 2 and 4)
= 4 V (sink)
(TG)
(PH)
Duty cycle < 2%, tpw < 100 µs,
= 4.5 V, V = 0.5 V (src)
I
I
1.4
1.3
2
A
A
O(srcBG)
V
CC
(BG)
Duty cycle < 2%, tpw < 100 µs,
3.3
O(sinkBG)
V
V
V
V
V
= 4.5 V, V
= 4 V (src)
(BG)
CC
r
r
r
r
– V
– V
= 4.5 V, V
= 4.5 V, V
= 4 V
2.5
1.5
2.5
1.5
Ω
Ω
Ω
Ω
o(srcTG)
o(sinkTG)
o(srcBG)
o(sinkBG)
f(TG)
(BOOT)
(BOOT)
(PH)
(PH)
TG
TG
= 0.5 V
Output resistance (see Note 4)
= 4.5 V, V
= 4.5 V, V
= 4 V
CC
CC
(BG)
(BG)
= 0.5 V
t
t
t
t
TG fall time (AC) (see Note 5)
TG rise time (AC) (see Note 5)
BG fall time (AC) (see Note 5)
BG rise time (AC) (see Note 5)
C = 3.3 nF, V
= 4.5 V,
l
(BOOT)
10
10
ns
ns
V
(PH)
= GND
r(TG)
f(BG)
C = 3.3 nF, V
l CC
= 4.5 V
r(BG)
High-Side DRIVER Quiescent Current
VR_ON grounded, or VCC below
Ihighdrq1
HIGHDRIVE (TG) quiescent current
UVLO threshold; V
PH grounded
= 5 V,
10
µA
(BOOT)
Adaptive Deadtime Circuit
V
V
V
V
TG – PH High-level input voltage
TG – PH Low-level input voltage
BG High-level input voltage
BG Low-level input voltage
2.4
3
IH(TG)
IL(TG)
IH(BG)
IL(BG)
1.33
V
= 0.925 V – 2 V (see Note 2)
V
(IS–)
1.7
50
CBG = 9 nF, 10% threshold on BG,
= 5 V
t
Driver nonoverlap time (AC)
ns
(NUL)
V
CC
NOTES: 2. Ensured by design, not production tested.
4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar
and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET
transistors. The output resistance is the r
saturation voltage of the bipolar transistor.
of the MOSFET transistor when the voltage on the driver output is less than the
ds(on)
5. Rise and fall times are measured from 10% to 90% of pulsed values.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 4.3 V – 28 V (see test circuits) (unless otherwise noted) (continued)
IN
PARAMETER
Linear Regulator OUTPUT DRIVERs (IO, CLK) (see Note 4)
= 5 V,
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
I
VSENSE_IO = 0.9 × V
(see Note 2)
134
14
mA
O(srcLDODR)
(REFIO)
(REFIO)
Peak output current linear
regulator driver IO
V
= 5 V,
CC
I
VSENSE_IO = 1.1 × V
µA
O(sinkLDODR)
(see Note 2)
V
V
= 5 V, V = 1.5 V, I = 1 A
ref
–1.65%
–1.5%
1.65%
1.5%
CC
O
Initial accuracy IO condition:
closed loop; linear regulator
V
= 5 V, V = 1.5 V, I = 1 A,
(CUM_ACC IO)
CC
ref
O
T = 25°C (see Note 2)
J
V
= 5 V,
≥ 15, 0 ≤ I
CC
V
V
Load regulation IO
25
mV
mV
(Load Reg IO)
β
≤ 2 A, (see Note 2)
NPN
Load
5.5 V ≥ V
3 V ≤ V (IO) ≤ 6 V, (see Note 2)
IN
≥ 4.5 V,
CC
VIN line regulation IO
5
(IN Line Reg IO)
V
= 5 V,
CC
I
VSENSE_IO = 0.9 × V
10
14
mA
O(srcLDODR)
O(sinkLDODR)
(REFIO)
(REFIO)
(see Note 2)
Peak output current regulator,
driver CLK
V
= 5 V,
CC
I
VSENSE_IO = 1.1 × V
µA
(see Note 2)
Initial accuracy CLK condi-
tion: closed loop
V
V
= 5 V, V = 2.5 V, I = 75 mA
ref
–1.55%
–1.5%
1.55%
1.5%
CC
O
V
(CUM_ACCCLK)
= 5 V, V = 2.5 V, I = 75 mA,
CC
ref
O
Linear regulator
T = 25°C, (see Note 2)
J
V
= 5 V
≥ 15, 0 ≤ I
CC
V
V
Load regulation CLK
Line regulation CLK
β
≥ 150 mA,
5
5
mV
mV
(LoadRegCLK)
NPN
Load
(see Note 2)
5.5 V ≥ V
≥ 4.5 V,
CC
IN(LineRegCLK)
3 V ≤ V (CLK) ≤ 6 V, (see Note 2)
IN
NOTES: 2. Ensured by design, not production tested.
4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar
and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET
transistors. The output resistance is the r
saturation voltage of the bipolar transistor.
of the MOSFET transistor when the voltage on the driver output is less than the
ds(on)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
Table 1. Voltage Programming Code
VID PINS
0 = GROUND, 1 = FLOATING, OR PULLUP TO 5 V
V
ref
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(Vdc)
No CPU – Off
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
No CPU – Off
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
NOTE: If the VID bits are set to 11111 or 01111, then the high-side and low-side driver outputs
will be set low..
Table 2. PSM Program Modes
Pin Voltage
< (ANAGND – 0.3 V)
ANAGND to 1.8 V
2.3 V to VBIAS
Function
1
2
3
4
Disable PSM and disable fault latch
Disable PSM and enable fault latch
Enable PSM and enable fault latch
Enable PSM and disable fault latch
> (VBIAS + 0.3 V)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
detailed description
reference/voltage identification
The reference /voltage programming (VP) section consists of a temperature-compensated, bandgap reference
and a 5-bit voltage selection network. The five VID pins are inputs to the VID selection network and are TTL
compatible inputs that are internally pulled up to V
with pullup resistors. The internal reference voltage can
CC
be programmed from 0.925 V to 2 V with the VID pins. The VID codes are listed in Table 1. The output voltage
of the VP network, V , is within ±1.5% of the nominal setting. The ±1.5% tolerance is over the full VP range
ref
of 0.925 V to 2 V, and includes a junction temperature range of 0°C to 125°C, and a V
range of 4.5 V to 5.5
CC
V. The output of the reference/VP network is indirectly brought out through a buffer to the VREFB pin. The
voltage on this pin will be within ±5 mV of V . It is not recommended to drive loads with VREFB, other than
ref
setting the hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging
current for the slowstart capacitor. Refer to the slowstart section for additional information.
dynamic VID change
Dynamic VID change controls the rate of change of the programmed VID to allow transitioning within 100 µs,
while controlling the dv/dt to avoid large input surge currents. VID could change with any input voltage, output
voltage, or output current. A new change is ignored until the current transition is finished. Program the transition
by adding a capacitor from DT_SET to ANAGND.
I
Dt
REF
14 µA Dt
* V
Dt
CDT_SET
+
+
DV
V
REF2
REF1
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by two external resistors and is centered around VREFB. The two external resistors form a resistor divider
from VREFB to ANAGND, and the divided down voltage connects to the VHYST terminal. The hysteresis of the
comparator will be equal to twice the voltage that is across the VREFB and VHYST pins. The maximum
hysteresis setting is 60 mV.
ramp generator
The ramp generator circuit is partially composed of the PSM circuit. An external resistor from PH to
VSENSE_CORE superimposes a ramp (proportional to V and V ) onto the feedback voltage. This allows
I
O
increasing the operating frequency, and reduces frequency dependance on the output filter values. A capacitor
can be used to provide ac-coupling. Also, connecting a resistor from V to VSENSE_CORE allows feed forward
I
to counteract any dc offsets due to the ramp generator or propagation delays limiting duty cycle.
power saving mode/latch
The power saving mode circuit reduces the operating frequency of the ripple regulator during light load. This
helps boost the efficiency during light loads by reducing the switching losses. Care should be taken to not allow
rms current losses to exceed the switching losses. A 2-bit binary weighted resistor ramp circuit allows setting
four operating frequencies.
The PSM/LATCH terminal allows disabling of the fault latch (see Table 2). This allows the user to troubleshoot
or implement an external protection circuit.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
detailed description (continued)
active voltage DROOP positioning
The droop compensation network reduces the load transient overshoot/undershoot on V , relative to V
.
O
ref
V
is programmed to a voltage greater than V in the mechanical data drawing by an external resistor
O(max)
ref
divider from V to the VSENSE pin to reduce the undershoot on V
during a low to high load transient. The
O
OUT
overshoot during a high to low load transient is reduced by subtracting the voltage that is on the DROOP pin
from V . The voltage on the IOUT pin is divided down with an external resistor divider, and connected to the
ref
DROOP pin. Thus, under loaded conditions, V is regulated to V
– V
. The continuous sensing
O
O(max)
(DROOP)
of the inductor current allows a fast regulating voltage adjustment allowing higher transient repetition rates.
low-side driver
The low-side driver is designed to drive low r
, N-channel MOSFETs. The current of the driver is typically
ds(on)
2-A source and 3.3-A sink. The supply to the low-side driver is internally connected to V
.
CC
high-side driver
The high-side driver is designed to drive low r
N-channel MOSFETs. The current of the driver is typically
ds(on)
2-A source and 3.3-A sink. The high-side driver is configured as a floating bootstrap driver. The internal
bootstrap diode, connected between the DRV and BOOT pins, is a Schottky diode for improved drive efficiency.
The maximum voltage that can be applied between the BOOT pin and ground is 35 V.
deadtime control
The deadtime control prevents shoot-through current from flowing through the main power FET’s during the
switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not
allowed to turn on until the gate drive voltage to the low-side FET is below 1.7 V. The low-side driver is not
allowed to turn on until the gate drive voltage from high-side FET to PH is below 1.3 V.
current sensing
Current sensing is achieved by sensing the voltage across a current-sense resistor placed in series between
the output inductor and the output capacitors. The sensing network consists of a high bandwidth differential
amplifier with a gain of 25x to allow using sense resistors with values as low as 1 mΩ. Sensing occurs at all times
toallowhavingrealtimeinformationforquickresponseduringanactivevoltagedrooppositioningtransition. The
voltage on the IOUT pin equals 25 times the sensed voltage.
VR_ON
The VR_ON terminal is a TTL compatible digital pin that is used to enable the controller. When VR_ON is low,
the output drivers are low, the linear regulator drivers are off, and the slowstart capacitor is discharged. When
VR_ON goes high, the short across the slowstart capacitor is released and normal converter operation begins.
When the system logic supply is connected to the VR_ON pin, the VR_ON pin can control power sequencing
by locking out controller operation until the system logic supply exceeds the input threshold voltage of the
VR_ON circuit. Thus, V
and the system logic supply (either 5 V or 3.3 V) must be above UVLO thresholds
CC
before the controller is allowed to start up. Likewise, a microprocessor or other external logic can also control
the sequencing through VR_ON.
V
undervoltage lockout
BIAS
The VBIAS undervoltage-lockout circuit disables the controller, while VBIAS is below the 4.46-V start threshold
during power up. The controller is disabled when VBIAS goes below 3.3 V. While the controller is disabled, the
output drivers will be low and the slowstart capacitor will be shorted. When VBIAS exceeds the start threshold,
the short across the slowstart capacitor is released and normal converter operation begins.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
detailed description (continued)
IO linear regulator driver
The IO linear regulator driver circuit drives a high power NPN external power transistor, allowing external power
dissipation. The IO voltage is ramped up with the slowstart with the other two converters. Under voltage
protectionprotectsagainsthardshortsorextremeloading. TheVSENSE_IOvoltageismonitoredbytheVGATE
(powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.
CLK linear regulator driver
The CLK linear regulator driver circuit drives a lower power NPN external power transistor, allowing external
power dissipation. The CLK voltage is ramped up with the slowstart with the other two converters. Under voltage
protection protects against hard shorts or extreme loading. The VSENSE_CLK voltage is monitored by the
VGATE (powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.
slowstart
The slowstart circuit controls the rate at which V
powers up. A capacitor is connected between the SLOWST
OUT
and ANAGND pins and is charged by an internal current source. The value of the current source is proportional
to the reference voltage, so that the charging rate of C is proportional to the reference voltage. By making
slowst
the charging current proportional to V , the power up time for V will be independent of V . Thus, C can
ref
O
ref
slowst
remain the same value for all VP settings. The slowstart charging current is determined by the following
equation:
I(VREFB)
I
+
(amps)
SLOWSTART
5
where I
is the current flowing out of the V
terminal. It is recommended that no additional loads be
(VREFB)
REFB
connected to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus, these resistor
values will determine the slowstart charging current. The maximum current that can be sourced by the VREFB
circuit is 500 µA. The equation for setting the slowstart time is:
t
= 5 × C
× R
(seconds)
SLOWSTART
SLOWSTART
VREFB
where R
is the total external resistance from VREFB to ANAGND.
(VREFB)
VGATE
The VGATE circuit monitors for an undervoltage condition on V
, V
, and V
. If any V is
(out_core) (out_IO)
(out_CLK) O
7% below its reference voltage, or if any UVLO (V , VR_ON) threshold is not reached, then the VGATE pin is
cc
pulled low. The VGATE terminal is an open drain output.
overvoltage protection
The overvoltage protection circuit monitors Vout_core, Vout_IO, and Vout_CLK for an overvoltage condition.
If any V is 15% above its reference voltage, then a fault latch is set, then both the ripple regulator output drivers
O
and the linear regulator drivers are turned off. The latch will remain set until V
lockout value or until VR_ON is pulled low.
goes below the undervoltage
BIAS
overcurrent protection
The overcurrent protection circuit monitors the current through the current sense resistor. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND terminals, with the divider
voltage connected to the OCP terminal. If the voltage on the OCP terminal exceeds 200 mV, then a fault latch
is set and the output drivers (ripple regulator and linear regulators) are turned off. The latch remains set until
V
goes below the undervoltage lockout value or until VR_ON is pulled low.
BIAS
thermal shutdown
Thermal shutdown disables the controller if the junction temperature exceeds the 165°C thermal shutdown trip
point. The hysteresis is 10°C.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
APPLICATION INFORMATION
Vout IO
Vio 3.3/5V
Vclk 3.3/5V
Vout CLK
ENABLE_EXT
29
DRV_CLK
DRV_IO
32
DROOP
10
VSENSE_IO
31
VSENSE_CLK
V_GATE
OCP
IOUT
1
2
15
9
11
V
is dominant
SS
Protection Circuitry
VR_ON
22
if V < V
SS ref(CLK)
UVLO Enables
IC When
VR_ON > 2.5V
and
UVLO
V
SS
Vcc > 4.46V
IS–
IS+
13
Vref CLK
x 25
OCP_OVP
14
Enables Device
When
Shutdown
PWRGD
is LOW if
Vsense Core
or Vsense IO
or Vsense CLK
> 0.93 of their
Vref
V
is dominant
if V < V
SS ref(IO)
SS
OCP Core > 200mV
or Vsense Core
or Vsense IO
OCP_OVP
PWRGD
VBIAS
Vcc
VBIAS
or Vsense CLK
> 1.15 of their Vref
30
V
SS
Vref IO
UVP is
Enabled When
Vss > Vref CLK,
and
VCC(+5V)
18
Vcc (5V)
Vbatt
Q
Q
S
R
Shutdown
Vsense Core
or Vsense IO
or Vsense CLK
< 0.75 of their
Vref
ShutdownB
Clock and IO
Regulator
Drivers
UVP
BOOT
21
Latch
disabled
TG
PH
20
19
Core Voltage
Regulator
Controller
V
O
Vss is dominant if
Vss<Vref
Vref
_
27
VID0
+
BG
VID1 26
VID2 25
VID3 24
VID4 23
17
16
Vss
Vcc
Bandgap
Vref
DRVGND
and DAC
Power
Save
ANAGND
4
Hyst.
Set
Mode
Control
3
7
8
6
5
12
28
RAMP
DT_SET
VREFB
VSENSE_CORE
VHYST
SLOWST
PSM/LATCH
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
MECHANICAL DATA
DAP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
0,30
0,19
0,65
38
M
0,13
20
Thermal Pad
(see Note D)
6,20
8,40
NOM 7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°-ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
28
30
32
38
DIM
9,80
9,60
11,10
10,90
11,10
10,90
12,60
12,40
A MAX
A MIN
4073257/A 07/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
相关型号：
TPS5300DAPG4
3.3A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO32, GREEN, PLASTIC, HTSSOP-32
TI
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