TSA1005-40IF_技术文档

TSA1005-40

DUAL-CHANNEL, 10-BIT, 40MSPS, 150mW A/D CONVERTER

Preliminary Data

■ 10-bit, dual-channel A/D converter in deep

submicron CMOS technology

PIN CONNECTIONS (top view)

■ Single supply voltage: 2.5V

Independent supply for CMOS output stage

with 2.5V/3.3V capability

■ ENOB=9.4 @ 40Msps, Fin=10MHz

■ SFDR typically up to 73dB @ 40Msps,

Fin=10MHz.

■ 40Msps sampling frequency

■ 1GHz analog bandwidth Track-and-Hold

■ Common clocking between channels

■ Multiplexed outputs

index

corner

48 47 46 45 44 43 42 41 40 39 38 37

D0(LSB)

D1

36

35

AGND

INI

1

2

3

D2

34

AGND

INIB

4

5

D3

D4

33

32

AGND

6

7

31

D5

IPOL

30 D6

AVCCB

TSA1005-40

D7

29

8

9

AGND

INQ

D8

28

D9(MSB)

10

AGND

27

DESCRIPTION

26 VCCBE

INBQ 11

AGND

25 GNDBE

12

The TSA1005-40 is a new generation of high

speed, dual-channel Analog to Digital converter

processed in a mainstream 0.25µm CMOS tech-

nology yielding high performances.

13 14 15 16 17 18 19 20 21 22 23 24

The TSA1005-40 is specifically designed for appli-

cations requiring very low noise floor, high SFDR

and good isolation between channels. It is based

on a pipeline structure and digital error correction

to provide high static linearity at Fs=40Msps, and

Fin=10MHz.

BLOCK DIAGRAM

SELECT

OEB

VCCBE

+2.5V/3.3V

CLK

For each channel, a voltage reference is integrat-

ed to simplify the design and minimize external

components. It is nevertheless possible to use the

circuit with external references.

Timing

VINI

10

AD 10

I channel

VINBI

Each ADC outputs are multiplexed in a common

VINCMI

common mode

bus with small number of pins.

VREFPI

REF I

VREFMI

Differential or single-ended analog inputs can be

applied. A tri-state capability is available for the

outputs, allowing chip selection.

The TSA1005-40 is available in extended (0 to

+85°C) temperature range, in a small 48 pins

TQFP package.

10

D0

TO

D9

M

U

X

Buffers

Polar.

IPOL

VREFPQ

VREFMQ

VINCMQ

REF Q

common mode

VINQ

AD 10

Q channel

10

APPLICATIONS

VINBQ

■ Medical imaging and ultrasound

■ I/Q signal processing applications

■ High speed data acquisition system

■ Portable instrumentation

GND

GNDBE

PACKAGE

■ High resolution fax and scanners

ORDER CODE

7 × 7 mm TQFP48

Temperature

Range

Part Number

Package

Condition ing

Marking

TSA1005-40IF

0°C to +85°C

TQFP48

Tray

SA1005I

TSA1005-40IFT 0°C to +85°C

Tape & Reel

EVAL1005/BA

Evaluation board

September 2002

1/19

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice

TSA1005-40

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=10.13MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V

Tamb = 25°C (unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

SFDR Spurious Free Dynamic Range

-73

59

dBc

dB

SNR

THD

Signal to Noise Ratio

Total Harmonics Distortion

-73

58.5

dBc

dB

SINAD Signal to Noise and Distortion Ratio

TIMING CHARACTERISTICS

Symbol

Parameter

Sampling Frequency

Test conditions

Min

Typ

Max

Unit

FS

DC

0.5

45

40

55

MHz

%

Clock Duty Cycle

50

12.5

5

TC1

TC2

Tod

Clock pulse width (high)

Clock pulse width (low)

ns

Data Output Delay (Clock edge to Data Valid) 10pF load capacitance

Data Pipeline delay for I channel

ns

Tpd I

7

cycles

ns

Tpd Q Data Pipeline delay for Q channel

7.5

1

Ton

Toff

Falling edge of OEB to digital output valid data

Rising edge of OEB to digital output tri-state

1

ns

TIMING DIAGRAM

Simultaneous sampling

on I/Q channels

N+4

N+5

N+13

N+3

N+6

N+12

I

N+11

N+7

N+2

N-1

N

N+1

N+8

N+10

N+9

Q

CLK

Tpd I + Tod

Tod

SELECT

OEB

CLOCK AND SELECT CONNECTED TOGETHER

sample N+2

Q channel

sample N-6

Q channel

sample N-8

I channel

sample N+1

Q channel

sample N

Q channel

DATA

OUTPUT

sample N-9

I channel

sample N-7

Q channel

sample N+3

I channel

sample N+1

I channel

sample N+2

I channel

2/19

TSA1005-40

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Values

Unit

1)

AVCC

DVCC

0 to 3.3

0 to 3.6

V

Analog Supply voltage

1)

Digital Supply voltage

1)

VCCBE

Digital buffer Supply voltage

VCCBI

IDout

Tstg

0 to 3.3

-100 to 100

+150

V

Digital buffer Supply voltage

Digital output current

mA

°C

Storage temperature

2)

HBM: Human Body Model

2

ESD

kV

3)

1.5

CDM: Charged Device Model

4)

Latch-up

A

Class

1). All voltages values, except differential voltage, are with respect to network ground terminal .The magnitude of input and output voltages must not exceed -0.3V or VCC

2). ElectroStati cDischarge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ

3). Discharge to Ground of a device that has been previously charged.

4). Corporate ST Microelectronics procedu renumber 0018695

PIN CONNECTIONS (top view)

i

nd ex

c

orner

37

48 47 46 45 44 4 3 42 4 1 40 39 3 8

D0( L SB)

D1

A GND

INI

1

36

3 5

34

2

3

D2

A GND

INIB

4

5

33 D3

3 2 D4

A GND

IPO L

6

7

31 D5

D6

D7

30

29

A V CCB

TSA1005-40

8

9

A GND

INQ

28 D8

D9( MSB)

10

A GND

2 7

2 6 VC CB E

INB Q 11

A GND

GND BE

25

12

1 3 14 1 5 1 6 1 7 1 8 1 9 20 2 1 22 23 2 4

PIN DESCRIPTION

Pin No

Name

Description

Analog ground

Observation

Pin No

Name

Description

Digital buffer ground

Observation

1

2

AGND

INI

0V

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

GNDBE

VCCBE

D9(MSB)

D8

0V

I channel analog input

Analog ground

1Vpp

0V

Digital Buffer power supply

Most Significant Bit output

Digital output

2.5V/3.3V

3

AGND

INBI

CMOS output (2.5V/3.3V)

4

I channel inverted analog input

Analog ground

1Vpp

0V

5

AGND

IPOL

D7

Digital output

6

Analog bias current input

Analog power supply

Analog ground

D6

Digital output

7

AVCC

AGND

INQ

2.5V

0V

D5

Digital output

8

D4

Digital output

9

Q channel analog input

Analog ground

1Vpp

0V

D3

Digital output

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

AGND

INBQ

D2

Digital output

Q channel inverted analog input

Analog ground

1Vpp

0V

D1

Digital output

AGND

REFPQ

REFMQ

INCMQ

AGND

AVCC

DVCC

DGND

CLK

D0(LSB)

NC

Least Significant Bit output

Non connected

Q channel top reference voltage

Q channel bottom reference voltage

Q channel input common mode

Analog ground

1V

0V

NC

Non connected

0.5V

0V

VCCBE

GNDBE

VCCBI

OEB

Digital Buffer power supply

Digital buffer ground

Digital Buffer power supply

Digital Power Supply

Output Enable input

Analog power supply

I channel input common mode

I channel bottom reference voltage

I channel top reference voltage

2.5V/3.3V - See Application Note

0V

Analog power supply

Digital power supply

Digital ground

2.5V

0V

2.5V

2.5V/3.3V CMOS input

Clock input

2.5V CMOS input

AVCC

INCMI

REFMI

REFPI

2.5V

0.5V

0V

SELECT

DGND

DVCC

GNDBI

Channel selection

2.5V CMOS input

Digital ground

0V

Digital power supply

Digital buffer ground

2.5V

0V

1V

3/19

TSA1005-40

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V

Tamb = 25°C (unless otherwise specified)

OPERATING CONDITIONS

Symbol

Parameter

Analog Supply voltage

Min

Typ

Max

Unit

AVCC

DVCC

2.25

2.5

2.7

3.5

2.7

V

Digital Supply voltage

VCCBE

VCCBI

External Digital buffer Supply voltage

Internal Digital buffer Supply voltage

VREFPI

1)

0.6

0

0.88

0

1.4

0.4

1

V

Forced top voltage reference

VREFPQ

VREFMI

1)

Forced bottom reference voltage

VREFMQ

INCMI

Forced input common mode voltage

0.2

0.46

INCMQ

1)

Condition VRefP-VRefM>0.3V

ANALOG INPUTS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

VIN-VINB Full scale reference voltage

0.3

2.0

7

2.8

Vpp

pF

Cin

Req

BW

Input capacitance

Equivalent input resistor

Analog Input Bandwidth

Effective Resolution Bandwidth

1.6

1000

70

KΩ

Vin@Full Scale, Fs=40Msps

MHz

ERB

DIGITAL INPUTS AND OUTPUTS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Clock and Select inputs

VIL

Logic ”0” voltage

Logic ”1” voltage

0

0.8

V

VIH

2.0

2.5

OEB input

0.25 x

VCCBE

VIL

Logic ”0” voltage

Logic ”1” voltage

0

V

0.75 x

VCCBE

VIH

VCCBE

Digital Outputs

VOL

Iol=10µA

Ioh=10µA

0.1 x

VCCBE

Logic ”0” voltage

Logic ”1” voltage

0

V

VOH

IOZ

0.9 x

VCCBE

-1.67

VCCBE

0

High Impedance leakage current OEB set to VIH

Output Load Capacitance

1.67

15

µA

C

pF

L

4/19

TSA1005-40

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V

Tamb = 25°C (unless otherwise specified)

REFERENCE VOLTAGE

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

VREFPI

Top internal reference voltage

0.81

0.88

0.94

V

VREFPQ

VINCMI

Input common mode voltage

0.41

0.46

0.50

V

VINCMQ

POWER CONSUMPTION

Symbol

Parameter

Min

Typ

Max

Unit

ICCA

ICCD

ICCBE

ICCBI

Pd

Analog Supply current

Digital Supply Current

50

4

mA

Digital Buffer Supply Current (10pF load)

Digital Buffer Supply Current

6

mA

274

150

80

uA

Power consumption in normal operation mode

Thermal resistance (TQFP48)

mW

°C/W

Rthja

ACCURACY

Symbol

Parameter

Min

Typ

Max

Unit

OE

GE

DNL

INL

-

Offset Error

LSB

%

Gain Error

Differential Non Linearity

Integral Non Linearity

Monotonicity and no missing codes

±0.5

±0.7

LSB

Guaranteed

MATCHING BETWEEN CHANNELS

Symbol

Parameter

Min

Typ

Max

Unit

GM

OM

Gain match

0.04

0.5

1

%

LSB

dg

Offset match

Phase match

Crosstalk rejection

PHM

XTLK

85

dB

5/19

TSA1005-40

Static parameter: Integral Non Linearity

Fs=40MSPS; Icca=45mA; Fin=10MHz

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0

200

400

600

800

1000

Output Code

Static parameter: Differential Non Linearity

Fs=40MSPS; Icca=45mA; Fin=10MHz

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

0

200

400

600

800

1000

Output Code

Linearity vs. Fin

Distortion vs. Fin

Fs=40MHz; Icca=45mA

0

-20

-40

100

90

10

9

ENOB_Q

SNR_Q

ENOB_I

80

8

THD_I

SFDR_I

70

60

50

SINAD_Q

7

-60

-80

6

SFDR_Q

THD_Q

SNR_I

SINAD_I

20

5

-100

-120

40

30

4

0

40

60

0

20

40

60

Fin (MHz)

6/19

TSA1005-40

Linearity vs. AVCC

Fs=40MSPS; Icca=45mA; Fin=5MHz

Distortion vs. AVCC

Fs=40MSPS; Icca=45mA; Fin=5MHz

-30

-40

-50

100

90

10

9.5

9

SFDR_Q

THD_Q

ENOB_Q ENOB_I

80

8.5

8

-60

-70

SFDR_I

70

7.5

7

-80

SNR_Q

SINAD_Q

SNR_I

-90

60

50

40

THD_I

6.5

6

-100

-110

-120

SINAD_I

2.35

5.5

5

2.25

2.35

2.45

2.55

2.65

2.25

2.45

2.55

2.65

AVCC (V)

Linearity vs. DVCC

Fs=40MSPS; Icca=45mA; Fin=10MHz

Distortion vs. DVCC

Fs=40MSPS; Icca=45mA; Fin=10MHz

0

-20

-40

100

10

9.5

9

90

80

70

60

50

40

ENOB_Q

ENOB_I

8.5

8

SFDR_I

SFDR_Q

-60

-80

7.5

7

SINAD_Q

SNR_Q

6.5

6

THD_I

THD_Q

SNR_I

-100

-120

SINAD_I

5.5

5

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

DVCC (V)

Linearity vs. VCCBI

Fs=40MSPS; Icca=45mA; Fin=10MHz

Distortion vs. VCCBI

Fs=40MSPS; Icca=45mA; Fin=10MHz

-40

90

10

9.5

9

-50

85

THD_Q

ENOB_Q

-60

-70

SFDR_Q

ENOB_I

80

8.5

8

75

-80

70

7.5

7

-90

SINAD_Q

THD_I

SNR_Q

65

60

55

50

SFDR_I

6.5

6

-100

-110

-120

SINAD_I

2.35

5.5

5

SNR_I

2.25

2.35

2.45

2.55

2.65

2.25

2.45

2.55

2.65

VCCBI (V)

7/19

TSA1005-40

Linearity vs. VCCBE

Fs=40MSPS; Icca=45mA; Fin=10MHz

Distortion vs. VCCBE

Fs=40MSPS; Icca=45mA; Fin=10MHz

-30

-40

90

85

80

10

9.8

9.6

9.4

9.2

9

-50

-60

SFDR_Q

THD_Q

ENOB_Q

ENOB_I

75

70

-70

-80

8.8

8.6

8.4

8.2

8

65

THD_I

SNR_I

SINAD_I

-90

SFDR_I

60

-100

-110

-120

SINAD_Q

3.25

55

50

SNR_Q

2.25

2.75

3.25

2.25

2.75

VCCBE (V)

Linearity vs. Duty Cycle

Fs=40MHz; Icca=45mA; Fin=5MHz

Distortion vs. Duty Cycle

Fs=40MHz; Icca=45mA; Fin=5MHz

-40

100

10

9.5

9

-50

SFDR

90

ENOB

-60

-70

8.5

8

80

70

60

50

40

7.5

7

-80

SNR

SINAD

THD

-90

-100

-110

-120

6.5

6

5.5

5

45

47

49

51

53

55

45

47

49

51

53

55

Positive Duty Cycle (%)

Single-tone 8K FFT at 39.7Msps - Q Channel

Fin=10MHz; Icca=45mA, Vin@-1dBFS

0

-20

-40

-60

-80

-100

-120

-140

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

8/19

TSA1005-40

DEFINITIONS OF SPECIFIED PARAMETERS

STATIC PARAMETERS

Signal to Noise Ratio (SNR)

The ratio of the rms value of the fundamental

component to the rms sum of all other spectral

Static measurements are performed through

method of histograms on a 2MHz input signal,

sampled at 40Msps, which is high enough to fully

characterize the test frequency response. The

input level is +1dBFS to saturate the signal.

components in the Nyquist band (f /2) excluding

s

DC, fundamental and the first five harmonics.

SNR is reported in dB.

Signal to Noise and Distortion Ratio (SINAD)

Differential Non Linearity (DNL)

Similar ratio as for SNR but including the harmonic

distortion components in the noise figure (not DC

signal). It is expressed in dB.

The average deviation of any output code width

from the ideal code width of 1 LSB.

From the SINAD, the Effective Number of Bits

(ENOB) can easily be deduced using the formula:

SINAD= 6.02 × ENOB + 1.76 dB.

Integral Non linearity (INL)

An ideal converter presents a transfer function as

being the straight line from the starting code to the

ending code. The INL is the deviation for each

transition from this ideal curve.

When the applied signal is not Full Scale (FS), but

has an A amplitude, the SINAD expression

0

becomes:

SINAD =SINAD

+ 20 log (2A /FS)

0

2Ao

Full Scale

SINAD =6.02 × ENOB + 1.76 dB + 20 log (2A /

2Ao

0

FS)

DYNAMIC PARAMETERS

The ENOB is expressed in bits.

Dynamic measurements are performed by

spectral analysis, applied to an input sine wave of

various frequencies and sampled at 40Msps.

Analog Input Bandwidth

The maximum analog input frequency at which the

spectral response of a full power signal is reduced

by 3dB. Higher values can be achieved with

smaller input levels.

The input level is -1dBFS to measure the linear

behavior of the converter. All the parameters are

given without correction for the full scale ampli-

tude performance except the calculated ENOB

parameter.

Effective Resolution Bandwidth (ERB)

The band of input signal frequencies that the ADC

is intended to convert without loosing linearity i.e.

the maximum analog input frequency at which the

SINAD is decreased by 3dB or the ENOB by 1/2

bit.

Spurious Free Dynamic Range (SFDR)

The ratio between the power of the worst spurious

signal (not always an harmonic) and the amplitude

of fundamental tone (signal power) over the full

Nyquist band. It is expressed in dBc.

Pipeline delay

Delay between the initial sample of the analog

input and the availability of the corresponding

digital data output, on the output bus. Also called

data latency. It is expressed as a number of clock

cycles.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first five harmonic

distortion components to the rms value of the

fundamental line. It is expressed in dB.

9/19

TSA1005-40 APPLICATION NOTE

DETAILED INFORMATION

The TSA1005-40 is a dual-channel, 10-bit resolu-

tion analog to digital converter based on a pipeline

structure and the latest deep sub micron CMOS

process to achieve the best performances in

terms of linearity and power consumption.

Each channel achieves 10-bit resolution through

the pipeline structure. A latency time of 7 clock pe-

riods is necessary to obtain the digitized data on

the output bus.

The input signals are simultaneously sampled on

both channels on the rising edge of the clock. The

output data is valid on the rising edge of the clock

for I channel and on the falling edge of the clock

for Q channel. The digital data out from the differ-

ent stages must be time delayed depending on

their order of conversion. Then a digital data cor-

rection completes the processing and ensures the

validity of the ending codes on the output bus.

The structure has been specifically designed to

accept differential signals. In this case, you will ob-

tain the best performances. Nevertheless, sin-

gle-ended signals can drive the ADC with few lin-

earity degradation.

SELECT

The digital data out from each ADC core are mul-

tiplexed together to share the same output bus.

This prevents from increasing the number of pins

and enables to keep the same package as single

channel ADC like TSA1002.

The selection of the channel information is done

through the ”SELECT” pin. When set to high level

(VIH), the I channel data are present on the bus

D0-D9. When set to low level (VIL), the Q channel

data are on the output bus D0-D9.

Connecting SELECT to CLK allows I and Q chan-

nels to be simultaneously present on D0-D9; I

channel on the rising edge of the clock and Q

channel on the falling edge of the clock. (see tim-

ing diagram page 2).

REFERENCES AND COMMON MODE

CONNECTION

VREFM must be always connected externally.

The TSA1005-20 is pin to pin compatible with the

dual 10bits/40Msps TSA1005, the dual 12bits/

20Msps TSA1204 and the dual 12bits/40Msps

TSA1203.

Internal reference and common mode

In the default configuration, the ADC operates with

its own reference and common mode voltages

generated by its internal bandgap. VREFM pins

are connected externally to the Analog Ground

while VREFP (respectively INCM) are set to their

internal voltage of 0.88V (respectively 0.46V). It is

recommended to decouple the VREFP and INCM

in order to minimize low and high frequency noise

(refer to Figure 1)

COMPLEMENTARY FUNCTIONS

Some functionalities have been added in order to

simplify as much as possible the application

board. These operational modes are described as

followed.

Output Enable (OEB)

Figure 1 : Internal reference and common mode

setting

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state while the

converter goes on sampling. When OEB is set to a

low level again, the data are then present on the

output with a very short Ton delay.

Therefore, this allows the chip select of the device.

The timing diagram summarizes this functionality.

In order to remain in the normal operating mode,

this pin should be grounded through a low value of

resistor.

330pF 10nF 4.7uF

VREFP

VIN

TSA1005

INCM

330pF 10nF 4.7uF

VINB

VREFM

10/19

TSA1005-40

External reference and common mode

might also use a higher impedance ratio (1:2 or

1:4) to reduce the driving requirement on the

analog signal source.

Each analog input can drive a 1Vpp amplitude in-

put signal, so the resultant differential amplitude is

2Vpp.

Each of the voltages VREFP and INCM can be

fixed externally to better fit to the application

needs

(Refer

to

table

’OPERATING

CONDITIONS’ page 4 for min/max values).

The VREFP, VREFM voltages set the analog

dynamic at the input of the converter that has a full

scale amplitude of 2*(VREFP-VREFM). Using

internal references, the dynamic range is 1.8V.

The INCM is the mid voltage of the analog input

signal.

Figure 3 : Differential input configuration with

transformer

ADT1-1

Analog source

1:1

VIN

TSA1005

50Ω

33pF

I or Q ch.

VINB

It is possible to use an external reference voltage

device for specific applications requiring even

INCM

better

linearity,

accuracy

or

enhanced

temperature behavior.

330pF

10nF

470nF

Using the STMicroelectronics TS821 or

TS4041-1.2 Vref leads to optimum performances

when configured as shown on Figure 2 .

Figure 4 represents the biasing of a differential

input signal in AC-coupled differential input

configuration. Both inputs VIN and VINB are

centered around the common mode voltage, that

can be let internal or fixed externally.

Figure 2 : External reference setting

1kΩ

330pF 10nF 4.7uF

VCCA VREFP

Figure 4 : AC-coupled differential input

TS821

TS4041

VIN

TSA1005

VINB

external

reference

VIN

VREFM

10nF

50Ω

100kΩ

TSA1005

33pF

INCM

common

mode

100kΩ

VINB

10nF

50Ω

DRIVING THE ANALOG INPUT

Differential inputs

Figure 5 shows a DC-coupled configuration with

forced VREFP and INCM to the 1V DC analog

input while VREFM is connected to ground; we

achieve a 2Vpp differential amplitude.

The TSA1005-40 has been designed to obtain

optimum performances when being differentially

driven. An RF transformer is a good way to

achieve such performances.

Figure 3 describes the schematics. The input

signal is fed to the primary of the transformer,

while the secondary drives both ADC inputs. The

common mode voltage of the ADC (INCM) is

connected to the center-tap of the secondary of

the transformer in order to bias the input signal

around this common voltage, internally set to

0.46V. It determines the DC component of the

analog signal. As being an high impedance input,

it acts as an I/O and can be externally driven to

adjust this DC component. The INCM is

decoupled to maintain a low noise level on this

node. Our evaluation board is mounted with a 1:1

ADT1-1WT transformer from Minicircuits. You

Figure 5 : DC-coupled 2Vpp differential analog

input

analog

AC+DC

VREFP

VIN

DC

TSA1005

VINB

VREFM

INCM

330pF 10nF

4.7uF

VREFP-VREFM = 1 V

11/19

TSA1005-40

Single-ended input configuration

- The transition to single-ended configuration

implies to connect the unused input (VINB for

instance) to the DC component of the single input

(VIN) and also to the input common mode in order

to be well balanced. The mid-code is achieved at

the crossing between VIN and VINB, therefore

inputs are conveniently biased.

- Unlikely other structures of converters in which

the unused input can be grounded; in our case it

will end with unbalanced inputs and saturation of

the internal amplifiers leading to a non respect of

the output codes.

The single-ended input configuration of the

TSA1005-40 requires particular biasing and driv-

ing. The structure being fully differential, care has

to be taken in order to properly bias the inputs in

single-ended mode. Figure 6 summarizes the link

from the differential configuration to the sin-

gle-ended one; a wrong configuration is also pre-

sented.

- With differential driving, both inputs are centered

around the INCM voltage.

Figure 6 : Input dynamic range for the various configurations

Differential configuration

Single-ended configuration:

balanced inputs

Single-ended configuration:

unbalanced inputs

+FS : code 1023

+FS + offset : code > 1023

VIN - VINB

+FS : code 1023

VIN - VINB

VIN

VINB

VIN

0 : code 511

INCM

0 : code 511

-FS : code 0

-FS + offset : code > 0

-FS : code 0

Ao + ac

VIN

VINB

INCM

Ao

Wrong configuratio n !

The applications requiring single-ended inputs

can be configured like reported on Figure 7 for an

AC-coupled input or on Figure 8 for a DC-coupled

input.

Figure 7 : AC-coupled Single-ended input

Signal source

10nF

VIN

In the case of AC-coupled analog input, the

analog inputs VIN and VINB are biased to the

same voltage that is the common mode voltage of

the circuit (INCM). The INCM and reference

voltages may remain at their internal level but can

also be fixed externally.

100kΩ

50Ω

TSA1005

INCM

33pF

100kΩ

VINB

In the case of DC-coupled analog input with 1V

DC signal, the DC component of the analog input

set the common mode voltage. As an example

figure 8, VREFP and INCM are set to the 1V DC

12/19

TSA1005-40

analog input while VREFM is connected to

ground; we achieve a 2Vpp differential amplitude.

The figure 9 sums up the relevant data.

Figure 9 : analog current consumption

optimization depending on Rpol value

Figure 8 : DC-coupled 2Vpp analog input

100

90

250

200

150

100

50

Analog

AC+DC

VREFP

VIN

80

DC

TSA1005

70

VINB

60

VREFM

ICCA

50

INCM

40

30

20

330pF

10nF

4.7uF

VREFP-VREFM = 1 V

10

RPOL

0

5

15

25

35

45

55

Dynamic characteristics, while not being as

remarkable as for differential configuration, are

still of very good quality.

Fs (MHz)

APPLICATION

Clock input

Layout precautions

The TSA1005-40 performance is very dependant

on your clock input accuracy, in terms of aperture

jitter; the use of low jitter crystal controlled

oscillator is recommended.

To use the ADC circuits in the best manner at high

frequencies, some precautions have to be taken

for power supplies:

- First of all, the implementation of 4 separate

proper supplies and ground planes (analog,

digital, internal and external buffer ones) on the

PCB is recommended for high speed circuit

applications to provide low inductance and low

resistance common return.

The duty cycle must be between 45% and 55%.

The clock power supplies must be separated from

the ADC output ones to avoid digital noise

modulation at the output.

The separation of the analog signal from the

digital part is mandatory to prevent noise from

coupling onto the input signal. The best

compromise is to connect from one part AGND,

DGND, GNDBI in a common point whereas

GNDBE must be isolated. Similarly, the power

supplies AVCC, DVCC and VCCBI must be

separated from the VCCBE one.

It is recommended to always keep the circuit

clocked, even at the lowest specified sampling

frequency of 0.5Msps, before applying the supply

voltages.

Power consumption

- Power supply bypass capacitors must be placed

as close as possible to the IC pins in order to

improve high frequency bypassing and reduce

harmonic distortion.

- Proper termination of all inputs and outputs must

be incorporated with output termination resistors;

then the amplifier load will be only resistive and

the stability of the amplifier will be improved. All

leads must be wide and as short as possible

especially for the analog input in order to decrease

parasitic capacitance and inductance.

So as to optimize both performance and power

consumption of the TSA1005-40 according the

sampling frequency, a resistor is placed between

IPOL and the analog Ground pins. Therefore, the

total dissipation is adjustable from 35Msps up to

50Msps.

The TSA1005-40 will combine highest perfor-

mances and lowest consumption at 40Msps when

Rpol is equal to 30kΩ. This value is nevertheless

dependant on application and environment.

At lower sampling frequency range, this value of

resistor may be adjusted in order to decrease the

analog current without any degradation of

dynamic performances.

- To keep the capacitive loading as low as

possible at digital outputs, short lead lengths of

routing are essential to minimize currents when

the output changes. To minimize this output

13/19

TSA1005-40

capacitance, buffers or latches close to the output

pins will relax this constraint.

- Choose component sizes as small as possible

(SMD).

The transducer is a piezoelectric ceramic such as

zirconium titanate. The whole array can reach up

to 512 channels.

The TX beam former, amplified by the HV TX

amps, delivers up to 100V amplitude excitation

pulses with phase and amplitude shifts.

The mux and T/R switch is a two way input signal

transmitter/ output receiver.

Digital Interface application

Thanks to its wide external buffer power supply

range, the TSA1005-40 is perfectly suitable to

plug in to 2.5V low voltage DSPs or digital interfac-

es as well as to 3.3V ones.

To compensate for skin and tissues attenuation

effects, The Time Gain Compensation (TGC) am-

plifier is an exponential amplifier that enables the

amplification of low voltage signals to the ADC in-

put range. Differential output structure with low

noise and very high linearity are mandatory fac-

tors.

Medical Imaging application

Driven by the demand of the applications requiring

nowadays either portability or high degree of par-

allelism (or both), this product has been devel-

oped to satisfy medical imaging, and telecom in-

frastructures needs.

These applications need high speed, low power

and high performance ADCs. 10-12 bit

resolution is necessary to lower the quantification

noise. As multiple channels are used, a dual con-

verter is a must for room saving issues.

The input signal is in the range of 2 to 20MHz

(mainly 2 to 7MHz) and the application uses most-

ly a 4 over-sampling ratio for Spurious Free Dy-

namic Range (SFDR) optimization.

As a typical system diagram shows figure 10, a

narrow input beam of acoustic energy is sent into

a living body via the transducer and the energy re-

flected back is analyzed.

Figure 10 : Medical imaging application

The next RX beam former and processing blocks

enable the analysis of the outputs channels ver-

sus the input beam.

HV TX amps

TX

beamformer

Mux and

T/R

switches

RX

beamformer

ADC

TGC amplifie r

Processing

and display

14/19

TSA1005-40

EVAL1005/BA evaluation board

The dataready signal is the acquisition clock of the

logic analyzer.

The ADC digital outputs are latched by the octal

buffers 74LCX573.

All characterization measurements have been

made with:

- SFSR=1dB for static parameters.

- SFSR=-1dB for dynamic parameters.

The EVAL1005/BA is a 4-layer board with high

decoupling and grounding level. The schematic of

the evaluation board is reported figure 14 and its

top overlay view figure 13.The characterization of

the board has been made with a fully ADC

devoted test bench as shown on Figure 11. The

analog input signal must be filtered to be very

pure.

Figure 11 : Analog to Digital Converter characterization bench

HP8644

Data

ADC

evaluation

board

Vin

Sine Wave

Generator

Logic

Analyzer

PC

Clk

Pulse

HP8133

HP8644

Generator

Sine Wave

Generator

Operating conditions of the evaluation board:

Find below the connections to the board for the

power supplies and other pins:

board

internal

voltage (V)

external

connection

voltage (V)

notation

GB1

VB1

board

internal

external

GNDBI

VCCBI

0

2.5

0

connection

voltage (V)

notation

AV

AG

AVCC

AGND

REFPI

REFMI

INCMI

REFPQ

REFMQ

INCMQ

DVCC

2.5

0

GB2

VB2

GNDBE

VCCBE

GNDB3

VCCB3

2.5/3.3

0

0.89

0.6 to 1.4

0 to 0.4

0.2 to 1

0.6 to 1.4

0 to 0.4

0.2 to 1

2.5

RPI

GB3

VB3

RMI

CMI

RPQ

RMQ

CMQ

DV

2.5

0.46

0.89

Care should be taken for the evaluation board

considering the fact that the outputs of the con-

verter are 2.5V/3.3V (VB2) tolerant whereas the

74LCX573 external buffers are operating up to

2.5V.

0.46

The ADC outputs on the connector J6 are D11

(MSB) to D2 (LSB).

DG

DGND

0

15/19

TSA1005-40

Single and Differential Inputs:

With the strap connected:

The ADC board components are mounted to test

the TSA1005-40 with single analog input; the

ADT1-1WT transformer enables the differential

drive into the converter; in this configuration, the

resistors RSI6, RSI7, RSI8 for I channel (respec-

tively RSQ6, RSQ7, RSQ8 for Q one) are con-

nected as short circuits whereas RSI5, RSI9 (re-

spectively RSQ5, RSQ9) are open circuits.

The other way is to test it via JI1 and JI1B differen-

tial inputs. So, the resistances RSI5, RSI9 for I

channel (respectively RSQ5, RSQ9 for Q one) are

connected as short circuits whereas RSI6, RSI7,

RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q

one) are open circuits.

- to the upper connectors, the I channel at the out-

put is selected.

- horizontally, the Q channel at the output is se-

lected.

- to the lower connectors, both channels are se-

lected, relative to the clock edge.

Figure 12 : mode select

SELECT

I channel

SELECT

Grounding consideration

Q channel

So as to better reject noise on the board, connect

on the bottom overlay AG (AGND), DG(DGND),

GB1(GNDBI) together from one part, and

GB2(GNDBE) with GB3(GNDB3) from the other

part.

I/Q channels

CLK

DGND DVCC

schematic

board

Mode select

Consumption adjustment

So as to evaluate a single channel or the dual

ones, you have to connect on the board the

relevant position for the SELECT pin.

Before any characterization, care should be taken

to adjust the Rpol (Raj1) and therefore Ipol value

in function of your sampling frequency.

Figure 13 : Printed circuit of evaluation board.

16/19

TSA1005-40

Figure 14 : TSA1005-40 Evaluation board schematic

+

c B V 3 c

G n d B 3

c B V 2 c

G n d B 2

c B V 1 c

G n d B 1

+

N C

G N D B I

D V C C

D G N D

S E L E C T

C L K

D G N D

D V C C

A V C C

A G N D

3 7

3 8

2 4

2 3

2 2

V C C B E

G N D B E

V C C B I

+

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

2 1

2 0

1 9

1 8

1 7

1 6

O E B

A V C C

I N C M I

R E F M I

R E F P I

I N C M Q

1 5

R E F M Q

1 4

R E F P Q

1 3

N D

C C

+

I N C M

R E F M

R E F P

I N C M

R E F M

R E F P

17/19

TSA1005-40

Figure 15 : Printed circuit board - List of components

Name Part Footprint Name Part

Footprint Name Part

Type

Footprint Name Part

Type

Footprint

Type

0

47

Type

10nF

RSQ6

RSQ7

RSQ8

RSI6

RSI7

RSI8

R3

805

603

CD2

C40

C39

603

C26

C20

C33

C25

CI1

CQ1

C34

C42

C35

C44

C36

C32

C37

330pF 603

33pF 603

47µF RB.1

470nF 805

CQ6 NC

805

TSSOP20

SOT23-6

CI6

U2

U3

NC

74LCX573

STG719

CQ12 10nF

CQ9

C52

C18

C21

C4

C15

C27

C11

CI9

10nF

U1

JA

ANALOGIC connector

J17

J25

J4

BUFPOW

CKDATA

CLK

connector

SMA

SIP2

connector

SMA

R5

RQ19 47

47

RI1

RQ1

J27

J26

JD

JI1

JI1B

JQ1

CON2

DIGITAL

InI

InIB

InQ

RI19 47

RSI9 0NC 805

RSQ5 0NC 805

CI12 10nF

CI31 10nF

CQ31 10nF

CQ30 330pF 603

CI11 330pF 603

CQ10 470nF 805

C28

CI10

0NC

0NC 805

0NC

0NC 805

1K

47K 603

RSQ9

RSI5

R24

R23

R21

R22

R2

R12

R11

Raj1

805

470nF 805

JQ1B InQB

SW1 SWITCH

CQ32 470nF 805

CQ13 470nF 805

connector

805

S5

S4

SW-SPST

C51

C2

C17

CD3

C10

CQ8

330pF 603

CI32

C13

C53

C16

C3

C22

CI13

C38

CD1

C19

470nF 805

TI2

TQ2

JI2

JQ2

J6

T2-AT1-1WT ADT

VREFI

VREFQ

32Pin

603

connector

IDC-32

47K

200K

603

VR5

trimmer

1210

10µF 1210

CQ11 330pF 603

connector

10µF

C23

C41

C29

CI8

C14

330pF 603

NC: non soldered

CI30 330pF 603

18/19

TSA1005

PACKAGE MECHANICAL DATA

48 PINS - PLASTIC PACKAGE

A

A2

A1

e

48

37

0,10 mm

.004 inch

SEATING PLANE

1

36

25

12

13

24

D3

D1

D

0,25 mm

.010 inch

GAGE PLANE

K

Millimeters

Typ.

Inches

Typ.

Dim.

Min.

Max.

Min.

Max.

A

1.60

0.15

1.45

0.27

0.20

0.063

0.006

0.057

0.011

0.008

A1

A2

B

0.05

1.35

0.17

0.09

0.002

0.053

0.007

0.004

1.40

0.22

0.055

0.009

C

D

9.00

7.00

5.50

0.50

9.00

7.00

5.50

0.60

1.00

0.354

0.276

0.216

0.0197

0.354

0.276

0.216

0.024

0.039

D1

D3

e

E

E1

E3

L

0.45

0.75

0.018

0.030

L1

K

0° (min.), 7° (max.)

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco

Singapore - Spain - Sweden - Switzerland - United Kingdom

http://www.st.com

19/19


型号：	TSA1005-40IF
厂家：	ETC
描述：	Analog to Digital Converter 模拟数字转换器\n 转换器
文件：	总19页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSA1005-40IF [ETC]

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