TXC-04216AIBG_技术文档

E1Mx16 Device

E1 Mapper 16-Channel

TXC-04216

DATA SHEET

FEATURES

DESCRIPTION

• Add/drop sixteen 2.048 Mbit/s signals from an

STM-1 VC-4/AU-3, STS-3, or an STS-1

• Independent add and drop bus timing modes

• Selectable HDB3 positive/negative rail or NRZ E1

interface. Performance counter provided for illegal

coding violations.

The E1 Mapper 16-Channel device is designed for add/drop

multiplexer, terminal multiplexer, and dual and single unidi-

rectional ring applications. Four field-proven QE1M Quad E1

Mapper chips are interconnected in a single compact pack-

age to permit higher application board densities.

Sixteen E1 2.048 Mbit/s signals are mapped to and from

asynchronous Tributary Unit-12s (TU-12s) or Virtual Tribu-

tary 2s (VT2s). The E1Mx16 interfaces to a multiple-seg-

ment, byte-parallel SDH/SONET-formatted Telecom Bus at

the 19.44 Mbit/s byte rate for STM-1/STS-3 operation or at

the 6.48 Mbit/s byte rate for STS-1 operation. This Bus per-

mits the E1Mx16 to connect directly to other TranSwitch

devices in application designs. The E1 signals can be either

HDB3 positive/negative rail or NRZ format. The E1Mx16

provides performance counters, alarm detection, and the

ability to generate errors and Alarm Indication Signals (AIS).

E1 facility and line loopback capabilities are also provided.

• Digital desynchronizers

• J2 16-byte ETSI trail trace comparison

• Drop buses are monitored for parity, loss of clock,

upstream AIS and H4 multiframe errors

• TU Tandem Connection ETSI message

processing and generation

• Performance counters are provided for TU/VT

pointer movements, BIP-2 errors and Far End

Block Errors (REIs)

• TU/VTs are monitored for Loss Of Pointer, New

Data Flags (NDFs), AIS, Remote Defect

Indication (RDI), and size errors (S-bits)

• V5 Byte Signal Label Mismatch and Unequipped

detection

• E1 facility and line loopbacks, generation of BIP-2

and REI errors, and send RDI capability

• Intel / Motorola compatible microprocessor bus

interface with interrupt capability

APPLICATIONS

• STM-1/STS-3/STS-1 to 2.048 Mbit/s add/drop

mux/demux

• Programmable internal RISC processor

implements VT-POH and VT-alarm handling

• Boundary scan capability (IEEE 1149.1)

• Single +5V, ±5% power supply

• Unidirectional or bidirectional ring applications

• STM-1/STS-3/STS-1 termination terminal mode

multiplexer

• STM-1/STS-3/STS-1 test equipment

• 388-lead plastic ball grid array

(35 x 35 mm) package

STM-1/STS-3/STS-1

TELECOM BUS SIDE

2.048 Mbit/s

TRIBUTARY SIDE

External Clock

+5V

7

Channel 1

•

A - side

drop bus

13

•

P & N data

and clock for

receive and

•

E1Mx16

•

A - side

add bus

•

14

13

14

•

E1 Mapper 16-Channel

TXC-04216

•

transmit, plus

receive data

zero-output

control

B - side

drop bus

7

B - side

add bus

Channel 16

5

3

Y

Boundary Microprocessor Controls

Scan interface

NAR

I

M

U.S. Patents No. 4,967,405; 5,033,064;

5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218

U.S. and/or foreign patents issued or pending

E1Mx16 is a trademark of TranSwitch Corporation

TranSwitch and TXC are registered trademarks of TranSwitch Corporation

PRELI

Document Number:

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

TranSwitch Corporation

3 Enterprise Drive

Shelton, Connecticut 06484

www.transwitch.com

USA

•

Tel: 203-929-8810

Fax: 203-926-9453

•

E1Mx16

TXC-04216

DATA SHEET

TABLE OF CONTENTS

SECTION

PAGE

List of Figures ...................................................................................................................3

Overview ............................................................................................................................4

Features .............................................................................................................................5

Block Diagram ..................................................................................................................10

Block Diagram Description ...............................................................................................11

Lead Diagram ..................................................................................................................15

Lead Descriptions ............................................................................................................16

Absolute Maximum Ratings and Environmental Limitations ............................................25

Thermal Characteristics ...................................................................................................25

Power Requirements .......................................................................................................25

Input, Output and Input/Output Parameters .....................................................................26

Timing Characteristics .....................................................................................................29

Operation ................................................................................................................... 44-87

Bus Interface Modes .............................................................................................. 44

Bus Mode Selection ............................................................................................... 45

SDH/SONET Add/Drop Multiplexing Format Selections ........................................ 45

Drop TU/VT Selection ............................................................................................ 46

Add TU/VT Selection ............................................................................................. 47

Bus Timing ............................................................................................................. 48

Unequipped Operation ........................................................................................... 48

Drop Bus Multiframe Alignment ............................................................................. 50

Add Bus Multiframe Alignment .............................................................................. 51

Performance Counters ........................................................................................... 52

Alarm Structure ...................................................................................................... 52

Interrupt Structure .................................................................................................. 53

SDH/SONET AIS Detection ................................................................................... 59

TU/VT Pointer Tracking ......................................................................................... 59

Remote Defect Indications ..................................................................................... 62

Overhead Communications Bit Access ................................................................. 66

J2 Byte Processing ................................................................................................ 67

N2 (Z6) Byte Processing (Tandem Connection) .................................................... 71

TUG-3 Null Pointer Indicator .................................................................................. 72

E1 Loopback Capability ......................................................................................... 73

PRBS Pattern Generator and Analyzer ................................................................. 74

Resets .................................................................................................................... 74

Start-Up Procedure ................................................................................................ 75

Pointer Leak Rate Calculations ............................................................................. 76

Jitter Measurements ................................................................................................77

Internal SPOT Processors ..................................................................................... 82

Boundary Scan ...................................................................................................... 86

Multiplex Format and Mapping Information ........................................................... 88

Memory Map ....................................................................................................................94

Memory Map Descriptions ..................................................................................... 100-133

Common Registers .............................................................................................. 100

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Port n Registers.....................................................................................................114

Application Examples ....................................................................................................134

Package Information ......................................................................................................135

Ordering Information ......................................................................................................136

Related Products ...........................................................................................................136

Standards Documentation Sources ...............................................................................137

List of Data Sheet Changes .......................................................................................... 139

Documentation Update Registration Form* ..............................................................143

* Please note that TranSwitch provides documentation for all of its products. Customers who are using

a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Depart-

ment to receive relevant updated and supplemental documentation as it is issued. They should also

contact the Applications Engineering Department to ensure that they are provided with the latest

available information about the product, especially before undertaking development of new designs

incorporating the product.

LIST OF FIGURES

Figure

Page

1. TXC-04216 Block Diagram ......................................................................................10

2. 2048 kbit/s Asynchronous Mapping .........................................................................13

3. E1Mx16 TXC-04216 Lead Diagram .........................................................................15

4. Groups 1-4, Ports 1-4 E1 Transmit Timing ...............................................................29

5. Groups 1-4, Ports 1-4 E1 Receive Timing ...............................................................30

6. STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus ...................31

7. STM-1/STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus .......32

8. STS-1 A/B Add Bus Signals, Timing Derived from Add Bus ....................................33

9. STM-1/STS-3 A/B Add Bus Signals, Timing Derived from Add Bus ........................34

10. Microprocessor Read Cycle Timing - Intel ...............................................................35

11. Microprocessor Write Cycle Timing - Intel ...............................................................37

12. Microprocessor Read Cycle Timing - Motorola .......................................................39

13. Microprocessor Write Cycle Timing - Motorola ........................................................41

14. Boundary Scan Timing ............................................................................................43

15. H4 Byte Floating VT Mode Bit Allocation .................................................................50

16. TU/VT Pointer Tracking State Machine ....................................................................61

17. Facility and Line Loopbacks .....................................................................................73

18. Jitter Tolerance and Jitter Test Arrangements ..........................................................78

19. Jitter Tolerance Measurements with Requirement ...................................................78

20. Jitter Transfer Measurements ...................................................................................79

21. Standard Pointer Test Sequences ............................................................................81

22. Schematic Diagram of E1Mx16 Showing SPOT Processor Interfaces ....................84

23. Recommended Implementation Flowchart for Reprogramming the SPOT Processor 85

24. Boundary Scan Schematic ......................................................................................87

25. Typical Application using the E1Mx16 ....................................................................134

26. E1Mx16 TXC-04216 388-Lead Plastic Ball Grid Array Package ............................135

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OVERVIEW

The E1Mx16 (TXC-04216) provides the mapping of sixteen 2048 kbit/s E1 asynchronous signals into a

multiple-segment, byte-parallel, SDH/SONET Telecom Bus for the STM-1, STS-3, or AU-3/STS-1 formats,

using sixteen programmed asynchronous mode TU12/VT2 tributary signals. The E1Mx16 interfaces on the

SDH/SONET side use four bus segments defined as A-side Drop and Add, and B-side Drop and Add. Selected

TU-12/VT2 tributaries are mapped to and from either a 270 or 90 SDH/SONET column format.

Using a dual bus architecture, the E1Mx16 can be configured in a system for dropping a TU-12/VT2 from either

bus only, adding a TU-12/VT2 to either bus only, dropping and adding a TU-12/VT2 to either the A or B sides,

dropping a TU-12/VT2 from either the A or B sides, and adding the TU-12/VT2 to the opposite bus (e.g. drop

from A, add to B), or dropping a TU-12/VT2 from either A or B buses and adding the TU-12/VT2 to both buses.

Bus timing for the Add side can be derived from either the Drop bus, or input signals to the Add bus.

Each drop has an optional H4 byte detector for detecting the starting location of the V1 byte in the TU-12/VT2.

Instead of using the H4 detector, a V1 pulse may be inputted to the E1Mx16. Each Drop bus is also equipped

with an optional H1/H2 or the E1 bytes AIS detector for detecting an upstream AIS state. Each of the selected

TU-12/VT2 for both the A and/or B drop buses has a pointer tracking state machine for determining the location

of the overhead bytes and the E1 asynchronous frame bits. Each of the overhead bytes in the selected TU-12/

VT2 is monitored for control and status information. The E1Mx16 can be configured to perform a J2 16- byte

trail trace message comparison, N2 tandem connection message comparison and generation with error

counters and status alarm indications, V5 single-bit or enhanced 3-bit RDI, REI, signal label mismatch and

unequipped detection and generation, and K4 byte access.

The E1Mx16 provides a desynchronizer/synchronizer for each port. An 8-bit pointer leak rate register is

provided. The E1Mx16 satisfies the various jitter tolerance, jitter transfer, mapping jitter, and combined jitter

requirements found in ITU and ANSI documents.

Each of the asynchronous E1 line inputs can be individually configured to provide either an NRZ interface or a

dual unipolar rail type interface. When configured for a rail interface, a B3ZS CODEC converts the rail signals

to and from a NRZ signal. Coding violations are counted in a 16-bit counter.

For overhead byte processing, the E1Mx16 uses an internal SPOT (SDH/SONET Processor for Overhead

Termination). The SPOT is divided into four segments corresponding to the four groups of four mappers. The

SPOT performs many of the overhead processing functions, such as J2 message comparisons. Programming

of the SPOT is performed through the microprocessor bus. The microprocessor can access four separate

segments of the SPOT which have individual select leads, corresponding to the four groups of four mappers.

SELp (p = 1 to 4) are the microprocessor port select signals. SEL1 selects the first group of four mappers

(channels 1-4) and SEL2, SEL3 and SEL4 select the other three groups of four mappers.

The E1Mx16 is compatible with either Intel or Motorola split bus microprocessors. The E1Mx16 also provides

interrupts to the microprocessor for operational alarm status indications.

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TXC-04216

DATA SHEET

FEATURES

The following features are supported by the E1Mx16:

SDH/SONET FORMATS:

• STM-1 AU-4 VC-4 TUG-3 TUG-2 format

• STM-1 AU-3 TUG-2

• STS-3

• STS-1

OPERATING MODES:

The E1Mx16 supports the following modes of operation which are programmable by the microprocessor.

• Drop mode only (Add bus tristated)

- Drop from A or B

• Add mode only

- Add to A or B

• Single unidirectional ring

- Drop from A, Add to A

- Drop from B, Add to B

• Multiplexer

- Drop from A, Add to B

- Drop from B, Add to A

• Dual protection ring

- Drop from A, Add to A and B

- Drop from B, Add to A and B

BUS TIMING:

The E1Mx16 provides the following bus timing modes by lead selection with software overwrite:

• Drop bus timing

- Add bus timing is derived from the same named Drop bus

• Add bus timing

- Add bus timing is independent of the Drop bus

SDH/SONET BUS INTERFACE:

• STM-1/STS-3

- 19.44 Mbyte/s parallel interface

• STS-1

- 6.48 Mbyte/s parallel interface

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• Drop bus timing enabled

- Drop bus inputs: Clock, SPE, C1J1V1, Data and parity

- Add bus outputs: data, parity and active bus indication

• Add bus timing enabled

- Drop bus inputs: Clock, SPE, C1J1V1, data, parity and bus indication

- Add bus inputs: Clock, SPE and C1J1V1

- Add bus outputs: Data, parity and active bus active indication

• Stuck clock indications

- Input parity check with alarm monitoring

Odd, even, data only, or all bus signals

- Input loss of clock detection

Stuck high or low

• SDH/SONET interface Add buses, A and B

- Output parity generation

Odd, even, data only, or all bus signals

- Bus indication (polarity selectable through control bit)

- Ability to High-Z the output bus signals

MAPPINGS:

The E1Mx16 has the following mapping features:

• Maximum of 16 E1 ports

- Up to 16 E1 asynchronous mappings to TU-12/VT2

• TU-12/VT2 selection

- Drop bus (common A and B sides)

- Add bus (common A and B sides)

• User’s responsibility to maintain TUG-2/VT group mappings

SDH/SONET FEATURES:

• In-band upstream path and line AIS detection

- H1/H2 pointer bits or

- E1 bytes (majority vote)

• TU/VT pointer tracking for A and B sides

- ETSI 1015-based state machine

- Size error indication

- 4-bit increment/decrement counters

• TU/VT A/B Drop and Add selection

• TU/VT pointer generation

- Fixed to 105 for 2048 kbit/s E1 asynchronous format

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• Low order TU/VT byte processing

- J2 byte (programmable per port)

64-byte host processor read cycle (no alignment)

16-byte host processor read with ITU TTC message comparison

- V5 byte and K4 (Z7) byte

Single-bit RDI or enhanced 3-bit RDI alarm detection (5 or 10 event

option, selectable through software control bit)

REI (FEBE) counter (8 bits)

BIP-2 detector and counter (8 bits) with block or bit error count

Detect RFI (bit 4 in V5 byte)

Signal label mismatch, unequipped detection,

Access to K4 byte

- N2 (Z6) byte

Host processor access or

Tandem connection option with:

Multiframe pattern alignment

16-byte message comparison

TC RDI, ODI alarm detection

REI and OEI counters

- V4 byte access

- Line AIS generation on SDH/SONET alarms with:

Masks

Microprocessor control

• Low order TU/VT byte insertion

- J2 byte with 16- or 64-byte message

- V5 and K4 (Z7) byte with:

REI (FEBE) insertion (from receive side)

RFI insertion (microprocessor control)

BIP-2 calculation and insertion

RDI insertion (from receive side) with:

Enable bits for alarms

Microprocessor control

Single-bit RDI or enhanced 3-bit RDI (selectable through software control bit)

Control of spare bits in K4 byte

- N2 (Z6) byte

Microprocessor or Tandem connection insertion with:

Multiframe pattern generation

16-byte message

TC RDI, ODI generation with:

Alarms and microprocessor control

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TC AIS, REI and OEI generation

- Unequipped channel generation with supervisory equipped generation

- TU/VT AIS generator

• Desynchronizer

- Meet ETSI and ANSI performance requirements for:

Pointer test sequence

Jitter

- External clock (also used for line AIS generation)

• O-bit channel microprocessor access

- For selected TU-12/VT2

LINE INTERFACE:

• Individual port NRZ or rail interface selection

• NRZ interface

- AIS detection

- External loss of signal may be inputted on negative rail

- Programmable clock edge

• Rail Interface

- HDB3 CODEC

- Bipolar violation counter (16 bits)

- Loss of signal detection

- AIS detection

• Quiet feature

- Force receive output to 0

• High-Z feature

TEST FEATURES:

• Boundary Scan based on IEEE 1149.1

- EXTEST, SAMPLE, BYPASS test instructions

• Loopbacks per port

- Facility

- Line

• High-Z all output leads option

• BIP-2 error mask per port

- Force inverted value continuous

• REI error mask per port

- Force REI to be sent as a 1

• Pseudo-random test generator and analyzer per port

- 2¹⁵-1 pattern defined in O.151

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MICROPROCESSOR INTERFACE:

• Split bus

- Intel

- Motorola

• Interrupt support

- Positive, negative, or positive/negative alarm transition

- Positive level option

- Software polling registers

- Mask bit alarm hierarchy

- Hardware enable control bit

- Hardware sense control

• Reset control bits

- Hardware reset

- Full software reset

- Software reset for A and B bus alarms

- Software reset per port

- Counter reset per port

- SPOT (internal processor) reset

SPOT PROCESSOR:

• Microcode is supplied for initialization

• Downloaded through memory map

• Sanity alarms

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BLOCK DIAGRAM

STM-1/STS-3/STS-1

TELECOM BUS SIDE

2.048 Mbit/s

TRIBUTARY SIDE

EXTCK

QUIETpn

ADCLK

ADSPE

Repeated for Ports 1 through 16

TU/VT

Terminate

A Side

A Receive

(A Drop)

RPOpn

RNOpn

RCOpn

ADC1J1V1

12

AD(7-0)

HDB3

Coder

Destuff

Desync

8

ADPAR

ADINDp

Add/Drop

4

TU/VT

Terminate

B Side

B Receive

(B Drop)

Bus A

Interface

to

Channel

blocks

#1-16

SPOT RISC

Processor

and RAM

Alarms & Controls

AACLK

AASPE

AAC1J1V1

AA(7-0)

Alarms

Controls,

& Timing

8

AAPAR

AADDp

AAINDp

A Transmit

(A Add)

TU/VT Build

A Side

Stuff/Sync

A Side

3

4

11

TPIpn

HDB3

Decoder

TNIpn/TLOSpn

TCIpn

B Transmit

(B Add)

TU/VT Build

B Side

Stuff/Sync

B Side

BDCLK

BDSPE

Repeated for Ports 1 through 16

BDC1J1V1

BD(7-0)

Note: p=1-4; n=1-4

(16 Channel blocks)

12

8

BDPAR

BDINDp

Add/Drop

4

TCK

TDO

Bus B

Interface

to

Channel

blocks

#1-16

Channel

p

n

Channel

p

n

Test

Access Port

Interface

(Boundary

Scan)

T

A

P

1

2

3

4

5

6

7

8

1

2

1

2

3

4

1

2

3

4

9

3

4

1

2

3

4

1

2

3

4

TRS

TDI

10

11

12

13

14

15

16

TMS

BACLK

BASPE

RESET

BAC1J1V1

BA(7-0)

HIGHZ

ABUST

TESTp

8

BAPAR

3

BADDp

BAINDp

11

4

TESTp

4

TXCTI(1-5)

1

Microprocessor Interface and Common Control/Status I/O

Note: p=1-4 (for four groups of four mappers)

4

8

4

11

D

(7-0)

IRQp

SELp

LDS

DTACKp

INTSH

A

MOTOROLA

MOTO

RD/WR

(10-0)

4

8

11

4

D

(7-0)

INTp

SELp

WR

RDYp

INTSH

A

INTEL

MOTO

RD

(10-0)

Figure 1. TXC-04216 Block Diagram

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BLOCK DIAGRAM DESCRIPTION

The block diagram for the E1 Mapper 16-Channel device is shown in Figure 1. The E1Mx16 interfaces to four

buses, designated as A Drop, B Drop, A Add, and B Add. The four buses run at the STM-1/STS-3 rate of 19.44

Mbyte/s, or at the STS-1 rate of 6.48 Mbyte/s. For North American applications, the asynchronous E1 signals

are carried in floating Virtual Tributary 2 (VT2) format in a Synchronous Transport Signal - 1 (STS-1), or in an

STS-1 that is carried in a Synchronous Transport Signal - 3 (STS-3). For ITU-T applications, the E1 signals are

carried in floating mode Tributary Unit - 12 (TU-12) format in the STM-1 Virtual Container - 4 structure (VC-4)

using Tributary Unit Group - 3 (TUG-3), or in the STM-1 Virtual Container - 3 structure (VC-3) using Tributary

Unit Group - 2 (TUG-2) mapping schemes. Sixteen E1 signals can be dropped from one bus (A Drop or B

Drop), or from any combination of the two drop buses, to the E1 lines. Sixteen asynchronous E1 signals are

converted into TU-12 or VT2 format and are added to either one or both of the add buses, depending upon the

mode of operation. When the E1Mx16 is configured for drop bus timing, the add buses are, by definition, byte-

synchronous and multiframe-synchronous with their like-named drop buses, but are delayed by one byte time

because of internal processing. For example, if a byte in the STM-1 Virtual Container - 4 structure (VC-4) using

a Tributary Unit Group - 3 (TUG-3) TU-12/VT2 is to be added to the A Add bus, the time of its placement on the

bus is derived from the A Drop bus timing, and from software instructions specifying which TU/VT number is

being dropped/added. When the device is configured for add bus timing, the add bus, parity, and add indicator

signals are derived from the add clock, C1J1V1 and SPE signals.

The A Receive block is identical to the B Receive block. The TU/VT Terminate block is repeated 32 times, two

for each port (A and B sides). The Destuff, Desync, and HDB3 Coder blocks are repeated sixteen times, one

for each port. The interface between a drop bus and Receive block consists of 12 input leads, and an optional

output lead: a byte clock, byte-wide data, a C1J1 indicator which may be carrying a V1 indication making the

signal a C1J1V1 indicator, an SPE indicator, and an odd parity lead for the last-named ten leads. Parity is

selectable by control bits for even parity and for the data byte only. The output lead is an optional TU/VT select

indicator signal. The Drop C1J1V1 signal is used in conjunction with the Drop SPE signal to determine the

location of the various pulses. The C1 pulse identifies the location of the C1 byte when the SPE signal is low. A

single J1 pulse identifies the starting location of the J1 byte in the VC-4 format, when the SPE signal is high.

Three J1 pulses are provided for the STS-3 format, each identifying the starting location of the J1 byte in each

of the STS-1 signals.

The E1Mx16 can operate with a V1 pulse in the C1J1V1 signal, or it can use an internal H4 detector for deter-

mining the location of the V1 pulse. The V1 pulse location is used to determine the location of the pointer byte

V1. For STM-1 VC-4 operation, if the C1J1V1 signal is used, a single V1 pulse must occur during three drop

bus clock cycles every four frames following the J1 pulse when the SPE signal is high. For STS-3 operation,

three V1 pulses must be present every four frames. Each of the three V1 pulses must be present three clock

cycles after the corresponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the J1

pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH bytes. In the next

column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second clock

cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the start of TUG-3 A.

This column is where the V1 pulse occurs every four frames. However, the actual V1 byte location is six clock

cycles after the V1 pulse.

For STS-1 operation, one V1 pulse must be present if the C1J1V1 signal is used. The V1 pulse must occur on

the next clock cycle after the J1 pulse, and when the SPE signal is high. The J1 pulse identifies the J1 byte

location (defined as the starting location for the STS-1) in the POH bytes. In the next column (first clock cycle)

the TUs start. Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the

V1 bytes for the 21 TU-12/VT2s are also aligned with respect to the V1 pulse.

Each bus is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and an upstream

SDH/SONET AIS indication. The E1Mx16 can monitor either the TOH E1 bytes or the H1/H2 bytes for an AIS

indication. Which E1 byte and H1/H2 bytes are selected is a function of the TU/VT selected.

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Each TU/VT Terminate block (A and B side) performs pointer processing based on the location of the V1 and

V2 bytes. The pointer bytes are monitored for loss of pointer, TU AIS indication, and NDF. The pointer tracking

process is based on the latest ETSI standard, which also meets ANSI/Bellcore requirements. Pointer incre-

ments and decrements are also counted, and the SS-bits are monitored for the correct value. This block also

monitors the various alarms found in the V5 and K4 (formerly known as Z7) bytes, including signal label mis-

match detection, unequipped status detection, BIP-2 parity error detection and error counter, REI counter, and

the three RDI indications. The E1Mx16 performs a 16-byte J2 trail trace comparison on the channels selected.

For 64-byte messages, the bytes are stored in a memory map segment for a microprocessor read cycle. The

device also provides the TU tandem connection feature and performs the 16-byte message comparison for the

N2 (formerly known as Z6) byte message.

A control bit for each port selects the TU/VT from either the A Drop or B Drop bus. The TU/VT is destuffed in

the Destuff block using majority logic rules for the three sets of three justification control bits to determine if the

two S-bits are data bits or frequency justification bits.

The Desync block removes the effects on the E1 output of systemic jitter that might occur because of signal

mappings and pointer movements in the network. The Desync block contains two parts, a pointer leak buffer,

and an E1 loop buffer. The pointer leak buffer can accept up to five consecutive pointer movements, and can

adjust the effect over time. The E1 Loop Buffer consists of a digital loop filter, which is designed to track the fre-

quency of the received E1 signal and to remove both transmission and stuffing jitter.

An option for each port provides either NRZ data, or an HDB3-encoded positive and negative rail signal for the

E1 interface. Receive data (towards the E1 line), for all sixteen channels, can be clocked out on either rising or

falling edges of the clock. In addition, control bits are provided for forcing the data and clock signals to a high

impedance state (tri-state). A control lead is provided for forcing the output leads to the 0 state.

In the add direction, the E1Mx16 accepts clock and either NRZ data or HDB3-encoded positive and negative

rail signals. Data, for all sixteen channels, can be clocked in on either the falling or rising edge of the clock. In

the NRZ mode, an external loss of clock indication input signal can be provided. For the rail signal, coding vio-

lations are counted, and there is monitoring for loss of signal. An E1AIS detector is also provided.

The data signal is written into a FIFO in one of the 32 Stuff/Sync blocks. Threshold modulation is used for the

frequency justification process. Timing information from the drop bus or add bus is used to read the FIFO and

perform the TU/VT justification process. This block permits tracking of an incoming E1 signal having an aver-

age frequency offset as high as 120 ppm, and up to 1.5 UI of peak-to-peak jitter. Since the E1Mx16 supports a

ring architecture, two sets of blocks are provided for each port. The TU/VT selection is the same for both

blocks. A control bit, and transmit line alarms, can generate an E1AIS.

The 32 TU/VT Build blocks format the TU/VT into a STS-1, STS-3 or STM-1 structure for the asynchronous

2048 kbit/s signals, as shown in Figure 2. The pointer value carried in the V1 and V2 bytes is transmitted with

a fixed value of 105. Transmit access is provided for the 8 overhead communications channel bits (O-bits) via

the microprocessor. The microprocessor also writes the signal label, and the value of the J2 message, either

as a 16-byte or a 64-byte message. The E1Mx16 provides the TU tandem connection feature for the TU,

including the transmission of the 16-byte message and the various alarms associated with the tandem connec-

tion feature. The device provides single-bit or 3-bit RDI using the V5 and K4 (Z7) bytes, respectively. Local

alarms, or the microprocessor, can generate the remote payload, server, or connectivity defect indications. The

Far End Block Error FEBE (REI) is inserted from the BIP-2 errors detected on the receive side, and BIP-2 par-

ity is generated for the V5 byte. Control bits are provided for generating unequipped status, generating TU/VT

AIS, and inserting REI and BIP-2 errors. The ability to generate Null Pointer Indicators (NPIs) is also provided

for the STM-1 VC-4 format.

PRELIMINARY TXC-04216-MB

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Ed. 2, October 2000

E1Mx16

TXC-04216

DATA SHEET

Figure 2. 2048 kbit/s Asynchronous Mapping

VC-12

TU-12/VT2

V5

V1 (Pointer Byte)

R R R R R R R R

32 bytes

(2048 kbit/s Data)

35 bytes

R R R R R R R R

J2

C₁C₂O O O O R R

V2 (Pointer Byte)

35 bytes

32 bytes

(2048 kbit/s Data)

R R R R R R R R

N2 (Z6)

C₁C₂O O O O R R

32 bytes

V3 (Action)

35 bytes

(2048 kbit/s Data)

I = Information

R R R R R R R R

K4 (Z7)

O = Overhead communications

C_t= Justification control

S_q= Justification opportunity

R = Fixed stuff (set to 0)

C₁C₂R R R R R S₁

S₂I I I I I I I

31 bytes

V4 (Reserved)

35 bytes

(2048 kbit/s Data)

R R R R R R R R

140 Bytes

REI

500 µs

Path Overhead

144 Bytes

(V5) Byte

L₁

L₂

L₃

RDI

BIP-2

1

RFI

Signal Label

(FEBE)

(FERF)

BIT 1

8

V₁

V₂

BIP-2 = Bit Interleaved Parity (2 bits)

REI = Remote Error Indication

(formerly FEBE, Far End

Block Error Indication)

RFI = Remote Failure Indication

L₁L₂L₃= Signal Label

RDI = Remote Defect Indication

(formerly FERF, Far End

NDF

New Data Flag

Normal = 0110, 1110, 0010, 0100 or 0111

New = 1001, 0001, 1101, 1011 or 1000

S₁S₂

I

D

I

D

I

D

I

D

I

D

Size

S₁S₂= 10

Receive Failure Indication)

Positive Justification = Invert five I-bits

Negative Justification = Invert five D-bits

Pointer Range = 0 - 139 decimal

PRELIMINARY TXC-04216-MB

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E1Mx16

TXC-04216

DATA SHEET

The A Transmit block is identical to the B Transmit block. The interface between an add bus and a Transmit

block consists of three input leads and eleven output leads, when the add bus timing mode is selected. The

input leads are a byte clock, a C1J1V1 indicator, and an SPE indicator. The output leads are byte-wide data, a

parity indicator, an add indicator, and an optional TU/VT selection indicator signal. The Add C1J1V1 signal is

used in conjunction with the Add SPE signal to determine the location of the various pulses. An option is pro-

vided in which the drop side V1 reference pulse, either from the drop bus C1J1V1 indicator or from the H4 mul-

tiframe detector, may be used as the add side V1 reference pulse.

When drop bus timing is selected, the output leads are byte-wide data, a parity indicator, an add indicator, and

an optional TU/VT selection indicator signal. The add bus clock, SPE and C1J1V1 signals are disabled.

The E1Mx16 can be configured to operate with either Intel or Motorola-compatible microprocessors via the

Microprocessor Interface blocks. Separate address, data and control leads are provided. The microprocessor

can access four separate segments of memory which have individual select, ready/acknowledge and interrupt

leads, corresponding to the four groups of four mappers. Interrupt capability is provided with mapper group and

individual mapper mask bits as well as activity registers to guide software to the exact cause of an interrupt in

the most expeditious manner. A wide variety of alarms is provided on a mapper group level as well as on a per

mapper channel level. Each alarm or error is reflected in a current status register or counter as well as a

latched value register that may be set on the rising, falling, both transitions or positive level of an alarm. Any

latched value may trigger an interrupt, unless it is masked to prevent it causing an interrupt. An option is pro-

vided which permits the interrupt polarity to be inverted.

Control bits are provided which enable an E1 facility or line loopback. Because of the complexity of the SDH/

SONET interface and the two timing modes, SDH/SONET loopback of the TU/VTs is not supported.

The SPOT (SONET Processor for Overhead Termination) block is a RISC processor with associated instruc-

tion and data memory that performs selected low-speed functions, including all overhead processing and

counter maintenance. The SPOT program must be loaded into the SPOT instruction memory after power-up.

Executable microcode is provided by TranSwitch. All four SPOT blocks can be programmed at the same time

by simultaneously activating all four SELp leads in write mode.

The Boundary Scan Interface Block provides a five-lead Test Access Port (TAP) that conforms to the IEEE

1149.1 standard. This standard provides external boundary scan functions to read and write the external I/O

leads from the TAP for board and component test.

PRELIMINARY TXC-04216-MB

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Ed. 2, October 2000

E1Mx16

TXC-04216

DATA SHEET

LEAD DIAGRAM

26

51

58

51

58

51

58

51

58

25

24

23

22

21

20

19

18

17

58

51

16

15

14

13

12

11

10

9

8

7

6

5

4

58

51

58

51

58

51

3

2

1

AE

AC

AA Y W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

AF

AD

AB

Notes: This is the bottom view. The leads are solder balls. See Figure 26 for package information.

Figure 3. E1Mx16 TXC-04216 Lead Diagram

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

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E1Mx16

TXC-04216

DATA SHEET

LEAD DESCRIPTIONS

In the following tables the mapper-group identification variable “p” stands for “(1-4)”, and the corresponding

leads are listed in the order 1, 2, 3, 4.

POWER SUPPLY, GROUND AND NO CONNECT

Symbol

Lead No.

I/O/P * Type

Name/Function

+5 volt supply voltage, ±5%.

VDD:

VDD

A2, A14, B26,

C23, D3, L12,

L13, L14, L15,

M11, M16, N1,

N11, N16, P11,

P16, P26, R11,

R16, T12, T13,

T14, T15,

P

AC24, AD4,

AE1, AF13,

AF25

Ground:

0 volt reference.

GND

A1, A13, A26,

D4, D21, D22,

D23, E4, F4,

L11, L16, M12,

M13, M14,

P

M15, N12, N13,

N14, N15, N26,

P1, P12, P13,

P14, P15 R12,

R13, R14, R15,

T11, T16,

AA23, AB23,

AC4, AC5, AC6,

AC23, AF1,

AF14, AF26

Note: I = Input; O = Output; P = Power; T=Tristate

PRELIMINARY TXC-04216-MB

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E1Mx16

TXC-04216

DATA SHEET

Symbol

Lead No.

I/O/P * Type

Name/Function

NC leads are not to be connected, not even to

another NC lead, but must be left floating. Connection of these

leads may impair performance or cause damage to the device.

No Connect:

NC

B7, C6, C7, C8,

C17, C19, C20,

D5, D6, D7,

D17, D19, D20,

E2, E3, F24,

G24, J1, J2, K1,

K2, K4, K23,

L1, L3, L23, M3,

M4, M23, M24,

N3, N4, P2, P3,

P23, R3, T2,

T3, T23, U3,

U4, U23, V3,

V4, V23, V24,

V25, W23,

W24, Y23, Y24,

Y25, AA24,

AA25, AB4,

AB24, AB25,

AB26, AC1,

AC2, AC13,

AC14, AC15,

AC21, AC22,

AD1, AD5,

AD6, AD13,

AD14, AD21,

AD23, AD24,

AE6, AE21,

AE24, AE25,

AE26, AF2

A DROP AND A ADD BUS I/O (p=1-4)

Symbol Lead No. I/O/P Type *

Name/Function

A Drop Bus Clock:

This clock operates at 19.44 MHz for STM-1/

ADCLK

R2

I

TTL

STS-3 operation, and at 6.48 MHz for STS-1 operation. A Drop bus

byte-wide data (AD7-AD0), the parity bit (ADPAR), SPE indication

(ADSPE), and the C1J1V1 indication (ADC1J1V1) are clocked in on

falling edges of this clock. This clock may also be used for timing and

deriving the like-named add bus byte-wide data, add and TU/VT indica-

tions, and parity bits. The add bus signals are clocked out on rising

edges of the clock during the time slots that correspond to the selected

TU/VT.

A Drop Bus Parity Bit:

An odd parity bit input signal representing the

ADPAR

AF15

I

TTL

parity calculation for each data byte, SPE, and C1J1V1 signal from the

drop bus. Control bits are provided in address 012H which enable par-

ity to be calculated as even (control bit DPEp is 1), and/or for the data

byte only (control bit PDDOp is 1).

*See Input, Output and Input/Output Parameters section below for Type definitions.

PRELIMINARY TXC-04216-MB

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TXC-04216

DATA SHEET

Symbol Lead No. I/O/P Type *

Name/Function

Byte-wide data that corresponds to the

STM-1/STS-3/STS-1 signal from the drop bus. The first bit received

(dropped) corresponds to bit 7.

A Drop Bus Data Byte:

AD(7-0) AF3, AE3,

AE4, AF4,

AE5,

I

TTL

AE18,

AF17,

AF18

A Drop Bus SPE Indicator:

A signal that is active high during each

byte of the STM-1/STS-3/STS-1 payload, and low during Transport

Overhead times.

ADSPE

AC3

AB2

I

TTL

A Drop Bus C1J1V1 Indications:

ADC1J1V1

An active high timing signal that

carries STM-1/STS-3/STS-1 starting frame and SPE information. This

signal works in conjunction with the ADSPE signal. The C1 pulse iden-

tifies the location of the first C1 byte in the STM-1/STS-3 signal, and

the C1 byte in the STS-1 signal, when ADSPE is low. The J1 signal

identifies the starting location of the J1 signal when ADSPE is high.

One or more V1 pulses may be present depending upon the format.

The V1 pulses may be used in place of the H4 byte as the multiframe

indication.

A Drop Bus TU/VT Selection Indication:

Enabled when control bit

G3, K3,

AA2,

AD16

O

I

CMOS

ADINDp

AACLK

4mA ADnENp is written with a 1. An active low signal that is clocked out for

the time slots determined by TU/VT selection (RTUNnp register) for

each port (n=port number, 1-4; p=group number, 1-4).

A Add Bus Clock:

When the add bus timing mode is selected, this

N2

TTL

input must be provided for add bus timing. This clock operates at 19.44

MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation.

The add bus SPE indication (AASPE), and the C1J1V1 indication

(AAC1J1V1) are clocked in on falling edges of this clock. Add bus byte-

wide data (AA7-AA0), add indicator (AADDp), and parity bit (AAPAR)

are clocked out on rising edges of the clock during the time slots that

correspond to the selected TU/VT. When drop bus timing is selected,

this input is disabled.

A Add Bus Parity Bit:

An odd parity output signal that is calculated

AAPAR

AA(7-0)

AF19

O(T) CMOS

4mA over the byte-wide add data. This tristate lead is only active when there

is data being added to the add bus. When control bit APEp is 1, even

parity is calculated.

A Add Bus Data Byte:

Byte-wide data that corresponds to the

4mA selected TU/VT.

AF21,

AF20,

O(T) CMOS

AF6, AE7,

AF7, AD7,

AC7, AE8

A Add Bus SPE Indicator:

When the add bus timing mode is selected,

AASPE

M1

I

TTL

this signal must be provided for add bus timing. This signal must be

high during each byte of the STM-1/STS-3/STS-1 payload, and low

during Transport Overhead byte times.

PRELIMINARY TXC-04216-MB

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TXC-04216

DATA SHEET

Symbol Lead No. I/O/P Type *

Name/Function

A Add Bus C1J1V1 Indications:

When the add bus timing mode is

AAC1J1V1

AB1

I

TTL

selected, this signal must be provided for add bus timing. An active

high timing signal that carries STM-1/STS-3/STS-1 starting frame and

SPE information. This signal works in conjunction with the AASPE sig-

nal. The C1 pulse identifies the location of the first C1 byte in the

STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when

AASPE is low. The J1 signal identifies the starting location of the J1

signal when AASPE is high. The J1 signal identifies the location of the

J1 byte. One or more V1 pulses may be present depending upon the

format. The V1 pulses are used in place of the H4 byte as the multi-

frame indication.

A Add Bus TU/VT Selection Indication:

Enabled when control bit

H2, J3,

AA3,

AC16

O

CMOS

AAINDp

AADDp

4mA AAnENp is written with a 1. An active low signal that is clocked out for

the time slots determined by TU/VT selection (TTUNnp register) for

each port (n=port number, 1-4; p=group number, 1-4).

A Add Bus Add Data Present Indicator:

This normally active low sig-

R4,AD26,

AF5,

CMOS

4mA nal is present when output data to the A Add bus is valid. It identifies

the location of all of the TU/VT time slots being selected. When control

bit ADDIp is 1, the indicator is active high instead of active low.

AE19

B DROP AND B ADD BUS I/O (p=1-4)

Symbol Lead No. I/O/P Type

Name/Function

B Drop Bus Clock:

BDCLK

P25

I

TTL

This clock operates at 19.44 MHz for STM-1/

STS-3 operation, and at 6.48 MHz for STS-1 operation. B Drop bus

byte-wide data (BD7-BD0), the parity bit (BDPAR), SPE indication

(BDSPE), and the C1J1V1 indication (BDC1J1V1) are clocked in on

falling edges of this clock. This clock may also be used for timing and

deriving the like-named add bus byte-wide data, add and TU/VT indica-

tions, and parity bits. The add bus signals are clocked out on rising

edges of the clock during the time slots that correspond to the selected

TU/VT.

B Drop Bus Parity Bit:

An odd parity bit input signal representing the

BDPAR

J23

I

TTL

parity calculation for each data byte, SPE, and C1J1V1 signal from the

drop bus. Control bits are provided in address 012H which enable par-

ity to be calculated as even (control bit DPEp is 1), and/or for the data

byte only (control bit PDDOp is 1).

B Drop Bus Data Byte:

Byte-wide data that corresponds to the

STM-1/STS-3/STS-1 signal from the drop bus. The first bit received

(dropped) corresponds to bit 7.

BD(7-0) J26, J25,

J24, K26,

I

TTL

K25, K24,

L26, L25

B Drop Bus SPE Indicator:

A signal that is active high during each

BDSPE

H24

byte of the STM-1/STS-3/STS-1 payload, and low during Transport

Overhead times.

PRELIMINARY TXC-04216-MB

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E1Mx16

TXC-04216

DATA SHEET

Symbol Lead No. I/O/P Type

Name/Function

B Drop Bus C1J1V1 Indications:

BDC1J1V1

H25

I

TTL

An active high timing signal that car-

ries STM-1/STS-3/STS-1 starting frame and SPE information. This sig-

nal works in conjunction with the BDSPE signal. The C1 pulse

identifies the location of the first C1 byte in the STM-1/STS-3 signal,

and the C1 byte in the STS-1 signal, when BDSPE is low. The J1 signal

identifies the starting location of the J1 signal when BDSPE is high.

One or more V1 pulses may be present depending upon the format.

The V1 pulses may be used in place of the H4 byte as the multiframe

indication.

B Drop Bus TU/VT Selection Indication:

Enabled when control bit

L24, G26,

AA26,

Y26

O

I

CMOS

BDINDp

BACLK

4mA BDnENp is written with a 1. An active low signal that is clocked out for

the time slots determined by TU/VT selection (RTUNnp register) for

each port (n=port number, 1-4; p=group number, 1-4).

B Add Bus Clock:

When the add bus timing mode is selected, this

M25

TTL

input must be provided for add bus timing. This clock operates at 19.44

MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation.

The add bus SPE indication (BASPE), and the C1J1V1 indication

(BAC1J1V1) are clocked in on falling edges of this clock. Add bus byte-

wide data (BA7-BA0), add indicator (BADDp), and parity bit (BAPAR)

are clocked out on rising edges of the clock during the time slots that

correspond to the selected TU/VT. When drop bus timing is selected,

this input is disabled.

B Add Bus Parity Bit:

An odd parity output signal that is calculated

BAPAR

BA(7-0)

AD25

O(T) CMOS

4mA over the byte-wide add data. This tristate lead is only active when there

is data being added to the add bus. When control bit APEp is 1, even

parity is calculated.

B Add Bus Data Byte:

Byte-wide data that corresponds to the

4mA selected TU/VT.

AE23,

AF23,

O(T) CMOS

AE22,

AF22,

AD22,

AF10,

AF9, AF8

B Add Bus SPE Indicator:

When the add bus timing mode is selected,

BASPE

AC26

I

TTL

this signal must be provided for add bus timing. This signal must be

high during each byte of the STM-1/STS-3/STS-1 payload, and low

during Transport Overhead byte times.

B Add Bus C1J1V1 Indications:

BAC1J1V1

H26

When the add bus timing mode is

selected, this signal must be provided for add bus timing. An active high

timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE

information. This signal works in conjunction with the BASPE signal.

The C1 pulse identifies the location of the first C1 byte in the STM-1/

STS-3 signal, and the C1 byte in the STS-1 signal, when BASPE is low.

The J1 signal identifies the starting location of the J1 signal when

BASPE is high. The J1 signal identifies the location of the J1 byte. One

or more V1 pulses may be present depending upon the format. The V1

pulses are used in place of the H4 byte as the multiframe indication.

PRELIMINARY TXC-04216-MB

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E1Mx16

TXC-04216

DATA SHEET

Symbol Lead No. I/O/P Type

Name/Function

B Add Bus TU/VT Selection Indication:

Enabled when control bit

F23, G25,

AF12,

O

CMOS

BAINDp

4mA BAnENp is written with a 1. An active low signal that is clocked out for

the time slots determined by TU/VT selection (TTUNnp register) for

each port (n=port number, 1-4; p=group number, 1-4).

W26

B Add Bus Add Data Present Indicator:

This normally active low sig-

AC25,

M26,

AF11,

AF24

O

CMOS

BADDp

4mA nal is present when output data to the B Add bus is valid. It identifies

the location of all of the TU/VT time slots being selected. When control

bit ADDIp is 1, the indicator is active high instead of active low.

GROUP p, PORT n LINE INTERFACE (p = 1-4; n = 1-4)

Symbol Lead No. I/O/P Type

RCOpn F3, B11, D1, O(T) CMOS

Name/Function

Receive Group p, Port n Output Clock:

A 2.048 MHz clock output.

A16, D16,

D26, D12,

C22, W2,

4mA Data is normally clocked out on rising edges of this clock. When con-

trol bit RCLKIp is 1, data is clocked out on falling edges of this clock.

When control bit RnENp is 0, this lead is forced to a high impedance

state.

AC9, W1,

AD9, AD18,

U25, AE9, T25

Note: RCO11 is lead F3, RCO12 is lead B11, RCO13 is lead D1,

RCO14 is lead A16, RCO21 is lead D16, etc.

Receive Group p, Port n Data Positive Rail or NRZ:

RPOpn F1, C11, E1, O(T) CMOS

When control

B10, B16,

E23, C15,

D24, Y4,

AE10, W3,

AC8, AC12,

T26, AC18,

R26

4mA bit BYPASnp is 0, positive rail data is provided on this lead. When

control bit BYPASnp is 1, an NRZ signal is provided on this lead.

When control bit RnENp is 0, this lead is forced to a high impedance

state.

Note: RPO11 is lead F1, RPO12 is lead C11, RPO13 is lead E1,

RPO14 is lead B10, RPO21 is lead B16, etc.

Receive Group p, Port n Data Negative Rail:

When control bit

RNOpn

TCIpn

TPIpn

F2, D9, D2, O(T) CMOS

B8, C16, E25,

D13, D25, Y1,

AD17, W4,

AD8, AC17,

T24, AE17,

R24

4mA BYPASnp is 0, negative rail data is provided on this lead. When con-

trol bit RnENp is 0, or control bit BYPASnp is 1, this lead is forced to

a high impedance state.

Note: RNO11 is lead F2, RNO12 is lead D9, RNO13 is lead D2,

RNO14 is lead B8, RNO21 is lead C16, etc.

Transmit Group p, Port n Input Clock:

A 2.048 MHz clock input.

G1, C10, B2,

B12, D8, E26,

C14, C24, Y2,

AD10, U1,

AD11, AD15,

U26, AC20,

N25

I

TTL

Data is normally clocked in on falling edges of this clock. When con-

trol bit TCLKIp is 1, data is clocked in on the rising edges of this

clock.

Note: TCI11 is lead G1, TCI12 is lead C10, TCI13 is lead B2, TCI14

is lead B12, TCI21 is lead D8, etc.

Transmit Group p, Port n Data Positive Rail or NRZ:

H3, C9, C2,

B14, D18,

When con-

trol bit BYPASnp is 0, positive rail input data is provided on this lead.

When control bit BYPASnp is 1, an NRZ signal is provided on this

lead.

Note: TPI11 is lead H3, TPI12 is lead C9, TPI13 is lead C2, TPI14 is

lead B14, TPI21 is lead D18, etc.

F26, H4, C26,

AA4, AE12,

V2, AD19,

AF16, V26,

AC19, R23

PRELIMINARY TXC-04216-MB

- 21 -

Ed. 2, October 2000

E1Mx16

TXC-04216

DATA SHEET

Symbol

Lead No.

I/O/P Type

I TTL

Name/Function

Transmit Group p, Port n Data Negative Rail/External Loss Of

TNIpn/ H1, D10, C1,

Signal:

B13, C18,

F25, B9, C25,

AA1, AC11,

V1, AD12,

When control bit BYPASnp is 0, negative rail input data is

TLOSpn

provided on this lead. When control bit BYPASnp is 1, this lead may

be used to input an active low external loss of signal indicator from

the line interface device.

AE16, W25,

AD20, N24

Note: TNI11/TLOS11 is lead H1, TNI12/TLOS12 is lead D10, TNI13/

TLOS13 is lead C1, TNI14/TLOS14 is lead B13, TNI21/TLOS21 is

lead C18, etc.

Quiet Group p, Port n:

A high forces the RPOpn and RNOpn leads

to the 0 state for either a rail or NRZ interface, overriding control bit

RnENp when it is 0. A low disables this feature.

Note: QUIET11 is lead G2, QUIET12 is lead D11, QUIET13 is lead

B1, QUIET14 is lead C12, QUIET21 is lead G4, etc.

QUIETpn G2, D11, B1,

C12, G4, E24,

B15, B24, Y3,

AC10, U2,

I

TTL

AE11, AE13,

U24, AE20,

N23

MICROPROCESSOR BUS INTERFACE SELECTION

Symbol Lead No. I/O/P Type

Name/Function

Motorola Mode

MOTO

R1

I

TTL

: Intel bus interface is selected when low. Motorola bus

interface is selected when high. This selection modifies some bus inter-

face lead functions, as described in the next section of this table.

MICROPROCESSOR BUS INTERFACE - SPLIT BUS FOR MOTOROLA (M) OR INTEL (I) (p=1-4)

Symbol Lead No. I/O/P

A(10-0) A15, C3,

Type

Name/Function

Address Bus:

I

TTL

These address line inputs are used for accessing an

B3, A3, (Note 1) (Note 1) E1Mx16 memory location for a read/write cycle. A10 is the most sig-

A4, C5,

B20, A7,

A20, B21,

A8

nificant bit. High is logic 1.

Data Bus:

Bidirectional data lines used for transferring data to or

8mA from an E1Mx16 memory location. D7 is the most significant bit.

High is logic 1.

D(7-0) C21, B22,

A22, A9,

I/O

TTL

A23, B23,

A24, A10

Select:

A low enables data transfers between the microprocessor

and a group p address of the E1Mx16 memory during a read/write

cycle. Only one SELp lead may be held low for a read cycle.

A6, A19,

P4, B18

I

TTL

SELp

Read (I mode) or Read/Write (M mode):

Intel Mode - An active low signal generated by the microprocessor

for reading the E1Mx16 memory locations.

D14

RD /

RD/WR

Motorola Mode - An active high signal generated by the micropro-

cessor for reading the E1Mx16 memory locations. An active low sig-

nal is used to write to memory locations.

PRELIMINARY TXC-04216-MB

- 22 -

Ed. 2, October 2000

E1Mx16

TXC-04216

DATA SHEET

Symbol Lead No. I/O/P

Type

Name/Function

Write (I mode) or Device Select (M mode):

Intel Mode - An active low signal generated by the microprocessor

for writing to the E1Mx16 memory locations.

D15

I

TTL

WR /

LDS

Motorola Mode - The SELp and LDS inputs are logically OR-gated

inside the E1Mx16, generating an internal active low select signal

(CS) that is similar to SELp. This internal signal is used to enable

data transfer. This lead can be used for the interface with the Motor-

ola 68302 microprocessor. If it is not used, it should be tied to

ground, so that CS is the same signal as SELp.

Ready (I mode) or Data Transfer Acknowledge (M mode):

A11, A25,

A17, P24

O(T)

TTL

RDYp/

8mA Intel Mode - A high is an acknowledgment from the addressed group

p E1Mx16 memory location that the transfer can be completed. A

low indicates that the Mapper cannot complete the transfer cycle,

and that microprocessor wait states must be generated for that

group.

DTACKp

Motorola Mode - During a read bus cycle, a low signal indicates that

the information on the data bus is valid. During a write bus cycle, a

low signal acknowledges the acceptance of data. This lead is

tristated.

Interrupt:

When INTSH is high, a high on this output lead signals an

INTp / B5, B17,

O(T)

I

TTL

J4, G23

8mA interrupt request INTp to the microprocessor, as required for Intel.

When INTSH is low, a low signals an interrupt request IRQp to the

microprocessor, as required for Motorola.

IRQp

Interrupt Sense High:

Interrupt polarity select. A high on this lead

INTSH

A18

TTL

causes the interrupt sense to be high when an interrupt occurs. A

low causes the interrupt sense to be low when an interrupt occurs.

This lead must be set to meet the interrupt polarity requirement of

the microprocessor.

Note 1: Leads A(10-0) are implemented as I/O type TTL 4mA to support production tests but are used as TTL inputs.

CONTROLS, EXTERNAL CLOCK AND TEST LEADS (p=1-4

Symbol Lead No. I/O/P Type

)

Name/Function

TranSwitch Test Leads:

TESTp A12, B25,

M2, R25

I

CMOS

TTLp

TTL

A low must be placed on these leads.

TranSwitch Test Leads:

internal pull-up to V_DD. They must be left floating or held high.

B6, B19,

T4, H23

These leads are pulled high internally by an

TESTp

TranSwitch Test Leads:

tion.

TXCTI1

TXCTI2

A5,

T1

These leads must be tied low for proper opera-

TranSwitch Test Leads:

to another lead and must be left floating. Connection of these leads may

impair performance or cause damage to the device.

TXCTI3

TXCTI4

TXCTI5

L4,

AD2,

AE15

TTLp

These leads are not to be connected, not even

External Reference Clock:

This clock is used for desynchronizer opera-

EXTCK

C13

I

CMOS

tion and other purposes. The clock frequency must be 58.32 MHz (± 30

ppm over life) and the clock duty cycle must be (50 ± 10) %.

PRELIMINARY TXC-04216-MB

- 23 -

Ed. 2, October 2000

E1Mx16

TXC-04216

DATA SHEET

Symbol Lead No. I/O/P Type

Name/Function

When an active low pulse is applied to this lead for a

Hardware Reset:

B4

I

TTL

RESET

minimum duration of 150 nanoseconds after power is applied, this pulse

clears all performance counters and alarms, resets the control bits

(except those bits that force a high impedance state for the add buses),

and initializes the internal FIFOs and internal SPOT processor. The

microprocessor must write the control bit states for normal operation.

High Impedance Select:

A21

C4

I

TTL

A low forces all output leads to the high imped-

ance state for testing purposes (except TDO).

Add Bus Timing Select:

HIGHZ

ABUST

A low selects the A and B Add bus clock, SPE

and C1J1V1 input signals for deriving timing for the A and B Add buses. A

high selects the like-named drop bus for deriving timing (e.g., A Drop bus

for A Add bus). This control lead is disabled for group p when a 1 is writ-

ten to control bit SBTENp. Control bit DRPBTp then makes the timing

source selection for group p.

BOUNDARY SCAN INTERFACE SIGNALS

Symbol Lead No. I/O/P Type

Name/Function

IEEE 1149 1 Test Port Serial Scan Clock:

This signal is used to shift

TCK

AE2

I

TTL

.

data into TDI on the rising edge, and out of TDO on the falling edge. The

maximum clock frequency is 10 MHz.

IEEE 1149.1 Test Port Mode Select:

TMS

AD3

I

TTLp

TMS is sampled on the rising edge

of TCK, and is used to place the Test Access Port controller into various

states as defined in IEEE 1149.1. This lead is set high internally by an

internal pull-up to V_DDfor normal framer operation.

IEEE 1149.1 Test Port Serial Scan Data In:

TDI

L2

I

TTLp

Serial test instructions and

data are clocked into this lead on the rising edge of TCK. This input has

an internal pull-up to V_DD

IEEE 1149.1 Test Port Serial Scan Data Out:

Serial test instructions and

.

TDO

AE14

AB3

O(T) TTL

4mA data are clocked out of this lead on the falling edge of TCK. When inactive,

this 3-state output will be put into its high impedance state.

IEEE 1149.1 Test Port Reset Lead:

This lead will asynchronously reset

I

TTLp

TRS

the Test Access Port (TAP) controller. This lead is to be held low, asserted

low or pulsed low (for a minimum duration of 20 ns) to reset the TAP con-

troller on E1Mx16 power-up. This input has an internal pull-up to V_DD

.

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 24 -

E1Mx16

TXC-04216

DATA SHEET

ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS

Parameter

Symbol

Min

Max

Unit

Conditions

Supply voltage

V_DD

V_IN

T_S

-0.5

-55

-40

+6.0

V_DD+ 0.5

150

V

^oC

^oC x s

Note 1

DC input voltage

Storage temperature range

Ambient Operating Temperature

Component Temperature x Time

Moisture Exposure Level

Note 1

T_A

85

0 ft/min linear airflow

Note 1

TI

270 x 5

ME

5

Level

per EIA/JEDEC

JESD22-A112-A

Relative Humidity, during assembly

Relative Humidity

ESD Classification

LATCH-UP

RH

30

0

60

%

V

Note 2

non-condensing

Note 3

100

ESD

LU

absolute value 1500

Meets JEDEC 78

Notes:

1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max

values for extended periods may impair device reliability.

2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the

"CAUTION" label on the drypack bag in which devices are supplied.

3. Test method for ESD per MIL-STD-883D, Method 3015.7.

THERMAL CHARACTERISTICS

Parameter

Min

Typ

Max

Unit

Test Conditions

Thermal resistance:

15

^oC/W

0 ft/min linear airflow

junction to ambient

POWER REQUIREMENTS

Parameter

Min

Typ

Max

Unit

Test Conditions

V_DD

4.75

5.0

280

5.25

310

V

I_DD

mA

mW

mA

mW

STS-1

Power dissipation, P_DD

I_DD

1400

310

1627

340

STS-1

STM-1 or STS-3

Power dissipation, P_DD

1550

1785

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 25 -

E1Mx16

TXC-04216

DATA SHEET

INPUT, OUTPUT AND INPUT/OUTPUT PARAMETERS

INPUT PARAMETERS

Input Parameters For CMOS

Parameter

Min

Typ

Max

Unit

Test Conditions

V_IH

V_IL

0.7 x V_DD

V

4.75 < V_DD< 5.25

0.3 x V_DD

Input capacitance (leads TESTp)

Input capacitance (lead EXTCK)

7.5

30

pF

Input Parameters For TTL

Parameter

Min

Typ

Max

Unit

Test Conditions

V_IH

V_IL

2.0

V

4.75 < V_DD< 5.25

0.8

Input capacitance (leads TCIpn,

TPIpn, TNIpn/TLOSpn, QUIETpn

and SELp)

7.5

30

pF

Input capacitance (all other leads)

pF

Input Parameters For TTLp

Parameter

Min

Typ

Max

Unit

Test Conditions

V_IH

V_IL

2.0

V

4.75 < V_DD< 5.25

0.8

Input capacitance

(leads TDI, TESTp, TXCTI3,

TXCTI4 and TXCTI5)

7.5

70

pF

Input resistance

kΩ

(leads TDI, TESTp, TXCTI3,

TXCTI4 and TXCTI5)

Input capacitance

(all other leads)

30

pF

Input resistance

(all other leads)

17.5

kΩ

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 26 -

E1Mx16

TXC-04216

DATA SHEET

OUTPUT PARAMETERS

Output Parameters For CMOS 4mA

Parameter

Min

Typ

Max

Unit

Test Conditions

V_OH

V_OL

I_OL

V_DD- 0.7

V

V_DD= 4.75; I_OH= -4.0

V_DD= 4.75; I_OL= 4.0

0.4

4.0

mA

pF

I_OH

-4.0

Input capacitance (leads AAPAR,

AA(7-0), BAPAR and BA(7-0))

30

Input capacitance (all other leads)

7.5

pF

Output Parameters For TTL 4mA

Parameter

Min

Typ

Max

Unit

Test Conditions

V_OH

2.4

V

V_DD= 4.75; I_OH= -4.0

V_DD= 4.75; I_OL= 4.0

V_OL

0.4

4.0

I_OL

mA

pF

I_OH

-4.0

Input capacitance

7.5

Output Parameters For TTL 8mA

Parameter

Min

Typ

Max

Unit

Test Conditions

V_OH

2.4

V

V_DD= 4.75; I_OH= -8.0

V_DD= 4.75; I_OL= 8.0

V_OL

0.4

8.0

I_OL

mA

pF

I_OH

-8.0

Input capacitance

7.5

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 27 -

E1Mx16

TXC-04216

DATA SHEET

INPUT/OUTPUT PARAMETERS

Input/Output Parameters For TTL 4mA

Parameter

Min

Typ

Max

Unit

Test Conditions

V_IH

V_IL

2.0

V

4.75 < V_DD< 5.25

V_DD= 4.75; I_OH= -4.0

V_DD= 4.75; I_OL= 4.0

0.8

V_OH

V_OL

I_OL

2.4

V

0.4

4.0

V

mA

pF

I_OH

-4.0

Input capacitance

30

Input/Output Parameters For TTL 8mA

Parameter Min

Typ

Max

Unit

Test Conditions

V_IH

V_IL

2.0

V

4.75 < V_DD< 5.25

V_DD= 4.75; I_OH= -8.0

V_DD= 4.75; I_OL= 8.0

0.8

V_OH

V_OL

I_OL

2.4

V

0.4

8.0

V

mA

pF

I_OH

-8.0

Input capacitance

30

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 28 -

E1Mx16

TXC-04216

DATA SHEET

TIMING CHARACTERISTICS

Detailed timing diagrams for the E1Mx16 device are illustrated in Figures 4 through 14, with values of the tim-

ing intervals tabulated below the waveform diagrams. The tristate condition of a signal waveform is shown as

midway between high and low. The timing parameters are measured at voltage levels of (V_IH+ V_IL)/2 for input

signals or (V_OH+ V_OL)/2 for output signals, unless otherwise indicated. Where a waveform diagram describes

both A and B bus signals, their symbols are combined in labeling the waveform (e.g., A/BADDp for AADDp and

BADDp).

Figure 4. Groups 1-4, Ports 1-4 E1 Transmit Timing

t_CYC

t_PWH

t_PWL

TCIpn

(Input)

t_SU

t_H

TPIpn/TNIpn

(Input)

Note: p = 1 - 4 identifies a group of four ports

n = 1 - 4 identifies one of four ports

Notes:

1. TCIpn is shown for TCLKIp = 0, where data is clocked in on falling edges. Data is clocked in on rising edges when

TCLKIp =1.

2. For NRZ operation, TNIpn is not used for data input and may instead be used as the input for an external active low

loss of signal indication TLOSpn. Otherwise, this lead must be held high.

Parameter

TCIpn clock period

Symbol

Min

Typ

Max

Unit

t_CYC

t_PWL

t_PWH

t_SU

488.28

ns

TCIpn clock low time

150

10

TCIpn clock high time

TPIpn/TNIpn data setup time before TCIpn↓

TPIpn/TNIpn data hold time after TCIpn↓

t_H

3.0

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 29 -

E1Mx16

TXC-04216

DATA SHEET

Figure 5. Groups 1-4, Ports 1-4 E1 Receive Timing

t_CYC

t_PWL

t_PWH

RCOpn

(Output)

t_OD

RPOpn/RNOpn

(Output)

Note: p = 1 - 4 identifies a group of four ports

n = 1 - 4 identifies one of four ports

Note: RCOpn is shown for RCLKIp=0, where data is clocked out on rising edges. Data is clocked out on falling edges when

RCLKIp=1.

Parameter

RCOpn clock period

Symbol

Min

Typ

Max

Unit

t_CYC

t_PWL

t_PWH

t_PWL

t_PWH

t_OD

480

498

ns

RCOpn clock low time (RCLKIp = 0)

RCOpn clock high time (RCLKIp = 0)

RCOpn clock low time (RCLKIp = 1)

RCOpn clock high time (RCLKIp = 1)

RPOpn/RNOpn data delay after RCOpn↑

257

222

241

257

2.0

5.0

Note: All output times are measured with a maximum 75 pF load capacitance.

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 30 -

E1Mx16

TXC-04216

DATA SHEET

Figure 6. STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus

t

CYC

t

PWH

A/BDCLK

(Input)

t

SU(1)

H(1)

A/BD(7-0)

A/BDPAR

(Input)

TU/VT

Selected

A1

A2

C1

Data

J1

Data

t

SU(2)

t

H(2)

A/BDSPE

(Input)

Occurs every four frames

when provided in place

of the H4 byte

t

SU(3)

H(3)

A/BDC1J1V1

(Input)

C1

J1

V1

Drop Bus TU/VT Time Slot when enabled

t

D(1)

A/BDINDp

(Output)

t

OD(3)

t

OD(2)

A/BA(7-0)

A/BAPAR

(Output)

TU/VT

Selected

t

OD(5)

t

OD(1)

A/BADDp

(Output)

Add Bus TU/VT Time Slot when enabled

t

OD(4)

A/BAINDp

(Output)

Note: For illustration purposes, a single TU/VT (TU number 21) is shown. The V1 pulse may or may not be present. If it is

not present, the H4 byte must be provided. An additional byte time of delay in A/BA(7-0) is provided when control bit

ABDp is written with a 1. The table omits A/B parameter prefixes. p=1-4 in both the table and figure. DSPE edges are

at payload boundaries.

Parameter

Symbol Load

Min

Typ

Max

Unit

DCLK clock period

DLCK duty cycle t_{PWH CYC}

t_CYC

154.32

50

ns

%

/t

40

10

60

D(7-0)/DPAR data /parity setup time before DCLK↓

D(7-0)/DPAR data /parity hold time after DCLK↓

DSPE setup time before DCLK↓

t_SU(1)

t_H(1)

t_SU(2)

t_H(2)

t_SU(3)

t_H(3)

ns

5.0

10

DSPE hold time after DCLK↓

5.0

10

DC1J1V1 setup time before DCLK↓

DC1J1V1 hold time after DCLK↓

5.0

7.0

9.0

8.0

9.0

7.0

DINDp drop bus indication output delay from DCLK↑

A(7-0)/APAR data /parity out valid delay from DCLK↑

A(7-0)/APAR data /parity to tristate delay from DCLK↑

ADDp add indicator delay from DCLK↑

t_D(1)

10 pF

45 pF

30

39

20

30

9.0

t_OD(2)

t_OD(3)

t_OD(1)

t_OD(4)

t_OD(5)

10 pF

45 pF

AINDp add bus indication output delay from DCLK↑

A(7-0)/APAR data /parity out tristate to driven delay

from DCLK↑

Note: All output times are measured with the specified load capacitance.

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 31 -

E1Mx16

TXC-04216

DATA SHEET

Figure 7. STM-1/STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus

t

CYC

t

PWH

A/BDCLK

(Input)

t_SU(1)

t_H(1)

A/BD(7-0)

A/BDPAR

(Input)

TU/VT

Selected

J1 Byte

STS-1 #1

Data

STS-1 #1

C1(1)

C1(2)

C1(3)

Data

STS-1 #2

STS-1 #3

t

SU(2)

t

H(2)

A/BDSPE

(Input)

Occurs every four frames

when provided in place

of the H4 byte

t_SU(3)

t_H(3)

A/BDC1J1V1

(Input)

C1(1)

J1 STS-1 #1 J1 STS-1 #2 J1 STS-1 #3 V1 STS-1 #1

Drop Bus TU/VT Time Slot selected when enabled

t

D(1)

A/BDINDp

(Output)

t

OD(2)

t

OD(3)

A/BA(7-0)

APAR

(Output)

TU/VT

Selected

t

OD(5)

t

OD(1)

A/BADDp

(Output)

Add Bus TU/VT Time Slot

selected when enabled

t

OD(4)

A/BAINDp

(Output)

Note: A single TU/VT is shown for illustration purposes. It also shows the TU/VT selection for the drop bus and add bus

(number 21 in STS-1 number 3). The format is an AU-3/STS-3. For VC-4 operation, one J1 pulse and one optional

V1 pulse are present. An additional byte time of delay in A/BA(7-0) is provided when control bit ABDp is written with

a 1. The table omits A/B parameter prefixes. p=1-4 in both the table and figure. DSPE edges are at payload bound-

aries.

Parameter

Symbol Load

Min

Typ

Max

Unit

DCLK clock period

DCLK duty cycle t_{PWH CYC}

t_CYC

51.44

50

ns

%

/t

40

10

60

D(7-0)/DPAR data /parity setup time before DCLK↓

D(7-0)/DPAR data /parity hold time after DCLK↓

DSPE setup time before DCLK↓

t_SU(1)

t_H(1)

t_SU(2)

t_H(2)

t_SU(3)

t_H(3)

ns

5.0

10

DSPE hold time after DCLK↓

5.0

10

DC1J1V1 setup time before DCLK↓

DC1J1V1 hold time after DCLK↓

5.0

7.0

9.0

8.0

9.0

7.0

DINDp drop bus indication output delay from DCLK↑

A(7-0)/APAR data /parity out valid delay from DCLK↑

A(7-0)/APAR data /parity to tristate delay from DCLK↑

ADDp add indicator delay from DCLK↑

t_D(1)

10 pF

45 pF

30

39

20

30

9.0

t_OD(2)

t_OD(3)

t_OD(1)

t_OD(4)

t_OD(5)

10 pF

45 pF

AINDp add bus indication output delay from DCLK↑

A(7-0)/APAR data /parity out tristate to driven delay from

DCLK↑

Note: All output times are measured with the specified load capacitance.

- 32 -

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

E1Mx16

TXC-04216

DATA SHEET

Figure 8. STS-1 A/B Add Bus Signals, Timing Derived from Add Bus

t

CYC

t

PWH

A/BACLK

(Input)

t

SU(2)

t

H(2)

A/BASPE

(Input)

Occurs every four frames

when provided

t

H(1)

SU(1)

A/BAC1J1V1

(Input)

C1

J1

V1

t

OD(2)

t

OD(3)

A/BA(7-0)

A/BAPAR

(Output)

TU/VT

Selected

t

OD(5)

t

OD(1)

A/BADDp

(Output)

Add Bus TU/VT Time Slot when enabled

t

OD(4)

A/BAINDp

(Output)

Note: For illustration purposes, a single TU/VT is shown. The location of this TU/VT corresponds to TU/VT number 21. An

additional byte time of delay in A/BA(7-0) is provided when control bit ABDp is written with a 1. The table omits A/B

parameter prefixes. p=1-4 in both the table and figure. ASPE edges are at payload boundaries.

Symbo

Parameter

Load

Min

Typ

Max

Unit

l

ACLK clock period

t_CYC

154.32

50

ns

%

ACLK duty cycle, t_PWH/t_CYC

40

10

60

AC1J1V1 setup time before ACLK↓

t_SU(1)

t_H(1)

t_SU(2)

t_H(2)

ns

AC1J1V1 hold time after ACLK↓

5.0

10

ASPE setup time before ACLK↓

ASPE hold time after ACLK↓

5.0

7.0

5.0

A(7-0)/APAR data /parity out valid delay from ACLK↑

A(7-0)/APAR data /parity to tristate delay from ACLK↑

ADDp add indicator delay from ACLK ↑

AINDp add bus indication output delay from ACLK↑

t_OD(2)

t_OD(3)

t_OD(1)

t_OD(4)

31

16

24

7.0

45 pF

10 pF

A(7-0)/APAR data /parity out tristate to driven delay from t_OD(5)45 pF

ACLK↑

Note: All output times are measured with the specified load capacitance.

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 33 -

E1Mx16

TXC-04216

DATA SHEET

Figure 9. STM-1/STS-3 A/B Add Bus Signals, Timing Derived from Add Bus

t

CYC

t

PWH

A/BACLK

(Input)

t

SU(2)

t

H(2)

A/BASPE

(Input)

Occurs every four frames

t_SU(1)

t_H(1)

when enabled

A/BAC1J1V1

(Input)

C1(1)

J1 STS-1 #1 J1 STS-1 #2 J1 STS-1 #3 V1 STS-1 #1 V1 STS-1 #2 V1 STS-1 #3

t

OD(2)

t

OD(3)

A/BA(7-0)

A/BAPAR

(Output)

TU/VT

Selected

OD(5)

OD(1)

t

A/BADDp

(Output)

Add Bus TU/VT Time Slot

selected when enabled

t

OD(4)

A/BAINDp

(Output)

Note: A single TU/VT is shown for illustration purposes. It also shows the TU/VT selection for the drop bus and add bus

(number 21 in STS-1 number 3). The format is an AU-3/STS-3. For VC-4 operation, one J1 pulse and one optional

V1 pulse are present. An additional byte time of delay in A/BA(7-0) is provided when control bit ABDp is written with

a 1. The table omits A/B parameter prefixes. p=1-4 in both the table and figure. ASPE edges are at payload bound-

aries.

Symbo

Parameter

Load

Min

Typ

Max Unit

l

ACLK clock period

t_CYC

51.44

50

ns

ACLK duty cycle, t_PWH/t_CYC

40

10

60

%

ns

AC1J1V1 setup time before ACLK↓

t_SU(1)

t_H(1)

t_SU(2)

t_H(2)

AC1J1V1 hold time after ACLK↓

5.0

10

ASPE setup time before ACLK↓

ASPE hold time after ACLK↓

5.0

7.0

5.0

A(7-0)/APAR data /parity out valid delay from ACLK↑

A(7-0)/APAR data /parity to tristate delay from ACLK↑

ADDp add indicator delay from ACLK↑

AINDp add bus indication output delay from ACLK↑

t_OD(2)

t_OD(3)

t_OD(1)

t_OD(4)

31

16

31

7.0

45 pF

10 pF

A(7-0)/APAR data /parity out tristate to driven delay from t_OD(5)45 pF

ACLK↑

Note: All output times are measured with the specified load capacitance.

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 34 -

E1Mx16

TXC-04216

DATA SHEET

Figure 10. Microprocessor Read Cycle Timing - Intel

t_H(1)

A(10-0)

(Input)

Address

t_D(5)

Data

t_F(1)

D(7-0)

(Output)

t_SU(1)

t_D(1)

SELp

(Input)

t_SU(2)

t_H(2)

t_PW(1)

RD

(Input)

t_D(3)

t_F(2)

t_D(4)

t_D(2)

RDYp

(Output)

t_PW(2)

Note: p=1-4 in both the table and figure.

Parameter

Symbol

Min

Typ

Max

Unit

Address setup time to SELp↓

t_SU(1)

t_H(1)

0.0

3.0

2.0

10

ns

Address hold time after RD↑

Data output float time after RD↑

SELp↓ setup time to RD↓

RD pulse width

t_F(1)

11

t_SU(2)

t_PW(1)

t_H(2)

40

SELp↓ hold time after RD↓

RDYp↑ delay after SELp↓

RDYp↓ delay after RD↓

RDYp float time after SELp↑

0.0

2.0

4.0

2.0

t_D(2)

10

20

t_D(3)

t_F(2)

10

Register read

t_PW(2)

0.0

RDYp pulse width

SPOT instruction read (Note 2)

Data RAM read (Note 3)

6 x SPcyc

9 x SPcyc

7 x SPcyc

33 x SPcyc ns

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 35 -

E1Mx16

TXC-04216

DATA SHEET

Parameter

Symbol

Min

Typ

Max

Unit

Data output valid delay Register read only

t_D(1)

8.0

28

ns

after RD↓

Data output valid delay SPOT instruction read and data

after RDYp↑ RAM read only

t_D(4)

0.0

ns

Data output tristate to driven delay after RD↓

t_D(5)

2.0

Notes:

1. All output times are measured with a maximum 75 pF load capacitance.

2. One SPcyc equals two EXTCK clock cycles.

(The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.)

3. Excessive external microprocessor data RAM access could interfere with the E1Mx16 internal data processing, result-

ing in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is

detected, E1Mx16 tries to slow down the external microprocessor access rate by lengthening the RDYp pulse width to

as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency for

each of the four E1Mx16 SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet).

a. For each group selected (via SELp) use 16 wait states for a read or write access if the RDYp signal is not being

used. Forcing a longer wait state for every access may create unwanted delays in the internal process for the

E1Mx16. Using the 16 wait states will provide reliability without causing excessive process delays (at the 25

MHz microprocessor frequency). For other frequencies, use an equivalent number of wait states that equals

approximately 640 ns.

b. For each group selected (via SELp) maintain no more than 16 microprocessor accesses per 125 µs frame

period.

c. For each group selected (via SELp) maintain a minimum of 600 ns between microprocessor accesses.

PRELIMINARY TXC-04216-MB

- 36 -

Ed. 2, October 2000

E1Mx16

TXC-04216

DATA SHEET

Figure 11. Microprocessor Write Cycle Timing - Intel

t_H(1)

A(10-0)

(Input)

Address

t_H(2)

D(7-0)

(Input)

Data

t_SU(2)

t_SU(1)

t_SU(4)

SELp

(Input)

t_SU(3)

t_PW(1)

WR

(Input)

t_D(1)

t_D(2)

t_F

RDYp

(Output)

t_PW(2)

Note: p=1-4 in both the table and figure.

Parameter

Symbol

Min

Typ

Max

Unit

Address setup time to SELp↓

Address hold time after WR↑

Data input valid setup time to WR↑

Data input hold time after WR↑

SELp setup time to WR↓

WR pulse width

t_SU(1)

t_H(1)

t_SU(2)

t_H(2)

t_SU(3)

t_PW(1)

t_D(1)

t_D(2)

t_F

0.0

3.0

12

ns

6.0

10

40

RDYp↑ delay after SELp↓

RDYp↓ delay after WR↓

2.0

4.0

2.0

10

20

10

RDYp float time after SELp↑

PRELIMINARY TXC-04216-MB

Ed. 2, October 2000

- 37 -

E1Mx16

TXC-04216

DATA SHEET

Parameter

Symbol

Min

Typ

Max

Unit

Register write

t_PW(2)

0.0

ns

RDYp pulse width

SPOT instruction write (Note 2)

Data RAM write (Note 3)

5 x SPcyc

9 x SPcyc

7 x SPcyc

29 x SPcyc ns

ns

Data valid setup time SPOT instruction write and data

t_SU(4)-1 x SPcyc

to WR↓

RAM write only