U6264ADK10 [ETC]
STANDARD 8K X 8 SRAM; 标准的8K ×8 SRAM
| 型号： | U6264ADK10 |
| 厂家： | 
ETC |
| 描述： | STANDARD 8K X 8 SRAM |
| 文件： | 总9页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U6264A
Standard 8K x 8 SRAM
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: PDIP28 (600 mil)
SOP28 (300 mil)
DQ0 - DQ7. After the address
Features
change, the data outputs go High-Z
until the new read information is
available. The data outputs have no
preferred state. If the memory is
driven by CMOS levels in the active
state, and if there is no change of
the address, data input and control
signals W or G, the operating cur-
rent (at IO = 0 mA) drops to the
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
8192 x 8 bit static CMOS RAM
70 and 100 ns Access Times
Common data inputs and
outputs
Three-state outputs
Typ. operating supply current
70 ns: 45 mA
SOP28 (330 mil)
Description
The U6264A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
100 ns: 37 mA
Data retention current
at 3 V: < 10 µA (standard)
Standby current standard < 30 µA
Standby current low power
(L) < 10 µA
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
6-transistor cell.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
Standby current very low power
(LL) < 1 µA
The circuit is activated by the rising inputs consist of NOR gates, so that
edge of E2 (at E1 = L), or the falling no pull-up/pull-down resistors are
Standby current for LL-version
at 25 °C and 5 V: typ. 50 nA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
edge of E1 (at E2
= H). The required. This gate circuit allows to
address and control inputs open achieve low power standby require-
simultaneously. According to the ments by activation with TTL-levels
information of W and G, the data too.
inputs, or outputs, are active. If the circuit is inactivated by
During the active state (E1 = L and E2 = L, the standby current (TTL)
E2 = H), each address change drops to 150 µA typ.
leads to a new Read or Write cycle.
Power supply voltage 5 V
Operating temperature ranges:
0 to 70 °C
-25 to 85 °C
In a Read cycle, the data outputs
-40 to 85 °C
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
Pin Description
Pin Configuration
n.c.
A12
A7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
VCC
2
W (WE)
E2 (CE2)
A8
3
A6
4
Signal Name Signal Description
A5
5
A9
A0 - A12
Address Inputs
Data In/Out
A4
6
A11
DQ0 - DQ7
A3
7
G (OE)
A10
PDIP
SOP
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
E1
A2
8
E2
A1
9
E1 (CE1)
DQ7
G
A0
10
11
12
13
14
W
DQ0
DQ1
DQ2
VSS
DQ6
VCC
VSS
DQ5
DQ4
not connected
n.c.
DQ3
Top View
December 12, 1997
1
U6264A
Block Diagram
A4
A5
Memory Cell
Array
A6
A7
A8
256 Rows x
256 Columns
A9
A11
A12
A0
A1
A2
A3
A10
DQ0
DQ1
Sense Amplifier/
Write Control Logic
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
E2
E1
VSS
W
G
VCC
1
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
*
H
L
L
L
L
*
*
*
*
*
High-Z
High-Z
Standby/not
selected
Internal Read
Read
H
H
H
H
H
L
H
L
*
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
-
7
V
V
VCC + 0.5
VCC + 0.5
1
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
C-Type
G-Type
K-Type
0
-25
-40
70
85
85
°C
°C
°C
Storage Temperature
Tstg
-55
125
°C
December 12, 1997
2
U6264A
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
Data Retention Voltage
VCC
4.5
2.0
5.5
V
V
VCC(DR)
Input Low Voltage*
VIL
VIH
-0.3
2.2
0.8
V
Input High Voltage
VCC + 0.3
V
* -2 V at Pulse Width 10 ns
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
VIH
= 5.5 V
= 0.8 V
= 2.2 V
Standard
tcW
tcW
=
70 ns
70
60
mA
mA
= 100 ns
Low Power (L)
Very Low Power (LL)
tcW
tcW
=
70 ns
70
60
mA
mA
= 100 ns
tcW
tcW
=
70 ns
55
45
mA
mA
= 100 ns
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
ICC(SB)1
ICC(DR)
VCC
= 5.5 V
VE1 = VE2 = VCC - 0.2 V
or VE2
= 0.2 V
Standard
Low Power (L)
Very Low Power (LL)
30
10
1
µA
µA
µA
Supply Current - Standby Mode
(TTL level)
VCC
= 5.5 V
VE1 = VE2 = 2.2 V
or VE2
= 0.2 V
Standard
Low Power (L)
Very Low Power (LL)
5
5
3
mA
mA
mA
Supply Current - Data Retention
Mode
VCC(DR)
VE1 = VE2 = VCC(DR) - 0.2 V
or VE2 = 0.2 V
=
3 V
Standard
Low Power (L)
Very Low Power (LL)
10
10
1
µA
µA
µA
December 12, 1997
3
U6264A
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Output High Voltage
VOH
VCC
IOH
VCC
IOL
= 4.5 V
= -1.0 mA
= 4.5 V
2.4
V
Output Low Voltage
VOL
0.4
V
= 3.2 mA
Input Leakage Current
Standard &
Low Power (L)
High
Low
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
2
µA
µA
-2
=
0 V
Very Low Power (LL) High
Low
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
1
µA
µA
-1
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-1
mA
mA
3.2
Output Leakage Current
Standard &
Low Power (L)
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
2
µA
µA
Low at Three-State Outputs
-2
-1
=
0 V
Very Low Power (LL)
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
1
-
µA
µA
Low at Three-State Outputs
=
0 V
December 12, 1997
4
U6264A
Symbol
Min.
Max.
Unit
Switching Characteristics
Alt.
IEC
07
10
07
10
Time to Output in Low-Z
tLZ
tt(QX)
5
5
10
10
ns
Cycle Time
Write Cycle Time
Read Cycle Time
tWC
tRC
tcW
tcR
70
70
100
100
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
tACE
tOE
tAA
ta(E)
ta(G)
ta(A)
-
-
-
-
-
-
70
40
70
100
50
100
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
tWP
tCW
tw(W)
tw(E)
50
65
70
90
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
tAS
tCW
tWP
tDS
tsu(A)
tsu(E)
tsu(W)
tsu(D)
0
0
ns
ns
ns
ns
65
50
35
90
70
40
Data Hold Time
Address Hold from End of Write
tDH
tAH
th(D)
th(A)
0
0
0
0
ns
ns
Output Hold Time from Address
Change
tOH
tv(A)
5
5
ns
E1 HIGH or E2 LOW to Output in
High-Z
tHZCE
tdis(E)
0
0
25
35
ns
W LOW to Output in High-Z
G HIGH to Output in High-Z
tHZWE
tHZOE
tdis(W)
tdis(G)
0
0
0
0
30
25
35
35
ns
ns
Data Retention Mode E2-Controlled
Data Retention Mode E1-Controlled
VCC
VCC
E2
4.5 V
4.5 V
V
CC(DR) ≥ 2 V
V
CC(DR) ≥ 2 V
2.2 V
2.2 V
E1
Data Retention
tDR
trec
trec
tDR
Data Retention
0.8 V
0.8 V
VE2(DR) ≤ 0.2 V
0 V
0
V
V
E2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
CC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
tDR
:
min 0 ns
min tcR
trec
:
December 12, 1997
5
U6264A
Test Configuration for Functional Check
5 V
VCC
A0
A1
A2
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A4
960
A5
VIH
A6
A7
A8
A9
A10
A11
A12
VIL
V
O
30 pF1)
E1
E2
W
G
510
VSS
1) In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF.
Capacitance
Conditions
Symbol
Min.
Max.
Unit
V
CC = 5.0 V
Input Capacitance
CI
8
pF
VI = VSS
f
= 1 MHz
Output Capacitance
CO
10
pF
Ta = 25 °C
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U6264A
D
G
07
L
Type
Package
Internal Code
D
S
= PDIP
= SOP (330 mil)
S1 = SOP (300 mil)
Operating Temperature Range
Power Consumption
C
=
0 to 70 °C
G = -25 to 85 °C
= -40 to 85 °C
= Standard
= Low Power
LL = Very Low Power
L
Access Time
07 = 70 ns
10 = 100 ns
K
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
December 12, 1997
6
U6264A
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)
tcR
Ai
Addresses Valid
ta(A)
Output Data
Valid
Previous
Data Valid
DQi
Output
tv(A)
Read Cycle 2 (during Read cycle: W = VIH)
tcR
Ai
Addresses Valid
ta(E)
tsu(A)
tt(QX)
tdis(E)
tdis(E)
E1
ta(E)
tsu(A)
tt(QX)
E2
ta(G)
tdis(G)
G
tt(QX)
DQi
Output
High-Z
Output Data
Valid
Write Cycle 1 (W-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
tsu(E)
E2
tsu(A)
tw(W)
W
th(D)
tsu(D)
DQi
Input
Input Data
Valid
tdis(W)
tt(QX)
DQi
High-Z
Output
G
December 12, 1997
7
U6264A
Write Cycle 2 (E1-controlled)
tcW
Addresses Valid
tw(E)
Ai
tsu(A)
th(A)
E1
E2
tsu(E)
tsu(W)
W
tsu(D)
th(D)
DQi
Input
Input Data
Valid
tdis(W)
tt(QX)
DQi
Output
High-Z
G
Write Cycle 3 (E2-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
E2
tsu(A)
tw(E)
tsu(W)
W
th(D)
tsu(D)
DQi
Input
Input Data
Valid
tdis(W)
tt(QX)
DQi
Output
High-Z
G
L- or H-level
undefined
December 12, 1997
8
Memory Products 1998
Standard 8K x 8 SRAM U6264A
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
The information describes the type of component and shall not be considered as
assured characteristics.
Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH
Grenzstraße 28 • D-01109 Dresden• P. O.B. 800134 •D-01101 Dresden•Germany
Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de
Internet Web Site: http://www.zmd.de
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