UC1697VGAA_技术文档

UC1697v

128x128RGB CSTN Controller-Driver

UC1697v

Single-Chip, Ultra-Low Power

128COM x 128RGB Matrix

Passive Color LCD Controller-Driver

INTRODUCTION

UC1697v is an advanced high-voltage mixed-

signal CMOS IC, specially designed for the

display needs of low power hand-held devices.

•

Support both row-ordered and column-

ordered display buffer RAM access.

Support industry standard 4-wire, 3/4-wire,

and 3-wire serial bus (S8, S8uc, S9) and

16-bit/8-bit parallel bus (8080 or 6800).

In addition to low power COM and SEG drivers,

UC1697v contains all necessary circuits for high-

V LCD power supply, bias voltage generation,

temperature compensation, timing generation,

and graphics data memory.

•

Special driver structure and gray shade

modulation scheme. Low power

consumption under all display patterns.

UC1697v employs UltraChip’s unique DCC

(Direct Capacitor Coupling) driver architecture

and LRM (Line Rate Modulation) gray-shade

modulation scheme to achieve well balanced

shading, vivid colors, and natural-looking images.

Fully programmable Mux Rate, partial

display window, Bias Ratio and Line Rate

allow many flexible power management

options.

•

Four software programmable temperature

compensation coefficients.

With UC1697v, LCD makers can now achieve

TFT-like image quality, while maintaining the

same STN advantages in power consumption,

unit cost, ease of customization and production

flexibility.

Software programmable, self-configuring

10x charge pump.

Flexible data addressing/mapping schemes

to support wide ranges of software models

and LCD layout placements.

MAIN APPLICATIONS

•

Cellular Phones and other battery operated

hand held devices or portable Instruments

•

Pad layouts support COG applications.

V_DD(digital) range: 1.8V(Typ.) ~ 3.3V

FEATURE HIGHLIGHTS

V_DD(analog) range: 2.6V(Typ.) ~ 3.3V

•

Single chip controller-driver for 128x128

matrix C-STN LCD with comprehensive

support for input format and color depth:

LCD V_OPrange: 6.4V ~ 16.5V

•

Available MTP trimming supports precise

LCD contrast matching.

8-bit RGB:

12-bit RGB:

16-bit RGB:

256-color

4K-color

64K-color

Available in gold bump dies.

COM/SEG bump information

•

A software-readable ID bit (ID0) to support

configurable vender identification.

Bump pitch:

Bump gap:

Bump surface:

26.5 µM

12.0 µM

2001 µM²

ID pin (ID1)-switched input data sets (D[7:0]

or D[14,12,10,8,6,4,2,0]) for 8-bit mode.

Partial scroll function and programmable

data update window to support flexible

manipulation of screen data.

Revision A_0.6

1

ULTRACHIP

High-Voltage Mixed-Signal IC

ORDERING INFORMATION

GOLD BUMPED DIE

Part Number

MTP

I²C

Description

UC1697vGAA

Yes

No

Gold bumped die, with MTP function.

General Notes

APPLICATION INFORMATION

For improved readability, the specification contains many application data points. When application information is given, it

is advisory and does not form part of the specification for the device.

BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing. There is no post

waffle saw/pack testing performed on individual die. Although the latest processes are utilized for wafer sawing and die

pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or

assembly of the die. Accordingly, it is the responsibility of the customer to test and qualify their applications in which the

die is to be used. UltraChip assumes no liability for device functionality or performance of the die or systems after

handling, packing or assembly of the die.

MTP LIGHT & ESD SENSITIVITY

The MTP memory cell is sensitive to photon excitation and ESD. Under extended exposure to strong ambient light, or

when TST4 pin is exposed to ESD strikes, the MTP cells can lose its content before the specified memory retention time

span. The system designer is advised to provide proper light & ESD shields to realize full MTP content retention

performance.

LIFE SUPPORT APPLICATIONS

These devices are not designed for use in life support appliances, or systems where malfunction of these products can

reasonably be expected to result in personal injuries. Customer using or selling these products for use in such

applications do so at their own risk.

CONTENT DISCLAIMER

UltraChip believes the information contained in this document to be accurate and reliable. However, it is subject to change

without notice. The information and data provided herein is for reference only. No responsibility is assumed by UltraChip

for the use of information contained in this datasheet. Always contact UltraChip for commit to mass production for the

latest product information and operation parameters.

CONTACT INFORMATION

UltraChip Inc. (Headquarter)

2F, No. 70, Chowtze Street,

Nei Hu District, Taipei 114,

Taiwan, R. O. C.

Tel: +886 (2) 8797-8947

Fax: +886 (2) 8797-8910

Sales e-mail: sales@ultrachip.com

Web site: http://www.ultrachip.com

2

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

BLOCK DIAGRAM

COLUMN ADDRESS

GENERATOR

POWER ON &

RESET

CONTROL

CLOCK &

TIMING

GENERATOR

DISPLAY DATA RAM

CONTROL &

STATUS

REGISTER

DISPLAY DATA LATCHES

LEVEL SHIFTERS

SEG DRIVERS

COMMAND

C_L

V_LCD& BIAS

GENERATOR

HOST INTERFACE

C_B1

C_B0

Revision A_0.6

3

ULTRACHIP

High-Voltage Mixed-Signal IC

PIN DESCRIPTION

Name

Type

# of Pads

Description

MAIN POWER SUPPLY

V_DD2/V_DD3is the analog power supply and it should be connected to

the same power source. V_DDis the digital power supply and it

should be connected to a voltage source that is no higher than

V_DD

V_DD2

V_DD3

9

2

V_DD2/V_DD3

.

PWR

GND

Please maintain the following relationship:

V_DD+1.3V ꢀ V_DD2/3ꢀ V_DD

Minimize the trace resistance for V_DDand V_DD2/V_DD3

.

V_SS

V_SS2

12

Ground. Connect V_SSand V_SS2to the shared GND pin.

Minimize the trace resistance for this node.

LCD POWER SUPPLY & VOLTAGE CONTROL

LCD SEG driving voltages. These are the voltage sources to

provide SEG driving currents. These voltages are generated

internally. Connect a capacitor, C_BX, between V_BX+and V_BX–

.

V_B1+, V_B1–

V_B0+, V_B0–

6, 6

PWR

The resistance of these traces directly affects the driving strength

of SEG electrodes and impacts the image of the LCD module.

Minimize the trace resistance is critical in achieving high quality

image.

High voltage LCD Power Supply. When internal V_LCDis used,

connect these pins together. When external V_LCDis used, connect

external V_LCDsource to V_LCDINpins and leave V_LCDOUTopen.

V_LCD-IN

V_LCD-OUT

2

Capacitor C_Lshould be connected between V_LCDand V_SS. In COG

applications, keep the ITO trace resistance under 30 Ω.

NOTE

•

Recommended capacitor values:

C_Bx: 2.2µF/5V or 300x LCD load capacitance, whichever is higher.

C_L: 330nF (25V) is appropriate for most applications.

4

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

Name

Type

# of Pads

Description

HOST INTERFACE

Bus mode: The interface bus mode is determined by BM[1:0] and

{DB15, DB13} by the following relationship:

BM[1:0]

11

{DB15, DB13}

Mode

Data

0x

6800/16-bit

8080/16-bit

6800/8-bit

8080/8-bit

10

01

BM0

BM1

1

00

0x

I

3-wire SPI w/ 9-bit token

(S9: conventional)

01

00

10

11

4-wire SPI w/ 8-bit token

(S8: conventional)

3/4-wire SPI w/ 8-bit token

(S8uc: Ultra-Compact)

CS0

CS1

1

Chip Select. Chip is selected when CS1=”H” and CS0 = “L”. When the

chip is not selected, D[15:0] will be high impedance.

I

When RST=”L”, all control registers are re-initialized by their default

states.

RST

CD

1

An RC Filter has been included on-chip. There is no need for external

RC noise filter. When RST is not used, connect the pin to V_DD

.

Select Control data or Display data for read/write operation. In S9, CD

pin is not used. Connect CD to V_SSwhen not used.

I

”L”: Control data

”H”: Display data

Used for production control.

Connect ID0 to V_DDfor “H” or V_SSfor “L”.

ID0

ID1

1

The wiring status of ID0 is available with PID[1:0] of the Get Status

command.

Select input data set for 8-bit mode.

ID1=0 : 8-bit input data are D[0, 2, 4, 6, 8, 10, 12, 14]

ID1=1 : 8-bit input data are D[0:7]

I

The wiring status of ID1 is available with PID[1:0] of the Get Status

command. Other than 8-bit mode, connect ID1 to V_DDfor “H” or V_SSfor

“L”.

WR[1:0] controls the read/write operation of the host interface. See

section Host Interface for more detail.

WR0

WR1

1

In parallel mode, the meaning of WR[1:0] depends on whether the

interface is in the 6800 mode or the 8080 mode. In serial interface

modes, these two pins are not used, connect them to V_SS

.

Revision A_0.6

5

ULTRACHIP

High-Voltage Mixed-Signal IC

Name

Type

# of Pads

Description

DATA BUS

Bi-directional bus for parallel host interfaces.

In serial modes, connect DB[0] to SCK, DB[8] to SDA.

BM=1x

(16-bit)

BM=0x

(8-bit)

ID1=0

BM=0x

(8-bit)

ID1=1

BM=01

(S9)

BM=00

(S8/S8uc)

DB0

DB1

DB2

D0

D1

D2

D0/D8

D1/D9

D2/D10

SCK

–

SCK

–

D1/D9

DB3

D3

–

D3/D11

–

DB4

D4

D2/D10

D4/D12

–

DB5

DB6

D5

D6

–

D5/D13

D6/D14

–

D0~D15

I/O

16

D3/D11

DB7

D7

–

D7/D15

–

DB8

DB9

D8

D9

D4/D12

–

0

SDA

–

0

–

1

SDA

–

DB10

DB11

DB12

DB13

DB14

DB15

D10

D11

D12

D13

D14

D15

D5/D13

–

D6/D14

–

D7/D15

0

–

0:S8 / 1:S8uc

–

1

Always connect unused pins to either V_SSor V_DD

.

6

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

Name

Type

# of Pads

Description

HIGH VOLTAGE LCD DRIVER OUTPUT

SEG1 ~

SEG384

SEG (column) driver outputs. Support up to 128xRGB pixels.

Leave unused SEG drivers open-circuit.

HV

384

COM (row) driver outputs. Support up to 128 rows.

COM1 ~

COM128

When designing LCM, always start from COM1. If the LCM has N

pixel rows and N is less than 128, set CEN to be N-1, and leave COM

drivers [N+1 ~ 128] open-circuit.

HV

128

MISC. PINS

Auxiliary V_DD. These pins are connected to the main V_DDbus within

the IC. These pads are provided to facilitate chip configurations in

COG application.

V_DDX

O

5

2

These pins should NOT be used to provide V_DDpower to the chip. It is

not necessary to connect V_DDXto main V_DDexternally.

Test control. This pin has on-chip pull-up resistor. Leave it open

during normal operation.

TST4

I/HV

O

TST4 is also used as one of the high voltage power supply for MTP

programming operation. For COG designs, please wire out TST4 with

trace resistance between 30~50 Ω.

TST1

TST2

1

Test I/O pins. Leave these pins open during normal use.

NOTE:

Several control registers will specify “0 based index” for COM and SEG electrodes. In those situations,

COMX or SEGX will correspond to index X-1, and the value ranges for those index registers will be 0~127

for COM and 0~383 for SEG.

Revision A_0.6

7

ULTRACHIP

High-Voltage Mixed-Signal IC

RECOMMENDED COG LAYOUT

D15

D14

D13

D12

D11

D10

D9

COM<106>

COM<108>

COM<110>

COM<112>

COM<114>

COM<116>

COM<118>

COM<120>

COM<122>

COM<124>

COM<126>

COM<128>

COM<18>

COM<16>

COM<14>

COM<12>

COM<10>

COM<8>

COM<6>

COM<4>

COM<2>

SEG<384>

SEG<383>

SEG<382>

SEG<381>

SEG<380>

SEG<379>

SEG<378>

SEG<377>

SEG<376>

SEG<375>

SEG<374>

SEG<373>

SEG<372>

SEG<371>

SEG<370>

SEG<369>

SEG<368>

SEG<367>

SEG<366>

SEG<365>

SEG<364>

SEG<363>

SEG<362>

SEG<361>

SEG<360>

SEG<359>

SEG<358>

SEG<357>

SEG<356>

SEG<355>

SEG<354>

SEG<353>

SEG<352>

SEG<351>

SEG<350>

SEG<349>

SEG<348>

SEG<347>

SEG<346>

SEG<345>

SEG<344>

SEG<343>

SEG<342>

SEG<341>

SEG<340>

SEG<339>

SEG<338>

SEG<337>

SEG<336>

SEG<335>

SEG<334>

SEG<333>

SEG<332>

SEG<331>

SEG<330>

SEG<329>

SEG<328>

SEG<327>

SEG<326>

SEG<325>

SEG<324>

SEG<323>

SEG<322>

SEG<321>

SEG<320>

SEG<319>

SEG<318>

SEG<317>

SEG<316>

SEG<315>

SEG<314>

SEG<313>

SEG<312>

SEG<311>

SEG<310>

SEG<309>

SEG<308>

SEG<307>

SEG<306>

SEG<305>

SEG<304>

SEG<303>

SEG<302>

SEG<301>

SEG<300>

SEG<299>

SEG<298>

SEG<297>

SEG<296>

SEG<295>

SEG<294>

SEG<293>

SEG<292>

SEG<291>

SEG<290>

SEG<289>

SEG<288>

SEG<287>

SEG<286>

SEG<285>

SEG<284>

SEG<283>

SEG<282>

SEG<281>

SEG<280>

SEG<279>

SEG<278>

SEG<277>

SEG<276>

SEG<275>

SEG<274>

SEG<273>

SEG<272>

SEG<271>

SEG<270>

SEG<269>

SEG<268>

SEG<267>

SEG<266>

SEG<265>

SEG<264>

SEG<263>

SEG<262>

SEG<261>

SEG<260>

SEG<259>

SEG<258>

SEG<257>

SEG<256>

SEG<255>

SEG<254>

SEG<253>

SEG<252>

SEG<251>

SEG<250>

SEG<249>

SEG<248>

SEG<247>

SEG<246>

SEG<245>

SEG<244>

SEG<243>

SEG<242>

SEG<241>

SEG<240>

SEG<239>

SEG<238>

SEG<237>

SEG<236>

SEG<235>

SEG<234>

SEG<233>

SEG<232>

SEG<231>

SEG<230>

SEG<229>

SEG<228>

SEG<227>

SEG<226>

SEG<225>

SEG<224>

SEG<223>

SEG<222>

SEG<221>

SEG<220>

SEG<219>

SEG<218>

SEG<217>

SEG<216>

SEG<215>

SEG<214>

SEG<213>

SEG<212>

SEG<211>

SEG<210>

SEG<209>

SEG<208>

SEG<207>

SEG<206>

SEG<205>

SEG<204>

SEG<203>

SEG<202>

SEG<201>

SEG<200>

SEG<199>

SEG<198>

SEG<197>

SEG<196>

SEG<195>

SEG<194>

SEG<193>

SEG<192>

SEG<191>

SEG<190>

SEG<189>

SEG<188>

SEG<187>

SEG<186>

SEG<185>

SEG<184>

SEG<183>

SEG<182>

SEG<181>

SEG<180>

SEG<179>

SEG<178>

SEG<177>

SEG<176>

SEG<175>

SEG<174>

SEG<173>

SEG<172>

SEG<171>

SEG<170>

SEG<169>

SEG<168>

SEG<167>

SEG<166>

SEG<165>

SEG<164>

SEG<163>

SEG<162>

SEG<161>

SEG<160>

SEG<159>

SEG<158>

SEG<157>

SEG<156>

SEG<155>

SEG<154>

SEG<153>

SEG<152>

SEG<151>

SEG<150>

SEG<149>

SEG<148>

SEG<147>

SEG<146>

SEG<145>

SEG<144>

SEG<143>

SEG<142>

SEG<141>

SEG<140>

SEG<139>

SEG<138>

SEG<137>

SEG<136>

SEG<135>

SEG<134>

SEG<133>

SEG<132>

SEG<131>

SEG<130>

SEG<129>

SEG<128>

SEG<127>

SEG<126>

SEG<125>

SEG<124>

SEG<123>

SEG<122>

SEG<121>

SEG<120>

SEG<119>

SEG<118>

SEG<117>

SEG<116>

SEG<115>

SEG<114>

SEG<113>

SEG<112>

SEG<111>

SEG<110>

SEG<109>

SEG<108>

SEG<107>

SEG<106>

SEG<105>

SEG<104>

SEG<103>

SEG<102>

SEG<101>

SEG<100>

SEG<99>

SEG<98>

SEG<97>

SEG<96>

SEG<95>

SEG<94>

SEG<93>

SEG<92>

SEG<91>

SEG<90>

SEG<89>

SEG<88>

SEG<87>

SEG<86>

SEG<85>

SEG<84>

SEG<83>

SEG<82>

SEG<81>

SEG<80>

SEG<79>

SEG<78>

SEG<77>

SEG<76>

SEG<75>

SEG<74>

SEG<73>

SEG<72>

SEG<71>

SEG<70>

SEG<69>

SEG<68>

SEG<67>

SEG<66>

SEG<65>

SEG<64>

SEG<63>

SEG<62>

SEG<61>

SEG<60>

SEG<59>

SEG<58>

SEG<57>

SEG<56>

SEG<55>

SEG<54>

SEG<53>

SEG<52>

SEG<51>

SEG<50>

SEG<49>

SEG<48>

SEG<47>

SEG<46>

SEG<45>

SEG<44>

SEG<43>

SEG<42>

SEG<41>

SEG<40>

SEG<39>

SEG<38>

SEG<37>

SEG<36>

SEG<35>

SEG<34>

SEG<33>

SEG<32>

SEG<31>

SEG<30>

SEG<29>

SEG<28>

SEG<27>

SEG<26>

SEG<25>

SEG<24>

SEG<23>

SEG<22>

SEG<21>

SEG<20>

SEG<19>

SEG<18>

SEG<17>

SEG<16>

SEG<15>

SEG<14>

SEG<13>

SEG<12>

SEG<11>

SEG<10>

SEG<9>

D15

VDDX

D14

D8

D7

D13

D12

D6

D11

D10

D5

D4

D9

D8

D3

D2

D7

D6

D1

D5

D4

D0

RST

WR0

WR1

CD

D3

D2

D1

D0

RST

WR0

VDDX

WR1

CD

CS0

BM0

BM1

TST4

ID0

ID1

CS0

VDDX

CS1

BM0

VDDX

BM1

TST4

TST1

TST2

ID0

VDDX

ID1

VSS

Dummy

VSS2

VDD

Dummy

VDD

VDD2

Dummy

VDD3

VBO+

VB0+

VB1+

VB1-

VB0-

VLCd

VB1+

VB1-

VB0-

VLCDIN

VLCDOUT

SEG<8>

SEG<7>

SEG<6>

SEG<5>

SEG<4>

COM<127>

COM<125>

COM<123>

COM<121>

COM<119>

COM<117>

COM<115>

COM<113>

COM<111>

COM<109>

COM<107>

COM<105>

SEG<3>

SEG<2>

SEG<1>

COM<1>

COM<3>

COM<5>

COM<7>

COM<9>

COM<11>

COM<13>

COM<15>

COM<17>

Note for V_DDand V_SSwith COG:

The operation condition V_DD=1.8V (typical) must be satisfied under all operating conditions. With its high

speed data-write condition, UC1697v’s peak current (I_DD) can be up to ~15mA range during high speed data

write to UC1697v’s on-chip SRAM. Such high pulsing current mandates very careful design of V_DD, V_SSITO

trances in COG glass modules. When V_DDand V_SStrace resistance is not low enough, the pulsing I_DD

current can cause the actual on-chip V_DDto drop below 1.65V and cause the IC to malfunction.

8

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

CONTROL REGISTERS

UC1697v contains registers which control the chip operation. The following table is a summary of these

control registers, a brief description and the default values. These registers can be modified by commands,

which will be described in the next two sections, starting with a summary table, followed by a detailed

instruction-by-instruction description.

Name:

The Symbolic reference of the register.

Note that, some symbol name refers to bits (flags) within another register.

Default: Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset.

Name

Bits

Default

Description

SL

7

0H

Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is

between 0 (no scrolling) and (127 – 2x(FLT+FLB)). Setting SL outside of

this range causes undefined effect on the displayed image.

FLT

FLB

4

0H

Fixed Lines. The top FLTx2 and bottom FLBx2 lines (relative to CEN) of

each frame are fixed and are not affected by scrolling (SL).

When FLT and/or FLB are non-zero, the screen is effectively separated into

three regions: one scrollable, surrounded by two non-scrollable regions.

When partial display mode is activated, the display of these 2xFLT and

2xFLB lines is also controlled by LC[0]. When LC[0]=1, the display will have

three sections: 2xFLT on one side non-scrollable, 2xFLB on the other side

also non-scrollable, and scrollable DST~DEN in the middle.

CA

RA

BR

7

3

0H

3H

Display Data RAM Column Address (counted in RGB triplet)

(Used in Host to Display Data RAM access)

Display Data RAM Row Address

(Used in Host to Display Data RAM access)

Bias Ratio. The ratio between V_LCDand V_BIAS

.

000b : 6

100b : 9

001b : 10

010b : 11

011b : 12

TC

2

0H

Temperature Compensation (per ^oC)

00b : -0.00%

10b : -0.15%

01b : -0.10%

11b : -0.05%

PM

8

6

5CH

00H

Electronic Potentiometer to fine tune V_BIASand V_LCD

PM offset.

PMO

PMO[5]=1: The effective PM value, PMV = PM - PMO[4:0]

PMO[5]=0: The effective PM value, PMV = PM + PMO[4:0]

PC

AC

4

EH

1H

Power Control.

PC[1:0] : 0xb: LCD: ꢁ 13nF

PC[3:2] : 00b: External V_LCD

1xb: 13 < LCD < 22nF

11b: Internal V_LCD(10x charge pump)

Address Control:

AC[0] : WA: Automatic column/row Wrap Around (1 : ON)

AC[1] : Auto-Increment order

0 : Column (CA) first

1 : Row (RA) first

AC[2] : RID: RA (row address) auto increment direction (0 : +1 1 : -1)

AC[3] : Window Program Mode

0 : Inside Mode: Write to SRAM within the window defined

by (WPC0, WPP0), (WPC1, WPP1)

1 : Outside Mode: Write to SRAM but skip the window defined

by (WPC0, WPP0), (WPC1, WPP1)

Revision A_0.6

9

ULTRACHIP

High-Voltage Mixed-Signal IC

Name

Bits

Default

Description

DC

5

18H

Display Control:

DC[0] : PXV: Pixels Inverse. Bit-wise data inversion. (Default 0: OFF)

DC[1] : APO: All Pixels ON (Default 0: OFF)

DC[2] : Display ON/OFF (Default 0: OFF)

When DC[2] is set to 0, the IC will enter Sleep mode.

DC[3] : Gray-shade Modulation mode.

0 : On/Off mode

1 : 32-shade Mode

DC[4] : Green Enhance Mode. Only valid in 4K-color mode.

0 : Enable. Allows an extra display bit for green color.

1 : Disable

LC

10

090H

LCD Control:

LC[0] : Enable the top FLTx2 and bottom FLBx2 lines in partial display

mode (Default OFF).

LC[1] : MX, Mirror X. SEG/Column sequence inversion (Default: OFF)

LC[2] : MY, Mirror Y. COM/Row sequence inversion (Default: OFF)

LC[4:3] : Line Rate (Klps: Kilo-Line-per-second)

00b : 20.1 Klps

10b : 29.6 Klps

01b : 24.4 Klps

11b : 35.8 Klps

Line Rate (for 8-color On/Off mode)

00b : 5.5 Klps

10b : 8.0 Klps

01b : 6.6 Klps

11b : 9.7 Klps

(Line-Rate = Frame-Rate x Mux-Rate)

LC[5] : RGB filter order (as mapped to SEG1, SEG2, SEG3)

0 : BGR-BGR

LC[7:6] : Color and input mode

when DC[4]=1:

1 : RGB-RGB

00b : 256 color mode

01b : 4K color mode

10b : 64K color mode

3R-3G-2B ( 8-bit/RGB)

4R-4G-4B (12-bit/RGB)

5R-6G-5B (16-bit/RGB)

when DC[4]=0:

00b : 256 color mode

01b : 4K color mode

10b : 64K color mode

3R-3G-2B ( 8-bit/RGB)

4R-5G-3B (12-bit/RGB)

5R-6G-5B (16-bit/RGB)

LC[9:8] : Partial Display Control

0xb: Disable Mux-Rate = CEN+1 (DST, DEN not used)

10b: Enabled Mux-Rate = CEN+1

11b: Enabled Mux-Rate = DEN-DST+1+LC[0] x (FLT+FLB) x 2

NIV

7

3

51H

0H

N-Line Inversion:

NIV[5:0] :

00000b: Disable

00001b ~ 111111b: 1~ 63 lines ( Default: 17lines )

NIV[6] : 0b: no-XOR 1b: XOR

COM Scan Function

CSF

CSF[0] : 0b : LRM sequence: AEBCD-AEBCD

1b : LRM sequence: AEBCD-EBCDA

CSF[1] : 0b :FRC Disable

1b : FRC Enable

CSF[2] : Shade-1 / Shade-30 option

0 : Dither directly on input data (SRAM Change)

1 : PWM on SEG output stage

10

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

Name

Bits

Default

Description

CEN

DST

DEN

7

7FH

00H

7FH

COM scanning end (last COM with full line cycle, 0 based index)

Display start (first COM with active scan pulse, 0 based index)

Display end (last COM with active scan pulse, 0 based index)

Please maintain the following relationship:

CEN = the actual number of pixel rows on the LCD - 1

CEN ꢀ DEN ꢀ DST+ 9

WPC0

WPP0

WPC1

WPP1

MTPC

7

5

00H

7FH

10H

Window program starting column address. Value range: 0 ~127.

Window program starting row address. Value range: 0~127.

Window program ending column address. Value range: 0~127.

Window program ending row address. Value range: 0~127.

MTP Programming Control:

MTPC[2:0] : MTP command

000 : Idle

001 : Read

010 : Erase

011 : Program

1xx : For UltraChip’s debug use only

MTPC[3] : MTP Enable (automatically cleared after each MTP command)

MTPC[4] : Ignore/Use MTP. 0: Ignore

1: Use

MTP

MTPM

APC

6

2

--

Multiple-Time Programming. For V_LCDfine tune.

MTP Write Mask. Bit =1: program, Bit=0: no action.

00H

N/A

Advanced Program Control. For UltraChip only. Please do not use.

Status Registers

OM

2

–

Operating Modes (Read only)

00b: Reset

10b: Sleep

01b: (Not used)

11b: Normal

MD

MS

WS

ID

1

2

–

MTP option flag: 1 for MTP version, 0 for non-MTP version.

MTP programming in-progress

–

MTP Operation Succeeded

Access the connected status of ID pins.

Revision A_0.6

11

ULTRACHIP

High-Voltage Mixed-Signal IC

COMMAND TABLE

The following is a list of host commands supported by UC1697v

C/D: 0: Control,

1: Data

W/R: 0: Write Cycle,

#: Useful Data bits

1: Read Cycle

–: Don’t Care

Command

Write Data Byte

Read Data Byte

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Action

Write 1 byte

Read 1 byte

Default

N/A

1

2

1

0

1

#

GE MX MY WA DE WS MD MS

Get {Status, Ver,

N/A

3

Get Status & PM

0

1

PMO, Product Code, Product Code

Ver

PMO[6:0]

PID[2:0]

PID, MID}

(5h)

Product Code

0

#

R

#

0

#

0

#

0

1

#

0

#

0

#

1

0

#

R

#

1

#

0

#

0

#

0

1

Set Column Address LSB

Set Column Address MSB

Set Temp. Compensation

Set Panel Loading

Set Pump Control

Set Adv. Program Control

(double-byte command)

0

#

0

1

#

1

#

1

-

1

#

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

0

#

1

0

#

0

#

0

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

0

-

0

1

#

0

1

0

#

0

#

1

0

#

0

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

-

0

1

0

1

#

0

1

0

1

0

#

0

1

#

0

#

1

0

#

0

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

0

1

0

#

0

#

0

#

0

1

0

#

0

1

0

1

#

0

1

0

#

1

0

#

0

#

0

#

0

#

0

#

0

#

0

#

1

#

1

#

1

0

1

0

#

0

#

1

#

0

#

0

1

#

0

#

0

1

#

0

1

#

0

#

0

#

0

#

1

#

1

#

1

#

1

#

0

#

0

#

Set CA[3:0]

Set CA[6:4]

Set TC[1:0]

Set PC[1:0]

Set PC[3:2]

Set APC[R][7:0],

R = 0, 1, or 2

Set SL[3:0]

Set SL[6:4]

Set RA[3:0]

Set RA[6:4]

0

00b

1xb

11b

4

5

6

7

8

9

N/A

Set Scroll Line LSB

0

Set Scroll Line MSB

Set Row Address LSB

Set Row Address MSB

Set V_BIASPotentiometer

(double-byte command)

10

11

Set PM[7:0]

5CH

12 Set Partial Display Control

13 Set RAM Address Control

Set LC[9:8]

Set AC[2:0]

0xH

001b

14 Set Fixed Lines

Set {FLT, FLB}

0

15 Set Line Rate

16 Set All-Pixel-ON

17 Set Inverse Display

18 Set Display Enable

19 Set LCD Mapping Control

Set LC[4:3]

Set DC[1]

Set DC[0]

Set DC[4:2]

Set LC[2:0]

10b

0b

110b

000b

20 Set N-Line Inversion

0

Set NIV[6:0]

51H

21 Set Color Pattern

22 Set Color Mode

23 Set COM Scan Function

24 System Reset

25 NOP

Set Test Control

(double-byte command)

27 Set LCD Bias Ratio

0

Set LC[5]

Set LC[7:6]

0 (BGR)

10b

000b

N/A

Set CSF[2:0]

System Reset

No operation

For testing only.

Do not use.

N/A

TT

26

N/A

011b: 12

127

#

0

#

1

#

1

#

0

#

0

#

1

#

1

#

0

#

0

#

1

#

0

#

1

#

0

#

1

#

0

#

1

#

0

#

1

#

Set BR[2:0]

28 Set COM End

Set CEN[6:0]

29 Set Partial Display Start

30 Set Partial Display End

Set DST[6:0]

Set DEN[6:0]

0

127

0

Set Window Program

31

Set

Starting Column Address

WPC0

Set

WPP0

Shared

with

MTP

Set Window Program

Starting Row Address

Set Window Program

Ending Column Address

Set Window Program

Ending Row Address

32

0

Set

33

127

Commands

WPC1

Set

WPP1

Set AC[3]

34

127

0: Inside

10H

35 Window Program Mode

Set

MTP

Operation

36

Set MTPC[4:0]

Set MTPM[5:0]

control

0

-

1

#

37 Set MTP Write Mask

0

12

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

Command

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Action

Default

0

1

#

1

#

1

#

1

#

0

#

1

#

0

#

0

#

Set

MTP1

38 Set V_MTP1Potentiometer

N/A

Shared with

Window

Program

0

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

1

#

0

#

0

#

0

#

1

#

1

#

1

#

0

#

1

#

1

#

1

#

0

#

1

#

Set

MTP2

Set

MTP3

Set

MTP4

39 Set V_MTP2Potentiometer

40 Set MTP Write Timer

41 Set MTP Read Timer

N/A

commands

NOTE:

•

All bit patterns other than commands listed above, may result in undefined behavior.

The interpretation of commands (37)~(41) depends on the setting of register MTPC[3].

o

Commands (38)~(41) are shared with commands (31)~(34). These two sets of commands share

exactly the same code and control registers. When MTPC[3]=0, they are interpreted as Window

Program commands and registers. When MTPC[3]=1, they function as MTP Control commands

and registers.

•

After MTP ERASE or PROGRAM operation, before resuming normal operation, please always

a) Remove TST4 power source,

b) Do a full V_DDON-OFF-ON cycle.

Under 16-bit bus mode and CD=0, D[15:8] is ignored and only D[7:0] is used. As a result, the bus cycles

for commands under 16-bit bus and 8-bit bus are the same, and double-byte commands still need two

bus cycles under 16-bit bus mode.

Example:

8-bit bus mode:

Set PL[1:0] = 2’b11 :

D[7:0] = 0010 1011

Set PM[7:0] = 8’h8b : 1^stD[7:0] = 1000 0001

2^ndD[7:0] = 1000 1011

16-bit bus mode:

Set PL[1:0] = 2’b11:

D[15:0] = 0000 0000 0010 1011

Set PM[7:0] = 8’h8b: 1^stD[15:0] = 0000 0000 1000 0001

2^ndD[15:0] = 0000 0000 1000 1011

Revision A_0.6

13

ULTRACHIP

High-Voltage Mixed-Signal IC

COMMAND DESCRIPTION

(1) WRITE DATA TO DISPLAY MEMORY

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

8-bit data write to SRAM

Write data

1

0

UC1697v will convert input RAM data to 16-bit of RGB data. Please refer to command Set Color Mode

for detail of data-write sequence.

(2) READ DATA FROM DISPLAY MEMORY

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

8-bit data from SRAM

Read data

1

Each RGB triplet is stored as 16-bit in the display RAM. Each 16-bit of RGB data takes 1 / 2 RAM read

cycles for 16 / 8 – bit bus mode, respectively. The read out RGB data is after-extension for 64K color mode.

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

B1

B0

1^st8-bit Read

2^nd8-bit Read

Write/Read Data Byte (command (1) / (2)) operation uses internal Row Address register (RA) and Column

Address register (CA). RA and CA can be programmed by issuing commands Set Row Addressand Set

Column Address. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the CA

boundary, and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when

CA reaches end of column address, CA will be reset to 0 and RA will be increased or decreased, depending

on the setting of Row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0

or 127), RA will be wrapped around to the other end of RAM and continue.

(3) GET STATUS & PM

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

GE MX MY WA DE WS MD MS

Get Status & PM

Ver

PMO[5:0]

PID[2:0]

Product Code

0

Status1 definitions:

GE: Green Enhancing enable flag. Green Enhance Mode is disabled when GE = 1.

MX: Status of register LC[1], mirror X.

MY: Status of register LC[2], mirror Y.

WA: Status of register AC[0]. Automatic column/row wrap around.

DE: Display enable flag. DE=1 when display is enabled

WS: MTP Operation succeeded

MD: MTP Option (1 for MTP version, 0 for non-MTP version)

MS: MTP action status

Status2 definitions:

Ver:

Version Code. 00 ~ 11.

PMO[5:0]: PM offset value.

Status3 definitions:

Product Code: 1110b (Eh)

PID[1:0]: Provide access to ID pins connection status.

If multiple Get Statuscommands are issued consecutively within one single CD 1Ö0Ö1 transaction, the

Get Statuscommand will return {Status1, Status2, Status3, Status1, Status2, Status3, Status1..}

alternately.

14

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(4) SET COLUMN ADDRESS

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Column Address LSB CA[3:0]

Set Column Address MSB CA[6:4]

0

1

CA3 CA2 CA1 CA0

CA6 CA5 CA4

0

Set SRAM column address for read/write access. CA is counted in RGB triplets, not individual SEG

electrode.

CA value range: 0~127

(5) SET TEMPERATURE COMPENSATION

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Temperature Comp. TC[1:0]

0

1

0

1

TC1 TC0

Set VBIAS temperature compensation coefficient (%-per-degree-C)

Temperature compensation curve definition:

00b = -0.00%/^oC

01b = -0.10%/^oC

10b = -0.15%/^oC

11b = -0.05%/^oC

(6) SET PANEL LOADING

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

PC1 PC0

Set Panel Loading PC[1:0]

0

1

0

1

0

Set PC[1:0] according to the capacitance loading of LCD panel.

Panel loading definition:

0xb: LCD: ꢁ 13nF

1xb: LCD: 13~22nF

(7) SET PUMP CONTROL

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

PC3 PC2

Set Pump Control PC[3:2]

0

1

0

1

Set PC[3:2] to program the build-in charge pump stages. Always make sure the IC is in a RESET state

before changing PC[3:2] value. Avoid changing PC[3:2] setting when the display is enabled.

Pump control definition:

00b = External V_LCD

11b = Internal V_LCD(x10)

(8) SET ADVANCED PROGRAM CONTROL

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set APC[R][7:0]

0

1

0

R

(Double-byte command)

APC register parameter

For UltraChip only. Please do NOT use.

Revision A_0.6

15

ULTRACHIP

High-Voltage Mixed-Signal IC

(9) SET SCROLL LINE

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Scroll Line LSB SL[3:0]

0

1

0

1

SL3 SL2 SL1 SL0

SL6 SL5 SL4

Set Scroll Line MSB SL[6:4]

0

Set the number of lines for scroll area.

Scroll line setting will scroll the displayed image up by SL rows. The valid value for SL is between

0 (no scrolling) and 127-2x(FLT+FLB) (full scrolling). FLT and FLB are the register values programmed by

the Set Fixed Linescommand.

row 0

Fixed Area

(2xFLT rows)

Fixed Area

(2xFLT rows)

:

row 2xFLT-1

Image row 0

row 2xFLT

Image row N

row 2xFLT

:

Scroll Area

:

Scroll Area

:

Image row N-1

Image row N

Image row 127-2xFL

Image row 0

:

Image row 127-2xFL

row 127

Image row N-1

row 127

SL=0

SL=N

(10) SET ROW ADDRESS

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Row Address LSB RA [3:0]

Set Row Address MSB RA [6:4]

0

1

0

1

RA3 RA2 RA1 RA0

RA6 RA5 RA4

0

Set SRAM row address for read/write access.

Possible value = 0~127

(11) SET VBIAS POTENTIOMETER

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set V_BIASPotentiometer. PM [7:0]

(Double-byte command)

0

1

0

1

PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

Program V_BIASPotentiometer (PM[7:0]). See section LCD Voltage Setting for more detail.

Effective range: 0 ~ 255

16

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(12) SET PARTIAL DISPLAY CONTROL

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

LC9 LC8

Set Partial Display Enable LC [9:8]

0

1

0

1

This command is used to enable partial display function.

LC[9:8] : 0xb: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used.)

10b: Enable Partial Display, Mux-Rate = CEN+1

11b: Enable Partial Display, Mux-Rate = DEN-DST+1+ LC[0]x(FLT+FLB)x2

(13) SET RAM ADDRESS CONTROL

Action

Set AC [2:0]

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

AC2 AC1 AC0

0

1

0

1

Program registers AC[2:0] for RAM address control.

AC[0]: WA, Automatic column/row wrap around.

0: CA or RA (depends on AC[1]= 0 or 1) will stop incrementing after reaching boundary

1: CA or RA (depends on AC[1]= 0 or 1) will restart, and RA or CA will increment by one step.

AC[1]: Auto-Increment order

0 : column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+/-1).

1 : row (RA) increment (+/-1) first until RA reach RA boundary, then CA will increment by (+1).

AC[2]: RID, row address (RA) auto increment direction ( 0/1 = +/- 1 )

When WA=1 and CA reaches CA boundary, RID controls whether row address will be adjusted by

+1 or -1.

AC[2:0] controls the auto-increment behavior of CA and RA. For Window Program enabling (AC[3]=ON), see

section Command Description (34) ~ (37) for more details. If WPC[1:0] and WPP[1:0] values are the default

values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[3] is.

Revision A_0.6

17

ULTRACHIP

High-Voltage Mixed-Signal IC

(14) SET FIXED LINES

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Fixed Lines {FLT, FLB}

(Double-byte command)

0

1

0

1

0

FLT[3:0]

FLB[3:0]

The fixed line function is used to implement the partial scroll function by dividing the screen into scroll and

fixed area. The Set Fixed Linescommand will define the fixed area, which will not be affected by the SL

scroll function. The fixed area covers the top 2xFLT and bottom 2xFLB rows for mirror Y (MY) is 0, or covers

the top 2xFLB and bottom 2xFLT rows for MY=1. One example of the visual effect on LCD is illustrated in

the figure below.

Fixed Area

(2xFLT)

1

Fixed Area

(2xFLB)

1

Scroll Area

Fixed Area

(2xFLB)

Fixed Area

128

(2xFLT) 128

MY = 0

MY = 1

When partial display mode is activated, the display of these 2x(FLT+FLB) lines is also controlled by LC[0].

Before turning on LC[0], please make sure

MY=0 DST ꢀ FLTx2

DEN ꢁ (CEN-FLBx2).

MY=1 DST ꢀ FLBx2

DEN ꢁ (CEN-FLTx2)

(15) SET LINE RATE

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

LC4 LC3

Set Line Rate LC [4:3]

0

1

0

1

0

Program LC [4:3] for line rate setting (Frame-Rate = Line-Rate / Mux-Rate). The line rate is automatically

scaled down by 2/3, 1/2, 1/3 and 1/4 at Mux-Rate = 87, 65, 44 and 33.

The following are line rates at Mux Rate = 88 ~ 128.

00b: 20.1 Klps

In On/Off Mode

00b: 5.5 Klps

01b: 24.4 Klps

10b: 29.6 Klps

10b: 8.0 Klps

11b: 35.8 Klps

11b: 9.7 Klps

01b: 6.6 Klps

(Klps: Kilo-Line-per-second)

(16) SET ALL PIXEL ON

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

DC1

Set All Pixel ON DC [1]

0

1

0

1

0

1

0

Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data

stored in display RAM.

(17) SET INVERSE DISPLAY

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

DC0

Set Inverse Display DC [0]

0

1

0

1

0

1

Set DC[0] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM. This

function has no effect on the existing data stored in display RAM.

18

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(18) SET DISPLAY ENABLE

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

DC4 DC3 DC2

Set Display Enable DC [4:2]

0

1

0

1

0

1

This command is for programming register DC[4:2].

When DC[2] is set to 0, the IC will put itself into Sleep mode. All drivers, voltage generation circuit and timing

circuit will be halted to conserve power. When DC[2] is set to 1, UC1697v will first exit from Sleep mode,

restore the power and then turn on COM drivers and SEG drivers. There is no other explicit user action or

timing sequence required to enter or exit the Sleep mode.

DC[3] controls the gray shade modulation modes. UC1697v has two gray shade modulation modes: an

On/Off mode and a 32-shade mode. The modulation curves are shown below. Horizontal axes are the gray

shade data. The vertical axes are the ON-OFF ratio.

50

45

40

35

30

25

20

15

10

5

0

4

8

12

16 20

24

28

DC[4] Green Enhance Mode. Refer to command Set Color Modefor more information.

0b: Green Enhancing Mode enabled 1b: Green Enhancing Mode disabled

NOTE:

1. For red and blue colors, shades mapped to data 1 and 30 (shown as red points above) are achieved by

special dithering. This will be solved when the PWM function is enabled.

2. Green shades are created by combining FRC and special dithering. Six of the shades (1, 2, 3, 59, 60,

and 61) are created by special dithering. This will be solved when the PWM function is enabled. Data 62

and 63 are mapped to the same shade.

3. When the internal DC-DC converter starts to operate and pump out current to V_LCD, there will be an in-

rush pulse current between V_DD2and V_SS2initially. To avoid this current pulse from causing potential

harmful noise, do NOT issue any command or write any data to UC1697v for 5~10mS after setting DC[2]

to 1.

Revision A_0.6

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High-Voltage Mixed-Signal IC

(19) SET LCD MAPPING CONTROL

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

MY MX LC0

Set LCD Mapping Control LC [2:0]

0

1

0

This command is used for programming LC[2:0] to control COM (row) mirror (MY), SEG (column) mirror

(MX).

LC[2] controls Mirror Y (MY): MY is implemented by reversing the mapping order between RAM and COM

electrodes. The data stored in RAM is not affected by the MY action. MY will have immediate effect on

the display image.

LC[1] controls Mirror X (MX): MX is implemented by selecting the CA or 127-CA as write/read (from host

interface) display RAM column address so this function will only take effect after rewriting the RAM

data.

LC[0] controls whether soft icon sections (2xFLT, 2xFLB) are displayed during partial display mode.

(20) SET N-LINE INVERSION

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set N-line Inversion, NIV[4:0]

(Double-byte command)

0

1

0

1

0

NIV6 NIV5 NIV4 NIV3 NIV2 NIV1 NIV0

-

N-Line Inversion:

NIV[5:0]: 000000b: Disable

000001b ~ 111111b: 1~63 lines ( Default : 17 lines )

NIV[6]: 0b: non-XOR 1b: XOR

13

2

13

11

NIV[6]=0

13

NIV[6]=1

2

Frame 1

Frame 2

(21) SET COLOR PATTERN

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

LC5

Set Color Pattern LC [5]

0

1

0

1

0

UC1697v supports on-chip swapping of RÙB data mapping to the SEG drivers.

SEG388 SEG389 SEG390

LC[5]

0

1

SEG1 SEG2 SEG3 SEG4 SEG5 SEG6

…

B

R

G

R

B

R

G

R

B

R

G

R

B

The definition of R/G/B input data is determined by LC[7:6], as described in Set Color Modebelow.

20

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(22) SET COLOR MODE

Action

Set Color Mode LC [7:6]

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

LC7 LC6

0

1

0

1

0

1

Program color mode and RGB input pattern. Color mode (LC[7:6]) definition:

Note: For serial bus modes, please refer to 8-bit tables below.

Green Enhance Mode disabled (DC[4] = 1):

LC[7:6] = 00b ( RRR-GGG-BB, 256-color )

8 bits of input RGB data are stored to 16 RAM bits. No dither is performed.

Data Write Sequence (8-bit)

1^stWrite Data Cycle

D[7:0]

R2 R1 R0 G2 G1 G0 B1 B0

Data Write Sequence (16-bit)

1^stWrite Data Cycle

D[15:0]

0

R2 R1 R0 G2 G1 G0 B1 B0

LC[7:6] = 01b ( RRRR-GGGG-BBBB, 4K-color )

12 bits of input RGB data are stored to 16 RAM bits. No dither is performed. Every 3 bytes of input data

will be merged into 2 sets of RGB data.

Data Write Sequence (8-bit)

1^stWrite Data Cycle

2^ndWrite Data Cycle

3^rdWrite Data Cycle

D[7:0]

R3 R2 R1 R0 G3 G2 G1 G0

B3 B2 B1 B0 R3 R2 R1 R0

G3 G2 G1 G0 B3 B2 B1 B0

Data Write Sequence (16-bit)

1^stWrite Data Cycle

2^ndWrite Data Cycle

D[15:0]

0

R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0

LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 64K-color )

16 bits of input data are stored to 16 RAM bits directly.

Data Write Sequence (8-bit)

1^stWrite Data Cycle

2^ndWrite Data Cycle

D[7:0]

R4 R3 R2 R1 R0 G5 G4 G3

G2 G1 G0 B4 B3 B2 B1 B0

Data Write Sequence (16-bit)

1^stWrite Data Cycle

D[15:0]

R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0

Revision A_0.6

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High-Voltage Mixed-Signal IC

Green Enhance Mode enabled (DC[4]=0):

LC[7:6] = 00b ( RRR-GGG-BB, 256-color )

8 bits of input RGB data are stored to 16 RAM bits. No dither is performed.

Data Write Sequence (8-bit)

1^stWrite Data Cycle

D[7:0]

R2 R1 R0 G2 G1 G0 B1 B0

Data Write Sequence (16-bit)

1^stWrite Data Cycle

D[15:0]

0

R2 R1 R0 G2 G1 G0 B1 B0

LC[7:6] = 01b ( RRRR-GGGGG-BBB, 4K-color )

12 bits of input data are extended and stored to 16 RAM bits. Every 3 bytes of input data will be merged

into 2 sets of RGB data.

Data Write Sequence (8-bit)

1^stWrite Data Cycle

2^ndWrite Data Cycle

3^rdWrite Data Cycle

D[7:0]

R3 R2 R1 R0 G4 G3 G2 G1

G0 B2 B1 B0 R3 R2 R1 R0

G4 G3 G2 G1 G0 B2 B1 B0

Data Write Sequence (16-bit)

1^stWrite Data Cycle

2^ndWrite Data Cycle

D[15:0]

0

R3 R2 R1 R0 G4 G3 G2 G1 G0 B2 B1 B0

LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB, 64K-color )

The behaviors of 8-bit input mode and 16-bit input mode do not change with DC[4] setting. Refer to

previous section for more information on these two input modes.

(23) SET COM SCAN FUNCTION

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

CSF2 CSF1 CSF0

Set COM Scan Function CSF[2:0]

0

1

0

1

COM scan function

CSF[0]: LRM sequence option

0b: LRM sequence: AEBCD-AEBCD

1b : LRM sequence: AEBC-EBCDA

CSF[1]: FRC option

0b: FRC Disable

1b: FRC Enable

CSF[2]: Shade-1, Shade-30 option

0 : Dither directly on input data(SRAM Change)

1 : PWM on SEG output stage

(24) SYSTEM RESET

Action

System Reset

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

This command will activate the system reset. Control register values will be reset to their default values.

Data stored in RAM will not be affected.

(25) NOP

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

No Operation

0

1

0

1

This command is used for “no operation”.

22

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(26) SET TEST CONTROL

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set TT

0

1

0

1

TT

(Double-byte command)

Testing parameter

This command is used for UltraChip production testing. Do NOT use.

(27) SET LCD BIAS RATIO

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

BR2 BR1 BR0

Set Bias Ratio BR [2:0]

0

1

0

1

Bias ratio definition:

000b = 6

100b = 9

001b = 10

010b = 11

011b = 12

(28) SET COM END

Action

Set CEN [6:0]

(Double-byte command)

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

-

CEN register parameter

This command programs the ending COM electrode. CEN defines the number of used COM electrodes, and

it should correspond to the number of pixel-rows in the LCD. When the LCD has less than 128 pixel rows,

the LCM designer should set CEN to N-1 (where N is the number of pixel rows) and use COM1 through

COM-N as COM driver electrodes.

(29) SET PARTIAL DISPLAY START

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set DST [6:0]

0

1

0

1

0

(Double-byte command)

-

DST register parameter

This command programs the starting COM electrode, which has been assigned a full scanning period and

will output an active COM scanning pulse.

Revision A_0.6

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High-Voltage Mixed-Signal IC

(30) SET PARTIAL DISPLAY END

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set DEN [6:0]

0

1

0

1

(Double-byte command)

-

DEN register parameter

This command programs the ending COM electrode, which has been assigned a full scanning period and

will output an active COM scanning pulse.

CEN, DST, and DEN are 0-based indexes of COM electrodes. They control only the COM electrode activity,

and do not affect the mapping of display RAM to each COM electrodes. The image displayed by each pixel

row is therefore not affected by the setting of these three registers.

When LC[9]=1, two partial display modes are possible with UC1697v:

LC[8]=1: ON-OFF only, ultra-low-power mode (if Mux-Rate ꢁ 33, set BR=6).

LC[8]=0: Full gray shade low power mode (BR and PM stays the same)

When LC[9:8]=10b, the Mux-Rate is still CEN+1. This is achieved by suppressing only the scanning pulses,

but not the scanning time slots, for COM electrodes that is outside of DST~DEN. Under this mode, the gray-

scale quality of the display is preserved, while the power can be reduced significantly.

When LC[9:8]=11b, the Mux-Rate is narrowed down DEN-DST +1 + 2x(FLT+FLB)xLC[0]. When MUX rate is

reduced, reduce the line rate accordingly to reduce power. Changing MUX rate also require BR and V_LCDto

be readjusted. When Mux-Rate is under 33, it is recommend to set BR=6.

For minimum power consumption, set LC[9:8]=11b, set (DST, DEN, FL, CEN) to minimize MUX rate, use

slowest line rate which satisfies the flicker requirement, use On-Off mode, set PC[1:0]=00b, and use lowest

BR, lowest V_LCDwhich satisfies the contrast requirement.

In either case, DST/DEN defines a small subsection of the display which will remain active while shutting

down all the rest of the display to conserve energy.

Scan Method

when LC[9:8]=10b

when LC[9:8]=11b:

Display Result:

0

..

Not scanned

Pulse Disable

DST

DEN

CEN

..

Display segment

Pulse Enable

Not scanned

Pulse Enable

Pulse Disable

Not Scanned

127

24

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(31) SET WINDOW PROGRAM STARTING COLUMN ADDRESS

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

Set WPC0 [6:0]

(Double-byte command)

-

WPC0 register parameter

This command is to program the starting column address of RAM program window.

(32) SET WINDOW PROGRAM STARTING ROW ADDRESS

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

Set WPP0 [6:0]

(Double-byte command)

-

WPP0 register parameter

This command is to program the starting row address of RAM program window.

(33) SET WINDOW PROGRAM ENDING COLUMN ADDRESS

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

Set WPC1 [6:0]

(Double-byte command)

-

WPC1 register parameter

This command is to program the ending column address of RAM program window.

(34) SET WINDOW PROGRAM ENDING ROW ADDRESS

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

Set WPP1 [6:0]

(Double-byte command)

-

WPP1 register parameter

This command is to program the ending row address of RAM program window.

Revision A_0.6

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High-Voltage Mixed-Signal IC

(35) SET WINDOW PROGRAM MODE

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

AC3

Set Window Program Enable AC[3]

0

1

0

This command controls the Window Program function.

AC[3]=0: Inside Mode

When Window Programming is under “Inside” mode , the CA and RA increment and wrap-around will

be performed automatically around the boundaries as defined by registers WPC0, WPC1, WPP0, and

WPP1, so that the CA/RA address will stay within the defined window of SRAM address, and therefore

allow effective data update within the window.

AC[3]=1: Outside Mode

When Window Programming is under “Outside” mode, the CA and RA increment and wrap-around

boundary will cover the entire UC1697v SRAM map (CA: 0~127, RA:0~127). However, when CA/RA

points to a memory location within the window defined by registers WPC0, WPC1, WPP0, and WPP1,

the SRAM data update operation will be suspended, the existing data will be retained and the input data

will be ignored.

The direction of Window Program will depend on the WA (AC[0]), RID (AC[2]), auto-increment order (AC[1])

and MX (LC[1]) register setting.

y

WA decides whether the program RAM address advances to next row/column after reaching the

specified window column / row boundary.

RID controls the RAM address incrementing from WPP0 toward WPP1 (RID=0) or reverse the direction

(RID=1).

y

Auto-increment order directs the RAM address increment vertically (AC[1]=1) or horizontally (AC[1]=0).

MX results the RAM column address incrementing from 127-WPC0 to 127-WPC1 (MX=1) or WPC0 to

WPC1 (MX=0).

By different combination of RID, AC[1], MX, and by setting CA, RA at proper corners of the “window”, effects

such as mirrors and rotations can be easily achieved.

Setting or resetting AC[3] does not affect the values of CA and RA. So, always remember to reposition CA

and RA properly after changing the setting of AC[3].

26

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

Function Setting

AIO MX RID

Image in the Host (MPU)

Image in Display Data Ram

Display Data

Direction

(Start : ●)

(Physical origin: upper left corner)

AC[1] LC[1] AC[2]

Normal

0

1

Y-mirror

X-mirror

0

1

0

X-mirror

Y-mirror

0

1

0

1

0

1

X-Y Exchange

Y-mirror

X-Y Exchange

X-mirror

1

0

1

X-Y Exchange

X-mirror

Y-mirror

Revision A_0.6

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High-Voltage Mixed-Signal IC

(36) SET MTP OPERATION CONTROL

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

Set MTPC [4:0]

(Double-byte command)

MTPC register

0

-

parameter

This command is for MTP operation control:

MTPC[2:0] : MTP command

000 : Sleep

010 : MTP Erase

001 : MTP Read

011 : MTP Program

1xx : For UltraChip use only.

MTPC[3] : MTP Enable ( automatically cleared each time after MTP command is done )

MTPC[4] : MTP value valid (ignore MTP value when L )

DC[2] and MTPC[3] are mutually exclusive. Only one of these two control flags can be set to ON at any time.

In other words, when DC[2] is ON, all MTP operations will be blocked, and, when MTP operation is active,

set DC[2] to 1 will be blocked.

28

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

The following commands, (37) ~ (41), are used as MTP commands only when MTPC[3]=1.

(37) SET MTP WRITE MASK

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

Set MTPM [6:0]

(Triple-byte command)

-

MTPM register parameter

This command enables Write to each of the 7 individual MTP bits.

When MTPM[x]=1, the x-th bit of the MTP memory will be programmed to “1”. MTPM[x]=0 means no Write

action for x-th bit. And the content of this bit will not change.

The amount of “programming current” increases with the number of 1’s in MTPM. If the “programming

current” appears to be too high for the LCM design (e.g. TST4 ITO trace is not wide enough to supply the

current), use multiple write cycles and distribute the 1’s evenly into these cycles.

MTPM[6:0] : Set PMO value

MTPM1[1:0]: Set MID value

This command is only valid when MTPC[3]=1.

(38) SET V_MTP1POTENTIOMETER

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

Set MTP1

(Double-byte command)

Shared register parameter

This command is for fine tuning V_OPT1setting (use with BR=000) and is only valid when MTPC[3]=1.

(39) SET V_MTP2POTENTIOMETER

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

Set MTP2

(Double-byte command)

Shared register parameter

This command is for fine tuning V_MTP2PM setting (use with BR=001) and is only valid when MTPC[3]=1.

(40) SET MTP WRITE TIMER

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

Set MTP3

(Double-byte command)

Shared register parameter

This command is only valid when MTPC[3]=1.

(41) SET MTP READ TIMER

Action

C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

Set MTP4

(Double-byte command)

Shared register parameter

This command is only valid when MTPC[3]=1.

Revision A_0.6

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High-Voltage Mixed-Signal IC

LCD VOLTAGE SETTING

MULTIPLEX RATES

V_LCDGENERATION

V_LCDmay be supplied either by internal charge

pump or by external power supply. The source of

V_LCDis controlled by PC[3:2].

Multiplex Rate is completely software

programmable in UC1697v via registers CEN,

DST, DEN, FLT, FLB, and partial display control

flags LC[9:8] and LC[0].

When V_LCDis generated internally, the voltage

level of V_LCDis determined by three control

registers: BR (Bias Ratio), PM (Potentiometer),

and TC (Temperature Compensation), with the

following relationship:

Combined with low power partial display mode

and a low bias ratio of 6, UC1697v can support

wide variety of display control options. For

example, when a system goes into stand-by

mode, a large portion of LCD screen can be

turned off to conserve power.

V_LCD= (C_{V 0}+ C_PM× PM ) × (1+ (T − 25) × C_T%)

BIAS RATIO SELECTION

where

Bias Ratio (BR) is defined as the ratio between

C_V0and C_PMare two constants, whose value

depends on the setting of BR register, as

illustrated in the table on the next page,

V

_LCDand V_BIAS, i.e.

BR = V_LCD/V_BIAS

where V_BIAS= V_B1+– V_B1–= V_B0+– V_B0–

The theoretical optimum Bias Ratio can be

estimated by . BR of value 15~20%

,

.

PM is the numerical value of PM register,

T is the ambient temperature in ^OC, and

Mux +1

C_Tis the temperature compensation coefficient

lower/higher than the optimum value calculated

above will not cause significant visible change in

image quality.

as selected by TC register.

V_LCDAND CONTRAST FINE TUNING

Due to the nature of STN operation, an LCD

designed for good gray-shade performance at

high Mux Rate (e.g. MR=128), can generally

perform very well as a black and white display, at

lower Mux Rate. However, it is also true that such

technique generally can not maintain LCD’s

quality of gray shade performance, since the

contrast of the LCD will increase as Mux Rate

decreases, and the shades near the two ends of

the spectrum will start to lose visibility.

Color STN LCD is sensitive to even a 0.5%

mismatch between IC driving voltage and the V_OP

of LCD. It is very difficult for LCD makers to

guarantee such high precision matching of parts

from different venders. It is therefore necessary

to adjust V_LCDto precisely match the actual V_OP

of each LCD.

For the best results, software or MTP based V_LCD

adjustment is the recommended method for V_LCD

fine tuning. System designers should always

consider the contrast fine tuning requirement

before finalizing on the LCM design.

UC1697v supports five BR as listed below. BR

can be selected by software program.

BR

0

1

2

3

4

LOAD DRIVING STRENGTH FOR COG

Bias Ratio

6

10

11

12

9

The power supply circuit of UC1697v is designed

to handle LCD panels with loading up to ~16nF

using 7-Ω/Sq ITO glass with V_DD2/3ꢀ 2.8V. For

larger LCD panels, use lower resistance ITO

glass.

Table 1: Bias Ratios

TEMPERATURE COMPENSATION

Four different temperature compensation

coefficients can be selected via software. The

four coefficients are given below:

Due to crosstalk consideration, ~16nF is also the

recommended maximum LCD panel loading for

COG applications. Using 4.5-Ω/Sq low resistance

ITO glass for the IC bonding substrate can help

improve image quality and operation tolerance.

TC

% per ^oC

0

1

2

3

-0.00 -0.10 -0.15 -0.05

Table 2: Temperature Compensation

.

30

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

V_LCDQUICK REFERENCE

16

14

12

10

8

6

4

0

32

64

96

PM

128

160

192

BR

CV0 (V)

CPM (mV)

PM_reg

VLCD (V)

0

255

0

6.40

9.75

6

6.402

13.14

10.67

16.25

11.74

16.51

12.80

16.51

9.60

10

11

12

9

10.670

11.737

12.804

9.603

21.90

24.09

26.28

19.71

255

0

198

0

141

0

255

14.63

V_LCD-PM-BR relationship at 25^oC

NOTE:

1. For good product reliability, please keep V_LCDunder 16.5V over all temperature.

2. The integer values of BR above are for reference only and may have slight shift.

Revision A_0.6

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High-Voltage Mixed-Signal IC

HI-V GENERATOR REFERENCE CIRCUIT

VDD

VB0+

VDD

CB0

CB1

VB0-

VB1+

VDD2/VDD3

VDD2

VDD3

VB1-

VLCDOUT

VLCDIN

VSS

VSS2

CL

RL

(OPTIONAL)

FIGURE 1: Sample circuit using internal Hi-V generator circuit

NOTE:

Sample component values: (The illustrated circuit and component values are for reference only. Please

optimize for specific requirements of each application.)

C_B0~1: 2.2 µF/5V or 300 x LCD load capacitance, whichever is higher.

C_L: 330 nF (25V) is appropriate for most applications.

R_L: 3.3~10 MΩ to act as a draining circuit when V_DDis shut down abruptly.

32

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

LCD DISPLAY CONTROLS

CLOCK & TIMING GENERATOR

DRIVER ENABLE (DE)

UC1697v contains a built-in system clock. All

required components for the clock oscillator are

built-in. No external parts are required.

Driver Enable is controlled by the value of DC[2]

via the Set Display Enablecommand. When

DC[2] is set to OFF (logic “0”), both COM and

SEG drivers will become idle and UC1697v will

put itself into Sleep mode to conserve power.

Four different line rates are provided for system

design flexibility. The line rate is controlled by

register LC[4:3]. When Mux-Rate is above 88,

frame rate is calculated as:

When DC[2] is set to ON, the DE flag will become

“1”, and UC1697v will first exit from Sleep mode,

restore the power (V_LCD, V_Detc.) and then turn on

COM and SEG drivers.

Line-Rate = Frame Rate x Mux-Rate.

When Mux-Rate is lowered to 87, 65, 44 and 33,

line rate will be scaled down automatically by 1.5,

2, 3 and 4 times to reduce power consumption.

ALL PIXELS ON (APO)

When set, this flag will force all SEG drivers to

output ON signals, disregarding the data stored

in the display buffer.

Flicker-free frame rate is dependent on LC

material and gray-shade modulation scheme.

Line rate 30 Klps or higher is recommended for

32-shade mode. Choose lower frame rate for

lower power, and choose higher frame rate to

improve LCD contrast and minimize flicker.

This flag has no effect when Display Enable is

OFF and it has no effect on data stored in RAM.

INVERSE (PXV)

When switching from 32-shade modulation to

On/Off mode, line rate will be scaled down

automatically by ~30% to reduce power.

When this flag is set to ON, SEG drivers will

output the inverse of the value it received from

the display buffer RAM (bit-wise inversion). This

flag has no impact on data stored in RAM.

Under most situations, flicker behavior is similar

between these two modulation schemes.

However, it is recommended to test each mode

to make sure the result is as expected.

PARTIAL SCROLL

Control register FLT and FLB specify two regions

of rows which are not affected by the SL register.

Since SL register can be used to implement scroll

function. FLT and FLB registers can be used to

implement fixed regions when the other part of

the display is scrolled by SL.

DRIVER MODES

COM and SEG drivers can be in either Idle mode

or Active mode, controlled by Display Enable flag

(DC[2]). When SEG drivers are in Idle mode, they

will be connected together to ensure zero DC

condition on the LCD.

PARTIAL DISPLAY

DRIVER ARRANGEMENTS

UC1697v provides flexible control of Mux Rate

and active display area. Please refer to

commands Set COM End, Set Partial

Display Start, and Set Partial Display

Endfor more detail.

The naming convention is COM(X), where

X =1~128, referring to the COM driver for the

X-th row of pixels on the LCD panel.

The mapping of COM(x) to LCD pixel rows is

fixed and it is not affected by SL, CST, CEN, DST,

DEN, MX or MY settings.

GRAY-SHADE MODULATION MODE

UC1697v has two gray-shade modulation modes:

32-shade and On/Off mode.

DISPLAY CONTROLS

There are three groups of display control flags in

the control register DC: Driver Enable (DE), All-

Pixel-ON (APO) and Inverse (PXV). DE has the

overriding effect over PXV and APO.

The On/Off mode will consume roughly 40~45%

less power than the 32-shade mode, and can be

used for situations where power consumption is

more critical than color fidelity.

Changing gray-shade modulation mode does not

affect the content of SRAM display buffer, and

the image data will remain the same after

switching back and forth between On/Off mode

and 32-shade mode.

Revision A_0.6

33

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High-Voltage Mixed-Signal IC

INPUT COLOR FORMATS

UC1697v supports the following two different

input color formats.

256C (8-bit/RGB): In this color mode, R/G/B will

be extended and the input data will be converted

into 3R-3G-2B format before they are stored to

display RAM.

4KC (12-bit/RGB): In this color mode, R/G/B will

be extended and the input data will be converted

into 5R-6G-5B format before they are stored to

display RAM.

64KC (16-bit/RGB): This is the native color mode.

Data will be stored directly to on-chip SRAM in

5R-6G-5B (16-bit) format (except shade1 and

shade30, which are achieved by special dithering.

See command Set Display Enablefor more

details). This is the default input format mode.

Changing color mode does not affect the content

already stored in the display buffer RAM. Users

can mix several color modes together and switch

among them in real time.

For example, the menu portion can be painted in

4K-color mode for fast update speed, and then

switch to 64K-color mode, together with window

programming function to effectively produce

smooth graphics images.

34

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

ITO LAYOUT AND LC SELECTION

Since COM scanning pulses of UC1697v can be as short as 15µS, it is critical to control the RC delay of

COM and SEG signal to minimize crosstalk and maintain good mass production consistency.

where

COM TRACES

C_COL: LCD loading capacitance of one pixel

Excessive COM scanning pulse RC decay can

cause fluctuation of contrast and increase COM

direction crosstalk.

column. It can be calculated by C_LCD

#_column, where C_LCDis the LCD panel

capacitance.

/

Please limit the worst case of COM signals RC

delay (RC_MAX) as calculated below

R_COL: ITO resistance over one column of

pixels within the active area

R_SEG: SEG routing resistance from IC to the

active area + SEG driver output

impedance.

(R_ROW/ 2.7 + R_COM) x C_ROW< 0.9µS

where

C_ROW: LCD loading capacitance of one row of

pixels. It can be calculated by C_LCD/Mux-

Rate, where C_LCDis the LCD panel

capacitance.

(Use worst case values for all calculations)

SELECTING LIQUID CRYSTAL

The selection of LC material is crucial to achieve

the optimum image quality of finished LCM.

R_ROW: ITO resistance over one row of pixels

within the active area

When (V₉₀-V₁₀)/V₁₀is too high, image contrast

and color saturation will deteriorate, and images

will look murky and dull.

R

_COM: COM routing resistance from IC to the

active area + COM driver output

impedance.

When (V₉₀-V₁₀)/V₁₀is too small, image contrast

will become too strong, visibility of shades will

suffer, and crosstalk may increase sharply for

medium shades.

In addition, please limit the min-max spread of

RC decay to be:

| RC_MAX– RC_MIN| < 0.22µS

so that the COM distortions on the top of the

screen to the bottom of the screen are uniform.

For the best result, it is recommended the LC

material has the following characteristics:

(Use worst case values for all calculations)

(V₉₀-V₁₀)/V₁₀= (V_ON-V_OFF)/V_OFFx 0.72~0.80

where V₉₀and V₁₀are the LC characteristics, and

V_ONand V_OFFare the ON and OFF V_RMSvoltage

produced by LCD driver IC at the specific Mux-

rate.

SEG TRACES

Excessive SEG signal RC decay can cause

image dependent changes of medium gray

shades and sharply increase of SEG direction

crosstalk.

Two examples are provided below:

For good image quality, please minimize SEG

ITO trace resistance and limit the worst case of

SEG signal RC delay as calculated below.

Duty

1/128

Bias

1/12

1/11

V_ON/V_OFF-1 x0.80

x0.72

6.4%

8.95%

8.85%

7.2%

7.1%

(R_COL/ 2.7 + R_SEG) x C_COL< 0.25µS

Revision A_0.6

35

ULTRACHIP

High-Voltage Mixed-Signal IC

RAM

W/R

POL

COM1

COM2

COM3

SEG1

SEG2

FIGURE 2: COM and SEG Driving Waveform

36

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

HOST INTERFACE

As summarized in the table below, UC1697v supports two parallel bus protocols, in either 8-bit or 16-bit bus

width, and three serial bus protocols.

Designers can either use parallel buses to achieve high data transfer rate, or use serial buses to create

compact LCD modules.

Bus Type

8080

6800

S8 (4wr)

S8uc (3/4wr)

Serial

S9 (3 wr)

Width

16-bit

8-bit

16-bit

8-bit

Access

Read/Write

Write Only

00

BM[1:0]

10

00

0x

11

01

0x

00

10

01

10

{DB[15], DB[13]}

CS[1:0]

CD

Data

11

Chip Select

Control / Data

0

___

__

_

WR0

WR1

0

WR

R/W

EN

___ __

0

–

RD

DB[1,3,5,7,9,11]

Data

–

Data

–

DB[0,2,4,6,8,10,12,14]

Data

DB[8]=SDA, DB[0]=SCK

* Connect unused control pins and data bus pins to V_DDor V_SS

CS

Disable

Interface

CS

Init bus

state

CD 1Ù0

Init bus

state

CD 1Ö0

Init color

mapping

RESET

Init bus

state

RESET

Init color

mapping

16-bit

8-bit

–

9

S8 or S9

S8uc

–

9

–

9

•

CS disable bus interface – CS can be used to disable Bus Interface Write / Read Access.

CD refers to CD transitions within valid CS window. CD = 0 means write command or read status.

CS Sync / RESET can be used to initialize bus state machine (like 8-bit / S8 / S9).

RESET can be pin reset / soft reset / power on reset.

CD can be used to initialize the multi-byte input RGB format to/from on-chip SRAM mapping.

Table 3: Host interfaces Summary

Revision A_0.6

37

ULTRACHIP

High-Voltage Mixed-Signal IC

PARALLEL INTERFACE

The timing relationship between UC1697v internal control signal RD, WR and their associated bus actions

are shown in the figure below.

The Display RAM read interface is implemented as a two-stage pipe-line. This architecture requires that,

every time memory address is modified, either in 8-bit mode or 16-bit mode, by either Set CA, or Set RA

command, a dummy read cycle needs to be performed before the actual data can propagate through the

pipe-line and be read from data port D.

There is no pipeline in write interface of Display RAM. Data is transferred directly from bus buffer to internal

RAM on the rising edges of write pulses.

16-BIT & 8-BIT BUS OPERATION

UC1697v supports both 8-bit and 16-bit bus width.

The bus width is determined by pin BM[1].

LSB, including the dummy read, which also

requires two clock cycles. The bus cycle of 8-bit

mode is reset each time CD pin changes state

(when CS is active).

8-bit bus operation exactly doubles the clock

cycles of 16-bit bus operation, MSB followed by

External

CD

___

WR

__

RD

D[15:0]

L_LSB

D_L

D_L+K

C_MSB

C_LSB

Dummy

D_C

D_C+1

M_MSB

M_LSB

Internal

Write

Read

Data

Latch

D_L

L+K

D_L+K

L+K+1

Dummy

D_C

C+1

D_C+1

C+2

D_C+2

C+3

Column

Address

L

C

M

FIGURE 3: 16-bit Parallel Interface & Related Internal Signals

38

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

SERIAL INTERFACE

UC1697v supports three serial modes, a 4-wire SPI mode (S8), a compact 3/4-wire mode (S8uc), and a 3-

wire mode (S9). Bus interface mode is determined by the wiring of the BM[1:0], DB[15] and DB[13]. See

table on last page for more detail.

S8 (4-WIRE) INTERFACE

Only write operations are supported in 4-wire serial

mode. Pin CS[1:0] are used for chip select and bus

cycle reset. Pin CD is used to determine the

content of the data been transferred. During each

write cycle, 8 bits of data, MSB first, are latched on

eight rising SCK edges into an 8-bit data holder.

If CD=0, the data byte will be decoded as

command. If CD=1, this 8-bit will be treated as data

and transferred to proper address in the Display

Data RAM on the rising edge of the last SCK pulse.

Pin CD is examined when SCK is pulled low for the

LSB (D0) of each token.

CS0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

SDA

SCK

CD

FIGURE 4.a: 4-wire Serial Interface (S8)

S8UC (3/4-WIRE) INTERFACE

Only write operations are supported in this 3/4-wire

serial mode. The data format is identical to S8. The

CD pin transitions will reset the bus cycle in this

mode. So, if CS pins are hardwired to enable chip-

select, the bus can work properly with only three

signal pins.

CS0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

SDA

SCK

CD

FIGURE 4.b: 3/4-wire Serial Interface (S8uc)

S9 (3-WIRE) INTERFACE

Only write operations are supported in this 3-wire

serial mode. Pin CS[1-0] are used for chip select

and bus cycle reset. On each write cycle, the first

bit is CD, which determines the content of the

following 8 bits of data, MSB first. These 8

command/data bits are latched on rising SCK

edges into an 8-bit data holder. If CD=0, the data

byte will be decoded as command. If CD=1, this

8-bit will be treated as data and transferred to

proper address in the Display Data RAM at the

rising edge of the last SCK pulse.

By sending CD information explicitly in the bit

stream, control pin CD is not used, and should be

connected to either V_DDor V_SS. The toggle of CS0

or CS1 for each byte of data/command is

recommended but optional.

CS0

CD D7

D6

D5

D4

D3

D2

D1

D0

CD D7

D6

SDA

SCK

FIGURE 4.c: 3-wire Serial Interface (S9)

Revision A_0.6

39

ULTRACHIP

High-Voltage Mixed-Signal IC

HOST INTERFACE REFERENCE CIRCUIT

VDD

VCC

D15~D0

DB15~DB0

CD

WR

RD

CD

WR0(WR)

WR1(RD)

ADDRESS

CS0

CS1

MPU

UC1697v

IORQ

DECODER

VDD

RST

ID0

ID1

VDD

BM1

BM0

GND

VSS

FIGURE 5: 8080/16-bit parallel mode example

VDD

VCC

DB15

DB13

DB7~DB0

DB7

~

DB0

CD

WR

RD

WR0(WR)

WR1(RD)

ADDRESS

IORQ

CS0

CS1

MPU

UC1697v

DECODER

VDD

RST

ID0

ID1

BM1

BM0

GND

VSS

FIGURE 6: 8080/8-bit parallel mode example

40

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

VDD

VCC

D15-D0

DB15~DB0

CD

R/W

E

CD

WR0(R/W)

WR1(E)

ADDRESS

IORQ

CS0

MPU

UC1697v

DECODER

CS1

VDD

RST

ID0

ID1

VDD

BM1

BM0

GND

VSS

FIGURE 7: 6800/16-bit parallel mode example

VDD

VCC

DB15

DB13

DB7-DB0

DB7

~

DB0

CD

R/W

E

WR0(R/W)

WR1(E)

ADDRESS

IORQ

CS0

MPU

UC1697v

DECODER

CS1

VDD

RST

ID0

ID1

BM1

BM0

GND

VSS

FIGURE 8: 6800/8-bit parallel mode example

Revision A_0.6

41

ULTRACHIP

High-Voltage Mixed-Signal IC

VDD

VCC

DB15

DB13

SCK

SDA

CD

SCK(DB0)

SDA(DB8)

CD

WR0

WR1

ADDRESS

IORQ

CS0

CS1

MPU

UC1697v

DECODER

VDD

RST

ID0

ID1

BM1

BM0

GND

VSS

FIGURE 9: 4-Wires SPI (S8) serial mode example

VDD

VCC

DB15

DB13

SCK

SDA

CD

SCK(DB0)

SDA(DB8)

CD

WR0

WR1

CS0

MPU

UC1697v

VDD

RST

ID0

ID1

CS1

BM1

BM0

GND

VSS

FIGURE 10: 3/4-Wires SPI (S8uc) serial mode example

42

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

VDD

VCC

DB15

DB13

SCK

SDA

SCK(DB0)

SDA(DB8)

CD

WR0

WR1

ADDRESS

IORQ

CS0

CS1

MPU

UC1697v

DECODER

VDD

RST

ID0

ID1

VDD

BM1

BM0

GND

VSS

FIGURE 11: 3/4-Wires SPI (S9) serial mode example

Revision A_0.6

43

ULTRACHIP

High-Voltage Mixed-Signal IC

DISPLAY DATA RAM

DATA ORGANIZATION

ROW MAPPING

The input display data (depend on color mode)

are stored to a dual port static RAM (RAM, for

Display Data RAM) organized as 128x128x16.

COM electrode scanning orders are not affected

by Scroll Line (SL), Fixed Line (FLT & FLB) or

Mirror Y (MY, LC[3]). Visually, register SL having

a non-zero value is equivalent to scrolling the

LCD display up or down (depends on MY) by SL

rows.

After setting CA and RA, the subsequent data

write cycles will store the data for the specified

pixel to the proper memory location.

Please refer to the map in the following page

between the relation of COM, SEG, SRAM, and

various memory control registers.

RAM ADDRESS GENERATION

The mapping of the data stored in the display

SRAM and the scanning COM electrodes can be

obtained by combining the fixed COM scanning

sequence and the following RAM address

generation formula.

DISPLAY DATA RAM ACCESS

The Display RAM is a special purpose dual port

RAM which allows asynchronous access to both

its column and row data. Thus, RAM can be

independently accessed both for Host Interface

and for display operations.

When FLT & FLB=0, during the display operation,

the RAM line address generation can be

mathematically represented as following:

For the 1^stline period of each field

DISPLAY DATA RAM ADDRESSING

Line = SL

A Host Interface (HI) memory access operation

starts with specifying Row Address (RA) and

Column Address (CA) by issuing Set Row

Addressand Set Column Address

commands.

Otherwise

Line = Mod(Line+1, 128)

Where Mod is the modular operator, and Line is

the bit slice line address of RAM to be outputted

to SEG drivers. Line 0 corresponds to the first bit-

slice of data in RAM.

If wrap-around (WA, AC[0]) is OFF (0), CA will

stop incrementing after reaching the end of row

(127), and system programmers need to set the

values of RA and CA explicitly.

The above Line generation formula produces the

“loop around” effect as it effectively resets Line to

0 when Line+1 reaches 128. Effects such as

scrolling can be emulated by changing SL

dynamically.

If WA is ON (1), when CA reaches the end of a

row, CA will be reset to 0 and RA will increment

or decrement, depending on the setting of row

Increment Direction (RID, AC[2]). When RA

reaches the boundary of RAM (i.e. RA = 0 or

127), RA will be wrapped around to the other end

of RAM and continue.

MY IMPLEMENTATION

Row Mirroring (MY) is implemented by reversing

the mapping order between COM electrodes and

RAM, i.e. the mathematical address generation

formula becomes:

MX IMPLEMENTATION

For the 1^stline period of each field

Column Mirroring (MX) is implemented by

selecting either (CA) or (127–CA) as the RAM

column address. Changing MX affects the data

written to the RAM.

Line = Mod(SL + MUX-1, 128)

where MUX = CEN + 1

Otherwise

Since MX has no effect on the data already

stored in RAM, changing MX does not have

immediate effect on the displayed pattern. To

refresh the display, refresh the data stored in

RAM after setting MX.

Line = Mod(Line-1, 128)

Visually, the effect of MY is equivalent to flipping

the display upside down. The data stored in

display RAM are not affected by MY.

44

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

WINDOW PROGRAM

Window program is designed for data-write in a

specified window range of SRAM address. The

procedure should start with window boundary

registers setting (WPP0, WPP1, WPC0 and WPC1)

and AC[3] setting for inside/outside window mode.

When AC[3] is set to ‘0’ (default value), data can

be written to SRAM within the window address

range which is specified by (WPP0, WPC0) and

(WPP1, WPC1). When AC[3] is set to ‘1’, data will

be written to whole SRAM excluding the specified

window area.

data-write can be consecutive within the range of

the specified window. AC[1] will control the data

write in either column or row direction. AC[2] will

result the data write starting either from row

WPP0 or WPP1. MX is for the initial column

address either from WPC0 to WPC1 or from (MC-

WPC0 to MC-WPC1).

Specify the starting point of data-write by issuing

commands Set Window Program Starting

Column Address, and Set Window Program

Starting Row Address.

The data-write direction will be determined by

AC[2:0] and MX settings. When AC[0]=1, the

Example1 (AC[2:0] = 001) :

AC[3]=0 MX=0

column

Example 2 (AC[2:0] = 111) :

AC[3] = 0 MX = 0

(0, 0)

(127, 0)

(WPP0, WPC0)

row

(WPP1,WPC1)

(0, 127)

Example1-1 :

Example 2-1 :

AC[3]=1 MX=0

AC[3] = 1 MX = 0

column

0

(127, 0)

(WPP0, WPC0)

row

(WPP1,WPC1)

(0, 127)

Revision A_0.6

45

ULTRACHIP

High-Voltage Mixed-Signal IC

Row

Adderss

RAM

MY=0

SL=0 SL=16

MY=1

SL=0

SL=16

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM17 COM128 COM16

COM18 COM127 COM15

COM19 COM126 COM14

COM20 COM125 COM13

COM21 COM124 COM12

COM22 COM123 COM11

COM23 COM122 COM10

COM24 COM121 COM9

COM25 COM120 COM8

COM10 COM26 COM119 COM7

COM11 COM27 COM118 COM6

COM12 COM28 COM117 COM5

COM13 COM29 COM116 COM4

COM14 COM30 COM115 COM3

COM15 COM31 COM114 COM2

COM16 COM32 COM113 COM1

COM17 COM33 COM112 COM128

COM18 COM34 COM111 COM127

COM19 COM35 COM110 COM126

COM20 COM36 COM109 COM125

COM21 COM37 COM108 COM124

COM22 COM38 COM107 COM123

COM23 COM39 COM106 COM122

COM24 COM40 COM105 COM121

COM25 COM41 COM104 COM120

COM26 COM42 COM103 COM119

COM27 COM43 COM102 COM118

COM28 COM44 COM101 COM117

COM29 COM45 COM100 COM116

68H

69H

6AH

6BH

6CH

6DH

6EH

6FH

70H

71H

72H

73H

74H

75H

76H

77H

78H

79H

7AH

7BH

7CH

7DH

7EH

7FH

COM105 COM121 COM24 COM40

COM106 COM122 COM23 COM39

COM107 COM123 COM22 COM38

COM108 COM124 COM21 COM37

COM109 COM125 COM20 COM36

COM110 COM126 COM19 COM35

COM111 COM127 COM18 COM34

COM112 COM128 COM17 COM33

COM113 COM1

COM114 COM2

COM115 COM3

COM116 COM4

COM117 COM5

COM118 COM6

COM119 COM7

COM120 COM8

COM121 COM9

COM122 COM10

COM123 COM11

COM124 COM12

COM125 COM13

COM126 COM14

COM127 COM15

COM128 COM16

COM16 COM32

COM15 COM31

COM14 COM30

COM13 COM29

COM12 COM28

COM11 COM27

COM10 COM26

COM9

COM8

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM25

COM24

COM23

COM22

COM21

COM20

COM19

COM18

COM17

Example for memory mapping: let MX = 0, MY = 0, SL = 0, LC[7:6] = 10b ( RRRRR-GGGGGG-BBBBB,

64K-color ), according to the data shown in the above table (R: 11111b, G: 111111b, B: 11111b):

⇒

1^stbyte of Write data: 11111111b

2^ndbyte of Write data: 11111111b

46

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

RESET & POWER MANAGEMENT

TYPES OF RESET

CHANGING OPERATION MODE

In addition to Power-ON-Reset, two commands will

initiate OM transitions:

UC1697v has two different types of Reset:

Power-ON-Reset and System-Reset.

Set Display Enable, and System Reset.

Power-ON-Reset is performed right after V_DDis

connected to power. Power-On-Reset will first wait

for about 150mS, depending on the time required

for V_DDto stabilize, and then trigger the System

Reset.

When DC[2] is modified by Set Display

Enable, OM will be updated automatically. There

is no other action required to enter Sleep mode.

OM changes are synchronized with the edges of

UC1697v internal clock. To ensure consistent

system states, wait at least 10µS after Set

Display Enableor System Resetcommand.

System Reset can also be activated by software

command or by connecting RST pin to ground.

In the following discussions, Reset means System

Reset.

Action

Mode

OM

Reset command

RST_ pin pulled “L”

Power ON reset

RESET STATUS

Reset

00

When UC1697v enters RESET sequence:

•

Operation mode will be “Reset”.

Set Driver Enable to “0”

Set Driver Enable to “1”

Sleep

10

11

Normal

All control registers are reset to default values.

Refer to section Control Registers for details of

their default values.

Table 5: OM changes

Both Reset mode and Sleep mode drain the

charges stored in the external capacitors C_B0, C_B1,

and C_L. When entering Reset mode or Sleep mode,

the display drivers will be disabled.

OPERATION MODES

UC1697v has three operating modes (OM):

Reset, Sleep, Normal.

The difference between Sleep mode and Reset

mode is that, Reset mode clears all control

registers and restores them to default values, while

Sleep mode retains all the control registers values

set by the user.

Mode

OM

Reset

00

Sleep Normal

10 11

Active Active

Host Interface

Clock

Active

OFF

ON

OFF

ON

It is recommended to use Sleep Mode for Display

OFF operations as UC1697v consumes very little

energy in Sleep mode (typically under 2µA).

LCD Drivers

Charge Pump

Draining Circuit

ON

OFF

EXITING SLEEP MODE

Table 4: Operating Modes

UC1697v contains internal logic to check whether

V_LCDand V_BIASare ready before releasing COM

and SEG drivers from their idle states. When

exiting Sleep or Reset mode, COM and SEG

drivers will not be activated until UC1697v internal

voltage sources are restored to their proper values.

Revision A_0.6

47

ULTRACHIP

High-Voltage Mixed-Signal IC

POWER-DOWN SEQUENCE

POWER-UP SEQUENCE

To prevent the charge stored in capacitors C_BXand

C_Lfrom damaging the LCD, when V_DDis switched

off, use Reset mode to enable the built-in draining

circuit and discharge these capacitors.

UC1697v power-up sequence is simplified by built-

in “Power Ready” flags and the automatic

invocation of System-Reset command after Power-

ON-Reset.

The draining resistor is 10 KΩ for both V_LCDand

V_B+. It is recommended to wait 3 x RC for V_LCDand

1.5 x RC for V_B. For example, if C_Lis 0.1uF, then

the draining time required for V_LCDis ~3 mS.

System programmers are only required to wait

150 mS before the CPU starting to issue

commands to UC1697v. No additional time

sequences are required between enabling the

charge pump, turning on the display drivers, writing

to RAM or any other commands.

When internal V_LCDis not used, UC1697v will NOT

drain V_LCDduring RESET. System designers need

to make sure external V_LCDsource is properly

There’s no delay needed while turning on V_DDand

drained off before turning off V_DD

.

V_DD2/3, and either one can be turned on first.

Figure 13: Reference Power-Down Sequence

Figure 12: Reference Power-Up Sequence

Either V_DDor V_DD2/3

may be turned on first.

V_DD2/3≥ 2.6V

V_DD≥ 1.8V

T_Wait> 10mS

V_DD< 0.1V

V_DD2/3≥ V_DD

T_f< 10 mS

10µS < T₁< 10 mS

Figure 14: Power Off-On Sequence

48

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

MULTI-TIME PROGRAM NV MEMORY

Although user can use Read Status command in

a polling loop to make sure {MS, WS}={0, 1}

before proceeding with the normal operations,

however, it may be simpler to just issue Set

Display Enablecommand every 0.5~2

second, repeatedly, together with other LCM

optimization settings, such as BR, CEN, TC, etc.

OVERVIEW

MTP feature is available for UC1697v such that

LCM makers can record an PM offset value in

non-volatile memory cells, which can then be

used to adjust the effective V_LCDvalue, in order to

achieve high level of consistency for LCM

contrast across all shipments.

The above “Periodical re-initializing” approach is

also an effective safeguard against accidental

display off events such as

To accomplish this purpose, three operations are

supported by UC1697v:

MTP-Erase, MTP-Program, MTP-Read.

•

ESD strikes

MTP-Program requires an external power source

supplied to TST4 pin. MTP allows to program at

least 10 times and should be performed only by

the LCM makers.

Mechanical shocks causing LCM

connector to malfunction temporarily

HARDWARE VS. SOFTWARE RESET

The auto-MTP-READ is only performed for

hardware RESET (power-ON and RST pin), but

not for software RESET command. This enables

the ICs to turn on display faster without the delay

caused by MTP-READ.

MTP-Read is facilitated by the internal DC-DC

converter built-in on UC1697v, no external power

source is required, and it is performed

automatically after hardware RESET (power-ON

or pin RESET).

It is recommended to use software RESET for

normal operation control purpose and hardware

RESET only during the event of power up and

power down.

OPERATION FOR THE SYSTEM USERS

For the MTP version of UC1697v, the content of

the NV memory will be read automatically after

the power-on and hardware pin RESET. There is

no user intervention or external power source

required. When set up properly, the V_LCDwill be

fine tuned to achieve high level of consistency for

the LCM contrast.

OPERATION FOR THE LCM MAKERS

Always ERASE the MTP NV memory cells,

before starting the Write process.

The MTP-READ is a relatively slow process and

the time required can vary quite a bit. For a

successful MTP-READ operation, the MS and

WS bits in the Read Status commands will exhibit

the following waveforms.

RST

150mS

MS

WS

As illustrated above, the {MS, WS} will go

through a {0,0}Ö{1,0}Ö{1,1}Ö{0,1} transition.

When the {MS, WS}={0,1} state is reached, it

means the LCM is ready to be turned on.

Revision A_0.6

49

ULTRACHIP

High-Voltage Mixed-Signal IC

MTP OPERATION FOR LCM MAKERS

1.

High voltage supply and timer setting

In MTP Program operation, two different high voltages are needed. In chip design, one high voltage is

generated by internal charge pump (V_LCD), the other high voltage must be input from TST4 by external

voltage source.

V_LCDvalue is controlled by register MTP3 and MTP2. The default values of these two registers are

appropriate for most applications.

External TST4 power source is required for MTP Program operation. MTP Programming speed

depends on the TST4 voltage. Considering the ITO trace resistance in COG modules, it is

recommended to program the MTP cells one at a time, so that the required 10V at TST4 can be

maintained with proper consistency.

No external power source is required for MTP Erase and Read operation. For these MTP operations,

TST4 should be open, or connected to V_DD3

.

V_LCD

TST4 (external input)

10V (1mA per bit)

Floating or V_DD3

Program

Erase

MTP3 : 3Dh (12V)

MTP2 : 00h (6.4V)

Read

Floating or V_DD3

Note:

1.

2.

Do Erase before Program and program one bit at a time.

When doing MTP Program or Erase, it’s required to use V_DD2/3ꢀ3.0V.

50

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

3.

Read MTP status bits

With normal Get Status method (CD=0, W/R=1), MTP operation status can be monitored in the real time.

There are 3 status bits (WS, MD, MS) in status register. MTP control circuit will read to verify if the operation

(program, erase) success or not. If the operation succeeded, and current operation will be ended with WS=1.

If it failed, last operation will be automatically retried two more times. If it fails 3 times, WS will be set to 0

and the operation is aborted. MD is MTP ID, which is either 1 for MTP IC. No transition.

Program: 10 V

TST4

Program/Erase

Erase: V_DD3

V_LCD=12V

Read to verify

V_LCD=6.4V

V_LCD

MTP

may repeat 3 times

Command

MD

MS

WS

MTP status bits, TST4 & V_LCDWaveform

MTP CELL VALUE USAGE

There are 6 MTP cell bits. They are divided into two groups for different purpose.

MTP[5:0] : V_LCDTrim

When PMO[5]=1: PM with trim = PM - PMO[4:0]

When PMO[5]=0: PM with trim = PM + PMO[4:0]

Revision A_0.6

51

ULTRACHIP

High-Voltage Mixed-Signal IC

MTP COMMAND SEQUENCE SAMPLE CODES

The following tables are examples of command sequence for MTP Program and Erase operations. These

are only to demonstrate some “typical, generic” scenarios. Designers are encouraged to study related

sections of the datasheet and find out what the best parameters and control sequences are for their specific

design needs.

MTP operations (Erase, Program, Read) and Set Display ON is mutual exclusive. There is no harm done to

the IC or the LCM if this is violated. However, the violating commands will be ignored.

Type

Required:

These items are required

Customized: These items are not necessary if customer parameters are the same as default

Advanced:

Optional:

We recommend new users to skip these commands and use default values.

These commands depend on what users want to do.

C/D

W/R

(1)

The type of the interface cycle. It can be either Command (0) or Data (1)

The direction of dataflow of the cycle. It can be either Write (0) or Read (1).

MTP Program Sample Code

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Chip Action

Set Line Rate

Comments

Set LC[4:3]=11b

R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Set V_MTP1Potentiometer

Set V_MTP2Potentiometer

Set MTP Write Timer

Set MTP Read Timer

Set MTP V_LCD

MTP2: 00h(6.4V)

Set MTP V_LCD

MTP3: 3Dh(12V)

Set MTP Timer

MTP4: 50h(100mS)

Set MTP Timer

MTP5: 08h(10mS)

Set MTP Bit Mask

Set MTP Write Mask

MTPM

Ex: To program MTPM[0] to be 1,

C

R

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

1

-

set the value to 00000001b *

Apply TST4 voltage

Program: 10V

R

0

1

-

0

-

1

0

1

0

1

0

1

0

1

Set MTP Control

Set MTPC[3]=1

Set MTPC[2:0]=011

Check MTP Status until MS=0,

WS=1

R

0

1

-

WS

-

MS Get Status & PM

R

Remove TST4 voltage

Power OFF

V_DD=0V

* It is recommended that users program one bit at a time.

52

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(2)

MTP Erase Sample Code

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Chip action

Set Line Rate

Comments

Set LC[4:3]=11b

Set MTP V_LCD

R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Set V_MTP1Potentiometer

Set V_MTP2Potentiometer

Set MTP Write Timer

Set MTP Read Timer

MTP2: 00h(6.4V)

Set MTP V_LCD

MTP3: 3Dh(12V)

Set MTP Timer

MTP4: 50h(100mS)

Set MTP Timer

MTP5: 08h(10mS)

Set MTP Bit Mask

Set MTP Write Mask

MTPM1

Ex: To erase MTPM[3:0],

set the value to 00001111b

C

0

1

R

0

1

-

0

-

1

0

1

0

1

0

1

0

Set MTP Control

Set MTPC[3]=1

Set MTPC[2:0]=010

Check MTP Status

until MS=0 WS=1

R

0

1

-

WS

-

MS Get Status & PM

R

V_DD=0V

Power OFF

Note: It is recommended that users clear first all the bits to be programmed.

Revision A_0.6

53

ULTRACHIP

High-Voltage Mixed-Signal IC

SAMPLE POWER MANAGEMENT COMMAND SEQUENCES

The following tables are examples of command sequence for power-up, power-down and display ON/OFF

operations. These are only to demonstrate some “typical, generic” scenarios. Designers are encouraged to

study related sections of the datasheet and find out what the best parameters and control sequences are for

their specific design needs.

C/D

W/R

Type

The type of the interface cycle. It can be either Command (0) or Data (1)

The direction of dataflow of the cycle. It can be either Write (0) or Read (1).

Required:

These items are required

Customized: These items are not necessary if customer parameters are the same as default

Advanced:

Optional:

We recommend new users to skip these commands and use default values.

These commands depend on what users want to do.

POWER-UP

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Chip action

Comments

R

–

Wait until V_DD, V_DD2/3are

stable

Turn on V_DDand V_DD2/3

R

C

A

C

–

0

–

0

–

0

1

–

0

1

0

1

–

1

0

1

0

1

–

0

1

0

–

0

1

–

1

#

0

1

0

–

#

–

#

Set RST pin Low

Set RST pin High

Wait 1mS after RST is Low

Automatic Power-ON Reset Wait 150mS

Set Temp. Compensation

Set LCD Mapping

Set Line Rate

Set up LCD format specific

parameters, MX, MY, etc.

Fine tune for power, flicker,

contrast, and shading.

Set Color Mode

LCD specific operating

voltage setting

Set LCD Bias Ratio

0

1

#

0

#

0

#

0

#

0

#

0

#

0

#

1

#

LCD specific operating

voltage setting

R

Set V_BIASPotentiometer

1

.

0

.

#

.

#

.

#

.

#

.

#

.

#

.

#

.

#

.

O

R

Write display RAM

Set Display Enable

Set up display image

.

1

0

#

1

#

0

#

1

#

0

#

1

#

1

#

1

#

1

POWER-DOWN

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Chip action

System Reset

Comments

R

0

–

0

–

1

–

1

–

1

–

0

–

0

–

0

–

1

–

0

–

Draining capacitor

Wait ~3mS before V_DDOFF

DISPLAY-OFF

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Chip action

Set Display Disable

Write display RAM

Comments

R

C

0

1

.

0

.

1

#

.

0

#

.

1

#

.

0

#

.

1

#

.

1

#

.

1

#

.

0

#

.

Set up display image (Image

update is optional. Data in

the RAM is retained through

the SLEEP state.)

.

1

0

#

1

#

0

#

1

#

0

#

1

#

1

#

1

#

1

R

Set Display Enable

54

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

ESD CONSIDERATION

UC1600 series products usually are provided in bare die format to customers. This makes the product

particularly sensitive to ESD damage during handling and manufacturing process. It is therefore highly

recommended that LCM makers strictly follow the "JESD 625-A Requirements for Handling Electrostatic-

Discharge-Sensitive (ESDS) Devices" when manufacturing LCM.

The following pins in UC1697v require special "ESD Sensitivity" consideration in particular:

Machine Mode

Human Body Mode

Test Mode

V_DD

V_SS

V_DD

V_SS

LCD Driver

200V

300V

--

200V

300V

2.0KV

3.0KV

--

2.0KV

3.0KV

LCM Interface

TST1/2/4

CB pins

V_LCDIN

LCM HV pin/

Test pin

V_LCDOUT

PWR / GND

According to UltraChip's Mass Production experiences, the ESD tolerance conditions are believed to be very

stable and can produce high yield in multiple customer sites. However, special care is still required during

handling and manufacturing process to avoid unnecessary yield loss due to ESD damages.

Revision A_0.6

55

ULTRACHIP

High-Voltage Mixed-Signal IC

ABSOLUTE MAXIMUM RATINGS

In accordance with IEC134, Note 1 and 2

Symbol

V_DD

Parameter

Min.

-0.3

--

Max.

Unit

V

Logic Supply voltage

+4.0

V_DD2

LCD Generator Supply voltage

Analog Circuit Supply voltage

V

V_DD3

+4.0

V

V_DD2/3-V_DDVoltage difference between V_DDand V_DD2/3

1.6

V

V_LCD

V_IN

LCD Driving voltage

Digital input signal

-0.3

-0.4

-30

-55

+19.8

V_DD+ 0.5

+85

V

T_OPR

T_STR

Operating temperature range

Storage temperature

^oC

+125

NOTE:

1. V_DDis based on V_SS= 0V

2. Stress beyond ranges listed above may cause permanent damages to the device.

56

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

SPECIFICATIONS

DC CHARACTERISTICS

Symbol

Parameter

Conditions

Min.

1.65

2.5

Typ.

Max. Unit

V_DD

V_DD2/3

V_LCD

V_D

Supply for digital circuit

Supply for bias & pump

Charge pump output

LCD data voltage

3.3

V

_DD2/3= 2.8V, 25^OC

V_DD2/3= 2.8V, 25^OC

15.2

16.5

0.93

1.76

V

V_IL

Input logic LOW

0.2V_DD

V_IH

Input logic HIGH

0.8V_DD

V

V_OL

V_OH

I_IL

Output logic LOW

Output logic HIGH

Input leakage current

0.2V_DD

V

1.5

50

µA

V_DD= V_DD2/3= 3.3V,

Temp = 85^oC

I_SB

Standby current

µA

C_IN

Input capacitance

Output capacitance

5

10

PF

Ω

C_OUT

5

10

R_ON(SEG)SEG output impedance

V_LCD= 16.5V

1000

1900

29.6

1200

2500

R_ON(COM)Upward COM output impedance

Ω

R_ONs(COM)Downward COM output impedance V_LCD= 16.5V

f_LINEAverage line rate

LC[4:3] = 10b, 25^OC

Ω

-10%

+10% Klps

Note : Voltages exceeding the Max. value may still keep the IC operating properly, yet might shorten its

lifetime.

POWER CONSUMPTION

V_DD= 2.7 V,

Bias Ratio = 12,

PM = 92,

V_LCD= 15.22 V,

Mux Rate = 128,

C_B= 2.2 µF,

Line Rate = 10 b,

Panel Loading (PC[1:0]) = 11 b,

C_L= 330 nF,

MTP= 00 H,

Bus mode = 6800,

Temperature = 25 ^oC,

Color Mode = 64 K mode,

N-line inversion = 17 lines

All HV outputs are open circuit.

Display Pattern

All-Pixel-OFF

2-pixel checker

None

Conditions

Bus = idle

Typ. (µA)

1233

Max. (µA)

(TBD)

5

Bus = idle

1692

Reset (stand-by current)

< 1

Revision A_0.6

57

ULTRACHIP

High-Voltage Mixed-Signal IC

AC CHARACTERISTICS

CD

t_AS80

t_AH80

CS0

CS1

t_CSSA80

t_CY80

t_CSH80

t_PWR80, t_PWW80

t_HPW80

WR0

WR1

t_DS80

t_DH80

Write

D[7:0]

t_ACC80

t_OD80

Read

D[7:0]

FIGURE 15: Parallel Bus Timing Characteristics (for 8080 MCU)

(2.5V ꢁ V_DD< 3.3V, Ta= –30 to +85^oC)

Symbol

Signal

Description

Condition

Min.

Max.

Units

t_AS80

t_AH80

t_CY80

CD

Address setup time

Address hold time

System cycle time

16-bit bus

0

–

nS

–

nS

170

130

100

80

(read)

(write)

(read)

(write)

8-bit bus

85

50

65

40

t_PWR80

t_PWW80

t_HPW80

WR1

WR0

Pulse width 16-bit (read)

8-bit

Pulse width 16-bit (write)

8-bit

High pulse width

16-bit bus (read)

(write)

–

nS

WR0, WR1

85

65

50

40

8-bit bus (read)

(write)

t_DS80

t_DH80

t_ACC80

t_OD80

t_CSSA80

t_CSH80

D0~D15

Data setup time

Data hold time

Read access time

Output disable time

30

0

–

15

0

–

nS

C_L= 100pF

60

30

CS1/CS0

Chip select setup time

0

58

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(1.65V ꢁ V_DD< 2.5V, Ta= –30 to +85^oC)

Symbol

Signal

Description

Condition

Min.

Max.

Units

t_AS80

t_AH80

t_CY80

Address setup time

Address hold time

System cycle time

0

–

nS

CD

–

nS

320

270

180

145

16-bit bus (read)

(write)

(read)

(write)

8-bit bus

160

90

135

72

t_PWR80

t_PWW80

t_HPW80

Pulse width 16-bit (read)

8-bit (read)

Pulse width 16-bit (write)

8-bit (write)

High pulse width

16-bit bus (read)

(write)

8-bits bus (read)

(write)

Data setup time

Data hold time

Read access time

Output disable time

–

nS

WR1

WR0

160

135

90

WR0, WR1

D0~D15

72

t_DS80

t_DH80

t_ACC80

t_OD80

t_CSSA80

t_CSH80

60

0

-

30

0

–

nS

C_L= 100pF

120

60

CS1/CS0

Chip select setup time

0

Revision A_0.6

59

ULTRACHIP

High-Voltage Mixed-Signal IC

CD

t_AS68

t_AH68

CS0

CS1

t_CSSA68

t_CY68

t_CSH68

t_PWR68, t_PWW68

t_LPW68

WR1

t_DS68

t_DH68

Write

D[7:0]

t_ACC68

t_OD68

Read

D[7:0]

FIGURE 16: Parallel Bus Timing Characteristics (for 6800 MCU)

(2.5V ꢁ V_DD< 3.3V, Ta= –30 to +85^oC)

Symbol

Signal

Description

Condition

Min.

Max.

Units

t_AS68

t_AH68

t_CY68

CD

Address setup time

Address hold time

System cycle time

0

–

nS

–

nS

170

130

100

80

16-bit bus

(read)

(write)

(read)

(write)

8-bit bus

85

50

65

40

t_PWR68

t_PWW68

t_LPW68

WR1

Pulse width 16-bit (read)

8-bit

Pulse width 16-bit (write)

8-bit

Low pulse width

16-bit bus (read)

(write)

–

nS

85

65

50

40

8-bit bus

(read)

(write)

t_DS68

t_DH68

t_ACC68

t_OD68

t_CSSA68

t_CSH68

D0~D7

Data setup time

Data hold time

Read access time

30

0

–

15

0

–

nS

C_L= 100pF

60

30

Output disable time

CS1/CS0

Chip select setup time

0

60

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

(1.65V ꢁ V_DD< 2.5V, Ta= –30 to +85^oC)

Symbol

Signal

Description

Condition

Min.

Max.

Units

t_AS68

t_AH68

t_CY68

CD

Address setup time

Address hold time

System cycle time

0

–

nS

–

nS

320

270

180

145

16-bit bus (read)

(write)

8-bit bus (read)

(write)

160

90

135

72

t_PWR68

t_PWW68

t_LPW68

WR1

Pulse width 16-bit (read)

8-bit (read)

Pulse width 16-bit (write)

8-bit (write)

Low pulse width

16-bit bus (read)

(write)

–

nS

160

135

90

8-bit bus (read)

(write)

72

t_DS68

t_DH68

t_ACC68

t_OD68

t_CSSA68

t_CSH68

D0~D7

Data setup time

Data hold time

Read access time

Output disable time

60

0

-

30

0

–

nS

C_L= 100pF

120

60

CS1/CS0

Chip select setup time

0

Revision A_0.6

61

ULTRACHIP

High-Voltage Mixed-Signal IC

CD

t_ASS8

t_AHS8

CS0

CS1

t_CSSAS8

t_CYS8

t_LPWS8

t_CSHS8

t_HPWS8

SCK

SDA

t_DSS8

t_DHS8

FIGURE 17: Serial Bus Timing Characteristics (for S8/S8uc)

(2.5V ꢁ V_DD< 3.3V, Ta= –30 to +85^oC)

Symbol

t_ASS8

Signal

Description

Address setup time

Address hold time

System cycle time

Low pulse width

Condition

Min.

0

Max.

Units

nS

CD

–

nS

t_AHS8

0

nS

t_CYS8

SCK

40

20

nS

t_LPWS8

t_HPWS8

t_DSS8

t_DHS8

nS

High pulse width

nS

SDA

Data setup time

Data hold time

15

0

nS

tCSSAS8

t_CSHS8

CS1/CS0

5

Chip select setup time

(1.65V ꢁ V_DD< 2.5V, Ta= –30 to +85^oC)

Symbol

t_ASS8

Signal

Description

Address setup time

Address hold time

System cycle time

Low pulse width

Condition

Min.

0

Max.

Units

nS

CD

–

nS

t_AHS8

0

nS

t_CYS8

SCK

75

37

nS

t_LPWS8

t_HPWS8

t_DSS8

t_DHS8

nS

High pulse width

nS

SDA

Data setup time

Data hold time

30

10

nS

tCSSAS8

t_CSHS8

CS1/CS0

15

Chip select setup time

62

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

CS0

CS1

t_CSS9

t_CYS9

t_WLS9

t_CSHS9

t_WHS9

SCK

SDA

t_DSS9

t_DHS9

FIGURE 18: Serial Bus Timing Characteristics (for S9)

(2.5V ꢁ V_DD< 3.3V, Ta= –30 to +85^oC)

Symbol

t_CYS9

Signal

Description

System cycle time

Low pulse width

High pulse width

Condition

Min.

40

Max.

Units

nS

SCK

–

t_LPWS9

t_HPWS9

t_DSS9

t_DHS9

20

nS

15

nS

SDA

Data setup time

Data hold time

15

0

nS

tCSSAS9

t_CSHS9

CS1/CS0

5

nS

Chip select setup time

(1.65V ꢁ V_DD< 2.5V, Ta= –30 to +85^oC)

Symbol

t_CYS9

Signal

Description

System cycle time

Low pulse width

High pulse width

Condition

Min.

75

Max.

Units

nS

SCK

–

t_LPWS9

t_HPWS9

t_DSS9

t_DHS9

40

nS

30

nS

SDA

Data setup time

Data hold time

30

0

nS

tCSSAS9

t_CSHS9

CS1/CS0

10

nS

Chip select setup time

Revision A_0.6

63

ULTRACHIP

High-Voltage Mixed-Signal IC

t_RW

RST

t_RD

WR[1:0]

FIGURE 19: Reset Characteristics

(1.65V ꢁ V_DD< 3.3V, Ta= –30 to +85^oC)

Symbol

t_RW

Signal

RST

Description

Condition

Min.

3

Max.

Units

Reset low pulse width

Reset to WR pulse delay

–

µS

mS

t_RD

RST, WR

10

64

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

PHYSICAL DIMENSIONS

PAD COORDINATES

DIE SIZE:

11309.6 µM x 1273 µM ± 40 µM

DIE THICKNESS:

400 µM ± 20 µM

AU BUMP HEIGHT:

15 µM

(H_MAX-H_MIN) within die ꢁ 2 µM

BUMP SIZE:

SEG /COM: 14.5x138 µM²

BUMP PITCH:

26.5 µM

BUMP GAP:

12.0 µM

PAD COORDINATE ORIGIN:

Chip center

(Drawing and coordinates are for the

Circuit/Bump view.)

Revision A_0.6

65

ULTRACHIP

High-Voltage Mixed-Signal IC

ALIGNMENT MARK INFORMATION

U-Left

Mark

U-Right

Mark

(0,0)

D-Left

Mark

D-Right

Mark

SHAPE OF THE ALIGNMENT MARK:

NOTE:

3

1

Alignment marks are on Metal3 under

Passivation.

3

C

2

4

The “x” and “+” marks are symmetric

both horizontally and vertically.

3

2

COORDINATES:

U-Left Mark (L)

U-Right Mark (X)

X

Y

X

Y

1

2

3

-5374.5

-5363.3

-5346.5

586

569.2

558

5346.5

5374.5

5353.5

586

558

586

D-Left Mark (+)

D-Right Mark (+)

X

Y

X

Y

1

2

3

4

C

-5419.8

-5399.8

-5452.3

-5367.3

-5409.8

-495

-580

-527.5

-547.5

-537.5

5399.8

5419.8

5367.3

5452.3

5409.8

-495

-580

-527.5

-547.5

-537.5

Note: The values of x-coordinate and y-coordinate in the tables are after-rounded.

TOP METAL AND PASSIVATION:

SiON / 10.5KÅ

Metal3 / 9KÅ

FOR MTP PROCESS CROSS-SECTION

66

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

PAD COORDINATES

#

1

2

3

4

5

6

7

Pad

X

Y

587.375

556.5

530

503.5

477

450.5

424

397.5

371

344.5

318

291.5

265

238.5

212

185.5

159

W

H

#

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Pad

D10

D9

D8

D7

D6

D5

D4

D3

X

Y

W

45

65

45

65

45

65

45

65

45

65

45

65

45

H

DUMMY

COM20

COM22

COM24

COM26

COM28

COM30

COM32

COM34

COM36

COM38

COM40

COM42

COM44

COM46

COM48

COM50

COM52

COM54

COM56

COM58

COM60

COM62

COM64

COM66

COM68

COM70

COM72

COM74

COM76

COM78

COM80

COM82

COM84

COM86

COM88

COM90

COM92

COM94

COM96

COM98

COM100

COM102

COM104

DUMMY

COM106

COM108

COM110

COM112

COM114

COM116

COM118

COM120

COM122

COM124

COM126

COM128

D15

-5551.3

-5325.05

-5298.55

-5272.05

-5245.55

-5219.05

-5192.55

-5166.05

-5139.55

-5113.05

-5086.55

-5060.05

-5033.55

-4853.9

-4793.9

-4733.9

-4487.9

-4427.9

-4181.9

138 23.25

-4121.9

-3875.9

-3815.9

-3569.9

-3509.9

-3263.9

-3203.9

-2957.9

-2897.9

-2651.9

-2591.9

-2415.1

-2333.5

-2253.7

-2173.9

-2092.3

-2010.7

-1930.9

-1851.1

-1769.5

-1689.7

-1609.9

-1530.1

-1470.1

-1059.225

-999.225

-818.8

-739

-659.2

-579.4

-519.4

-459.4

-399.4

-339.4

-279.4

-219.4

-159.4

-99.4

-39.4

20.6

80.6

140.6

228.775

313.6

373.6

433.6

493.6

-541.5

-541

-541.5

-541

-541.5

-541

-541.5

-541

-541.5

-541

119

118

119

118

119

118

119

118

119

118

119

118

119

138

14.5

8

9

D2

D1

D0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

RST_

WR0

VDDX

WR1

CD

CS0

VDDX

CS1

BM0

VDDX

BM1

TST4

TST1

TST2

ID0

132.5

106

79.5

53

26.5

0

-26.5

-53

-79.5

-106

-132.5

-159

-185.5

-212

-238.5

-265

-291.5

-318

-344.5

-371

-397.5

-424

-450.5

-477

-503.5

-530

-556.5

VDDX

ID1

-541.5

-541

VSS

DUMMY

VSS2

VDD

DUMMY

-541.5

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

-587.375 138 23.25

-533

-541.5

14.5

45

138

119

553.6

613.6

673.6

733.6

793.6

853.6

913.6

973.6

1033.6

1093.6

1153.6

1213.6

1273.6

1333.6

1519.525

1579.525

VDDX

D14

D13

D12

45

D11

45

Revision A_0.6

67

ULTRACHIP

High-Voltage Mixed-Signal IC

#

Pad

DUMMY

VDD2

DUMMY

VDD3

VB0+

VB1+

VB1-

X

Y

W

45

H

#

Pad

X

Y

-132.5

-106

-79.5

-53

-26.5

0

26.5

53

79.5

106

132.5

159

185.5

212

238.5

265

291.5

318

344.5

371

397.5

424

450.5

477

503.5

530

556.5

587.375

533

W

H

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

1639.525

1699.525

1759.525

1819.525

1879.525

1939.525

2125.45

2185.45

2245.45

2305.45

2365.45

2425.45

2485.45

2573.625

2750.3

-541.5

-533

119

138

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

COM71

COM69

COM67

COM65

COM63

COM61

COM59

COM57

COM55

COM53

COM51

COM49

COM47

COM45

COM43

COM41

COM39

COM37

COM35

COM33

COM31

COM29

COM27

COM25

COM23

COM21

COM19

DUMMY

COM17

COM15

COM13

COM11

COM9

5551.3

5313.25

5286.75

5260.25

5233.75

5207.25

5180.75

5154.25

5127.75

5101.25

5074.75

5048.25

5021.75

4995.25

4968.75

4942.25

4915.75

4889.25

4862.75

4836.25

4809.75

4783.25

4756.75

4730.25

4703.75

4677.25

4650.75

4624.25

4597.75

4571.25

4544.75

4518.25

4491.75

4465.25

4438.75

4412.25

4385.75

4359.25

138

14.5

2810.3

2878.45

2938.45

2998.45

3058.45

3266.6

3326.6

3386.6

3446.6

3654.75

3714.75

3774.75

3834.75

4042.9

4102.9

4162.9

4222.9

4562.9

VB1-

VB0-

VLCDIN

138 23.25

14.5

138

45

4622.9

4682.9

4742.9

COM7

COM5

COM3

COM1

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

161 VLCDOUT

162 VLCDOUT

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

COM127

COM125

COM123

COM121

COM119

COM117

COM115

COM113

COM111

COM109

COM107

COM105

DUMMY

COM103

COM101

COM99

COM97

COM95

COM93

COM91

COM89

COM87

COM85

COM83

COM81

COM79

COM77

COM75

COM73

5033.55

5060.05

5086.55

5113.05

5139.55

5166.05

5192.55

5219.05

5245.55

5272.05

5298.55

5325.05

5551.3

14.5

-533

SEG9

533

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

-587.375 138 23.25

-556.5

-530

-503.5

-477

-450.5

-424

-397.5

-371

-344.5

-318

-291.5

-265

-238.5

-212

138

14.5

5551.3

533

-185.5

-159

68

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

#

Pad

X

Y

W

H

#

Pad

X

Y

W

H

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

4332.75

4306.25

4279.75

4253.25

4226.75

4200.25

4173.75

4147.25

4120.75

4094.25

4067.75

4041.25

4014.75

3988.25

3961.75

3935.25

3908.75

3882.25

3855.75

3829.25

3802.75

3776.25

3749.75

3723.25

3696.75

3670.25

3643.75

3617.25

3590.75

3564.25

3537.75

3511.25

3484.75

3458.25

3431.75

3405.25

3378.75

3352.25

3325.75

3299.25

3272.75

3246.25

3219.75

3193.25

3166.75

3140.25

3113.75

3087.25

3060.75

3034.25

3007.75

2981.25

2954.75

2928.25

2901.75

2875.25

2848.75

2822.25

2795.75

2769.25

2742.75

2716.25

2689.75

2663.25

2636.75

533

14.5

138

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

SEG94

SEG95

SEG96

SEG97

SEG98

SEG99

2610.25

2583.75

2557.25

2530.75

2504.25

2477.75

2451.25

2424.75

2398.25

2371.75

2345.25

2318.75

2292.25

2265.75

2239.25

2212.75

2186.25

2159.75

2133.25

2106.75

2080.25

2053.75

2027.25

2000.75

1974.25

1947.75

1921.25

1894.75

1868.25

1841.75

1815.25

1788.75

1762.25

1735.75

1709.25

1682.75

1656.25

1629.75

1603.25

1576.75

1550.25

1523.75

1497.25

1470.75

1444.25

1417.75

1391.25

1364.75

1338.25

1311.75

1285.25

1258.75

1232.25

1205.75

1179.25

1152.75

1126.25

1099.75

1073.25

1046.75

1020.25

993.75

533

14.5

138

SEG100

SEG101

SEG102

SEG103

SEG104

SEG105

SEG106

SEG107

SEG108

SEG109

SEG110

SEG111

SEG112

SEG113

SEG114

SEG115

SEG116

SEG117

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

SEG126

SEG127

SEG128

SEG129

SEG130

SEG131

SEG132

SEG133

SEG134

SEG135

SEG136

SEG137

SEG138

SEG139

SEG140

SEG141

SEG142

SEG143

SEG144

SEG145

SEG146

SEG147

SEG148

SEG149

SEG150

SEG151

SEG152

SEG153

SEG154

SEG155

SEG156

SEG157

SEG158

967.25

940.75

914.25

Revision A_0.6

69

ULTRACHIP

High-Voltage Mixed-Signal IC

#

Pad

X

Y

W

H

#

Pad

X

Y

W

H

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

SEG159

SEG160

SEG161

SEG162

SEG163

SEG164

SEG165

SEG166

SEG167

SEG168

SEG169

SEG170

SEG171

SEG172

SEG173

SEG174

SEG175

SEG176

SEG177

SEG178

SEG179

SEG180

SEG181

SEG182

SEG183

SEG184

SEG185

SEG186

SEG187

SEG188

SEG189

SEG190

SEG191

SEG192

SEG193

SEG194

SEG195

SEG196

SEG197

SEG198

SEG199

SEG200

SEG201

SEG202

SEG203

SEG204

SEG205

SEG206

SEG207

SEG208

SEG209

SEG210

SEG211

SEG212

SEG213

SEG214

SEG215

SEG216

SEG217

SEG218

SEG219

SEG220

SEG221

SEG222

SEG223

887.75

861.25

834.75

808.25

781.75

755.25

728.75

702.25

675.75

649.25

622.75

596.25

569.75

543.25

516.75

490.25

463.75

437.25

410.75

384.25

357.75

331.25

304.75

278.25

251.75

225.25

198.75

172.25

145.75

119.25

92.75

533

14.5

138

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

512

513

514

515

516

SEG224

SEG225

SEG226

SEG227

SEG228

SEG229

SEG230

SEG231

SEG232

SEG233

SEG234

SEG235

SEG236

SEG237

SEG238

SEG239

SEG240

SEG241

SEG242

SEG243

SEG244

SEG245

SEG246

SEG247

SEG248

SEG249

SEG250

SEG251

SEG252

SEG253

SEG254

SEG255

SEG256

SEG257

SEG258

SEG259

SEG260

SEG261

SEG262

SEG263

SEG264

SEG265

SEG266

SEG267

SEG268

SEG269

SEG270

SEG271

SEG272

SEG273

SEG274

SEG275

SEG276

SEG277

SEG278

SEG279

SEG280

SEG281

SEG282

SEG283

SEG284

SEG285

SEG286

SEG287

SEG288

-834.75

-861.25

-887.75

-914.25

-940.75

-967.25

-993.75

533

14.5

138

-1020.25

-1046.75

-1073.25

-1099.75

-1126.25

-1152.75

-1179.25

-1205.75

-1232.25

-1258.75

-1285.25

-1311.75

-1338.25

-1364.75

-1391.25

-1417.75

-1444.25

-1470.75

-1497.25

-1523.75

-1550.25

-1576.75

-1603.25

-1629.75

-1656.25

-1682.75

-1709.25

-1735.75

-1762.25

-1788.75

-1815.25

-1841.75

-1868.25

-1894.75

-1921.25

-1947.75

-1974.25

-2000.75

-2027.25

-2053.75

-2080.25

-2106.75

-2133.25

-2159.75

-2186.25

-2212.75

-2239.25

-2265.75

-2292.25

-2318.75

-2345.25

-2371.75

-2398.25

-2424.75

-2451.25

-2477.75

-2504.25

-2530.75

66.25

39.75

13.25

-13.25

-39.75

-66.25

-92.75

-119.25

-145.75

-172.25

-198.75

-225.25

-251.75

-278.25

-304.75

-331.25

-357.75

-384.25

-410.75

-437.25

-463.75

-490.25

-516.75

-543.25

-569.75

-596.25

-622.75

-649.25

-675.75

-702.25

-728.75

-755.25

-781.75

-808.25

70

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

#

Pad

X

Y

W

H

#

Pad

X

Y

W

H

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

SEG289

SEG290

SEG291

SEG292

SEG293

SEG294

SEG295

SEG296

SEG297

SEG298

SEG299

SEG300

SEG301

SEG302

SEG303

SEG304

SEG305

SEG306

SEG307

SEG308

SEG309

SEG310

SEG311

SEG312

SEG313

SEG314

SEG315

SEG316

SEG317

SEG318

SEG319

SEG320

SEG321

SEG322

SEG323

SEG324

SEG325

SEG326

SEG327

SEG328

SEG329

SEG330

SEG331

SEG332

SEG333

SEG334

SEG335

SEG336

SEG337

SEG338

SEG339

SEG340

SEG341

SEG342

SEG343

SEG344

SEG345

SEG346

SEG347

SEG348

SEG349

SEG350

SEG351

SEG352

SEG353

-2557.25

-2583.75

-2610.25

-2636.75

-2663.25

-2689.75

-2716.25

-2742.75

-2769.25

-2795.75

-2822.25

-2848.75

-2875.25

-2901.75

-2928.25

-2954.75

-2981.25

-3007.75

-3034.25

-3060.75

-3087.25

-3113.75

-3140.25

-3166.75

-3193.25

-3219.75

-3246.25

-3272.75

-3299.25

-3325.75

-3352.25

-3378.75

-3405.25

-3431.75

-3458.25

-3484.75

-3511.25

-3537.75

-3564.25

-3590.75

-3617.25

-3643.75

-3670.25

-3696.75

-3723.25

-3749.75

-3776.25

-3802.75

-3829.25

-3855.75

-3882.25

-3908.75

-3935.25

-3961.75

-3988.25

-4014.75

-4041.25

-4067.75

-4094.25

-4120.75

-4147.25

-4173.75

-4200.25

-4226.75

-4253.25

533

14.5

138

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

613

614

615

616

617

618

619

620

621

SEG354

SEG355

SEG356

SEG357

SEG358

SEG359

SEG360

SEG361

SEG362

SEG363

SEG364

SEG365

SEG366

SEG367

SEG368

SEG369

SEG370

SEG371

SEG372

SEG373

SEG374

SEG375

SEG376

SEG377

SEG378

SEG379

SEG380

SEG381

SEG382

SEG383

SEG384

COM2

-4279.75

-4306.25

-4332.75

-4359.25

-4385.75

-4412.25

-4438.75

-4465.25

-4491.75

-4518.25

-4544.75

-4571.25

-4597.75

-4624.25

-4650.75

-4677.25

-4703.75

-4730.25

-4756.75

-4783.25

-4809.75

-4836.25

-4862.75

-4889.25

-4915.75

-4942.25

-4968.75

-4995.25

-5021.75

-5048.25

-5074.75

-5101.25

-5127.75

-5154.25

-5180.75

-5207.25

-5233.75

-5260.25

-5286.75

-5313.25

533

14.5

138

COM4

COM6

COM8

COM10

COM12

COM14

COM16

COM18

Revision A_0.6

71

ULTRACHIP

High-Voltage Mixed-Signal IC

TRAY INFORMATION

H20-58x453-22

72

ES Specifications

UC1697v

128x128RGB CSTN Controller-Driver

REVISION HISTORY

Revision

Contents

Date of Rev.

0.6

First Release

Feb. 7, 2007

Revision A_0.6

73


型号：	UC1697VGAA
厂家：	ETC
描述：	128 x 128RGB C-STN LCD Controller-Driver w/ 16-bit per RGB On-Chip SRAM 128× 128RGB C- STN LCD驱动器瓦特每RGB / 16位的片上SRAM 驱动器静态存储器 CD
文件：	总77页 (文件大小：881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UC1697VGAA [ETC]

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