UC1845N [ETC]
SMPS Controller ; SMPS控制器\n
| 型号： | UC1845N |
| 厂家： | 
ETC |
| 描述： | SMPS Controller
|
| 文件： | 总8页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
available
Current Mode PWM Controller
FEATURES
DESCRIPTION
•
Optimized For Off-line And DC
To DC Converters
The UC1842/3/4/5 family of control ICs provides the necessary features to
implement off-line or DC to DC fixed frequency current mode control schemes
with a minimal external parts count. Internally implemented circuits include
under-voltage lockout featuring start up current less than 1mA, a precision
reference trimmed for accuracy at the error amp input, logic to insure latched
operation, a PWM comparator which also provides current limit control, and a
totem pole output stage designed to source or sink high peak current. The
output stage, suitable for driving N Channel MOSFETs, is low in the off state.
•
•
Low Start Up Current (<1mA)
Automatic Feed Forward
Compensation
•
•
Pulse-by-pulse Current Limiting
Enhanced Load Response
Characteristics
Differences between members of this family are the under-voltage lockout
thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have
UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line
applications. The corresponding thresholds for the UC1843 and UC1845 are
8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles
approaching 100%. A range of zero to 50% is obtained by the UC1844 and
UC1845 by the addition of an internal toggle flip flop which blanks the output
off every other clock cycle.
•
Under-voltage Lockout With
Hysteresis
•
•
Double Pulse Suppression
High Current Totem Pole
Output
•
Internally Trimmed Bandgap
Reference
•
•
500khz Operation
Low RO Error Amp
BLOCK DIAGRAM
A/B
Note 1:
Note 2:
A = DIL-8 Pin Number. B = SO-14 and CFP-14 Pin Number.
Toggle flip flop used only in 1844 and 1845.
SLUS223A - APRIL 1997 - REVISED MAY 2002
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . 30V
Supply Voltage (ICC < 30mA) . . . . . . . . . . . . . . . . . Self Limiting
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
Output Energy (Capacitive Load). . . . . . . . . . . . . . . . . . . . . 5µJ
Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . . -0.3V to +6.3V
Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . . 10mA
Power Dissipation at TA ≤ 25°Χ (DIL−8) . . . . . . . . . . . . . . . . . . 1Ω
Power Dissipation at TA ≤ 25°C (SOIC-14) . . . . . . . . . . 725mW
Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C
Note 1:
All voltages are with respect to Pin 5.
All currents are positive into the specified terminal.
Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW)
N or J Package, D8 Package
PLCC-20 (TOP VIEW)
Q Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
1
N/C
COMP
N/C
2
3
N/C
4
VFB
5
N/C
6
ISENSE
N/C
7
8
N/C
9
SOIC-14, CFP-14. (TOP VIEW)
D or W Package
RT/CT
N/C
10
11
12
13
14
15
16
17
18
19
20
PWR GND
GROUND
N/C
OUTPUT
N/C
VC
VCC
N/C
VREF
DISSIPATION RATING TABLE
Package
TA ≤ 25°C
Power Rating
Derating Factor
Above TA ≤ 25°C
TA ≤ 70°C
Power Rating
TA ≤ 85°C
Power Rating
TA ≤ 125°C
Power Rating
W
700 mW
5.5 mW/°C
452 mW
370 mW
150 mW
2
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for the
UC184X; -40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC = 15V
(Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temp. Stability
Total Output Variation
Output Noise Voltage
Long Term Stability
Output Short Circuit
Oscillator Section
Initial Accuracy
Voltage Stability
Temp. Stability
Amplitude
TJ = 25°C, IO = 1mA
12 ≤ VIN ≤ 25V
1 ≤ I0 ≤ 20mA
4.95
4.9
5.00
6
5.05
20
4.90
4.82
5.00
6
5.10
20
V
mV
mV
6
25
6
25
(Note 2) (Note 7)
0.2
0.4
5.1
0.2
0.4 mV/°C
Line, Load, Temp. (Note 2)
10Hz ≤ f ≤ 10kHz, TJ = 25°C (Note2)
TA = 125°C, 1000Hrs. (Note 2)
5.18
V
50
5
50
5
µV
mV
mA
25
25
-30
47
-100
-180
-30
47
-100
-180
TJ = 25°C (Note 6)
52
0.2
5
57
1
52
0.2
5
57
1
kHz
%
12 ≤ VCC ≤ 25V
TMIN ≤ TA ≤ TMAX (Note 2)
VPIN 4 peak to peak (Note 2)
%
1.7
1.7
V
Error Amp Section
Input Voltage
VPIN 1 = 2.5V
2.45
2.50
-0.3
90
1
2.55
-1
2.42
2.50
-0.3
90
1
2.58
-2
V
µA
dB
MHz
dB
mA
mA
V
Input Bias Current
AVOL
2 ≤ VO ≤ 4V
(Note 2) TJ = 25°C
65
0.7
60
2
65
0.7
60
2
Unity Gain Bandwidth
PSRR
12 ≤ VCC ≤ 25V
70
6
70
6
Output Sink Current
Output Source Current
VOUT High
VPIN 2 = 2.7V, VPIN 1 = 1.1V
VPIN 2 = 2.3V, VPIN 1 = 5V
VPIN 2 = 2.3V, RL = 15k to ground
VPIN 2 = 2.7V, RL = 15k to Pin 8
-0.5
5
-0.8
6
-0.5
5
-0.8
6
VOUT Low
0.7
1.1
0.7
1.1
V
Current Sense Section
Gain
(Notes 3 and 4)
2.85
0.9
3
1
3.15
1.1
2.85
0.9
3
1
3.15
1.1
V/V
V
Maximum Input Signal
PSRR
VPIN 1 = 5V (Note 3)
12 ≤ VCC ≤ 25V (Note 3) (Note 2)
70
-2
70
-2
dB
µA
ns
Input Bias Current
Delay to Output
-10
-10
VPIN 3 = 0 to 2V (Note 2)
150
300
150
300
Note 2:
Note 3:
Note 4:
These parameters, although guaranteed, are not 100% tested in production.
Parameter measured at trip point of latch with VPIN 2 = 0.
Gain defined as
∆VPIN 1
∆VPIN 3
A =
,0 ≤VPIN 3 ≤ 0.8V
Note 5:
Note 6:
Adjust VCC above the start threshold before setting at 15V.
Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
Note 7:
Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
VREF (max) −VREF (min)
Temp Stability =
TJ (max ) −TJ (min)
VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate
temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
3
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
Unless otherwise stated, these specifications apply for −55°C ≤ TA ≤ 125°C for the
ELECTRICAL CHARACTERISTICS:
UC184X; −40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC =
15V (Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNITS
PARAMETER
TEST CONDITION
MIN
TYP
MAX
MIN
TYP
MAX
Output Section
Output Low Level
ISINK = 20mA
ISINK = 200mA
0.1
1.5
13.5
13.5
50
0.4
2.2
0.1
1.5
13.5
13.5
50
0.4
2.2
V
V
Output High Level
ISOURCE = 20mA
13
12
13
12
V
ISOURCE = 200mA
V
Rise Time
TJ = 25°C, CL = 1nF (Note 2)
TJ = 25°C, CL = 1nF (Note 2)
150
150
150
150
ns
ns
Fall Time
50
50
Under-voltage Lockout Section
Start Threshold
X842/4
X843/5
X842/4
X843/5
15
7.8
9
16
8.4
10
17
9.0
11
14.5
7.8
8.5
7.0
16
8.4
10
17.5
9.0
V
V
V
V
Min. Operating Voltage
After Turn On
11.5
8.2
7.0
7.6
8.2
7.6
PWM Section
Maximum Duty Cycle
X842/3
X844/5
95
46
97
48
100
50
0
95
47
97
48
100
50
0
%
%
%
Minimum Duty Cycle
Total Standby Current
Start-Up Current
0.5
11
34
1
0.5
11
34
1
mA
mA
V
Operating Supply Current
VPIN 2 = VPIN 3 = 0V
ICC = 25mA
17
17
VCC Zener Voltage
30
30
Note 2:
Note 3:
.
These parameters, although guaranteed, are not 100% tested in production.
Parameter measured at trip point of latch with VPIN 2 = 0
∆VPIN 1
Note 4:
Gain defined as: A =
;0 ≤VPIN 3 ≤ 0.8V .
∆VPIN 3
Note 5:
Note 6:
Adjust VCC above the start threshold before setting at 15V.
Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
ERROR AMP CONFIGURATION
Error Amp can Source or Sink up to 0.5mA
4
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output driver is activating the power switch with extraneous leakage
biased to sink minor amounts of current. Pin 6 should be currents.
shunted to ground with a bleeder resistor to prevent
CURRENT SENSE CIRCUIT
Peak Current (IS) is Determined By The Formula
ISMAX ′
RS
A small RC filter may be required to suppress switch transients.
OSCILLATOR SECTION
5
UC1842/3/4/5
UC2842/3/4/5
ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
OUTPUT SATURATION CHARACTERISTICS
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads ne- single point ground. The transistor and 5k potentiometer
cessitate careful grounding techniques. Timing and by- are used to sample the oscillator waveform and apply
pass capacitors should be connected close to pin 5 in a an adjustable ramp to pin 3.
SHUT DOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two clock cycle after the shutdown condition at pin 1 and/or
methods; either raise pin 3 above 1V or pull pin 1 below 3 is removed. In one example, an externally latched
a voltage two diode drops above ground. Either method shutdown may be accomplished by adding an SCR
causes the output of the PWM comparator to be high which will be reset by cycling VCC below the lower
(refer to block diagram). The PWM latch is reset domi- UVLO threshold. At this point the reference turns off, al-
nant so that the output will remain low until the next lowing the SCR to reset.
6
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
OFFLINE FLYBACK REGULATOR
5. Output Voltage:
Power Supply Specifications
A. +5V, 5%; 1A to 4A load
Ripple voltage: 50mV P-P Max
1. Input Voltages
5VAC to 130VA
(50 Hz/60Hz)
B. +12V, 3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
2. Line Isolation
3750V
3. Switching Frequency 40kHz
4. Efficiency at Full Load 70%
C. -12V , 3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
SLOPE COMPENSATION
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide
slope compensation for converters requiring duty
cycles over 50%.
7
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明