UC62LV2048KI [ETC]
Low Power CMOS SRAM; 低功耗CMOS SRAM
| 型号： | UC62LV2048KI |
| 厂家： | 
ETC |
| 描述： | Low Power CMOS SRAM |
| 文件： | 总9页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
ꢀFeatures:
• Vcc operation voltage : 1.5 V~ 3.6V
• Low power consumption :
15mA (Max.) operating current
1uA (Typ.) CMOS standby current
• High Speed Access time :
ꢀDescription
The UC62LV2048 is a high performance, low power
CMOS Static Random Access Memory organized as 131,072
words by 16 and operates from 1.5 V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide
both high speed and low power features with a typical CMOS
standby current of 1uA and maximum access time of 70ns in
1.5V operation.
70ns (Max.) at Vcc = 1.5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LV2048 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The US62LV2048 is available in the JEDEC standard 44
pin TSOP (Type II) and 48 ball BGA(6*8mm).
ꢀPRODUCT FAMILY
Speed
(ns)
Vcc=1.5V(Max.)
Power Consumption
Package
Operating
Tempature
Product Family
Vcc Range
1.5V ~ 3.6V
1.5V ~ 3.6V
STANDBY
Operating
Type
Vcc=3.3V(Typ.)
Vcc=3.6V(Max.)
UC62LV2048JC
UC62LV2048KC
UC62LV2048AC
UC62LV2048JI
UC62LV2048KI
TSOPII-44
BGA-48
DICE
0℃ ~ 70℃
55/70
1uA
1uA
15mA
15mA
TSOPII-44
BGA-48
-40℃ ~ 85℃
55/70
UC62LV2048AI
DICE
ꢀPIN CONFIGURATIONS
BLOCK DIAGRAM
A4
A3
1
A5
A6
A7
OE
UB
LB
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2
3
A2
A1
A0
4
5
ROW
Address
CE
6
7
8
9
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
MEMORY ARRAY
128K X 16 Bits
10
11
12
13
14
15
16
17
18
19
20
21
22
COL
Address
VCC
UC62LV2048JC
UC62LV2048JI
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
CE
CE
WE
OE
UB
LB
X16
WE
OE
I/O BUFFER
UB
LB
LB
DQ8
DQ9
GND
VCC
DQ14
DQ15
NC
OE
UB
A0
A3
A1
A4
A2
NC
DQ0
DQ2
VCC
GND
DQ6
DQ7
NC
DQ0 ~ DQ15
CE
DQ10
DQ11
DQ12
DQ13
NC
A5
A6
DQ1
DQ3
DQ4
DQ5
WE
A11
NC
NC
A14
A12
A9
A7
A16
A15
A13
A10
A8
U-Chip Technology Corp. LTD.
Preliminary Rev. 1.0
Reserves the right to modify document contents without notice.
Page
1
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
ꢀPIN DESCRIPTION
Name
A0 – A16
CE\
Type
Input
Input
Function
Address inputs for selecting one of the 131,072 x 16 bit words in the RAM
CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip
enable is not active, the device is deselected and not in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
The Write enable input is active LOW and controls read and write operations. With the chip
selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when
WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is selected
and the write enable is inactive, data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when OE\ is inactive.
Lower byte and upper byte data input/output control pins.
WE\
OE\
Input
Input
UB\ and LB\
DQ0 – DQ15
Vcc
Input
I/O
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Power
Power
Ground
Gnd
ꢀTRUTH TABLE
Mode
WE\
CE\
OE\
LB\
UB\
I/O 0 ~ 7
High Z
I/O 8 ~ 15
High Z
Vcc Current
ISB,ISB1
X
H
X
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
X
L
X
X
H
L
X
X
H
H
L
Not Selected
Output Disabled
High Z
High Z
ICC
DOUT
High Z
DOUT
DIN
High Z
DOUT
DOUT
High Z
DIN
Read
Write
ICC
L
H
L
L
L
X
X
X
L
H
L
ICC
L
H
L
High Z
DIN
L
L
DIN
ꢀABSOLUTE MAXIMUM RATINGS(1)
ꢀ OPERATING RANGE
AMBIENT
TEMPERATURE
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
UNIT
V
RANGE
VCC
Terminal Voltage with
Respect to GND
-0.5 to VCC+0.5
0℃ to 70℃
Commercial
Industrial
1.5V ~ 3.6V
1.5V ~ 3.6V
℃
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to 125
-50 to 150
0.5
-40℃ to 85℃
℃
TSTG
ꢀCAPACITANCE(1)(TA=25℃,f=1.0MHz)
PT
W
PARAMETER
IOUT
DC Output Current
10
mA
SYMBOL
CONDITIONS MAX.
UNIT
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Input
CIN
VIN=0V
VDQ
6
8
Capacitance
Input/Output
Capacitance
CDQ
pF
1. This parameter is guaranteed and not 100% tested.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
Page
2
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
ꢀDC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃)
Test Condition
Symbol
VIL
Comment
MIN.
TYP.(1)
MAX.
UNITS
V
Guaranteed Input Low
VCC=2.4V
-0.5
-
-
0.8
Voltage(2)
Guaranteed Input High
Voltage(2)
VIH
VCC=3.6V
2.0
Vcc-0.2
V
IL
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
VCC=MAX VIN=0V to VCC
-
-
1
1
uA
uA
V
VCC=MAX CE\=VIH or OE\=VIH
VIO=0V t VCC
IOL
-
-
VOL
VOH
ICC
VCC=3.6V, IOL=2mA
-
2.4
-
-
0.4
-
VCC=3.0V, IOH=-1mA
-
V
Operating Power Supply
Current
CE\=VIL,IDQ=0mA, F=Fmax(3)
CE\=VIH, VIN=VIH to VIL
-
15
1
mA
mA
uA
ISB1
ISB2
TTL Standby Current
-
-
CE\≧VCC-0.2V, VIN=VCC-0.2V
CMOS Standby Current
-
1
5
or 0.2V , F=0(4)
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
4. F=0 means input signals must be keep in static state.
ꢀDATA RETENTION CHARACTERISTICS ( TA=0℃ to 70℃)
Symbol
Comment
Test Condition
MIN.
1.2
-
TYP.(1)
MAX.
UNITS
V
CE\≧VCC - 0.2V
VIN≧VCC-0.2V or VIN≦0.2V
CE\≧VCC - 0.2V
VIN≧VCC-0.2V or VIN≦0.2V
VCC to Data Retention
Data Retention Current
VDR
-
-
0.5
-
ICCDR
tDR
0.05
uA
ns
Chip Deselect to Data
Retention Time
0
-
-
See Retention Waveform
(2)
Operation Recovery Time
tR
TRC
-
ns
1. VCC = 1.5V, TA = 25℃.
2. tRC = Read Cycle Time
ꢀLOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled)
Data Retention Mode
VDR >= 1.2V
Vcc
tCDR
VIH
tR
VIH
CE >= VCC - 0.2V
CE
U-Chip Technology Corp. LTD.
Preliminary Rev. 1.0
3
Reserves the right to modify document contents without notice.
Page
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
ꢀAC TEST CONDITIONS
ꢀKEY TO SWITCHING WAVEFORMS
Input Pulse Levels
VCC to 0V
1 V/ns
WAVEFORMS
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output Timing Reference Level
0.5VCC
MUST BE
STEADY
MUST BE
STEADY
ꢀAC TEST LOADS AND WAVEFORMS
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM H TO L
3.3V
3.3V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
WILL BE
CHANGE
FROM L TO H
MAY CHANGE
FROM L TO H
OUTPUT
OUTPUT
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE
STATE
UNKNOWN
FIGURE 1A
FIGURE 1B
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
DOES NOT
APPLY
TERMINAL EQUIVALENT
667Ω
OUTPUT
1.73V
ALL INPUT PULSES
VCC
90% 90%
10%
10%
GND
FIGURE 2
1V/ns
1V/ns
ꢀAC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=1.5V~3.6V)
READ CYCLE
JEDEC
PARAMETER
NAME
UC62LV2048-55
UC62LV2048-70
PARAMETER
NAME
DESCRIPTION
UNIT
Min
Typ
Max
Min
Typ
Max
tAVAX
tAVQV
tELQV
tBA
tRC
tAA
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
-
-
-
-
55
55
30
30
-
-
-
-
-
70
70
35
35
-
tCE
Chip Select Access Time
tBA
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output Low Z
Data Byte Control To Output Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Byte Control To Output High Z
Address Chang to Output Change
tGLQV
tELQX
tGLQX
tBE
tOE
-
10
5
-
-
-
-
10
5
-
-
-
tCLZ
tOLZ
tBE
-
-
10
-
10
-
tEHQZ
tGHQZ
tBDO
tCHZ
tOHZ
tBDO
tOH
-
-
20
20
20
-
-
-
20
20
20
-
-
-
-
-
tAXOX
10
-
10
-
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
Page 4
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
ꢀSWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
ADDRESS
DOUT
tAA
tOH
tOH
READ CYCLE2 (1,3,4)
CE
tCE
(5)
(5)
tCLZ
tCHZ
DOUT
READ CYCLE3 (1,4)
tRC
ADDRESS
OE
tAA
tOH
(1,5)
tOE
tOHZ
tOLZ
CE
tCE
(5)
(5)
tCLZ
tCHZ
UB/LB
tBA
tBDO
tBE
DOUT
NOTES:
1. WE\ is high in read cycle.
2. Device is continuously selected when CE\ = VIL
3. Address valid prior to or coincident with CE\ transition low.
4. OE\ = VIL.
5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
Page 5
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
ꢀAC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=1.5V~3.6V)
WRITE CYCLE
JEDEC
PARAMETER
NAME
UC62LV2048-55
UC62LV2048-70
PARAMETER
NAME
DESCRIPTION
UNIT
Min
55
Typ
-
Max
-
Min
70
Typ
-
Max
-
tAVAX
tE1LWH
tAVWL
tAVWH
tBW
tWC
tCW
tAS
Write Cycle Time
ns
ns
ns
ns
Ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to END of Write
Address Setup Time
40
0
-
-
-
-
-
-
50
0
-
-
-
-
-
-
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
Address valid to End of Write
Data Byte Control End of Write
Write Pulse Width
40
40
40
0
50
50
50
0
tWLWH
tWHAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold Time for Write End
Output Disable to Output In High Z
End of Write to Output Active
-
20
-
20
35
0
40
0
-
20
-
-
20
-
tOHZ
tOW
-
-
10
10
ꢀSWITCHING WAVEFORMS (WRITE CYCLE)
WRITECYCLE1(1)
tWC
ADDRESS
OE
tAW
(11)
(2)
tCW
CE
tAS
(4,10)
tWP
WE
tBW
UB/LB
DOUT
tOHZ
tDW
tDH
DIN
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
Page 6
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
WRITE CYCLE2(1,6)
tWC
ADDRESS
CE
tAW
(11)
(2)
tCW
tAS
tWP
WE
tWHZ
tOH
(7)
DOUT
(8)
tDW
tDH
DIN
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3.
TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = VIL).
7. DOUT is the same phase of write data of this write cycle.
8.
DOUT is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
Page 7
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
ꢀORDERING INFORMATION
UC62LV2048 AB -- YY
A => GRADE
J
:44pin TSOP(II) - 400 mil
:48Ball BGA - 6*8mm
:DICE
K
A
B => GRADE
C
I
:COMMERCIAL (0 ~ 70℃)
:INDUSTRIAL (-40 ~ 85℃)
YY => SPEED
55: 55ns
70: 70ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
Page 8
Low Power CMOS SRAM
128K X 16
UC62LV2048
-55/-70
PACKAGE DIMENSIONS
23
44
A
UNIT
INCH
MM
SYMBOL
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
0.0433±0.004
0.004±0.002
0.039±0.002
0.012 ~ 0.018
0.012 ~ 0.016
0.005 ~ 0.008
0.005 ~ 0.006
0.725±0.004
0.400±0.004
0.463±0.008
0.0315±0.004
0.0197±0.004
0.0197±0.004
0.004 Max.
1.10±0.1
0.1±0.05
1.00±0.05
0.3 ~ 0.45
0.3 ~ 0.4
0.12 ~ 0.21
0.12 ~ 0.16
18.41±0.1
10.16±0.1
11.76±0.20
0.80±0.10
0.50±0.1
θ
A
L
L1
22
1
"A"
b
e
D
DETAIL "A" (2:1)
0.80±0.1
0.1 Max.
0° ~ 8°
y
θ
0° ~ 8°
b
WITH PLATING
c
c1
Seating Plane "y"
b1
BASE METAL
SECTION A-A
TSOPII - 44
Side V iew
Ball pitch e=0.75
D
E
D1
E1
8.0
6.0
5.25
3.75
D±0.1
Solder Ball diam eter = 0.35 ± 0.05
D1
Fig. A
Fig. A
TOP V iew
48 M ini-BGA 6*8m m
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
Page 9
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