UCC2580QTR-3 [ETC]
Voltage-Mode SMPS Controller ; 电压型开关电源控制器\n
| 型号： | UCC2580QTR-3 |
| 厂家： | 
ETC |
| 描述： | Voltage-Mode SMPS Controller
|
| 文件： | 总10页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
Single Ended Active Clamp/Reset PWM
FEATURES
DESCRIPTION
• Provides Auxiliary Switch Activation
Complementary to Main Power
Switch Drive
The UCC3580 family of PWM controllers is designed to implement a variety
of active clamp/reset and synchronous rectifier switching converter topolo-
gies. While containing all the necessary functions for fixed frequency, high
performance pulse width modulation, the additional feature of this design is
the inclusion of an auxiliary switch driver which complements the main
power switch, and with a programmable deadtime or delay between each
transition. The active clamp/reset technique allows operation of single
ended converters beyond 50% duty cycle while reducing voltage stresses
on the switches, and allows a greater flux swing for the power transformer.
This approach also allows a reduction in switching losses by recovering en-
ergy stored in parasitic elements such as leakage inductance and switch
capacitance.
• Programmable deadtime (Turn-on
Delay) Between Activation of Each
Switch
• Voltage Mode Control with
Feedforward Operation
• Programmable Limits for Both
Transformer Volt- Second Product
and PWM Duty Cycle
The oscillator is programmed with two resistors and a capacitor to set
switching frequency and maximum duty cycle. A separate synchronized
ramp provides a voltage feedforward pulse width modulation and a pro-
grammed maximum volt-second limit. The generated clock from the oscilla-
tor contains both frequency and maximum duty cycle information.
• High Current Gate Driver for Both
Main and Auxiliary Outputs
• Multiple Protection Features with
Latched Shutdown and Soft Restart
• Low Supply Current (100µA Startup,
1.5mA Operation)
(continued)
BLOCK DIAGRAM
UDG-95069-2
Pin Numbers refer to DIL-16 and SOIC-16 packages
SLUS292 - FEBRUARY 1999
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
DESCRIPTION (cont.)
The main gate drive output (OUT1) is controlled by the Undervoltage lockout monitors supply voltage (VDD), the
pulse width modulator. The second output (OUT2) is in- precision reference (REF), input line voltage (LINE), and
tended to activate an auxiliary switch during the off time the shutdown comparator (SHTDWN). If after any of
of the main switch, except that between each transition these four have sensed a fault condition, recovery to full
there is deadtime where both switches are off, pro- operation is initiated with a soft start. VDD thresholds, on
grammed by a single external resistor. This design offers and off, are 15V and 8.5V for the -2 and -4 versions, 9V
two options for OUT2, normal and inverted. In the -1 and and 8.5V for the -1 and -3 versions.
-2 versions, OUT2 is normal and can be used to drive
The UCC1580-x is specified for operation over the mili-
PMOS FETs. In the -3 and -4 versions, OUT2 is inverted
tary temperature range of −55°C to 125°C. The
and can be used to drive NMOS FETs. In all versions,
UCC2580-x is specified from −40°C to 85°C. The
both the main and auxiliary switches are held off prior to
UCC3580-x is specified from 0°C to 70°C. Package op-
startup and when the PWM command goes to zero duty
tions include 16-pin surface mount or dual in-line, and
cycle. During fault conditions, OUT1 is held off while
20-pin plastic leadless chip carrier.
OUT2 operates at maximum duty cycle with a guaran-
teed off time equal to the sum of the two deadtimes.
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAMS
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
DIL-16, SOIC-16 (Top View)
J, N, or D Packages
I
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
LINE, RAMP . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to VDD + 1V
ILINE, IRAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3V
I
I
DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5mA
OUT1 (tpw < 1µs and Duty Cycle < 10%) . . . . . . . −0.6A to 1.2A
IOUT2 (tpw < 1µs and Duty Cycle < 10%) . . . . . . . −0.4A to 0.4A
ICLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100mA to 100mA
OSC1, OSC2, SS, SHTDWN, EAIN . . . . . −0.3V to REF + 0.3V
I
I
EAOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5mA to 5mA
REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30mA
PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2V to 0.2V
Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . −55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
PLCC-20 (Top View)
Q Packages
ORDER INFORMATION
2
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications are over the full temperature range, VDD
= 12V, R1 = 18.2k, R2 = 4.41k, CT = 100pF, R3 = 100k, COUT1 = 0, COUT2 = 0. TA = 0°C to 70°C for the UCC3580, −40°C to 85°C
for the UCC2580, −55°C to 125°C for the UCC1580, TA = TJ.
PARAMETER
Oscillator Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Frequency
370
650
4.3
400
750
4.7
0.3
430
850
kHz
ns
V
CLK Pulse Width
CLK VOH
ICLK = −3mA
CLK VOL
ICLK = 3mA
0.5
V
Ramp Generator Section
Ramp VOL
IRAMP = 100µA
50
100
mV
V
Flux Comparator Vth
Pulse Width Modulator Section
Minimum Duty Cycle
Maximum Duty Cycle
PWM Comparator Offset
Error Amplifier Section
EAIN
3.16
3.33
3.50
OUT1, EAOUT = VOL
OUT1, EAIN = 2.6V
0
%
%
V
63
66
69
0.9
0.1
0.4
EAOUT = EAIN
2.44
2.5
150
0.3
5
2.56
400
0.5
V
nA
V
IEAIN
EAOUT = EAIN
EAOUT, VOL
EAIN = 2.6V, IEAOUT = 100µA
EAIN = 2.4V, IEAOUT = −100µA
EAOUT, VOH
4
70
2
5.5
V
AVOL
80
6
dB
MHz
Gain Bandwidth Product
Softstart/Shutdown Section
Start Duty Cycle
SS VOL
f = 100kHz (Note 1)
EAIN = 2.4V
0
%
mV
mV
µA
V
ISS = 100µA
100
400
–20
0.5
50
350
550
–35
0.6
SS Restart Threshold
ISS
SHTDWN VTH
0.4
ISHTDWN
150
nA
Undervoltage Lockout Section
VDD On
UCC3580-2,-4
UCC3580-1,-3
14
8
15
9
16
10
V
V
VDD Off
LINE On
7.5
4.7
4.2
8.5
5
9.5
5.3
4.8
150
V
V
LINE Off
4.5
50
V
ILINE
LINE = 6V
nA
Supply Section
VDD Clamp
IVDD Start
IVDD = 10mA
VDD < VDD On
No Load
14
15
160
2.5
16
250
3.5
V
µA
mA
I
VDD Operating
Output Drivers Section
OUT1 VSAT High
OUT1 VSAT Low
OUT2 VSAT High
OUT2 VSAT Low
OUT1 Fall Time
IOUT1 = −50mA
IOUT1 =100mA
IOUT2 = −30mA
IOUT2 = 30mA
0.4
0.4
0.4
0.4
20
1.0
1.0
1.0
1.0
50
V
V
V
V
COUT1 = 1nF, RS = 3Ω
ns
ns
ns
OUT1 Rise Time
OUT2 Fall Time
COUT1 = 1nF, RS = 3Ω
40
80
COUT2 = 300pF, RS = 10Ω
20
50
3
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications are over the full temperature range, VDD
= 12V, R1 = 18.2k, R2 = 4.41k, CT = 100pF, R3 = 100k, COUT1 = 0, COUT2 = 0. TA = 0°C to 70°C for the UCC3580, −40°C to 85°C
for the UCC2580, −55°C to 125°C for the UCC1580, TA = TJ.
PARAMETER
Output Drivers Section (cont.)
OUT2 Rise Time
TEST CONDITIONS
MIN
TYP
MAX UNITS
COUT2 = 300pF, RS = 10Ω
20
40
ns
ns
ns
ns
ns
Delay 1 OUT2 to OUT1
R3 = 100k, COUT1 = COUT2 = 15pF
TA = TJ = 25°C
90
120
120
170
170
160
140
250
200
100
110
140
Delay 2 OUT1 to OUT2
R3 = 100k, COUT1 = COUT2 = 15pF
TA = TJ = 25°C
Reference Section
REF
IREF = 0
4.875
5
1
1
5.125
20
V
Load Regulation
Line Regulation
IREF = 0mA to 1mA
VDD = 10V to 14V
mV
mV
20
PIN DESCRIPTIONS
R1
R1+1.25 • R2
CLK: Oscillator clock output pin from a low impedance
CMOS driver. CLK is high during guaranteed off time.
CLK can be used to synchronized up to five other
UCC3580 PWMs.
Maximum Duty Cycle =
Maximum Duty Cycle for OUT1 will be slightly less due to
Delay1 which is programmed by R3.
DELAY: A resistor from DELAY to GND programs the
nonoverlap delay between OUT1 and OUT2. The delay
times, Delay1 and Delay2, are shown in Figure 1 and are
as follows:
OUT1: Gate drive output for the main switch capable of
sourcing up to 0.5A and sinking 1A.
OUT2: Gate drive output for the auxiliary switch with
± 0.3A drive current capability.
Delay1=1.1pF • R3
PGND: Ground connection for the gate drivers. Connect
PGND to GND at a single point so that no high frequency
components of the output switching currents are in the
ground plane on the circuit board.
Delay2 is designed to be larger than Delay1 by a ratio
shown in Figure 2.
EAIN: Inverting input to the error amplifier. The
noninverting input of the error amplifier is internally set to
2.5V. EAIN is used for feedback and loop compensation.
RAMP: A resistor (R4) from RAMP to the input voltage
and a capacitor (CR) from RAMP to GND programs the
feedforward ramp signal. RAMP is discharged to GND
when CLK is high and allowed to charge when CLK is
low. RAMP is the line feedforward sawtooth signal for the
PWM comparator. Assuming the input voltage is much
greater than 3.3V, the ramp is very linear. A flux
comparator compares the ramp signal to 3.3V to limit the
maximum allowable volt-second product:
EAOUT: Output of the error amplifier and input to the
PWM comparator. Loop compensation components
connect from EAOUT to EAIN.
GND: Signal Ground.
LINE: Hysteretic comparator input. Thresholds are 5.0V
and 4.5V. Used to sense input line voltage and turn off
OUT1 when the line is low.
Volt-Second Product Clamp = 3.3 • R4 • CR.
OSC1 & OSC2: Oscillator programming pins. A resistor
connects each pin to a timing capacitor. The resistor
connected to OSC1 sets maximum on time. The resistor
connected to OSC2 controls guaranteed off time. The
combined total sets frequency with the timing capacitor.
Frequency and maximum duty cycle are approximately
given by:
REF: Precision 5.0V reference pin. REF can supply up to
5mA to external circuits. REF is off until VDD exceeds 9V
(–1 and –3 versions) or activates the 15V clamp (–2 and
–4 versions) and turns off again when VDD droops below
8.5V. Bypass REF to GND with a 1µF capacitor.
SHTDWN: Comparator input to stop the chip. The
threshold is 0.5V. When the chip is stopped, OUT1 is low
and OUT2 continues to oscillate with guaranteed off time
equal to two non-overlap delay times.
1
Frequency =
(
)
R1+1.25 • R2 • CT
4
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
PIN DESCRIPTIONS (cont.)
SS: A capacitor from SS to ground programs the soft ceed 9V to start and remain above 8.5V to continue run-
start time. During soft start, EAOUT follows the amplitude ning. A shunt clamp from VDD to GND limits the supply
of SS’s slowly increasing waveform until regulation is voltage to 15V. The –2 and –4 versions do not start until
achieved.
the shunt clamp threshold is reached and operation con-
tinues as long as VDD is greater than 8.5V.
VDD: Chip power supply pin. VDD should be bypassed
to PGND. The –1 and –3 versions require VDD to ex-
APPLICATION INFORMATION
UDG-95070-2
Note: Waveforms are not to scale.
Figure 1. Output time relationships.
UVLO and Startup
this clamp must be activated as an indication of reaching
the UVLO on threshold. The internal reference (REF) is
brought up when the UVLO on threshold is crossed. The
startup logic ensures that LINE and REF are above and
SHTDWN is below their respective thresholds before
outputs are asserted. LINE input is useful for monitoring
actual input voltage and shutting off the IC if it falls be-
low a programmed value. A resistive divider should be
used to connect the input voltage to the LINE input. This
feature can protect the power supply from excessive
currents at low line voltages.
For self biased off-line applications, -2 and -4 versions
(UVLO on and off thresholds of 15V and 8.5V typical)
are recommended. For all other applications, -1 and -3
versions provide the lower on threshold of 9V. The IC re-
quires a low startup current of only 160µA when VDD is
under the UVLO threshold, enabling use of a large trickle
charge resistor (with corresponding low power dissipa-
tion) from the input voltage. VDD has an internal clamp
at 15V which can sink up to 10mA. Measures should be
taken not to exceed this current. For -2 and -4 versions,
5
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
The soft start pin provides an effective means to start
the IC in a controlled manner. An internal current of
20µA begins charging a capacitor connected to SS once
the startup conditions listed above have been met. The
voltage on SS effectively controls maximum duty cycle
on OUT1 during the charging period. OUT2 is also con-
trolled during this period (see Figure 1). Negation of any
of the startup conditions causes SS to be immediately
discharged. Internal circuitry ensures full discharge of
SS (to 0.3V) before allowing charging to begin again,
provided all the startup conditions are again met.
DelayTimes
1400
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
Delay Ratio
1200
1000
Delay2
800
600
Delay1
400
200
0
Oscillator
Simplified oscillator block diagram and waveforms are
shown in Figure 3. OSC1 and OSC2 pins are used to
program the frequency and maximum duty cycle. Ca-
pacitor CT is alternately charged through R1 and dis-
charged through R2 between levels of 1V and 3.5V. The
charging and discharging equations for CT are given by
t
0
100
200
300
400
500
600
700
800
900
1000
Ω
R3 ProgrammingResistor [k
]
Figure 2. Delay times.
VC(charge) = REF – 4.0 • e-
τ
1
t
VC(discharge) = 3.5 • e-
τ
2
where τ = R1 • CT and τ = R2 • CT. The charge time
1
2
and discharge time are given by
tCH = R1 • CT and tDIS = 1.25 • R2 • CT
The CLK output is high during the discharge period. It
blanks the output to limit the maximum duty cycle of
OUT1. The frequency and maximum duty cycle are
given by
1
Frequency =
(R1+1.25 • R2) • CT
R1
MaximumDuty Cycle =
R1+1.25 • R2
Maximum Duty Cycle for OUT1 will be slightly less due
to Delay1 which is programmed by R3.
Voltage Feedforward and Volt-Second Clamp
UCC3580 has a provision for input voltage feedforward.
As shown in Figure 3, the ramp slope is made propor-
tional to input line voltage by converting it into a charg-
ing current for CR. This provides a first order
cancellation of the effects of line voltage changes on
converter performance. The maximum volt-second
clamp is provided to protect against transient saturation
of the transformer core. It terminates the OUT1 pulse
when the RAMP voltage exceeds 3.3V. If the
feedforward feature is not used, the ramp can be gener-
ated by tying R4 to REF. However, the linearity of ramp
suffers and in this case the maximum volt-second clamp
is no longer available.
UDG-96016-1
Figure 3. Oscillator and ramp circuits.
6
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
Output Configurations
a single pin is used to program the delays between
OUT1 and OUT2 on both sets of edges. Figure 1 shows
the relationships between the outputs. Figure 2 gives the
ratio between the two delays. During the transition from
main to auxiliary switch, the delay is not very critical for
ZVS turn-on. For the first half of OUT1 off-time, the body
diode of the auxiliary switch conducts and OUT2 can be
turned on any time. The transition from auxiliary to main
switch is more critical. Energy stored in the parasitic in-
ductance(s) at the end of the OUT2 pulse is used to dis-
charge the parasitic capacitance across the main switch
during the delay time. The delay (Delay 1) should be op-
timally programmed at 1/4 the resonant period deter-
mined by parasitic capacitance and the resonant
inductor (transformer leakage and/or magnetizing induc-
tances, depending on the topology). However, depend-
ing on other circuit parasitics, the resonant behavior can
change, and in some cases, ZVS turn-on may not be ob-
tainable. It can be shown that the optimum delay time is
independent of operating conditions for a specific circuit
and should be determined specifically for each circuit.
The UCC3580 family of ICs is designed to provide con-
trol functions for single ended active clamp circuits. For
different implementations of the active clamp approach,
different drive waveforms for the two switches (main and
auxiliary) are required. The -3 and -4 versions of the IC
supply complementary non-overlapping waveforms
(OUT1 and OUT2) with programmable delay which can
be used to drive the main and auxiliary switches. Most
active clamp configurations will require one of these out-
puts to be transformer coupled to drive a floating switch
(e.g. Figure 5). The -1 and -2 versions have the phase of
OUT2 inverted to give overlapping waveforms. This con-
figuration is suitable for capacity coupled driving of a
ground referenced p-channel auxiliary switch with the
OUT2 drive while OUT1 is directly driving an n-channel
main switch (e.g. Figure 4).
The programmable delay can be judiciously used to get
zero voltage turn-on of both the main and auxiliary
switches in the active clamp circuits. For the UCC3580,
UDG-95071-2
Figure 4. Active clamp forward converter.
Note that Vicor Corporation has claimed that the use of active reset in a forward converter topology is covered by their U.S. Patent
No. 4,441,146. Unitrode is not suggesting or encouraging persons to infringe or use Vicor’s patented technology absent a license
from Vicor.
7
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
UDG-96017-1
Figure 5. Off-line active clamp flyback converter.
The use of active reset in a flyback power converter topology may be covered by U.S. Patent No. 5,402,329 owned by Technical
Witts, Inc., and for which Unitrode offers users a paid up license for application of the UCC1580 product family.
8
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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
UDG-96018-1
Figure 6. UCC3580 used in a synchronous rectifier application.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
9
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