UCC3957M-4TR [ETC]
Analog IC ; 模拟IC\n
| 型号： | UCC3957M-4TR |
| 厂家： | 
ETC |
| 描述： | Analog IC
|
| 文件： | 总12页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
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FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
Three- or Four-Cell Operation
Two-Tier Overcurrent Limiting
The UCC3957 is a BiCMOS three- or four-cell
lithium-ion battery pack protector designed to operate
with external P-channel MOSFETs. Utilizing external
P-channel MOSFETs provides the benefits of no
loss-of-system ground in an overdischarge state, and
protects the IC as well as battery cells from damage
during an overcharge state. An internal state machine
runs continuously to protect each lithium-ion cell from
30-µA Typical Supply-Current Consumption
3.5-µA Typical Supply Current in Sleep Mode
Smart Discharge Minimizes Losses in
Overcharge Mode
6.5-V to 20-V VDD Supply Range
overcharge
and
overdischarge.
A
separate
Highly Accurate Internal Voltage Reference
overcurrent-protection block protects the battery pack
from excessive discharge currents.
Externally Adjustable Delays in Overcurrent
Controller
If any cell voltage exceeds the overvoltage threshold,
the appropriate external P-channel MOSFET is turned
off, preventing further charge current. An external
N-channel MOSFET is required to level shift to this
high-side P-channel MOSFET. Discharge current can
still flow through the second P-channel MOSFET.
Likewise, if any cell voltage falls below the undervoltage
limit, the second P-channel MOSFET is turned off and
only charge current is allowed. Such a cell-voltage
condition causes the chip to go into low-power sleep
mode. Attempting to charge the battery pack wakes up
the chip. A cell-count pin (CLCNT) is provided to
program the IC for three- or four-cell operations.
D
Detection of Loss-of-Cell Sense Connections
M PACKAGE
(TOP VIEW)
VDD
CLCNT
WU
DVDD
AVDD
CDLY2
DCHG
CHG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
AN1
AN2
AN3
AN4
A two-tiered overcurrent controller and external current
shunt protect the battery pack from excessive discharge
currents. If the first overcurrent threshold level is
exceeded, an internal timing circuit charges an external
capacitor to provide a user programmable blanking
time. If at the end of the blanking time the overcurrent
condition still exists, the external discharge FET is
turned off for a period 17 times longer than the first
blanking period, and then the discharge FET is turned
back on. If at any time a second higher overcurrent
AN4
10 CDLY1
CHGEN
BATLO
9
threshold is exceeded for more than
a user
programmable time, the discharge FET is turned off,
and remains off for the same period as the first tier off
time. This two tiered overcurrent-protection scheme
allows for charging capacitive loads while retaining
effective short-circuit protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2001, Texas Instruments Incorporated
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
block diagram
VDD
CLCNT
WU
1
2
3
4
5
6
7
8
16 DVDD
15 AVDD
14 CDLY2
13 DCHG
12 CHG
CELL
VOLTAGE
SELECT
STATE
MACHINE
REFERENCE
VOLTAGE
SELECT AND
COMPARE
REF
CLOCK
AN1
S
R
Q
UV
SLEEP
AN2
VDD
+
AN3
11 AN4
AN4
10 CDLY1
OVERCURRENT
CONTROLLER
BATLO
9
CHGEN
UDG–00129
†‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Input voltage: (WU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mA
(AN1, AN3, CLCNT, CHGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VAN4 – VDD
Input voltage range (BATLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.5 V
Storage temperature range, T
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
J
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. Consult
Packaging Information section of the Portable Products Databook (TI Literature No. SLUD001) for thermal limitations and considerations of
packages. All voltages are referenced to the AN4 terminal.
AVAILABLE OPTIONS
†
PACKAGED DEVICES
SSOP (M)
T
A
NORMAL TO OVERCHARGE VOLTAGE (V)
4.25 4.30
UCC3957M–1 UCC3957M–2 UCC3957M–3 UCC3957M–4
4.20
4.35
–20°C to 70°C
†
The M package is available taped and reeled. Add TR suffix to device type (e.g.
UCC3957M–1TR) to order quantities of 2500 devices per reel.
2
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
electrical characteristics over recommended operating free-air temperature range, VDD = 16 V,
–20_C < T < 70_C, T = T . (unless otherwise noted)
A
A
J
supply
PARAMETER
TEST CONDITIONS
MIN
TYP
5.0
30
MAX UNIT
VDD
IDD
Minimum VDD
Supply current
5.5
40
V
min
µA
µA
I
Sleep-mode supply current
VDD = 10.4 V
3.5
7.5
SL
output
PARAMETER
TEST CONDITIONS
MIN
40
TYP
70
MAX UNIT
Driving-logic low,
Driving-logic high,
Driving-logic low,
Driving-logic high,
V
O
V
O
V
O
V
O
= 1 V
100
–3
µA
mA
µA
I
I
DCHG output current
DCHG
= (VDD – 1)
= 1 V
–20
40
–7
70
100
–3
CHG ouput current
CHG
= (VDD – 1V)
–20
–7
mA
state transitions
PARAMETER
TEST CONDITIONS
See Note 1
MIN
4.15
3.95
4.20
4.00
4.25
4.05
4.30
4.10
2.5
TYP
4.20
4.00
4.25
4.05
4.30
4.10
4.35
4.15
2.6
MAX UNIT
V
V
V
V
V
V
V
V
V
V
Normal to overcharge voltage
Overcharge to normal voltage
Normal to overcharge voltage
Overcharge to normal voltage
Normal to overcharge voltage
Overcharge to normal voltage
Normal to overcharge voltage
Overcharge to normal voltage
Undercharge to normal voltage
Normal to undercharge voltage
Overvoltage to CHG delay
Undervoltage to DCHG Delay
Cell sample rate
4.25
4.05
4.30
4.10
4.35
4.15
4.40
4.20
2.7
V
V
OV
UCC3957–1
UCC3957–2
UCC3957–3
UCC3957–4
OVR
OV
See Note 1
See Note 1
See Note 1
See Note 1
V
V
OVR
OV
V
V
OVR
OV
V
V
OVR
UV
V
2.2
2.3
2.4
V
UVR
td
10
17
23
ms
ms
ms
mV
mV
V
OV
UV
td
10
17
23
t
S
5
8.5
11.5
25
V
SM
V
WU
V
CE
Smart discharge threshold
Wakeup input threshold
BATLO voltage
5
15
With respect to VDD
50
230
1.3
750
2.6
Charge-enable input threshold
0.8
short-circuit protection
PARAMETER
First-tier threshold level
TEST CONDITIONS
MIN
120
275
30
TYP
150
375
50
MAX UNIT
V
V
V
V
180
450
70
mV
mV
ms
ms
µs
CL1
BATLO
Second-tier threshold level
First-tier blanking time
Restart time
CL2
BATLO
t
t
t
CDLY1 = 0.1 µF
CDLY1 = 0.1 µF
CDLY2 = 10 pF
B1
300
200
500
400
700
550
RST
B2
Second-tier blanking time
NOTE 1: Other overvoltage or undervoltage thresholds are available. Please consult the factory.
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AN1
NO.
4
I
I
Connects to the negative terminal of the top battery cell and the positive terminal of the second battery cell.
Connects to the bottom terminal of the second battery cell and the top terminal of the third battery cell.
AN2
AN3
5
6
Connects to the bottom terminal of the third battery cell and the top terminal of the fourth battery cell in a four
cell stack. In a three cell pack it connects to the bottom terminal of the third battery and to AN4.
I
I
AN4
7
Connects to the bottom terminal of the battery stack and the top of the current sense resistor.
AVDD
15
Internal analog supply bypass cap pin. Connect a 0.1-µF capacitor between this pin and AN4. This pin is
nominally 7.3 V.
O
I
BATLO
8
9
Connects to the bottom of the current sense resistor and the negative terminal of the battery pack.
CHGEN
The charge enable input for the protection IC. This point must be driven high to allow charging of the battery
pack. This pin has a very weak pulldown.
I
CDLY1
10
Delay control pin for the short-circuit protection feature. A capacitor connected between this point and AN4
determines the time delay from when an overcurrent situation is detected to when the FET is turned off. This
capacitor also controls the hiccup mode timeout period.
O
O
I
CDLY2
CLCNT
14
2
An external cap can be tied between this pin and AN4 to extend the blanking time on the second current limit
tier.
This pin programs the IC for three or four cell operation. Tying this pin low (to AN4) sets four cell operation,
w‘hile tying it high (to VDD or the preferred DVDD or AVDD) sets three cell operation. This pin is internally
pulled low, so open circuit conditions always result in four-cell mode.
DCHG
CHG
13
12
16
This pin is used to prevent overdischarge. If the state machine indicates that any cell is undervoltage, this pin
is driven high with respect to chip substrate so that the external P-channel MOSFET prevents further dis-
charge. If all cell voltages are above the minimum threshold, this pin is driven low.
O
O
This pin is used to control an external N-channel MOSFET, which in turn drives a P-channel MOSFET. If at
least one cell voltage is over the overvoltage threshold, this pin is driven low with respect to AN4. If all cell
voltages are below this threshold, this pin is driven high.
DVDD
Internal digital supply bypass capacitor pin. Connect a 0.1-µF capacitor between this pin and AN4. This pin is
nominally 7.3V.
O
I
VDD
WU
1
3
Supply voltage to the IC. Connect this point to the top of the lithium-ion battery stack.
This pin is used to provide a wakeup signal to the IC during sleep mode. Connect this pin to the drain of the
N-channel level shift MOSFET.
I
4
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
overview
The UCC3957 provides complete protection against overdischarge, overcharge and overcurrent for a three-
or four-cell lithium-ion battery pack. It uses a flying capacitor technique to sample the voltage across each
battery cell and compare it to a precision reference. If any cell is in overvoltage or undervoltage, the
internal-state machine takes the appropriate action to prevent further charge or discharge. High-side P-channel
MOSFETs are used to independently control charge and discharge current. Figure 1 shows a three-cell
litioum-ion protector application diagram with the optional charge-enable switch. In this application, the diode
D1 protects the MOSFET Q2 from inductive kick at turn-off.
R1
1 M
PACK (+)
Q1
IFR7416
CHARGE
Q3
2N7002
Q2
IFR7416
DISCHARGE
C1
0.1
F
F
VDD
1
2
3
4
5
6
7
8
16
DVDD
C2
0.1
C5
4.7
25 V
LI–ION
BATTERY
STACK
F
CLCNT
WU
AVDD 15
CDLY2 14
DCHG 13
CHG 12
C3
OPTIONAL
+
+
+
AN1
AN2
AN3
AN4
AN4 11
C4
22 pF
CDLY1 10
R
SENSE
0.25
PACK (–)
BATLO CHGEN
9
S1
CLOSE TO ENABLE CHARGING
UDG–98016
Figure 1. Three-Cell Lithium-Ion Protector Application Diagram
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
overview (continued)
Figure 2 shows a four-cell protector with optional components to protect the charge FET from excessive
gate-to-source transients. In this application, the Zener diode VR1 and the resistor R2 are optional. They protect
the MOSFET Q1 from excessive open-circuit charger voltage. Diode D1 protects MOSFET Q2 from inductive
kick during turn-off.
VR1 18 V
PACK (+)
R1 1 M
R2
Q1
IFR7416
CHARGE
10 k
D1
1 A, 50 V
Q3
2N7002
Q2
IFR7416
DISCHARGE
C5
4.7
25 V
C1
0.1
F
F
F
VDD
CLCNT
WU
1
2
3
4
5
6
7
8
16
DVDD
C2
0.1
LI–ION
BATTERY
STACK
AVDD 15
CDLY2 14
DCHG 13
CHG 12
C3
OPTIONAL
+
+
+
+
AN1
AN2
AN3
AN4
AN4 11
C4
22 pF
CDLY1 10
R
0.25
SENSE
BATLO CHGEN
9
PACK (–)
UDG–98017
Figure 2. Four-Cell Lithium-Ion Protector Application Diagram
connecting the cell stack
When connecting the cell stack to the circuit, it is important to do so in the proper order. First, the bottom of the
stack should be connected to AN4 . Next, the top of the stack should be connected to VDD. The cell taps can
then be connected to AN1, AN2, and AN3 in any order.
choosing three or four cells
For three-cell packs, the cell-count pin (CLCNT) should be connected to the DVDD pin, and the AN3 pin should
be tied to the AN4 pin. For four-cell applications, the CLCNT pin should be grounded (to AN4) and the AN3 pin
is connected to the positive terminal of the bottom cell in the stack.
6
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
undervoltage protection
When any cell is found to be overdischarged (below the normal-to-undercharge threshold), the state machine
turns off both high-side FETs and enters the sleep mode, where current consumption drops to about 3.5 µA.
It remains in sleep mode until the application of a charger is sensed by the wakeup pin (WU) being raised above
VDD.
charging
Once a charger has been applied, the charge FET is turned on as long as the charge-enable input pin (CHGEN)
is pulled up to the DVDD pin. If the CHGEN input is left open (or connected to AN4), the charge FET remains
off.
During charge, the discharge FET is off if the device is in the sleep state, when current is conducted through
the device’s body diode, until the cell voltages are all above the undercharge-to-normal threshold. Once the cell
voltages are above this threshold, the device enters the normal state and the discharge FET turns on,
minimizing power dissipation. Also, when charging while the device is in sleep state, the charge FET cycles off
and on until the cells are all above the undercharge-to-normal threshold. This cycling is a moderate duty cycle
with approximate on and off times of 7 ms and 10 ms respectively, measured on the TI evaluation module.
open wire protection
The UCC3957 provides protection against broken-cell sense connections within the pack. If the sense
connection to one of the cells (pins AN1, AN2, or AN3) should become disconnected, weak internal-current
sources make the cells that are connected to that wire appear to be in overcharge and charging of the pack is
prevented.
overvoltage protection and the smart discharge feature
If any cell is charged to a voltage exceeding the normal-to-overcharge threshold, the charge FET is turned off,
preventing further charge current. Hysteresis keeps the charge FET off until the cell voltages have dropped
below the overcharge-to-normal threshold. In most protector designs, the charge FET is held off completely
within this voltage band. During this time, discharge current must be conducted through the body diode of the
charge FET. This forward voltage drop can be as high as 1 V, causing significant power dissipation in the charge
FET and wasting precious battery power.
The UCC3957 has a unique smart discharge feature that allows the charge FET to return to on mode (for
discharge only) while still in the overcharge hysteresis band. This greatly reduces power dissipation in the
charge FET. This is accomplished by sensing the voltage drop across the current-sense resistor. If this drop
exceeds 15 mV (corresponding to 0.6 A of discharge current using a .025 Ω sense resistor), the charge FET
is turned back on. This threshold assures that only discharge current is conducted. In an example using a
20-mW FET with a 1-V body diode drop and a 1-A load, the power dissipation in Q1 would be reduced from 1
W to 0.02 W.
NOTE: A similar technique is not used during charge (when the discharge MOSFET is off due to
cells being in undervoltage) because the charge current should be low while the cells are in
undervoltage.
7
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
protection against a runaway charger
The use of a small N-channel level shifter (Q3 in the application diagrams) allows the IC to interface with the
high-side charge FET (Q1), even in the presence of a runaway charger. Only the drain-source voltage rating
of the charge FET limits the charge voltage that the protection circuit can withstand. The wakeup (WU) pin is
designed to handle input voltages greater than VDD, as long as the current is limited. In the examples shown,
the charge FET’s gate-source resistor (R1) provides this current limiting. Note that in Figure 2, a resistor and
zener (R2 and VR1) have been added to protect Q1 against any possibility of a voltage transient exceeding its
maximum gate-source rating.
overcurrent protection
The UCC3957 protects the battery pack from an overload or a hard short circuit using a two-tier overcurrent
protection scheme. The overcurrent protection is designed to go into a hiccup mode when the voltage drop
across an external-sense resistor (connected to the AN4 and BATLO pins) exceeds a certain threshold. In this
mode, the discharge FET is periodically turned off and on until the fault is removed. Once the fault is removed,
normal operation is automatically resumed.
To facilitate charging large capacitive loads, there are two overcurrent threshold voltages, each with its own
user-programmable time delay. This two-tier approach provides fast response to short circuits, while enabling
the battery pack to provide short-duration surge currents. It also facilitates the charging of large filter caps
without causing nuisance overcurrent trips.
The first-tier threshold is 150 mV nominal, corresponding to 6 A using a .025-Ω sense resistor as shown in the
examples of Figure 1 and Figure 2. If the pack-discharge current exceeds this amount for a period of time,
determined by the capacitor on the CDLY1 pin, it then enters the hiccup mode. The first-tier hiccup duty cycle
is fixed at approximately 6%, minimizing power dissipation in the event of a sustained overload. The absolute
on and off times of the discharge FET (Q2) are controlled by the CDLY1 capacitor. A curve relating the delay
(on time) to this capacitor value is shown in Figure 3. The off time is approximately 17 times longer than the on
time.
The second-tier overcurrent threshold is nominally 375 mV, corresponding to 15 A using a .025-Ω sense resistor.
If the pack current exceeds this value for a period of time, determined by the capacitor on the CDLY2 pin, it then
enters the hiccup-mode with a much lower duty cycle, typically less than 1%. The relationship of this time delay
(on time) to the CDLY2 capacitor value is shown in the curve of Figure 5. The off time during this hiccup mode
is still determined by the CDLY1 capacitor, as previously described. This technique greatly reduces the stress
and power dissipation in the FETs during short-circuit conditions.
In the examples shown in Figure 1 and Figure 2 (with CDLY1 = .022 µF), the first-tier overcurrent on time is
approxximately 10 msec, while the off time is approximately 170 msec, resulting in a 5.9% duty cycle for currents
over 6 A (but less than 15 A). If no CLDY2 capacitor is used, the second-tier on time is less than 200 msec
(assuming no stray capacitance), resulting in a duty cycle of about 0.1% for currents over 15 A. If CDLY2 = 22pF,
the typical on time for currents exceeding 15 A is approximately 800 µsec, resulting in a duty cycle of 0.5%.
8
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
protecting against inductive kick at turn-off
In the case of a short circuit, the di/dt that occurs when the discharge FET is turned off can result in a significant
voltage undershoot at the pack output due to stray inductance. This undershoot can potentially exceed the
breakdown voltage rating of the discharge FET. A clamp diode (D1 in Figure 1, Figure 2, and Figure 3), or a
capacitor across the pack output, protects against this possibility. A diode also provides protection from a
reverse-polarity charger.
During turn-off, a voltage overshoot can occur at the top of the cell stack, due to wiring inductance and the cells’
internal equivalent series inductance (ESL). During very high di/dt conditions, such as occurs when turning off
in response to a short circuit, this voltage overshoot can be significant and potentially damage the IC or the
discharge FET (Q2). For this reason, it is strongly recommended that a capacitor (C5 in Figure 1 and Figure 2)
be placed across the cell stack, from VDD to AN4, and that stray inductance be minimized in the battery-current
path. An alternative to adding a capacitor across the cell stack is to reduce the di/dt. This is discussed in the
next section.
controlling discharge FET turn-on and turn-off times
Slew-rate limiting the pack output voltage at turn-on greatly reduces the surge current into large capacitive
loads.
This allows the designer to select shorter overcurrent-delay times, minimizing the stress on Q1 and Q2 in the
event of a shorted pack output. A simple method of implementing slew-rate limiting is shown in Figure 3. It
consists of an RC network (R3 and C5) between gate and drain of the discharge FET (Q2) to control its turn-on
time. This circuit relies on the relatively high-sink impedance (about 20 kΩ) of the UCC3957’s DCHG output.
The values shown for R3 and C5 provide a pack output voltage rise time of about 4.5 msec when the discharge
FET (Q2) is turned on. Note that the addition of R3 and C5 has made it possible to eliminate the CDLY2
capacitor, for the quickest response to a true short circuit. While this circuit does not prevent a large surge current
when inserting a live battery pack into a highly-capacitive load, it does allow it to restart (after one hiccup cycle)
if this initial surge-current trips the overcurrent protection.
Increasing the turn-off time of the discharge FET (Q2) reduces the inductive kick that results during turn-off after
an overcurrent condition. This is accomplished by adding a resistor (R4) in series with the DCHG output. This
reduction of di/dt at turn-off minimizes (or eliminates) the need for a capacitor across the battery stack. It is
recommended that this resistor value not exceed a few hundred Ohms, in which case the ability to turn off quickly
enough into a short may be compromised.
Due to the relatively low-charge currents (typically a few Amperes max), controlling the turn-on and turn-off
times of the charge FET is not beneficial. In fact, the turn-off time of the charge FET is slow due to the large value
of R1, the gate-to-source resistor.
9
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
controlling discharge FET turn-on and turn-off times
Figure 3 shows a four-cell protector with slew-rate limiting the discharge FET. In this application, VR1 and R2
are optional, They protect Q1 from excessive open-circuit charger voltage. R3 and C5 are chosen based on
capacitive load that must be driven. R4 minimizes inductive kick at turn-off.
VR1 18 V
PACK (+)
R1 1 M
R2
Q1
IFR7416
CHARGE
10 k
D1
1 A, 50 V
R3 1
Q3
2N7002
Q2
IFR7416
DISCHARGE
C5
22 pF
R4 100
DVDD
C5
4.7
25 V
C1
0.1
F
F
F
VDD
1
2
3
4
5
6
7
8
16
C2
0.1
LI–ION
BATTERY
STACK
CLCNT
WU
AVDD 15
CDLY2 14
DCHG 13
CHG 12
C3
OPTIONAL
+
+
+
+
AN1
AN2
AN3
AN4
AN4 11
C4
22 pF
CDLY1 10
R
0.25
SENSE
BATLO CHGEN
9
PACK (–)
UDG–98018
Figure 3. Four-Cell Lithium-Ion Protector Application Diagram
10
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SLUS236A – JANUARY 1999 – REVISED JUNE 2001
TYPICAL CHARACTERISTICS
TYPICAL TIER-TWO OVERCURRENT DELAY TIME
TYPICAL TIER-ONE OVERCURRENT DELAY TIME
vs
vs
DELAY CAPACITANCE
DELAY CAPACITANCE
1000
1400
1200
100
10
1
1000
800
Off-time
600
400
Delay
200
0
0.1
0
10
20
30
40
0.001
0.01
0.1
C
– Delay Capacitance – pF
CDLY2
C
– Delay Capacitance – µF
Figure 4
CDLY1
Figure 5
11
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