UG2 [ETC]

UG2 [Updated 4/01. 7 Pages] FPGA Conversion ULC ; UG2 [更新4/01 。 7页] FPGA转换ULC\n


型号：	UG2
厂家：	ETC
描述：	UG2 [Updated 4/01. 7 Pages] FPGA Conversion ULC UG2 [更新4/01 。 7页] FPGA转换ULC\n
文件：	总7页 (文件大小：46K)
中文：	中文翻译
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UG2 Series

0.5µm ULC Series

Description

The UG2 series of ULCs is well suited for conversion of

medium- to-large sized CPLDs and FPGAs. Devices are

implemented in high-performance CMOS technology

with 0.5-µm (drawn) channel lengths, and are capable of

supporting flip-flop toggle rates of 625 MHz at 5V and

360 MHz at 3.3V, operating clock frequencies up to 150

MHz and input to output delays as fast as 5 ns, 200 ps at

5V.

has a very low standby consumption of 0.4 nA/gate

typically commercial temp, which would yield a

standby current of 0.4 nA/gate, 4 mA on a 10,000 gate

design. Operating consumption is a strict function of

clock frequency, which typically results in a power

reduction of 50% to 90% depending on the device being

compared.

The UG2 series provides several options for output

buffers, including a variety of drive levels up to 24 mA.

Schmitt trigger inputs are also an option. A number of

techniques are used for improved noise immunity and

reduced EMC emissions, including: several

independent power supply busses and internal

decoupling for isolation; slew rate limited outputs are

also available as required.

The architecture of the UG2 series allows for efficient

conversion of many PLD architecture and FPGA device

types with higher IO count. A compact RAM cell, along

with the large number of available gates allows the

implementation of RAM in FPGA architectures that

support this feature, as well as JTAG boundary-scan and

scan-path testing.

Conversion to the UG2 series of ULC can provide a

significant reduction in operating power when

compared to the original PLD or FPGA. This is

especially true when compared to many PLD and CPLD

architecture devices, which typically consume 100 mA

or more even when not being clocked. The UG2 series

The UG2 series is designed to allow conversions of high

performance 3-V devices as well as 5-V devices.

Support of mixed supply conversions is also possible,

allowing optimal trade-offs between speed and power

consumption.

Features

D High performance ULC family suitable for

medium- to large-sized CPLDs and FPGAs

D Conversions to over 700,000 FPGA gates

D Pin counts to over 582 pins

D High System Frequency Skew Control:

–

Clock Tree Synthesis Software

D 3 & 5 Volts Operation; Single or Dual Supply

Modes

D Any pin-out matched due to limited number of

D Low Power Consumption:

dedicated pads

–

0.6 µW/Gate/MHz @3 V

2.2 µW/Gate/MHz @5 V

D Full range of packages: DIP, SOIC, LCC/PLCC,

PQFP/TQFP, PGA/PPGA, PBGA/CABGA

D 3.3V and/or 5.0V operation.

D Power on Reset

D Standard 3, 6, 12 and 24mA I/Os

D CMOS/TTL/PCI Interface

D ESD (2 kV) and Latch–up Protected I/O

D High Noise & EMC Immunity:

D Low quiescent current: 0.04 nA/gate

D Available in commercial, industrial, automotive,

military and space grades.

D 0.5 µm Drawn CMOS, 3 Metal Layers

D Library Optimised for Synthesis, Floor Plan &

Automatic Test Generation (ATG)

–

I/O with Slew Rate Control

Internal Decoupling

Signal Filtering between Periphery & Core

Application Dependent Supply Routing &

Several

D High Speed Performances:

–

200 ps Typical Gate Delay @5 V

Typical 625 MHz Toggle Frequency @5V

and 360 MHz @3.3 V

Rev.L – 27 April, 2001

UG2 Series

Product Outline

Part Number*

Full programmable Pads

Equivalent FPGA Gates

UG2005

UP2104

UG215

UG222

UG244

UG291

UG2140

UG2194

UG2265

UG2360

4900

12500

100

111

127

171

235

285

331

384

435

24300

34800

58600

108500

156800

206300

318000

432000

* Check with factory for availability of product type.

Outputs

Architecture

Low noise buffers with 12 mA drive at 5 V.

The basic element of the UG2 family is called a cell.

One cell can typically implement between two to three

FPGA gates. Cells are located contiguously through out

the core of the device, with routing resources provided

in two or three metal layers above the cells. Some cell

blockage does occur due to routing, and utilization will

be significantly greater with three metal routing than

two. The sizes listed in the Product Outline are

estimated usable amounts using three metal layers. I/O

cells are provided at each pad, and may be configured as

I/O Options

Inputs

Each input can be programmed as TTL, CMOS, or

Schmitt Trigger, with or without a pull up or pull down

resistor.

Fast Output Buffer

inputs, outputs, I/Os, V or V as required to match

Fast output buffers are able to source or sink 3 to 12 mA

at 5 V according to the chosen option. 24mA achievable,

using 2 pads.

any FPGA or PLD pinout. Special function cells and

pins are located in the corners which typically are

unused.

Slew Rate Controlled Output Buffer

In order to improve noise immunity within the device,

In this mode, the p- and n-output transistor commands

are delayed, so that they are never set “ON”

simultaneously, resulting in a low switching current and

low noise. These buffer are dedicated to very high load

drive.

separate V

internal cells and the I/O cells.

and V busses are provided for the

I/O buffer interfacing

3.3-V Compatibility

I/O Fexibility

The UG2 series of ULCs is fully capable of supporting

high-performance operation at 3.3 V or 5 V. The

performance specifications of any given ULC design

however, must be explicitly specified as 3.3 V, 5 V or

both.

All I/O buffers may be configured as input, output,

bi–directional, oscillator or supply. A level translator

could be located close to each buffer.

Rev.L – 27 April, 2001

UG2 Series

D The power supplies of the input and output buffers

Power Supply and Noise Protection

are separated.

The speed and density of the UG2 technology cause

large switching current spikes for example either when:

D The rise and fall times of the output buffers can be

controlled by an internal regulator.

16 high current output buffers switch simultaneously,

D A design rule concerning the number of buffers

connected on the same power supply line has been

imposed.

10% of the 700 000 gates are switching within a window

of 1ns.

Matrix switching current protection

Sharp edges and high currents cause some parasitic

elements in the packaging to become significant. In this

frequency range, the package inductance and series

resistance should be taken into account. It is known that

an inductor slows down the setting time of the current

and causes voltage drops on the power supply lines.

These drops can affect the behaviour of the circuit itself

or disturb the external application (ground bounce).

This noise disturbance is caused by a large number of

gates switching simultaneously. To allow this without

impacting the functionality of the circuit, three new

features have been added:

D Decoupling capacitors are integrated directly on the

silicon to reduce the power supply drop.

D A power supply network has been implemented in

the matrix. This solution reduces the number of

parasitic elements such as inductance and resistance

and constitutes an artificial VDD and Ground plane.

One mesh of the network supplies approximately

150 cells.

D A low pass filter has been added between the matrix

and the input to the output buffer. This limits the

transmission of the noise coming from the ground or

the VDD supply of the matrix to the external world

via the output buffers.

In order to improve the noise immunity of the UG2 core

matrix, several mechanisms have been implemented

inside the UG2 arrays. Two kinds of protection have

been added: one to limit the I/O buffer switching noise

and the other to protect the I/O buffers against the

switching noise coming from the matrix.

I/O buffers switching protection

Three features are implemented to limit the noise

generated by the switching current:

Rev.L – 27 April, 2001

UG2 Series

Absolute Maximum Ratings

Recommended Operating Range

Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 to 5.5 V

Input Voltage (V ) . . . . . . . . . . . . . . . . . . . –0.5 V to V + 7.0 V

Operating Temperature

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150_C

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 to 85_C

Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 125_C

DC Characteristics

Specified at VDD = +5 V $ 10 %

Symbol

Parameter

Min

Typ

Max

Unit

Conditions

VIL

Input low voltage

CMOS input

TTL input

0.3 VDD

0.8

VIH

Input high voltage

CMOS input

TTL input

0.7 VDD

2.2

VDD

VOL

VOH

Output low voltage

TTL input

IOL = –12, 6, 3 mA*

0.4

Output high voltage

CMOS input

3.9

2.4

IOH = +12, 6, 3 mA*

TTL input

VT+

VT–

Scmitt trigger positive threshold

CMOS input

2.8

1.5

TTL input

Scmitt trigger negative threshold

CMOS input

1.2

1.0

TTL input

Input leakage

No pull up/down

Pull up

–5

µA

–120

–55

330

Pull down

IOZ

IOS

3–State Output Leakage current

–5

Output Short circuit current

Bout12

VOUT = 4.5 V

VOUT = VSS

IOSN

IOSP

ICCSB

Leakage current per cell

commercial

industrial

military

0.6

ICCOP

Operating current per cell

µA/MHz

* According buffer: Bout12, Bout6, Bout3, VDD = 4,5 V

Rev.L – 27 April, 2001

UG2 Series

DC Characteristics

Specified at VDD = +3 V $ 10 % or 3.3 $ 10 %

Symbol

Parameter

Min

Typ

Max

Unit

Conditions

VIL

Input low voltage

LVCMOS input

LVTTL input

0.3 VDD

0.8

VIH

Input high voltage

LVCMOS input

LVTTL input

0.7 VDD

2.0

VDD

VOL

VOH

VT+

Output low voltage

TTL input

IOL = –6, 3, 1.5 mA*

0.4

Output high voltage

TTL input

IOH = +4, 2, 1 mA*

2.4

Scmitt trigger positive threshold

LVCMOS input

1.1

1.5

LVTTL input

VT–

Scmitt trigger negative threshold

CMOS input

1.0

0.9

TTL input

Input leakage

No pull up/down

Pull up

–5

µA

–100

–30

200

Pull down

IOZ

IOS

3–State Output Leakage current

–5

µA

Output Short circuit current

Bout12

VOUT = VDD

VOUT = VSS

IOSN

IOSP

ICCSB

Leakage current per cell

commercial

industrial

military

ICCOP

Operating current per cell

0.3

µA/MHz

* According buffer: Bout12, Bout6, Bout3

Rev.L – 27 April, 2001

UG2 Series

AC Characteristics

TJ = 25°C, Process typical (all values in ns)

VDD

Buffer

Description

Load

Transition

BOUT12

Output buffer with 12 mA drive

60pf

Tplh

Tphl

3.18

2.35

4.67

3.33

VDD

Cell

Description

Load

Transition

BINCMOS

CMOS input buffer

15 fan

Tplh

Tphl

Tplh

Tphl

Tplh

Tphl

Tplh

Tphl

Tplh

Tphl

0.75

0.7

1.12

0.98

1.29

1.03

0.85

0.49

0.89

0.67

1.30

1.08

1.06

0.00

BINTTL

INV

TTL input buffer

Inverter

16 fan

12 fan

8 fan

0.88

0.65

0.54

0.39

0.57

0.49

0.86

0.73

0.44

0.00

NAND2

FDFF

2 – input NAND

D flip–flop, Clk to Q

Power Consumption

the outputs are tri-stated or in input mode. So this

term is zero.

Global formula for static consumption:

Static Power Consumption for UG2 Series ULCs

There are three main factors to consider:

–

Leakage in the core:

= V * I

= P + P

LC LIO

–

* number of used gates

CCSB

Dynamic Power Consumption for UG2 Series

ULCs

–

Leakage in inputs and tri-stated outputs:

–

= V * (I * N + I * M)

LIO DD IX OZ

where: N = number of inputs

There are four main factors to consider:

–

Static power dissipation is negligible compared to

dynamic and can be ignored.

M = number of tri-stated outputs

Care must be taken to include the appropriate

figure for pins with pull-ups or pull-downs. In

practice, the static consumption calculation is

typically done to determine the standby current

of a device; in this case only those pins sourcing

–

Dc power dissipation in I/O buffers due to resistive

loads:

–

P (mW) = V * Σ (D * I ) + ( V – V

)

Ln OLn

* Σ (D * I )

OHn

current should be included, i.e. where V or

where: Σ is a summation over all of the outputs

OUT

= V

and I/Os.

and I

are the appropriate values for

–

Dc power dissipation in driving I/O buffers due to

resistive loads:

OLn

OHn

driver n

–

= percentage of time n is being driven to V

–

In practice, the static consumption calculation is

typically done to determine the standby current

of a device, and under circumstances where all of

Ln OL

= percentage of time n is being driven to

Rev.L – 27 April, 2001

UG2 Series

–

It is difficult to obtain an exact value for this

factor, since it is determined primarily by

–

output capacitance from DC

OUT

Characteristics

external system parameters.

However, in

–

Global formula for dynamic consumption:

practice this can be simplified to one of two cases

where the device is either driving CMOS loads or

driving TTL loads. CMOS loads can be

approximated as purely capacitive loads,

allowing this term to be treated as zero. TTL

loads source significant current in the low state,

but not the high state, allowing the second

summation to be ignored. If a 50% duty cycle is

assumed for dynamic outputs driving TTL loads,

this can be approximated as:

P = P + P + P

Example:

Static calculation

–

A 100-pin ULC with 3000 used gates, 10 inputs,

20 I/Os in input mode, 40 outputs all tri-stated.

No pull-ups or pull-downs. Half of the pins are at

, half at V . Input clock is not toggling. For

this example only the current calculation is

desired, so the V

dropped.

term in the equations is

–

P (mW) = V * (Σ * I /2 + Σ * I

) (TTL

OLm

OLn

loads)

–

= 1 * 3000 = 3 mA

where n are dynamic outputs and m are static low

outputs.

= ((10 + 20) * 5 + 40 * 5)/2 = 105 mA

LIO

= 3 + 105 = 108 mA

–

Dynamic power dissipation for the internal gates:

Dynamic Calculation

–

P (mW) = V * I

* Σ (N * f )/1000

DDOP g f g

–

We take a 16-bit resettable ripple counter which

is approximately 100 gates, operating at a clock

frequency of 33 MHz, which gives an average

clock frequency of 33 MHz/16 for each bit and

each output. There are no static outputs on this

device. Operation is at 5 V, and 6-mA outputs are

used and loaded at 25 pF. The output buffers are

driving CMOS loads.

where:

= number of gates toggling at

frequency f

–

f = clock frequency of internal logic in MHz

Note: If the actual toggle rates are not known, a

rule of thumb is to assume that the average used

gate is toggling at one half of the input clock

frequency.

–

P = 0

–

Dynamic power dissipation in the outputs:

P = 5 * 0.5 * 100 * 33/16/1000 = 0.5 mW

–

P (mW) = V

* Σ f * (C

+ C )/1000

OUT n

P = 5 * 16 * 33/16 * (25 + 2)/1000 = 22 mW

where: f = clocking frequency in MHz of output

P = 0 + 0.5 + 22 = 22.5 mW

–

C = output load capacitance in pF of output n

Figure 1

Typical ULC Test Conditions

For AC specification purposes, an improved output

loading scheme has been defined for Atmel Wireless &

Microcontrollers high-drive (24 mA), high-speed ULC

devices. The schematic below (Figure 1) describes the

typical conditions for testing these ULC devices, using

the standard loading scheme commonly available on

high-end ATE.

12 mA

D.U.T.

1.5 V

Compared to a no-load condition, this provides the

following advantages:

12 mA

Comp

D Output load is more representative of “real life”

conditions during transitions.

D Transient energy is absorbed at the end of the line to

prevent reflections which would lead to inaccurate

ATE measurements.

Rev.L – 27 April, 2001

UG2 [ETC]

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